JP2024542933A5 - - Google Patents
Info
- Publication number
- JP2024542933A5 JP2024542933A5 JP2024520748A JP2024520748A JP2024542933A5 JP 2024542933 A5 JP2024542933 A5 JP 2024542933A5 JP 2024520748 A JP2024520748 A JP 2024520748A JP 2024520748 A JP2024520748 A JP 2024520748A JP 2024542933 A5 JP2024542933 A5 JP 2024542933A5
- Authority
- JP
- Japan
- Prior art keywords
- pseudo
- channel
- data bus
- selection device
- channel selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/452,606 US11893240B2 (en) | 2021-10-28 | 2021-10-28 | Reducing latency in pseudo channel based memory systems |
| US17/452,606 | 2021-10-28 | ||
| PCT/US2022/045561 WO2023075993A1 (en) | 2021-10-28 | 2022-10-03 | Reducing latency in pseudo channel based memory systems |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2024542933A JP2024542933A (ja) | 2024-11-19 |
| JP2024542933A5 true JP2024542933A5 (enExample) | 2025-09-30 |
Family
ID=84246003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024520748A Pending JP2024542933A (ja) | 2021-10-28 | 2022-10-03 | 擬似チャネルベースのメモリシステムにおけるレイテンシの低減 |
Country Status (7)
| Country | Link |
|---|---|
| US (3) | US11893240B2 (enExample) |
| EP (1) | EP4423618A1 (enExample) |
| JP (1) | JP2024542933A (enExample) |
| KR (1) | KR20240088958A (enExample) |
| CN (1) | CN118056195A (enExample) |
| TW (1) | TW202321896A (enExample) |
| WO (1) | WO2023075993A1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11893240B2 (en) | 2021-10-28 | 2024-02-06 | Qualcomm Incorporated | Reducing latency in pseudo channel based memory systems |
| US12147713B2 (en) * | 2022-08-09 | 2024-11-19 | Innosilicon Microelectronics (Zhuhai) Co., Ltd. | High-bandwidth DDR DIMM, memory system, and operation method thereof |
| US20250061070A1 (en) * | 2023-08-14 | 2025-02-20 | Micron Technology, Inc. | Memory device with a die having multiple pseudo channels per channel |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7269709B2 (en) * | 2002-05-15 | 2007-09-11 | Broadcom Corporation | Memory controller configurable to allow bandwidth/latency tradeoff |
| DE10339787B4 (de) | 2003-08-28 | 2005-11-03 | Infineon Technologies Ag | Speichermodul |
| US7263566B2 (en) * | 2004-12-30 | 2007-08-28 | Qualcomm Incorporated | Method and apparatus of reducing transfer latency in an SOC interconnect |
| US8164936B2 (en) | 2009-10-14 | 2012-04-24 | Seagate Technology Llc | Switched memory devices |
| US8819309B1 (en) * | 2013-06-14 | 2014-08-26 | Arm Limited | Low latency bypass buffer |
| US9430434B2 (en) * | 2013-09-20 | 2016-08-30 | Qualcomm Incorporated | System and method for conserving memory power using dynamic memory I/O resizing |
| KR20160076195A (ko) | 2014-12-22 | 2016-06-30 | 에스케이하이닉스 주식회사 | 다수의 채널로 동작할 수 있는 적층 반도체 장치 |
| US10402110B2 (en) * | 2016-08-04 | 2019-09-03 | Rambus Inc. | Adjustable access energy and access latency memory system and devices |
| KR102395463B1 (ko) | 2017-09-27 | 2022-05-09 | 삼성전자주식회사 | 적층형 메모리 장치, 이를 포함하는 시스템 및 그 동작 방법 |
| US10546628B2 (en) * | 2018-01-03 | 2020-01-28 | International Business Machines Corporation | Using dual channel memory as single channel memory with spares |
| US20190294548A1 (en) * | 2018-03-21 | 2019-09-26 | Macom Technology Solutions Holdings, Inc. | Prefetch module for high throughput memory transfers |
| US10884958B2 (en) * | 2018-06-25 | 2021-01-05 | Intel Corporation | DIMM for a high bandwidth memory channel |
| US10770129B2 (en) | 2018-08-21 | 2020-09-08 | Intel Corporation | Pseudo-channeled DRAM |
| US10937518B2 (en) | 2018-12-12 | 2021-03-02 | Micron Technology, Inc. | Multiple algorithmic pattern generator testing of a memory device |
| US11194726B2 (en) | 2019-02-25 | 2021-12-07 | Micron Technology, Inc. | Stacked memory dice for combined access operations |
| US11308017B2 (en) * | 2019-05-31 | 2022-04-19 | Micron Technology, Inc. | Reconfigurable channel interfaces for memory devices |
| US12347818B2 (en) | 2021-03-26 | 2025-07-01 | Intel Corporation | Logic die in a multi-chip package having a configurable physical interface to on-package memory |
| US11893240B2 (en) | 2021-10-28 | 2024-02-06 | Qualcomm Incorporated | Reducing latency in pseudo channel based memory systems |
| US20230013181A1 (en) * | 2022-09-14 | 2023-01-19 | Intel Corporation | Method to implement half width modes in dram and doubling of bank resources |
-
2021
- 2021-10-28 US US17/452,606 patent/US11893240B2/en active Active
-
2022
- 2022-10-03 CN CN202280067430.8A patent/CN118056195A/zh active Pending
- 2022-10-03 KR KR1020247013125A patent/KR20240088958A/ko active Pending
- 2022-10-03 TW TW111137535A patent/TW202321896A/zh unknown
- 2022-10-03 JP JP2024520748A patent/JP2024542933A/ja active Pending
- 2022-10-03 EP EP22800417.2A patent/EP4423618A1/en active Pending
- 2022-10-03 WO PCT/US2022/045561 patent/WO2023075993A1/en not_active Ceased
-
2023
- 2023-12-04 US US18/527,713 patent/US12307092B2/en active Active
-
2025
- 2025-04-21 US US19/184,994 patent/US20250251862A1/en active Pending
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