JP2024504747A - Component carrier with identification markings - Google Patents

Abstract

A component carrier comprising a stack of at least four electrically insulating layer structures and at least five electrically conductive layer structures stacked one above the other in an alternating manner along the stacking direction, wherein one of the electrically conductive layer structures is one of the conductive layer structures of the stack. forming a first outer conductive layer, wherein another one of the conductive layer structures forms a second outer conductive layer of the stack, the first outer conductive layer and the second outer conductive layer being opposite sides of the stack; The outer layer is the component carrier. The component carrier has a first identification mark detectable by the detection device, wherein the first identification mark is formed on the conductive layer structure disposed proximate the first outer conductive layer. a second identification mark, wherein the second identification mark is formed in a conductive layer structure disposed proximate to the second outer conductive layer. The first identification mark and the second identification mark are formed above each other in the stacking direction.

Description

The present invention relates to a component carrier provided with identification marks.

In the context of the growing capability of manufactured products of component carriers comprising one or more components, and the increasing miniaturization of such components, as well as the increasing number of components connected to component carriers, such as printed circuit boards, Increasingly powerful array-like components or packages are employed that have multiple contacts or connections with progressively smaller spaces between the contacts. In particular, component carriers must be mechanically strong, electrically reliable and capable of operating under harsh conditions. More and more functions are being integrated within component carriers.

During the manufacture of complex component carriers such as printed circuit boards (PCBs), it is important to precisely and precisely position and rotate the component carriers. In order to align the component carrier, identification marks can be formed inside the layered structure of the component carrier. The identification mark can be measured by a respective detection device, such as an X-ray detector, where the respective alignment of the component carrier can be determined on the basis of a measured photograph of the identification mark.

However, when each layer comprising an identification mark is covered by a plurality of further layers during the manufacturing process, the photograph of the identification mark (eg, the contrast and contour of the identification mark photograph) becomes even more obscure.

Therefore, it may be necessary to provide identification marks that can be appropriately determined by a detection device to provide proper alignment of the component carrier.

According to an exemplary embodiment of the invention, a component carrier is described. The component carrier comprises a stack of at least four electrically insulating layer structures and at least five electrically conductive layer structures stacked on top of each other along the lamination direction in an alternating manner. One of the conductive layer structures forms a first outer conductive layer of the stack and another one of the conductive layer structures forms a second outer conductive layer of the stack, where the first outer conductive layer and the second outer conductive layer The outer conductive layer is the opposing outer layer of the stack.

The component carrier further comprises a first identification mark detectable by the detection device, wherein the first identification mark is formed on the conductive layer structure. In an exemplary embodiment, the first identification mark is formed on a conductive layer structure disposed proximate to the first outer conductive layer, and the second identification mark is detectable by a detection device, where the second The identification mark is formed on the conductive layer structure. In an exemplary embodiment, a second identification mark is formed in a conductive layer structure disposed proximate to the second outer conductive layer. The first identification mark and the second identification mark are formed above each other in the stacking direction.

According to an exemplary embodiment of the invention, a method of manufacturing the component carrier described above is described. The electrically insulating layer structure and at least five conductive layer structures are stacked in an alternating fashion above each other along the lamination direction, one of the conductive layer structures forming the first outer conductive layer of the stack, and one of the conductive layer structures forming the first outer conductive layer of the stack. Another one forms a second outer conductive layer of the stack, where the first outer conductive layer and the second outer conductive layer are opposing outer layers of the stack. Furthermore, a first identification mark detectable by the detection device is formed on the conductive layer structure. In an exemplary embodiment, a first identification mark is formed in a conductive layer structure disposed proximate to the first outer conductive layer. A second identification mark detectable by the detection device is formed on the conductive layer structure. In an exemplary embodiment, a second identification mark is formed in a conductive layer structure disposed proximate to the second outer conductive layer. The first identification mark and the second identification mark are formed above each other in the stacking direction.

In the context of this application, the term "component carrier" refers to any support structure capable of housing one or more components on and/or within it to provide mechanical support and/or electrical connectivity. In particular, it can be shown. In other words, the component carrier may be configured as a mechanical and/or electronic carrier of the component. In particular, the component carrier may be one of a printed circuit board, an organic interposer, a metal core substrate, an inorganic substrate, and an IC (integrated circuit) substrate. The component carrier may also be a hybrid board combining different of the above-mentioned types of component carriers.

In the context of the present application, the term "component carrier material" specifically refers to a connected configuration of one or more electrically insulating layer structures and/or one or more electrically conductive layer structures, as used in the technology of component carriers. can be shown. More particularly, such component carrier material may be a material used for printed circuit boards (PCBs) or IC boards. In particular, the electrically conductive material of such component carrier material may comprise copper. The electrically insulating material of the component carrier material may comprise a resin, in particular an epoxy resin, optionally combined with reinforcing particles, such as glass fibers or glass spheres.

In embodiments, the component carrier is a stacked component carrier. In such embodiments, the component carrier is a composite of multiple layers that are stacked and connected to each other by applying pressure and/or heat.

In embodiments, the at least one electrically insulating layer structure is made of epoxy resins, cyanate ester resins, benzocyclobutene resins, bismaleimide triazine resins, polyphenylene derivatives (e.g. based on polyphenylene ether, PPE), polyimide (PI), polyamide. (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), and/or combinations thereof. Reinforcing structures such as webs, fibers, spheres, or other types of filled particles, made of glass (multilayer glass), can also be used to form composite materials. Fibers impregnated with semi-cured resins, such as those mentioned above, in combination with reinforcing agents are called prepregs. These prepregs are often named after their properties, e.g. FR4 or FR5 refer to their flame retardant properties. Typically, prepregs, especially FR4, are preferred for rigid PCBs, but other materials may also be used, especially epoxy-based buildup materials (such as buildup films) or photoimageable dielectric materials. For high frequency applications, high frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and/or cyanate ester resins may be preferred. Besides these polymers, low temperature co-fired ceramics (LTCC) or other low, ultra-low, or ultra-low DK materials may be applied within the component carrier as electrically insulating structures.

In embodiments, the at least one conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten, and magnesium. Copper is usually preferred, but other materials or coatings thereof may also be used, particularly those coated with superconducting materials or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), respectively. It is possible.

The first identification mark and the second identification mark are formed above each other in the stacking direction. For this purpose, the stack can be formed of a plurality of electrically insulating layer structures and a plurality of conductive layer structures, wherein respective identification marks are formed in the conductive layer structures in separate spaces of the stack. If the first identification mark and the second identification mark are formed in a stacking direction above each other, a suitable picture of the alignment of the identification marks obtained by the detection device can be presented. In other words, the first identification mark and the second identification mark are formed on a projection plane with a projection normal parallel to the stacking direction in such a way that the identification mark and the further identification mark completely overlap each other.

An identification mark is formed in one of the conductive layer structures. In particular, with this approach, the identification marks are each formed in one of the conductive layer structures closest to the outer conductive layer. Therefore, it becomes easier for a detection device (eg x-ray) to detect the circumferential shape and orientation of the identification mark, respectively.

According to an exemplary embodiment, at least one of the first and second identification marks comprises an inner volume free of material of the conductive layer structure. For example, the inner volume of the identification mark is hollow, eg free of copper. In an exemplary embodiment, the inner volume of the identification mark is filled with an electrically insulating material. The electrically insulating material may resemble an electrically insulating layer structure laminated on top of the respective conductive layer structure, such as polypropylene (PP).

According to an exemplary embodiment, the identification mark has a triangular shape. Providing a triangular shape makes it easier to detect the orientation and alignment of the identification mark and component carrier, respectively.

According to a further exemplary embodiment, the identification mark has the shape of an arrow. By providing an arrow shape, it is easier to detect the orientation and alignment of the identification mark and the component carrier, respectively.

According to a further exemplary embodiment, the identification mark comprises three identification points forming a triangular shape, each identification point comprising an inner volume free of electrically conductive material. The orientation of the identification marks is also possible, for example by providing hollow points or contours (circles, ovals or rectangles), which are arranged with respect to each other in such a way that a specific direction can be determined. For example, three identification points may be formed at the corners of a virtual triangle.

According to a further exemplary embodiment, the identification mark is formed on the edge of one conductive layer structure.

According to a further exemplary embodiment, the identification mark is formed at a corner of one conductive layer structure.

According to a further exemplary embodiment, the first identification mark and said second identification mark have the same circumferential shape. For example, both identification marks, in particular the first identification mark and the second identification mark, have the shape of a triangle or are in the shape of an arrow.

According to a further exemplary embodiment, the second identification mark is filled with electrically conductive material. For example, the second identification mark comprises only a circumferential extension or path without conductive material. Therefore, the detection device detects only the circumferential path of the identification mark. However, the second identification mark with an inner volume devoid of conductive material and the identification mark described above are formed above each other, so that an overlay of both identification marks in the photograph obtained from the detection device and matching, respectively, may be detected.

According to a further exemplary embodiment, the second identification mark comprises an inner volume devoid of electrically conductive material.

According to a further exemplary embodiment, the component carrier further comprises a separate core layer, wherein the separate core layer comprises at least one electrically insulating layer structure and at least one conductive layer structure on one side and at least one electrically conductive layer structure on the other side. It is removably arranged between the at least one further electrically insulating layer structure and the at least one further electrically conductive layer structure.

Thus, on both opposite sides of the isolated core layer, respective stacks of conductive and electrically insulating layer structures can be formed layer by layer. A first identification mark and a second identification mark can be arranged in each conductive layer structure arranged on opposite sides of the separated core layer. After the respective stacked parts on either side of the separated core layer have been formed, the separated core layer can be removed (e.g. by applying heat or a chemical solution) and each of the two stacked parts can be separated into one common manufacturing/processing part. Can be formed during the lamination stage. By forming the first identification mark and the second identification mark, the orientation of each component carrier can be detected before and after removing the separation core layer.

In embodiments, the first identification mark is disposed proximate the first outer conductive layer and/or the second identification mark is disposed proximate the second outer conductive layer.

In embodiments, the component carrier further comprises a further first identification mark and/or a further second identification mark formed on each of the other conductive layer structures except for the first and second outer conductive layers.

In an embodiment, the component carrier further comprises a further identification mark detectable by the detection device, wherein the further identification mark is located in the respective vicinity of the first outer conductive layer or the second outer conductive layer. Formed into a conductive layer structure.

In an embodiment, the stack comprises a mirror surface parallel to the stacking direction, wherein the further identification mark is arranged on opposite sides with respect to the mirror surface with respect to the first identification mark.

In an embodiment, the stack comprises a mirror surface parallel to the stacking direction, wherein the further identification mark is arranged on the same side with respect to the mirror surface with respect to the second identification mark.

In an embodiment, the further identification mark comprises an inner volume free of conductive material.

In embodiments, further identification marks are formed on each of the other conductive layer structures except for the first and second outer conductive layers.

In an embodiment, the further identification mark comprises an inner volume free of conductive material.

In an embodiment, the further identification mark comprises a triangular shape.

In an embodiment, the further identification mark comprises the shape of an arrow.

In an embodiment, the further identification mark comprises three identification points forming a triangular shape, where each identification point comprises an inner volume free of electrically conductive material.

In embodiments, further identification marks are formed at the edges of one conductive layer structure.

In embodiments, further identification marks are formed at the corners of the conductive layer structure.

In an embodiment, the further identification mark, the first identification mark and/or the second identification mark have the same circumferential shape.

In embodiments, the further identification mark is filled with conductive material.

In an embodiment, the further identification mark comprises an inner volume free of conductive material.

In an embodiment, the component carrier is shaped as a plate. This contributes to a compact design, and the component carrier nevertheless provides a large base for installing components on it. Furthermore, by virtue of their small thickness, bare dies can advantageously be integrated into thin plates, such as printed circuit boards, particularly for embedded electronic components.

In embodiments, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (particularly an IC board), and an interposer.

In the context of the present application, the term "printed circuit board" (PCB) means a structure formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, e.g. by the application of pressure and/or the supply of thermal energy. A plate-shaped component carrier formed may be particularly shown. As preferred materials for PCB technology, the conductive layer structure is made of copper, while the electrically insulating layer structure can have resin and/or glass fibers, so-called prepreg or FR4 materials. Various conductive layer structures can be created by forming holes through the laminate, e.g. by laser drilling or mechanical drilling, and by partially or completely filling them with conductive material (in particular copper). They may be connected to each other in any desired manner by forming vias or any other through-hole connections. A filled hole connects the entire stack (through-hole connection extending through several layers or the entire stack) or a filled hole connects at least two conductive layers and is called a via. . Similarly, optical interconnects can be formed through the individual layers of the stack to receive electro-optic circuit boards (EOCBs). Apart from one or more components that may be embedded in the printed circuit board, the printed circuit board is typically configured to receive one or more components on one or both opposing sides of the plate-shaped printed circuit board. be done. They may be connected to their respective major surfaces by soldering. The dielectric portion of the PCB may be made of resin having reinforcing fibers (such as glass fibers).

In the context of this application, the term "substrate" may specifically mean a small component carrier. A substrate, with respect to a PCB, may be a relatively small component carrier on which one or more components may be attached and which may serve as a connection medium between one or more pieces and another PCB. For example, the substrate may have substantially the same size as the components (particularly electronic components) mounted thereon (eg, in the case of a chip scale package (CSP)). In more detail, a board can be understood as a carrier for electrical connections or electrical networks, and as a component carrier comparable to a printed circuit board (PCB), but with a density of horizontally and/or vertically arranged connections. It will be quite expensive. The lateral connection may be, for example, a conductive track, and the longitudinal connection may be, for example, a drilled hole. These lateral and/or vertical connections are arranged within the substrate to provide electrical and thermal connections between contained or non-contained components (such as bare die), especially IC chips, with printed circuit boards or intermediate printed circuit boards. It may be used to provide physical and/or mechanical connections. Therefore, the term "substrate" also includes "IC substrate." The dielectric part of the substrate may be composed of a resin with reinforcing particles (such as reinforcing spheres, especially glass spheres).

The substrate or interposer can be at least a photoimageable or dry-etchable organic material such as glass, silicon (Si), and/or epoxy-based build-up materials (such as epoxy-based build-up films), or polyimide or polybenzene. It may have or consist of a layer of polymeric compounds, such as oxazole, which may or may not contain photo- and/or heat-sensitive molecules.

The at least one component may be embedded in the component carrier and/or be a surface mounted to the component carrier. Such components include non-conductive inlays, conductive inlays (such as metal inlays, preferably comprising copper or aluminum), heat transfer units (for example heat pipes), light guiding elements (for example optical waveguides or light guide connections). , electronic components, or a combination thereof. The inlay can be, for example, a metal block with or without an insulating material coating (IMS inlay) and can be embedded or surface mounted for the purpose of promoting heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W/mK. Such materials are often based on metals, metal oxides, and/or ceramics, such as, but not limited to, copper, aluminum oxide (Al2O3), or aluminum nitride (AlN). Other geometries with increased surface area are also often used to improve heat exchange capabilities. Additionally, the component may be an active electronic component (implementing at least one pn connection), a passive electronic component, such as a resistor, an inductance, or a capacitor, an electronic chip, a storage device (such as a DRAM or another data memory). , filters, integrated circuits (e.g. field programmable gate arrays (FPGAs), programmable array logic (PALs), generic array logic (GALs), and complex programmable logic devices (CPLDs)), signal processing components, power management components (e.g. electric field effect transistor (FET), metal oxide semiconductor field effect transistor (MOSFET), complementary metal oxide semiconductor (CMOS), junction field effect transistor (JFET), or insulated gate field effect transistor (IGFET), silicon carbide (SiC) ), all based on semiconductor materials such as gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), and/or any other suitable inorganic compound ), optoelectronic interface elements, light emitting diodes, optocouplers, voltage converters (e.g. DC/DC converters or AC/DC converters), cryptographic components, transmitters and/or receivers, electromechanical transducers, sensors, actuators, microelectronics It may be a mechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductance, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may be embedded in the component carrier. For example, it can be used as a magnetic element component. Such magnetic elements may be permanent magnetic elements (such as ferromagnetic, antiferromagnetic, multiferroic or ferrimagnetic elements, such as ferrite cores), or they may be paramagnetic elements. However, the component may also be an IC substrate, an interposer or a further component carrier, for example in a board-in-board configuration. The components may be surface mounted to and/or embedded within the component carrier. Furthermore, other components may also be used as components, in particular other components that generate and emit electromagnetic radiation and/or are sensitive to electromagnetic radiation propagating from the environment.

After processing the internal layer structure of the component carrier, one or both opposing major surfaces of the treated layer structure can be coated symmetrically or asymmetrically with one or more further electrically insulating and/or conducting layer structures ( Specifically, it can be covered (by lamination). In other words, the build-up may continue until the desired number of layers is obtained.

After the formation of the stack of electrically insulating and conductive layer structures has been completed, it is possible to proceed with the surface treatment of the resulting layer structure or component carrier.

In particular, electrically insulating solder resists may be applied to opposing major surfaces of one or both of the layer stack or the component carrier with respect to surface treatment. For example, forming such a solder resist over the entire major surface and subsequently patterning a layer of solder resist to form one or more conductive surfaces to be used to electrically couple the component carrier to peripheral electronics. It is possible to expose parts. The surface parts of the component carrier that remain covered with solder resist may be effectively protected against oxidation or corrosion, especially the copper-containing surface parts.

Regarding the surface treatment, it is also possible to selectively apply a surface finish to the exposed electrically conductive surface portions of the component carrier. Such a surface finish may be a conductive cover material on exposed conductive layer structures (such as pads, conductive tracks, etc., in particular comprising or consisting of copper) on the surface of the component carrier. If such exposed conductive layer structures are left unprotected, the exposed conductive component carrier material (especially copper) can oxidize, reducing the reliability of the component carrier. A surface finish may then be formed, for example, as an interface between the surface mount component and the component carrier. The surface finish has the function of protecting the exposed conductive layer structure (in particular the copper circuit) and allowing a joining process with one or more components, for example by soldering. Examples of suitable materials for surface finishing are organic solderability preservatives (OSP), Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Immersion, Electroless Palladium, Electroless Nickel Immersion Palladium Immersion Gold (ENIPIG), gold (especially hard gold), chemical tin, nickel gold, nickel palladium, etc.

The aspects defined above and further aspects of the invention are evident from the examples of embodiment described below and are explained with reference to these examples of embodiment.

1 shows a schematic diagram of a conventional component carrier with conventional identification markers; FIG.

1 shows a schematic diagram of a component carrier with a separate core layer and identification marks according to an example embodiment; FIG.

1 shows a schematic diagram of a component carrier with three identification marks, according to an example embodiment; FIG.

2 shows a schematic diagram of a component carrier with three identification marks arranged above each other along the stacking direction, according to an exemplary embodiment; FIG.

2 shows a schematic diagram of an identification mark in the form of an arrow, according to an exemplary embodiment; FIG.

Figure 3 shows a schematic diagram of an identification mark formed by three dots, according to an exemplary embodiment;

The illustrations in the drawings are schematic representations. Similar or identical elements in different drawings are given the same reference symbols.

FIG. 1 shows a schematic diagram of a conventional component carrier 1000 with conventional identification markers 1001, 1002.

A conventional component carrier 1000 comprises a stack 101 of electrically insulating layer structures 102 and conductive layer structures 103, 106 made of electrically insulating material and stacked in a stacking direction 104 above each other in an alternating manner.

The conventional identification mark 1001 is formed in a triangular shape in the conductive layer structure 103 (upper layer L6, inner pattern mirror). A further conventional identification mark 1002 is formed in the conductive layer structure 106 (lower layer L6) in the shape of a triangle. Identification markers 1001, 1002 are filled with conductive material. Both conventional identification marks 1001 and 1002 are not arranged above each other along the stacking direction 104, but are offset with respect to each other along the stacking direction 104. Furthermore, the conventional identification marks 1001, 1002 are mirror symmetrical and have the same pattern on the upper layer L6 and the lower layer L6. A (eg x-ray) detection device acquires each photograph 110 and detects the shape of the circumference and the orientation of the identification mark 107, respectively.

The outer covering conductive layer structure 103, 106 (L7) can be a copper foil carrier which can have a thickness between 3 μm and 18 μm. Due to the thick overlying conductive layer structure 103, 106 (L7), it influences the contrast of the photograph 110 of the detection device (for example an x-ray detection device). Even by adjusting the x-ray light source and contrast in each photograph 110, the triangular identification markers 1001, 1002 on both sides, which were oriented in different directions before core separation, affect the orientation identification. .

FIG. 2 shows a schematic diagram of a component carrier 100 with a separate core layer 109 and identification marks 107, 108, according to an exemplary embodiment.

The component carrier 100 comprises a stack 101 of four electrically insulating layer structures 102 and at least one conductive layer structure 103, 106 made of electrically conductive material, stacked in an alternating manner above each other along a stacking direction 104. . One of the conductive layer structures 103, 106 forms the first outer conductive layer 111 of the stack 101 and another one of the conductive layer structures 103, 106 forms the second outer conductive layer 112 of the stack 101, where First outer conductive layer 111 and second outer conductive layer 112 are opposing outer layers of stack 101 . The first identification mark 107 is formed so as to be detectable by a detection device. A first identification mark 107 is formed in the conductive layer structure 103 located closest to the first outer conductive layer 111 . Additionally, further first identification marks 107 and/or second identification marks 108 may also be formed in each of the other conductive layer structures 103, 106, excluding the outer conductive layers 111, 112.

Additionally, a second identification mark 108 is detectably formed by a detection device, where the second identification mark 108 is formed in the conductive layer structure 106 disposed proximate to the second outer conductive layer 112 . The first identification mark 107 and the second identification mark 108 are formed above each other in the stacking direction 104.

The first identification mark 107 and/or the second identification mark 108 comprises an inner volume free of conductive material. The identification marks 107, 108 extend along the plane of the respective conductive layer structure 103, 106 and have respective normals parallel to the normal of the plane of the respective conductive layer structure 103, 106.

In order to show the shape of the identification marks 107, 108 in the figure, the identification marks 107, 108 in the figure are shown tilted by 90°. Furthermore, conductive layers 103 and 106 are represented by layer numbers L4 to L8.

The identification marks 107, 108 are formed at least on one of the conductive layer structures 103, 106 (layer L6, mirror of the inner pattern) closest to the outer conductive layers 111, 112, respectively. In particular, for example, the identification mark 107 comprises an inner volume free of material of the conductive layer structure. For example, the inner volume of the identification mark 107 is hollow, eg, free of copper. The electrically insulating material may be similar to the electrically insulating layer structure 102 laminated on top of each conductive layer structure 103 . A (eg x-ray) detection device acquires each photograph 110 and detects the shape of the circumference and the orientation of the identification mark 107, respectively.

Covering the conductive layer structure 103, 106 (L7) can be a copper foil, which can have a thickness between 3 μm and 18 μm.

The first identification mark 107 and the second identification mark 108 are formed above each other in the stacking direction 104. As such, the stack 101 may be formed of a plurality of electrically insulating layer structures 102, 105 and a plurality of conductive layer structures 103, 106, where in the conductive layer structures 103, 106 in separate spaces of the stack 101, respective identification Marks 107 and 108 are formed. If the first identification mark 107 and the second identification mark 108 are formed above each other in the stacking direction 104, a suitable picture 110 of the alignment of the identification marks 107, 108 obtained by the detection device can be presented.

The identification marks 107, 108 have the same triangular shape in the example shown. In other words, the first identification mark 107 and the second identification mark 108 are completely aligned with each other on a projection plane having a projection normal parallel to the stacking direction 104. formed in an overlapping manner.

The component carrier 100 further comprises a separate core layer 109, where the separate core layer 109 is located between the central conductive layer structure 103 (L5) on one side and the further conductive layer structure 106 (L5) on the other side. It is removably placed in the. On both opposite sides of the isolated core layer 109, respective stack parts of the stack 101 made of the conductive layer structure 103, 106 and the electrically insulating layer structure 102, 105 can be formed layer by layer. A first identification mark 107 and a second identification mark 108 can be formed in each conductive layer structure 103 , 106 arranged on opposite sides of the isolated core layer 109 . After the respective stacks on either side of the isolated core layer 109 are formed, the isolated core layer 109 can be removed so that the two stacks can be formed in one common manufacturing/lamination step. By forming the identification marks 107 and 108, the orientation of each component carrier 100 can be detected before and after the separation core layer 109 is removed.

In FIG. 2, the three conductive layer structures 103, 106 (L5, L6, and L7) are layers of copper. The identification marks 107, 108 are formed in the conductive layer structure L6, since a patterning process is carried out in these layer structures L6, and the identification marks 107, 108 can be formed in such a respective patterning process. In the conductive layer structures 103, 106 closest to the isolated core layer 109, ie, L5, and the upper outer conductive layers 111, 112, ie, L7, no patterning process is accomplished prior to separation from the isolated core layer 109.

FIG. 3 shows a schematic diagram of a component carrier 100 with three identification marks 107, 301, according to an exemplary embodiment. Stack 101 comprising conductive layer structures L5, L6, and L7 is a flip stack portion of the upper portion of stack 101 of FIG. The first identification mark 107 is the same as the first identification mark 107 of FIG. 2, which may be formed in the conductive layer structure 103 (L6) before being separated from the isolated core layer 109, but The third identification mark 301 is a further mark formed in the conductive layer structures L5 and L7 after separation. The third identification mark 301 can have the same outline, for example a triangular outline, and is formed above each other in the stacking direction 104 and is similar to the first and second identification marks 107, 108 shown in FIG. . The stack 101 comprises a mirror surface 201 parallel to the stacking direction 104, where a further identification mark 301 is arranged on an opposite side with respect to the mirror surface 201 with respect to the first identification mark 107.

The component carrier 100 shown in FIG. 3 can be formed by laminating further electrically insulating layer structures 102, 105 and a further outer conductive layer 302 (L4, L8) on top of the outer conductive layer 111 (L5, L7). The identification mark 107 is located on the right side due to the flip of the upper stack part in FIG. 2 and is still formed in the conductive layer structure 103 (L6) now in the center of the stack 101. Therefore, although the central identification mark 107 is hardly visible in the photograph 110 of the detection device, the additional further identification mark 301 is located closest to the further outer conductive layer 302 (L4, L8) and thus to the surface of the stack 101. A conductive layer structure 103, 106 (L5, L7) is formed. Therefore, further representation of the shape of the identification mark 301 in the photograph 110 of the detection device is possible. The further identification mark 301 may comprise an inner volume devoid of electrically conductive material. Additionally, further identification marks 301 may also be formed on each of the other conductive layer structures 103, 106 except for the outer conductive layers 111, 112.

FIG. 4 shows a schematic diagram of a component carrier comprising three identification marks 108, 301 arranged above each other along the stacking direction 104, according to an exemplary embodiment. The component carrier 100 shown in FIG. 4 can be formed by laminating further electrically insulating layer structures 102, 105 and further outer conductive layers 302 (L4, L8) on top of outer conductive layers 112 (L5, L7).

The stack 101 comprising the conductive layer structures L5, L6 and L7 is the stack part of the lower part of the stack 101 of FIG. The second identification mark 108 is the same as the second identification mark 108 of FIG. 2, which may be formed on the conductive layer structure 103 (L6) before being separated from the isolated core layer 109, but The third identification mark 301 is a further mark formed in the conductive layer structures L5 and L7 after separation. The third identification mark 301 can have the same outline, for example a triangular outline, and is formed above each other in the stacking direction 104 and is similar to the first and second identification marks 107, 108 shown in FIG. . The stack 101 comprises a mirror surface 201 parallel to the stacking direction 104, where the further identification mark 301 is arranged on the same side with respect to the mirror surface 201 with respect to the second identification mark 108. Additionally, further identification marks 301 may also be formed on each of the other conductive layer structures 103, 106 except for the outer conductive layers 111, 112.

The second identification mark 108 and the third identification mark 301, having an inner volume free of conductive material, are formed above each other and overlay and overlay all the identification marks 108, 301 of the photograph 110 acquired by the detection device. Each match may be detected.

FIG. 5 shows a schematic diagram of a first identification mark 107 in the form of an arrow, according to an exemplary embodiment. The first identification mark 107 has the shape of an arrow. The second and third identification marks 108, 301 may also have respective shapes.

FIG. 6 shows a schematic diagram of an identification mark 107 formed by three dots, according to an exemplary embodiment. The three discrimination points form a triangular shape, where each discrimination point comprises an inner volume free of conductive material. For example, three identification points may be formed at the corners of a virtual triangle to form the identification mark 107. The second and third identification marks 108, 301 may also have respective shapes.

Note that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. Also, elements described in connection with different embodiments may be combined.

It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.

The implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, numerous variants are possible using the solution presented and the principles according to the invention, even in the case of radically different embodiments.

100 component carrier 101 stack 102 electrically insulating layer structure 103 electrically conductive layer structure 104 stacking direction 105 further electrically insulating layer structure 106 further electrically conductive layer structure 107 identification mark 108 second identification mark 109 separating core layer 110 radiograph 111 first outer side Conductive layer 112 Second outer conductive layer 201 Mirror surface 301 Third, further identification mark 302 Further outer conductive layer

Claims (33)

a stack of at least four electrically insulating layer structures and at least five conductive layer structures stacked on top of each other along the stacking direction in an alternating manner;
one of the conductive layer structures forming a first outer conductive layer of the stack and another one of the conductive layer structures forming a second outer conductive layer of the stack;
wherein the first outer conductive layer and the second outer conductive layer are opposing outer layers of the stack;
a first identification mark detectable by a detection device;
wherein the first identification mark is formed on a conductive layer structure;
a second identification mark detectable by a detection device;
wherein the second identification mark is formed on a conductive layer structure;
wherein the first identification mark and the second identification mark are formed above each other in the stacking direction;
Component carrier. the first identification mark comprises an inner volume free of conductive material;
Component carrier according to claim 1. the first identification mark has a triangular shape;
Component carrier according to claim 2. the first identification mark has an arrow shape;
Component carrier according to claim 2. the first identification mark comprises three identification points forming a triangular shape;
each identification point comprising an inner volume free of said electrically conductive material;
Component carrier according to claim 2. the first identification mark is formed on an edge of the one conductive layer structure;
Component carrier according to any one of claims 2 to 5. the first identification mark is formed at a corner of the one conductive layer structure;
Component carrier according to any one of claims 2 to 5. the first identification mark and the second identification mark have the same circumferential shape;
Component carrier according to any one of claims 1 to 7. the second identification mark is filled with a conductive material;
Component carrier according to claim 1. the second identification mark comprises only a circumferential path without conductive material;
Component carrier according to claim 9. the second identification mark comprises an inner volume free of conductive material;
Component carrier according to any one of claims 1 to 8. The component carrier is
Further comprising a separate core layer,
wherein said separating core layer comprises said at least one electrically insulating layer structure and said at least one electrically conductive layer structure on one side and said at least one further electrically insulating layer structure and at least one further electrically conductive layer structure on the other side. Detachably placed between the
Component carrier according to any one of claims 1 to 11. the first identification mark is located closest to the first outer conductive layer, and/or the second identification mark is located closest to the second outer conductive layer;
Component carrier according to any one of claims 1 to 12. The component carrier is
Claim further comprising: a further first identification mark and/or a further second identification mark formed on each of the other conductive layer structures except for the first outer conductive layer and the second outer conductive layer. 14. Component carrier according to any one of 1 to 13. The component carrier is
further comprising further identification marks detectable by a detection device;
wherein said further identification mark is formed on the respective conductive layer structure disposed closest to said first outer conductive layer or said second outer conductive layer;
Component carrier according to any one of claims 1 to 14. The stack has a mirror surface parallel to the stacking direction,
wherein the further identification mark is arranged on opposite sides with respect to the mirror surface with respect to the first identification mark;
Component carrier according to claim 15. The stack has a mirror surface parallel to the stacking direction,
wherein the further identification mark is arranged on the same side with respect to the mirror surface with respect to the second identification mark;
Component carrier according to claim 15. the further identification mark comprises an inner volume free of electrically conductive material;
Component carrier according to any one of claims 15 to 17. further identification marks are formed on each of the other conductive layer structures except for the first outer conductive layer and the second outer conductive layer;
Component carrier according to any one of claims 15 to 18. the further identification mark comprises a triangular shape;
Component carrier according to any one of claims 15 to 19. the further identification mark has the shape of an arrow;
Component carrier according to any one of claims 15 to 19. said further identification mark comprising three identification points forming a triangular shape;
each identification point comprising an inner volume free of conductive material;
Component carrier according to any one of claims 15 to 19. the further identification mark is formed on an edge of the one conductive layer structure;
Component carrier according to any one of claims 15 to 18. the further identification mark is formed at a corner of the conductive layer structure;
Component carrier according to any one of claims 15 to 18. the further identification mark, the first identification mark and/or the second identification mark have the same circumferential shape;
Component carrier according to any one of claims 15 to 24. the further identification mark is filled with a conductive material;
Component carrier according to any one of claims 15 to 17. The first identification mark and the second identification mark are arranged in such a manner that the first identification mark and the second identification mark completely overlap each other on a projection plane having a projection normal parallel to the lamination direction. It is formed,
Component carrier according to any one of claims 1 to 26. the first outer conductive layer and/or the second outer conductive layer covering the stack is in particular a copper foil with a thickness between 3 μm and 18 μm;
Component carrier according to any one of claims 1 to 27. forming a stack of at least four electrically insulating layer structures and at least five conductive layer structures stacked on top of each other along the stacking direction in an alternating manner;
one of the conductive layer structures forming a first outer conductive layer of the stack and another one of the conductive layer structures forming a second outer conductive layer of the stack;
wherein the first outer conductive layer and the second outer conductive layer are opposing outer layers of the stack;
providing a first identification mark detectable by a detection device;
forming the first identification mark on a conductive layer structure;
providing a second identification mark detectable by a detection device; and forming the second identification mark in a conductive layer structure.
wherein the first identification mark and the second identification mark are formed above each other in the stacking direction;
A method of manufacturing a component carrier comprising: forming a separate core layer;
wherein said separating core layer comprises said at least one electrically insulating layer structure and said at least one electrically conductive layer structure on one side and at least one further electrically insulating layer structure and at least one further electrically conductive layer structure on the other side. Detachably placed between
30. The method of claim 29, further comprising: 31. The method of claim 30, further comprising: detecting the orientation of each of the component carriers before and after removing the separation core layer by forming the first identification mark and the second identification mark. . 31. The method of claim 30, wherein the second identification mark is formed on the conductive layer structure before being separated from the separation core layer. forming a further identification mark detectable by a detection device;
wherein said further identification mark is formed in a respective conductive layer structure disposed proximate to said first outer conductive layer or said second outer conductive layer;
wherein said further identification mark is a further mark formed in said conductive layer structure after separation from said separation core layer;
33. The method of claim 32, further comprising:

Images