JP2024086885A - Semiconductor Device - Google Patents

Abstract

To provide a transistor which includes an oxide semiconductor and can operate at high speed, or to provide a highly reliable semiconductor device which includes the transistor.
An oxide semiconductor layer including a pair of low-resistance regions and a channel formation region is provided over an electrode layer embedded in a groove of a base insulating layer. The channel formation region is formed at a position overlapping with a gate electrode layer having sidewalls on its side walls. The groove has a deep region and a shallow region, the sidewalls overlap with the shallow region, and a connection to a wiring overlaps with the deep region.
[Selected Figure] Figure 1

Description

The present invention relates to a technology for miniaturizing semiconductor integrated circuits.
Elements constituting semiconductor integrated circuits include elements formed of compound semiconductors in addition to silicon semiconductors, and the present invention relates to a semiconductor device using an oxide semiconductor as one example, and a manufacturing method thereof.

In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all classified as semiconductor devices.

In recent years, semiconductor devices have been developed and are used as LSIs, CPUs, and memories.
A CPU has a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer, and is an assembly of semiconductor elements on which electrodes serving as connection terminals are formed.

2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as components of various electronic devices.

Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors used in semiconductor circuits. For example, Patent Document 1 proposes a structure in which the distance between a channel formation region and a contact portion is shortened to reduce the resistance between them in order to achieve high integration.

In addition to silicon, oxide semiconductors are also attracting attention as materials other than silicon. For example,
Patent Documents 2 and 3 disclose techniques in which a transistor is manufactured using zinc oxide or an In--Ga--Zn-based oxide as an oxide semiconductor and used as a switching element of a pixel of a display device.

JP 2004-327617 A JP 2007-123861 A JP 2007-96055 A

One object of the present invention is to realize miniaturized transistors by shortening the channel length L of transistors used in semiconductor integrated circuits such as LSIs, CPUs, and memories, thereby increasing the operating speed of circuits and reducing power consumption.

An object of one embodiment of the present invention is to provide a transistor which includes an oxide semiconductor and can operate at high speed and a manufacturing method thereof. Another object is to provide a highly reliable semiconductor device which includes the transistor and a manufacturing method thereof.

By removing impurities that serve as electron donors (donors) in an oxide semiconductor, a transistor in which a channel formation region is formed in an oxide semiconductor that is an intrinsic or substantially intrinsic semiconductor and has a larger energy gap than a silicon semiconductor is used to manufacture a semiconductor integrated circuit such as an LSI, a CPU, or a memory.

Contact resistance occurs between the oxide semiconductor and the conductive layer, and in order to reduce the contact resistance, it is necessary to ensure a sufficient contact area.

Thus, a conductive layer in contact with the upper surface of the oxide semiconductor layer and a conductive layer in contact with the lower surface of the oxide semiconductor layer are provided to ensure a sufficient contact area, thereby reducing contact resistance.

One embodiment of the present invention disclosed in this specification is a semiconductor device including: a semiconductor substrate; an insulating layer over the semiconductor substrate; an oxide semiconductor layer over the insulating layer; a gate insulating layer over the oxide semiconductor layer; a gate electrode layer over the gate insulating layer overlapping with the oxide semiconductor layer; a sidewall on a side surface of the gate electrode layer; a groove having a deep region and a shallow region in the insulating layer; and a conductive region in the groove, where the sidewall overlaps with the shallow region.

In the above structure, another feature is that the conductive layer is in contact with the sidewall and the oxide semiconductor layer.

In the above structure, it is also one of the features that an interlayer insulating layer is further provided on the gate electrode layer, and a wiring is provided on the interlayer insulating layer, the wiring overlapping the conductive region and being electrically connected to the deep region.

In the above structure, it is also one of the features that the conductivity type region has a shallow region having a first width in the channel length direction and a deep region having a second width in the channel length direction.

Moreover, a so-called MCP (Multi Chip Package) may be used, which is a package in which a plurality of semiconductor integrated circuits are mounted to increase the integration of the semiconductor device.

Furthermore, when mounting a semiconductor integrated circuit on a circuit board, it may be in a face-up configuration or a flip-chip configuration (face-down configuration).

The present invention also provides a manufacturing method of a semiconductor device, which includes the steps of forming a first insulating film over a first electrode layer, performing a first planarization treatment to expose an upper surface of the first electrode layer, forming a second electrode layer in contact with an upper surface of the first electrode layer, forming a second insulating film over the second electrode layer, performing a second planarization treatment to expose an upper surface of the second electrode layer, forming an oxide semiconductor film in contact with an upper surface of the second electrode layer, forming a gate insulating layer over the oxide semiconductor film, forming a gate electrode layer and an insulating film covering an upper surface of the gate electrode layer on the gate insulating layer, forming a sidewall that overlaps with the second electrode layer and is in contact with a side surface of the gate electrode layer, forming a conductive film that covers the gate electrode layer and the sidewall and is in contact with the oxide semiconductor film, and performing a third planarization treatment to remove a part of the conductive film overlapping with the gate electrode layer.

When the channel length L of a transistor used in a semiconductor integrated circuit such as an LSI, a CPU, or a memory is shortened, the contact resistance of an oxide semiconductor layer is reduced, thereby increasing the operating speed of the circuit and further reducing power consumption.

1A and 1B are examples of a cross-sectional view and a top view illustrating one embodiment of the present invention. 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. 1A to 1C are cross-sectional views showing a process of one embodiment of the present invention. 1A to 1C are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 1 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device.

Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that the form and details of the present invention can be modified in various ways. Furthermore, the present invention is not to be interpreted as being limited to the description of the embodiments shown below.

(Embodiment 1)
1A and 1B are a cross-sectional view and a top view of a transistor 420 as an example of a semiconductor device. FIG. 1A is a cross-sectional view of the transistor 420.
1B) along XY in FIG. 1B. Note that in FIG. 1B, some components of the transistor 420 (for example, an insulating film 407, an insulating film 410, an interlayer insulating film 415, and the like) are omitted for simplicity.

A transistor 420 illustrated in FIGS. 1A and 1B includes, over a substrate 400 having an insulating surface, a base insulating layer 436; electrode layers 425a and 425b which are embedded in the base insulating layer 436 and have at least a part of their upper surfaces exposed from the base insulating layer 436; an oxide semiconductor layer 403 including a pair of low-resistance regions 404a and 404b and a channel formation region 409 sandwiched between the low-resistance region 404a and the low-resistance region 404b; a gate insulating layer 402 provided on the oxide semiconductor layer 403; a gate electrode layer 401 provided on the channel formation region 409 with the gate insulating layer 402 interposed therebetween; and a sidewall insulating layer 412 provided on a side surface of the gate electrode layer 401.
a, 412b, an insulating film 413 provided on the gate electrode layer 401, and a source electrode layer 40
An insulating film 410 is provided on the drain electrode layer 405a and the drain electrode layer 405b, an interlayer insulating film 415 is provided on the insulating film 410, an insulating film 407 is provided on the interlayer insulating film 415, and an insulating film 407 is provided on the insulating film 405b.
07, the source electrode layer 40 is formed through an opening provided in the interlayer insulating film 415 and the insulating film 410.
5a and a second wiring layer 465b electrically connected to the drain electrode layer 405a and the drain electrode layer 405b, respectively.

The interlayer insulating film 415 is provided to flatten unevenness caused by the transistor 420.
The height of the upper surface is approximately the same as that of the sidewall insulating layers 412a and 412b and the insulating film 410. The sidewall insulating layers 412a and 412b are also called sidewalls.
12b and the top surface of the insulating film 413, and is higher than the top surface of the gate electrode layer 401. Note that the "height" referred to here means the height from the top surface of the substrate 400.

1, the electrode layers 425a and 425b are formed to fill a groove having a deep region and a shallow region in the base insulating layer 436.
The first wiring layer 465a and the second wiring layer 465b are formed at positions overlapping with the deep region.

In addition, in FIG. 1, the insulating film 407 is provided in contact with the interlayer insulating film 415 , the source electrode layer 405 a , the drain electrode layer 405 b , the sidewall insulating layers 412 a and 412 b , the insulating film 413 , and the insulating film 410 .

Note that a dopant is introduced into the oxide semiconductor film 403 in a self-aligned manner by using the gate electrode layer 401 as a mask, so that low-resistance regions 404a and 404b containing the dopant and having lower resistance than the channel formation region 409 are formed in the oxide semiconductor film 403 with the channel formation region 409 sandwiched therebetween. The dopant is an impurity which changes the conductivity of the oxide semiconductor film 403. The dopant can be introduced by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like.

The oxide semiconductor film 403 includes low-resistance regions 404 a and 404 b sandwiching a channel formation region 409 in the channel length direction, and the source electrode layer 40
5a and the drain electrode layer 405b, and the electrode layer 4
By including the gate insulating layer 425a and the electrode layer 425b, the transistor 420 has high on-state characteristics (eg, on-state current and field-effect mobility) and can operate at high speed and respond at high speed.

The oxide semiconductor used for the oxide semiconductor film 403 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that the oxide semiconductor contains In and Zn. In addition to the oxide semiconductor, the oxide semiconductor preferably contains gallium (Ga) as a stabilizer for reducing oxygen vacancies in the oxide semiconductor. Furthermore, it is preferable that the oxide semiconductor contains tin (Sn) as a stabilizer. Furthermore, it is preferable that the oxide semiconductor contains hafnium (Hf
) as a stabilizer. Also, it is preferable to have aluminum (Al) as a stabilizer. Also, it is preferable to have zirconium (Zr) as a stabilizer.

Other stabilizers include lanthanides such as lanthanum (La) and cerium (
The element may have one or more of the following: arsenic (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

Examples of oxide semiconductors include indium oxide, tin oxide, zinc oxide, In-Zn oxides, which are oxides of binary metals, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides, which are oxides of ternary metals (also referred to as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, and In-Gd-Zn oxides.
In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I
n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In
-Lu-Zn oxides, In-Sn-Ga-Zn oxides which are oxides of quaternary metals, I
n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-
Zn-based oxides, In--Sn--Hf--Zn-based oxides, and In--Hf--Al--Zn-based oxides can be used.

In addition, for example, an In-Ga-Zn oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn does not matter.
Metal elements other than a and Zn may be present.

In addition, the oxide semiconductor may be InMO ₃ (ZnO) _m (m>0, and m is not an integer).
In addition, M represents one or more metal elements selected from Ga, Fe, Mn, and Co. In addition, as _the oxide _{semiconductor} , a material represented by the formula:
A material expressed as (ZnO) _n (n>0, and n is an integer) may be used.

For example, In:Ga:Zn=1:1:1 (=1/3:1/3:1/3), In:Ga:Z
n=2:2:1 (=2/5:2/5:1/5), or In:Ga:Zn=3:1:2
In-Ga-Zn oxides having an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/6:1/3) or oxides having a similar composition can be used.
In-Sn with an atomic ratio of In:Sn:Zn=2:1:3 (=1/3:1/3:1/6:1/2) or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8)
It is preferable to use a -Zn-based oxide or an oxide having a composition close to that.

However, the present invention is not limited to these, and an appropriate composition may be used depending on the required semiconductor characteristics (mobility, threshold value, variation, etc.) In order to obtain the required semiconductor characteristics, it is preferable to appropriately select the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic bond distance, density, etc.

For example, high mobility can be obtained relatively easily in In--Sn--Zn oxides, but mobility can also be increased in In--Ga--Zn oxides by lowering the bulk defect density.

For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c (a+b+
The composition of the oxide in which the atomic ratio is In:Ga:Zn=A:B:C (A+B+C
= 1), a, b, and c are (a-A) ² + (b-B
) ² + (c−C) ² ≦r ² is satisfied. For example, r may be set to 0.05. The same applies to other oxides.

The oxide semiconductor film 403 is in a single crystal, polycrystalline (also referred to as polycrystalline), amorphous, or the like.

Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr
The film is a crystalline oxide semiconductor film.

Here, CAAC (C-Axis Aligned Crystal) refers to a mixed phase structure of crystal and amorphous in which the c-axis is oriented in a direction perpendicular to the surface on which the oxide semiconductor film is formed or the surface thereof, has a triangular or hexagonal atomic arrangement as viewed from a direction perpendicular to the a-b plane, and has metal atoms arranged in layers or metal atoms and oxygen atoms arranged in layers as viewed from a direction perpendicular to the c-axis. Note that the directions of the a-axis and b-axis of each of the CAACs in this mixed phase structure may be different from each other.

CAAC Oxide Semiconductor (CAAC-OS: C Axis Aligned Crystal
The CAAC-OS film is an oxide semiconductor film having a crystalline-amorphous mixed phase structure. The size of the crystals is estimated to be about several nm to several tens of nm.
According to observation using a transmission electron microscope (M), the boundary between the amorphous portion and the CAAC portion in the CAAC-OS film is not necessarily clear.
Furthermore, no crystal grain boundaries are found in the CAAC-OS film. Since the CAAC-OS film does not have crystal grain boundaries, a decrease in electron mobility due to crystal grain boundaries is unlikely to occur.

Note that in a CAAC-OS film, the distribution of crystalline regions in the film does not necessarily have to be uniform.
For example, when crystals grow from the surface side of the CAAC-OS film, the proportion of crystals in the vicinity of the surface of the CAAC-OS film may be high, and the proportion of amorphous material in the vicinity of the surface where the CAAC-OS film is formed may be high.

Since the c-axis of the crystalline portion of the CAAC faces in a direction perpendicular to the surface or the surface on which the CAAC-OS film is formed, the direction of the c-axis may differ depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface or the cross-sectional shape of the surface on which the CAAC-OS film is formed). Note that the c-axis of the crystalline portion of the CAAC faces in a direction approximately perpendicular to the surface or the surface on which the CAAC-OS film is formed. The CAAC is formed by performing a crystallization treatment such as a heat treatment simultaneously with or after the film formation.

By using the CAAC-OS film, change in electrical characteristics of a transistor due to irradiation with visible light or ultraviolet light can be reduced; therefore, a highly reliable transistor can be obtained.

Note that some of the oxygen constituting the oxide semiconductor film may be replaced with nitrogen.

The thickness of the oxide semiconductor film 403 is 1 nm to 30 nm (preferably, 5 nm to 10 nm).
m or less), and sputtering method, MBE (Molecular Beam Epitaxy)
xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Depth
The oxide semiconductor film 403 can be formed by a sputtering apparatus that performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicular to a surface of a sputtering target, which is a so-called CP sputtering apparatus (column plasma sputtering apparatus).
The film may be formed using a tering system.

2A to 2E and 3A to 3D show an example of a method for manufacturing a semiconductor device including a transistor 420. FIG.

First, electrode layers 422a and 422b are formed on a substrate 400 having an insulating surface.
For example, metal films containing elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or metal nitride films containing the above elements (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) can be used as the layers 22a and 422b.
Alternatively, a high melting point metal film such as Ti, Mo, W or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) may be laminated on either or both of the upper and lower sides of a metal film such as tungsten nitride film.

There is no particular limitation on the substrate that can be used for the substrate 400 having an insulating surface, but it is necessary that the substrate has at least a heat resistance sufficient to withstand a subsequent heat treatment. For example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate,
A quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can also be applied, and any of these substrates on which semiconductor elements are provided may be used as the substrate 400.

Next, an insulating film 423 is formed to cover the electrode layers 422a and 422b. The state up to this point is shown in FIG.

The insulating film 423 is formed by a plasma CVD method, a sputtering method, or the like using silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, or a mixed material of these.

Next, the insulating film 423 and the electrode layers 422a and 422b are cut (grinded or polished).
The grinding and polishing method is chemical mechanical polishing.
A chemical mechanical polishing (CMP) method can be suitably used.

Next, the electrode layers 424a and 424b are formed so as to overlap the electrode layers 422a and 422b. The electrode layers 424a and 424b may be made of, for example, Al, Cr, Cu, Ta, Ti, Mo,
A metal film containing an element selected from W, or a metal nitride film containing the above-mentioned elements (
A high melting point metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) may be used. Also, a configuration may be used in which a high melting point metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is laminated on either or both of the upper and lower sides of a metal film such as Al or Cu.

Next, an insulating film 426 is formed to cover the electrode layers 424a and 424b. The state up to this point is shown in FIG. 2B. Note that although the boundary between the insulating film 423 and the insulating film 426 is shown by a dotted line, if the same material is used, the boundary is not clearly defined. Therefore, the dotted line showing the boundary is omitted in the following drawings, and a stack of the insulating film 423 and the insulating film 426 is illustrated as a base insulating layer 436.
If the same material is used for the electrode layers 422a, 422b and the electrode layers 424a, 424b, there will be no clear boundary between them. Therefore, in the following drawings, the dotted lines indicating the boundaries will be omitted, and the electrode layers 422a, 422b and the electrode layer 42
The stack of layers 424a and 424b is illustrated as electrode layers 425a and 425b.

Next, the insulating film 426 and the electrode layers 424a and 424b are cut (grinded or polished).
The grinding and polishing method used is the CMP method.

Next, the oxide semiconductor film 403 is formed over the base insulating layer 436 and the electrode layers 425a and 425b.

In this embodiment, as a target for forming the oxide semiconductor film 403 by a sputtering method, an oxide target having a composition ratio of In:Ga:Zn=3:1:2 [atomic ratio] is used to form an In—Ga—Zn-based oxide film (IGZO film).

It is preferable that a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed be used as a sputtering gas used in forming the oxide semiconductor film 403 .

The substrate is held in a film-forming chamber that is maintained in a reduced pressure state. Then, while removing the residual moisture in the film-forming chamber, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is sputtered using the above target.
In order to remove residual moisture in the deposition chamber, it is preferable to use an adsorption type vacuum pump, such as a cryopump, an ion pump, or a titanium sublimation pump. Alternatively, a turbo molecular pump with a cold trap may be used as an exhaust means. The deposition chamber evacuated using a cryopump is, for example,
Since hydrogen atoms, compounds containing hydrogen atoms such as water (H ₂ O) (preferably compounds containing carbon atoms as well), and the like are exhausted, the concentration of impurities contained in the oxide semiconductor film 403 formed in the deposition chamber can be reduced.

The oxide semiconductor film 403 can be formed by processing a film-shaped oxide semiconductor film into an island-shaped oxide semiconductor film by a photolithography process.

Alternatively, a resist mask for forming the island-shaped oxide semiconductor film 403 may be formed by an inkjet method. When the resist mask is formed by an inkjet method, no photomask is used, which leads to reduced manufacturing costs.

The oxide semiconductor film may be etched by dry etching or wet etching, or may be etched by both. For example, a mixed solution of phosphoric acid, acetic acid, and nitric acid may be used as an etching solution for wet etching of the oxide semiconductor film.
O-07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.
For example, the IGZO film may be etched by an ICP etching method (etching conditions: etching gas (BCl ₃ :Cl ₂ =60 sccm:
20 sccm), power supply power of 450 W, bias power of 100 W, and pressure of 1.9 Pa, and the resulting mixture can be processed into an island shape.

Further, the oxide semiconductor film 403 may be subjected to heat treatment in order to remove excess hydrogen (including water or a hydroxyl group) (dehydration or dehydrogenation).
The heat treatment can be performed under reduced pressure or a nitrogen atmosphere. For example, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor film 403 is subjected to heat treatment at 450° C. in a nitrogen atmosphere for one hour.

The heat treatment device is not limited to an electric furnace, and a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, a GRTA (Gas Reactor Annular Annealing) may be used.
Rapid Thermal Annealing (LRTA) equipment, Lamp Rapid Thermal Annealing (LRTA)
RTA (Rapid Thermal Anneal) equipment
The LRTA apparatus is an apparatus that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. The high-temperature gas includes
An inert gas that does not react with an object to be treated by heat treatment, such as a rare gas such as argon or nitrogen, is used.

For example, as the heat treatment, GRTA may be performed in which the substrate is placed in an inert gas heated to a high temperature of 650° C. to 700° C., heated for several minutes, and then removed from the inert gas.

In the heat treatment, it is preferable that nitrogen or a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).
It is preferable that the content be less than or equal to 1 ppm.

Note that the heat treatment for dehydration or dehydrogenation may be performed after the formation of the oxide semiconductor film or after the formation of the island-shaped oxide semiconductor film 403.

The heat treatment for dehydration or dehydrogenation may be performed multiple times, or may be performed together with other heat treatments.

Further, oxygen (including at least any of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the oxide semiconductor film 403 that has been subjected to dehydration or dehydrogenation treatment to supply oxygen to the film.

In addition, oxygen, which is a main component material of the oxide semiconductor, may be simultaneously released and reduced by the dehydration or dehydrogenation treatment. In the oxide semiconductor film, oxygen vacancies are present in the portions from which oxygen is released, and the oxygen vacancies cause donor levels that cause fluctuations in the electrical characteristics of a transistor.

By introducing oxygen into the oxide semiconductor film 403 that has been subjected to dehydration or dehydrogenation treatment, the oxide semiconductor film 403 can be highly purified and made to be electrically i-type (intrinsic). A transistor including the highly purified and electrically i-type (intrinsic) oxide semiconductor film 403 has suppressed change in electrical characteristics and is electrically stable.

The oxygen can be introduced by ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like.

In the step of introducing oxygen into the oxide semiconductor film 403, oxygen may be introduced directly into the oxide semiconductor film 403 or may be introduced into the oxide semiconductor film 403 through other films such as the gate insulating layer 402.
In the case where oxygen is introduced through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like may be used; however, in the case where oxygen is directly introduced into the exposed oxide semiconductor film 403, plasma treatment or the like can be used.

Oxygen is preferably introduced into the oxide semiconductor film 403 after dehydration or dehydrogenation treatment, but is not particularly limited to this.
The introduction of oxygen into 3 may be carried out multiple times.

Next, a gate insulating layer 402 is formed to cover the oxide semiconductor film 403 (see FIG. 2C).
.

The thickness of the gate insulating layer 402 is set to 1 nm or more and 20 nm or less.
A deposition method, a CVD method, a pulsed laser deposition method, an ALD method, or the like can be appropriately used. The gate insulating layer 402 may be formed using a sputtering apparatus that performs film formation in a state in which a plurality of substrate surfaces are set approximately perpendicular to a sputtering target surface, that is, a so-called CP sputtering apparatus.

The gate insulating layer 402 can be formed using a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film.
It is preferable that the gate insulating layer 402 contains oxygen in the portion in contact with the gate insulating layer 403. In particular, it is preferable that the gate insulating layer 402 has an amount of oxygen in the film (bulk) that exceeds at least the stoichiometric ratio. For example, when a silicon oxide film is used as the gate insulating layer 402, the composition is SiO _{2 + α} (where α>0). In this embodiment, a silicon oxide film having a composition of SiO _{2 + α} (where α>0) is used as the gate insulating layer 402. This silicon oxide film is used as the gate insulating layer 402.
By using the gate insulating layer 402 as the gate insulating layer 2, oxygen can be supplied to the oxide semiconductor film 403, thereby improving the characteristics. Furthermore, the gate insulating layer 402 is preferably formed in consideration of the size of a transistor to be manufactured and the step coverage of the gate insulating layer 402.

The material of the gate insulating layer 402 may be hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x>0, y>0)), nitrogen-added hafnium silicate (HfSiO _x N _y (x>0, y>0)), hafnium aluminate (HfAl _x O
A gate leakage current can be reduced by using a high-k material such as lanthanum _oxide (x>0, y>0) or a gate insulating layer 402 having a single layer structure or a stacked layer structure.

Next, a stack of a conductive film and an insulating film is formed over the gate insulating layer 402, and the conductive film and the insulating film are etched to form a stack of a gate electrode layer 401 and an insulating film 413 (see FIG. 2C).

The gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material mainly composed of any of these metals. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used as the gate electrode layer 401. The gate electrode layer 401 may have a single-layer structure or a stacked structure.

Typically, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, or an aluminum nitride oxide film can be used for the insulating layer 413. The insulating layer 413 can be formed by a plasma CVD method, a sputtering method, or the like.

Next, a dopant 421 is added to the oxide semiconductor film 403 using the gate electrode layer 401 and the insulating film 413 as masks, so that low-resistance regions 404a and 404b are formed (see FIG. 2D).

The dopant 421 is an impurity that changes the electrical conductivity of the oxide semiconductor film 403. Examples of the dopant 421 include Group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), and argon (Ar).
One or more selected from the group consisting of arsenic (Ar), neon (Ne), indium (In), titanium (Ti), and zinc (Zn) can be used.

The dopant 421 is implanted through other films (e.g., the gate insulating layer 402) to
The dopant 421 can also be introduced into the oxide semiconductor film 403.
Ion implantation, ion doping, plasma immersion ion implantation, or the like can be used.

The process of introducing the dopant 421 may be controlled by appropriately setting implantation conditions such as acceleration voltage and dose amount, and the thickness of the film through which the dopant 421 passes. In this embodiment, phosphorus is used as the dopant 421, and phosphorus ions are implanted by an ion implantation method. The dose amount of the dopant 421 may be 1×10 ¹³ ions/cm ² or more and 5×10 ¹⁶ ions/cm ² or less.

The concentration of the dopant 421 in the low resistance region is 5×10 ¹⁸ /cm ³ or more and 1×10 ²²
/ ^cm3 or less is preferable.

The dopant 421 may be introduced while the substrate 400 is heated.

Note that the treatment of introducing the dopant 421 into the oxide semiconductor film 403 may be performed multiple times, and multiple types of dopants may be used.

After the introduction of the dopant 421, a heat treatment may be performed. The heat treatment is preferably performed under oxygen atmosphere at a temperature of 300° C. to 700° C., preferably 300° C. to 450° C., for 1 hour. The heat treatment may also be performed under nitrogen atmosphere, reduced pressure, or air (ultra-dry air).

In this embodiment, phosphorus (P) ions are implanted into the oxide semiconductor film 403 by an ion implantation method. Note that the phosphorus (P) ions are implanted under the following conditions: an acceleration voltage of 30 kV and a dose amount of 1.0×1.
0 ¹⁵ ions/ ^cm2 .

In the case where the oxide semiconductor film 403 is a CAAC-OS film, the following can be achieved by introducing the dopant 421:
In this case, the crystallinity of the oxide semiconductor film 403 can be restored by performing heat treatment after the introduction of the dopant 421.

Through the above steps, the oxide semiconductor film 403 is formed in which the low-resistance regions 404 a and 404 b are provided with the channel formation region 409 therebetween.

Next, an insulating film is formed over the gate electrode layer 401 and the insulating film 413, and the insulating film is etched to form sidewall insulating layers 412a and 412b.
The gate insulating layer is etched except for a region overlapping with 412b, to form a gate insulating layer 402 (see FIG. 3A).

The sidewall insulating layers 412a and 412b can be formed using a material and a method similar to those of the insulating film 413. In this embodiment mode, a silicon oxynitride film formed by a CVD method is used.

Next, a conductive film to be a source electrode layer and a drain electrode layer (including wirings formed from the same layer) is formed over the oxide semiconductor film 403, the gate insulating layer 402, the gate electrode layer 401, the sidewall insulating layers 412a and 412b, and the insulating film 413.

The conductive film is made of a material that can withstand the subsequent heat treatment. The conductive film used for the source electrode layer and the drain electrode layer is, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film containing the above-mentioned element (titanium nitride film,
Alternatively, a high melting point metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) may be laminated on either or both of the upper and lower sides of a metal film such as Al or Cu.

A resist mask is formed over the conductive film by a photolithography process, and selective etching is performed to form an island-shaped conductive film 445. After that, the resist mask is removed. Note that in this etching process, the conductive film 445 over the gate electrode layer 401 is not removed.

When a 30 nm thick tungsten film is used as the conductive film, the conductive film may be etched, for example, by a dry etching method to etch the tungsten film (etching conditions: etching gas ( _CF4 : _Cl2 : _O2 =55 sccm:45 sccm:55 sccm, source power 3000 W, bias power 140 W, pressure 0.67 Pa)) to form island-shaped tungsten films.

An insulating film 410 and an insulating film 446 which serve as interlayer insulating films are stacked over the island-shaped conductive film 445 (see FIG. 3B).

The insulating film 410 is formed using a highly dense inorganic insulating film (typically, an aluminum oxide film), may be a single layer or a stacked layer, and preferably includes at least an aluminum oxide film.

The insulating film 446 can be formed using a material and method similar to those of the insulating film 413. The insulating film 446 is formed to a thickness that can planarize unevenness caused by the transistor 420. In this embodiment, a silicon oxynitride film is formed to a thickness of 300 nm by a CVD method.

Next, the insulating film 446 and the conductive film 445 are polished by chemical mechanical polishing.
Part of the insulating film 446, the insulating film 410, and the conductive film 445 are removed so that 13 is exposed.

By this polishing treatment, the insulating film 446 is processed into an interlayer insulating film 415, the conductive film 445 over the gate electrode layer 401 is removed, and a source electrode layer 405a and a drain electrode layer 405b are formed.

In this embodiment mode, the insulating film 446, the insulating film 410, and the conductive film 445 are removed by a chemical mechanical polishing method; however, other cutting (grinding, polishing) methods may be used.
In the step of removing the conductive film 445 on the insulating film 446, the insulating film 410, and the conductive film 445, a cutting (grinding, polishing) method such as chemical mechanical polishing, an etching (dry etching, wet etching) method, a plasma treatment, or the like may be combined. For example, after the removal step by chemical mechanical polishing, a dry etching method or a plasma treatment (reverse sputtering, etc.) may be performed to improve the flatness of the treated surface. When the cutting (grinding, polishing) method is combined with an etching method, a plasma treatment, or the like, the order of the steps is not particularly limited and may be appropriately set according to the materials, film thicknesses, and surface unevenness of the insulating film 446, the insulating film 410, and the conductive film 445.

In this embodiment mode, the source electrode layer 405a and the drain electrode layer 405b are provided so as to be in contact with the side surfaces of the sidewall insulating layers 412a and 412b provided on the side surfaces of the gate electrode layer 401, and cover the side surfaces of the sidewall insulating layers 412a and 412b to a position slightly lower than the upper end portions. The shapes of the source electrode layer 405a and the drain electrode layer 405b vary depending on the conditions of the polishing treatment for removing the conductive film 445. As shown in this embodiment mode, the sidewall insulating layers 412a and 412b are
12b, the insulating film 413 may have a shape recessed in the film thickness direction from the polished surface of the insulating film 413. However, depending on the conditions of the polishing treatment,
In some cases, the upper end of the insulating layer 412b may be substantially aligned with the upper ends of the sidewall insulating layers 412a and 412b.

Through the above steps, the transistor 420 of this embodiment is manufactured (see Figure 3 (C)).

Such a manufacturing method can reduce a distance between a region (first contact region) where the source electrode layer 405a or the drain electrode layer 405b is in contact with the oxide semiconductor film 403, and the gate electrode layer 401. In addition, a distance between a region (second contact region) where the electrode layers 425a and 425b are in contact with the oxide semiconductor film 403, and the gate electrode layer 401 can also be reduced. Therefore, resistance between the region (first contact region) where the source electrode layer 405a or the drain electrode layer 405b is in contact with the oxide semiconductor film 403 and the gate electrode layer 401 is reduced, and the on-characteristics of the transistor 420 can be improved.

In addition, in the step of removing the conductive film 445 over the gate electrode layer 401 in the step of forming the source electrode layer 405 a and the drain electrode layer 405 b, a part of the insulating film 413 or the insulating film 4
Alternatively, the entirety of the gate electrode layer 13 may be removed. Also, an upper part of the gate electrode layer 401 may be removed. A transistor structure in which the gate electrode layer 401 is exposed is useful in an integrated circuit in which other wirings or semiconductor elements are stacked above the transistor.

A highly dense inorganic insulating film (typically, an aluminum oxide film) serving as a protective insulating film may be provided over the transistor 420 .

In this embodiment, the insulating film 413 is formed on and in contact with the source electrode layer 405 a, the drain electrode layer 405 b, the sidewall insulating layers 412 a and 412 b, the insulating film 410, and the interlayer insulating film 415.
07 is formed (see FIG. 3(D)).

The insulating film 407 may be a single layer or a stacked layer and preferably includes at least an aluminum oxide film.

The insulating film 407 can be formed by a plasma CVD method, a sputtering method, an evaporation method, or the like.

Besides the aluminum oxide film, typically, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film can be used as the insulating films 407 and 410. In addition, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film, or a metal nitride film (for example, an aluminum nitride film) can also be used.

In this embodiment, aluminum oxide films are formed by a sputtering method as the insulating films 407 and 410. By forming the aluminum oxide film with a high density (film density of 3.2 g/cm ³ or more, preferably 3.6 g/cm ³ or more), stable electrical characteristics can be imparted to the transistor 420. The film density can be measured by Rutherford backscattering spectroscopy (RBS).
The thickness can be measured by FTIR (Faraday backscattering spectrometry) or X-ray reflectivity measurement (XRR).

An aluminum oxide film that can be used as the insulating films 407 and 410 provided over the oxide semiconductor film 403 has a high blocking effect that does not allow impurities such as hydrogen and moisture and oxygen to pass through the film.

In addition, in FIG. 1A, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the insulating film 410, the interlayer insulating film 415, and the insulating film 407, and a wiring layer 435a is formed in the openings.
1 shows an example in which the wiring layers 435a and 435b are formed. By connecting to other transistors or elements using the wiring layers 435a and 435b, various circuits can be formed.

The wiring layer 435a and the wiring layer 435b can be formed using a material and a method similar to those of the gate electrode layer 401, the source electrode layer 405a, or the drain electrode layer 405b. For example, Al
It is possible to use a metal film containing an element selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film containing the above-mentioned element as a component (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.). It is also possible to use a configuration in which a high-melting point metal film such as Ti, Mo, or W or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is laminated on either or both of the lower and upper sides of a metal film such as Al or Cu.

(Embodiment 2)
In this embodiment, an example of a semiconductor device which includes the transistor described in Embodiment 1, can retain stored data even when power is not supplied, and has no limit on the number of times data can be written to the semiconductor device will be described.
Note that the semiconductor device of this embodiment mode is configured by using the transistor 420 described in Embodiment 1 as the transistor 162.

4A and 4B are cross-sectional views of a semiconductor device, each showing an example of a structure of the semiconductor device.
4A is a plan view of the semiconductor device, and FIG. 4B is a circuit diagram of the semiconductor device.
FIG. 4A corresponds to the cross sections taken along lines C1-C2 and D1-D2 in FIG.

4A and 4B includes a transistor 160 using a first semiconductor material in a lower portion and a transistor 162 using a second semiconductor material in an upper portion. The transistor 162 can have the same structure as the transistor 420 described in Embodiment 1.

Here, it is preferable that the first semiconductor material and the second semiconductor material have different forbidden band widths. For example, the first semiconductor material is a semiconductor material (such as silicon) other than an oxide semiconductor.
The second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor can easily operate at high speed. On the other hand, a transistor using an oxide semiconductor can hold charge for a long time owing to its characteristics.

The transistor 162 is a transistor including an oxide semiconductor and has a low off-state current; therefore, the use of this transistor enables stored data to be retained for a long time. In other words, a semiconductor memory device that does not require a refresh operation or requires an extremely low frequency of refresh operation can be provided, and power consumption can be sufficiently reduced.

Note that although the above transistors are all described as n-channel transistors, it goes without saying that p-channel transistors can also be used. Since the technical essence of the disclosed invention is in using an oxide semiconductor for the transistor 162 to retain data, it is not necessary to limit the specific configuration of the semiconductor device, such as a material used in the semiconductor device or a structure of the semiconductor device, to those described here.

The transistor 160 in FIG. 4A includes a channel formation region 116 provided in a substrate 100 containing a semiconductor material (e.g., silicon), impurity regions 120 provided to sandwich the channel formation region 116, and a metal compound region 124 in contact with the impurity region 120.
The transistor has a gate insulating layer 108 provided on a channel formation region 116 and a gate electrode layer 110 provided on the gate insulating layer 108. Although the source electrode and drain electrode are not explicitly shown in the drawings, such a state may be referred to as a transistor for convenience. In this case, the source electrode and drain electrode may be expressed including the source region and drain region in order to explain the connection relationship of the transistor. That is,
In this specification, the reference to a source electrode may include a source region.

An element isolation insulating layer 106 is provided over the substrate 100 so as to surround the transistor 160, and an insulating layer 130 is provided so as to cover the transistor 160. Note that in order to achieve high integration, it is preferable that the transistor 160 does not have a sidewall insulating layer as shown in FIG 4A. On the other hand, when emphasis is placed on the characteristics of the transistor 160, a sidewall insulating layer may be provided on the side surface of the gate electrode layer 110, and the impurity region 120 may include a region having a different impurity concentration.

4A is a transistor including an oxide semiconductor in a channel formation region.
The low-resistance region 144a is formed on and in contact with the conductive layer 143a, the low-resistance region 144b is formed on and in contact with the conductive layer 143b, and the channel formation region 144c is formed on and in contact with the insulating layer 154 sandwiched between the conductive layer 143a and the conductive layer 143b.

In the manufacturing process of the transistor 162, the electrode layers 142a and 142b which function as a source electrode layer and a drain electrode layer are formed by removing the conductive film provided over the gate electrode 148, the insulating film 137, and the sidewall insulating layers 136a and 136b by chemical mechanical polishing treatment.

Therefore, in the transistor 162, the distance between the region (contact region) where the electrode layers 142a and 142b functioning as source electrode layers or drain electrode layers are in contact with the oxide semiconductor layer 144 and the gate electrode 148 can be shortened. As a result, the resistance in the region (contact region) where the electrode layers 142a and 142b are in contact with the oxide semiconductor layer 144 and between the gate electrode 148 and the electrode layers 142a and 142b is in contact with the oxide semiconductor layer 144 can be reduced, and the on-characteristics of the transistor 162 can be improved.

An insulating film 149, an interlayer insulating film 135, and an insulating film 150 are provided as a single layer or a stacked layer over the transistor 162. In this embodiment, an aluminum oxide film is used as the insulating film 149 and the insulating film 150. When the aluminum oxide film has a high density (film density of 3.2 g/cm ³ or more, preferably 3.6 g/cm ³ or more), stable electrical characteristics can be imparted to the transistor 162.

A conductive layer 153 is provided in a region overlapping with the conductive layer 143a with the insulating film 149, the interlayer insulating film 135, and the insulating film 150 interposed therebetween, and a capacitor 164 is formed by the conductive layer 143a, the insulating film 149, the interlayer insulating film 135, the insulating film 150, and the conductive layer 153. That is, the conductive layer 143a functions as one electrode of the capacitor 164, and the conductive layer 153 functions as the other electrode of the capacitor 164. Note that when capacitance is not required, a structure in which the capacitor 164 is not provided is also possible. The capacitor 164 may be provided separately above the transistor 162.

An insulating film 152 is provided over the transistor 162 and the capacitor 164. Wirings 156a and 156b for connecting the transistor 162 to another transistor are provided over the insulating film 152. The wiring 156a is provided between the insulating film 149 and the interlayer insulating film 13.
The wiring 156b is electrically connected to the conductive layer 143a through an electrode formed in an opening formed in the insulating film 149, the interlayer insulating film 135, and the insulating film 150 and the insulating film 152.
The insulating film 150 and the conductive layer 143b are electrically connected to each other through an electrode formed in an opening formed in the insulating film 150, the insulating film 152, or the like.

In FIG. 4A and FIG. 4B, the transistor 160 and the transistor 162 are
At least a portion of the oxide semiconductor layer 144 overlaps with the source region or drain region of the transistor 160, and the oxide semiconductor layer 144 preferably overlaps with a portion of the source region or drain region of the transistor 160. The transistor 162 and the capacitor 164 are provided to overlap with at least a portion of the transistor 160. For example, the conductive layer 153 of the capacitor 164 is provided to overlap with at least a portion of the gate electrode layer 110 of the transistor 160. By employing such a planar layout, the area occupied by the semiconductor device can be reduced, and therefore high integration can be achieved.

Next, an example of a circuit configuration corresponding to Figures 4(A) and 4(B) is shown in Figure 4(C).

4C , a first wiring (1st Line) and a source electrode of the transistor 160 are electrically connected, a second wiring (2nd Line) and a drain electrode of the transistor 160 are electrically connected, a third wiring (3rd Line) and one of a source electrode or a drain electrode of the transistor 162 are electrically connected, and a fourth wiring (4th Line) and a drain electrode of the transistor 162 are electrically connected.
The wiring (4th Line) and the gate electrode layer of the transistor 162 are electrically connected to each other. The gate electrode layer of the transistor 160 and one of the source electrode and the drain electrode of the transistor 162 are electrically connected to the other electrode of the capacitor 164.
A fifth wiring (5th Line) and the other electrode of the capacitor 164 are electrically connected to each other.

In the semiconductor device illustrated in FIG. 4C, by utilizing the feature that the potential of the gate electrode layer of the transistor 160 can be held, data can be written, held, and read as follows.

The writing and holding of data will be described. First, the potential of the fourth wiring is set to
The potential at which the transistor 162 is turned on is set to a potential at which the transistor 162 is turned on.
The potential of the third wiring is applied to a node (node FG) to which the gate electrode layer of the transistor 160 and the capacitor 164 are connected. That is, a predetermined charge is applied to the node FG (writing). Here, it is assumed that one of charges that give two different potential levels (hereinafter referred to as low-level charge and high-level charge) is applied. After that,
The potential of the wiring is set to a potential at which the transistor 162 is turned off,
By turning off the node FG, the charge applied to the node FG is held (retained).

Since the off-state current of the transistor 162 is extremely small, the charge in the gate electrode layer of the transistor 160 is held for a long time.

Next, reading of data will be described. When a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (read potential) is applied to the fifth wiring, the second wiring takes on a different potential depending on the amount of charge held in the node FG. In general, when the transistor 160 is an n-channel type, the node FG (which can also be referred to as the gate electrode of the transistor 160)
The apparent threshold voltage _{Vth_H} when a high-level charge is applied to the node F
This is because the apparent threshold voltage _{Vth_L is lower than the apparent threshold voltage Vth_L} when a low-level charge is applied to node FG. Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary to turn the transistor 160 on. Therefore, by setting the potential of the fifth wiring to an intermediate potential _V0 between _{Vth_H} and _{Vth_L} , the charge applied to the node FG can be determined. For example, when a high-level charge is applied in writing, if the potential of the fifth wiring becomes _V0 (>Vth_H), the transistor 160 is turned on. When a low-level charge is applied, if the potential of the fifth wiring becomes _V0 (> _{Vth_H} ), the transistor 160 is turned on.
<V _{th — L} ), the transistor 160 remains in the “off state.” Therefore, the stored data can be read by monitoring the potential of the second wiring.

When memory cells are arranged in an array, it is necessary to read out only the information of a desired memory cell. When the information is not read out, the potential at which the transistor 160 is turned off regardless of the state of the gate electrode layer, that is, _{Vth_H}
Alternatively, a potential that turns on the transistor 160 regardless of the state of the gate electrode layer, that is, a potential larger than _{Vth_L} , may be applied to the fifth wiring.

In the semiconductor device described in this embodiment, by using a transistor which uses an oxide semiconductor and has an extremely low off-state current in a channel formation region, stored data can be retained for an extremely long period of time. That is, a refresh operation is not necessary or the frequency of the refresh operation can be reduced extremely, so that power consumption can be sufficiently reduced. Furthermore, even when there is no power supply (however, it is preferable that the potential is fixed), stored data can be retained for a long period of time.

In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data, and does not have a problem of element deterioration. For example, unlike a conventional nonvolatile memory, there is no need to inject electrons into a floating gate or extract electrons from the floating gate.
There is absolutely no problem of deterioration of the gate insulating layer. In other words, in the semiconductor device according to the disclosed invention, there is no limit to the number of times that data can be rewritten, which is a problem with conventional nonvolatile memories, and reliability is dramatically improved. Furthermore, since information is written depending on the on/off state of the transistor, high-speed operation can be easily achieved.

In addition, in the transistor 162, the low-resistance region 144a of the oxide semiconductor layer is in contact with and electrically connected to the conductive layer 143a embedded in the base insulating layer and the electrode layer 142a.
The contact resistance can be reduced, and the transistor can have excellent electrical characteristics (for example, high on-state current characteristics). Therefore, by using the transistor 162, a high performance semiconductor device can be achieved.
Since the transistor is highly reliable, the reliability of the semiconductor device can be improved.

The structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, methods, and the like described in other embodiments.

(Embodiment 3)
In this embodiment, a semiconductor device that uses the transistor described in Embodiment 1, can retain stored content even in a state where power is not supplied, and has no limit on the number of times writing is performed will be described with reference to FIGS. 5 and 6. Note that the semiconductor device in this embodiment is configured using the transistor described in Embodiment 1 as a transistor 162. Any of the structures of the transistors described in Embodiment 1 can be used for the transistor 162.

5A shows an example of a circuit configuration of a semiconductor device, and FIG. 5B is a conceptual diagram showing an example of the semiconductor device. First, the semiconductor device shown in FIG. 5A will be described, and then the semiconductor device shown in FIG.
The semiconductor device shown in FIG.

In the semiconductor device shown in Figure 5 (A), the bit line BL and the source electrode or drain electrode of the transistor 162 are electrically connected, the word line WL and the gate electrode layer of the transistor 162 are electrically connected, and the source electrode or drain electrode of the transistor 162 and the first terminal of the capacitor 254 are electrically connected.

The transistor 162 including an oxide semiconductor has an extremely small off-state current. For that reason, when the transistor 162 is turned off,
In this case, the potential of the terminal (or the charge stored in the capacitor 254) can be held for an extremely long period of time.

Next, writing and holding of data in the semiconductor device (memory cell 250) shown in FIG. 5A will be described.

First, the potential of the word line WL is set to a potential that turns on the transistor 162, thereby turning on the transistor 162. As a result, the potential of the bit line BL is applied to the first terminal of the capacitor 254 (write).
When the transistor 162 is turned off as a potential at which the capacitor 62 is turned off, the potential of the first terminal of the capacitor 254 is held (retained).

Since the off-state current of the transistor 162 is extremely small, the potential of the first terminal of the capacitor 254 (or the charge stored in the capacitor) can be held for a long time.

Next, reading of data will be described. When the transistor 162 is turned on, the bit line BL in a floating state and the capacitor 254 are electrically connected, and charge is redistributed between the bit line BL and the capacitor 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL varies depending on the potential of the first terminal of the capacitor 254 (or the charge stored in the capacitor 254).

For example, if the potential of the first terminal of the capacitor 254 is V, the capacitance of the capacitor 254 is C, the capacitance component of the bit line BL (hereinafter also referred to as bit line capacitance) is CB, and the potential of the bit line BL before the charge is redistributed is VB0, the potential of the bit line BL after the charge is redistributed is
Therefore, if the potential of the first terminal of the capacitance element 254 is in two states, V1 and V0 (V1>V0), the potential of the bit line BL when the potential V1 is held is (=CB×VB0+C×V1).
/(CB+C) is the potential of the bit line BL when the potential V0 is held (=CB×VB0
+ C × V0)/(CB + C)).

Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out.

5A, the charge stored in the capacitor 254 can be held for a long time because the off-state current of the transistor 162 is extremely small. In other words, a refresh operation is not necessary or the frequency of the refresh operation can be reduced significantly, so that power consumption can be sufficiently reduced. Furthermore, stored contents can be held for a long time even when power is not supplied.

Next, we will explain the semiconductor device shown in Figure 5 (B).

The semiconductor device shown in FIG. 5B has the memory cell 2 shown in FIG. 5A as a memory circuit in the upper portion.
50, and a peripheral circuit 253 required for operating the memory cell array 251a and the memory cell array 251b is provided below. Note that the peripheral circuit 253 is electrically connected to the memory cell array 251a and the memory cell array 251b.

By using the configuration shown in FIG. 5B, the peripheral circuit 253 is
In addition, since it can be provided directly under the memory cell array 251b, the semiconductor device can be made smaller.

It is preferable that the transistors provided in the peripheral circuit 253 are made of a semiconductor material different from that of the transistor 162. For example, silicon, germanium, silicon germanium,
Silicon carbide, gallium arsenide, or the like can be used, and it is preferable to use a single crystal semiconductor. Alternatively, an organic semiconductor material or the like may be used. A transistor using such a semiconductor material can operate at a sufficiently high speed. Therefore, the transistor can be used to suitably realize various circuits (logic circuits, driver circuits, etc.) that require high speed operation.

5B illustrates an example of a configuration in which two memory cell arrays, the memory cell array 251a and the memory cell array 251b, are stacked, but the number of stacked memory cell arrays is not limited to this. A configuration in which three or more memory cell arrays are stacked may also be used.

Next, a specific configuration of the memory cell 250 shown in FIG. 5A will be described with reference to FIG.

Fig. 6 shows an example of the configuration of a memory cell 250. Fig. 6A shows a plan view of the memory cell 250, and Fig. 6B shows a cross-sectional view taken along line AB in Fig. 6A.

The transistor 162 in FIGS. 6A and 6B can have the same structure as that described in Embodiment 1.

As shown in FIG 6B, the transistor 162 is provided over the electrode 502 and the electrode 504. The electrode 502 is a wiring that functions as the bit line BL in FIG 6A, and is provided in contact with the low resistance region of the transistor 162. The electrode 504 is a wiring that functions as the bit line BL in FIG 6A.
) and is provided in contact with the low-resistance region of the transistor 162. An electrode 506 provided in a region overlapping with the electrode 504 over the transistor 162 functions as the other electrode of the capacitor 254.

6A , the other electrode 506 of the capacitor 254 is electrically connected to a capacitor line 508. A gate electrode 148 provided over the oxide semiconductor layer 144 with a gate insulating layer 146 interposed therebetween is electrically connected to a word line 509.

FIG. 6C is a cross-sectional view of a connection portion between the memory cell array and the peripheral circuits.
The peripheral circuit includes, for example, an n-channel transistor 510 and a p-channel transistor 51
A semiconductor material other than an oxide semiconductor (such as silicon) is preferably used as a semiconductor material for the n-channel transistor 510 and the p-channel transistor 512. By using such a material, high-speed operation of the transistors included in the peripheral circuits can be achieved.

By employing the planar layout shown in FIG. 6A, the area occupied by the semiconductor device can be reduced, leading to high integration.

As described above, the memory cells formed in a multilayer structure in the upper portion are formed of transistors using an oxide semiconductor. A transistor using a highly purified and intrinsic oxide semiconductor has a small off-state current, and therefore, by using such a transistor, stored data can be retained for a long period of time. In other words, the frequency of refresh operations can be significantly reduced, and power consumption can be sufficiently reduced. In addition, the capacitor 254 has a capacitance as shown in FIG.
As shown in FIG. 1B, the electrode 504, the oxide semiconductor layer 144, the gate insulating layer 146, and the electrode 506
are stacked to form the film.

In this manner, a semiconductor device having unprecedented characteristics can be realized by integrating a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of operating at a sufficiently high speed) and a memory circuit using a transistor using an oxide semiconductor (in a broader sense, a transistor having a sufficiently small off-state current). In addition, by forming the peripheral circuit and the memory circuit into a stacked structure, the semiconductor device can be highly integrated.

This embodiment mode can be implemented in appropriate combination with structures described in other embodiment modes.

(Embodiment 4)
In this embodiment mode, an example in which the semiconductor device described in the above embodiment is applied to a portable device such as a mobile phone, a smartphone, or an electronic book will be described with reference to FIGS.

In portable devices such as mobile phones, smartphones, and e-books, SRAM or DRAM is used for temporary storage of image data, etc. The reason for using SRAM or DRAM is that flash memory has a slow response time and is not suitable for image processing.
On the other hand, when an SRAM or DRAM is used for temporary storage of image data, the following characteristics are observed.

In a normal SRAM, one memory cell has transistors 801 to 808 as shown in FIG.
The transistor 803, the transistor 805, and the transistor 806 are driven by an X-decoder 807 and a Y-decoder 808.
The MOSFET 804 and the transistor 806 constitute an inverter, enabling high-speed operation. However, since one memory cell is composed of six transistors, the cell area is large. When the minimum dimension of the design rule is F, the area of a memory cell in an SRAM is usually 100
^150F2 . For this reason, the cost per bit of SRAM is the highest among various types of memory.

In contrast, in a DRAM, a memory cell is composed of a transistor 811 and a storage capacitor 812 as shown in FIG. 7B, and is driven by an X-decoder 813 and a Y-decoder 814. One cell is composed of one transistor and one capacitor, and the area is small.
The memory cell area of a RAM is usually ¹⁰ F2 or less. However, a DRAM needs to be constantly refreshed, and consumes power even if it is not rewritten.

However, the memory cell area of the semiconductor device described in the above embodiment is about ¹⁰ F2, and frequent refresh is not required, so that the memory cell area can be reduced and power consumption can be reduced.

A block diagram of a portable device is shown in Fig. 8. The portable device shown in Fig. 8 is composed of an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, a touch sensor 919, an audio circuit 917, a keyboard 918, etc.
The application processor 906 is composed of a CPU 907, a DSP 908, an interface (IF) 909, and a gate driver 914.
In general, the memory circuit 912 is composed of an SRAM or a DRAM, and by employing the semiconductor device described in the above embodiment in this portion, data can be written and read at high speed, data can be stored for a long period of time, and power consumption can be sufficiently reduced.

9 shows an example in which the semiconductor device described in the above embodiment is used in a memory circuit 950 of a display. The memory circuit 950 shown in FIG. 9 is composed of a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. The memory circuit includes a signal line from image data (input image data), the memory 952, and the memory 953.
A display controller 956 that reads and controls the data (stored image data) stored in the memory 53 and a display 957 that displays images according to signals from the display controller 956 are connected.

First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in a memory 952 via a switch 954. The image data stored in the memory 952 (stored image data A) is then sent to a display 957 via a switch 955 and a display controller 956, and displayed.

When there is no change in the input image data A, the stored image data A is read out from the memory 952 via the switch 955 to the display controller 956, usually at a frequency of about 30 to 60 Hz.

Next, for example, when the user performs an operation to rewrite the screen (i.e., input image data A
If there is a change in the input image data B, the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this time, the stored image data A is read out periodically from the memory 952 via the switch 955. When the new image data (stored image data B) has been stored in the memory 953,
From the next frame of the display 957, the stored image data B is read out, and the switch 95
The stored image data B is sent to the display 957 via the display controller 956 and the display controller 956, and is displayed. This reading is continued until the next new image data is stored in the memory 952.

In this manner, the memory 952 and the memory 953 alternately write and read image data to and from each other, thereby displaying the image on the display 957.
The memory 952 and the memory 953 are not limited to being separate memories, and one memory may be divided and used. By employing the semiconductor device described in the above embodiment as the memory 952 and the memory 953, data can be written and read at high speed, data can be stored for a long period of time, and power consumption can be sufficiently reduced.

FIG. 10 shows a block diagram of an electronic book. FIG. 10 shows a battery 1001, a power supply circuit 1002, and
It is composed of a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.

Here, the semiconductor device described in the previous embodiment can be used for the memory circuit 1007 in FIG. 10. The memory circuit 1007 has a function of temporarily storing the contents of a book. For example, when a user is reading an electronic book and wants to mark a specific location (such as changing the display color, drawing an underline, making characters bold, or changing the font of characters), the memory circuit 1007 has a function of temporarily storing and storing information on the location specified by the user. When this information is to be stored for a long period of time, it may be copied to the flash memory 1004. Even in such a case, by employing the semiconductor device described in the previous embodiment, information can be written and read at high speed, memory can be stored for a long period of time, and power consumption can be sufficiently reduced.

As described above, the semiconductor device according to the above embodiment is mounted on the portable device described in this embodiment, which can read data at high speed, retain data for a long period of time, and consume less power.

The structure, method, and the like described in this embodiment can be used in appropriate combination with the structure, method, and the like described in other embodiments.

100 Substrate 106 Element isolation insulating layer 108 Gate insulating layer 110 Gate electrode layer 116 Channel formation region 120 Impurity region 124 Metal compound region 130 Insulating layer 135 Interlayer insulating film 136a Sidewall insulating layer 136b Sidewall insulating layer 137 Insulating film 142a Electrode layer 142b Electrode layer 143a Conductive layer 143b Conductive layer 144 Oxide semiconductor layer 144a Low resistance region 144b Low resistance region 144c Channel formation region 146 Gate insulating layer 148 Gate electrode 149 Insulating film 150 Insulating film 152 Insulating film 153 Conductive layer 154 Insulating layer 156a Wiring 156b Wiring 160 Transistor 162 Transistor 164 Capacitor 250 Memory cell 251a Memory cell array 251b Memory cell array 253 Peripheral circuit 254 Capacitor 400 Substrate 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor film 404a Low resistance region 404b Low resistance region 405 Electrode layer 405a Electrode layer 405b Electrode layer 407 Insulating film 409 Channel formation region 410 Insulating film 412a Sidewall insulating layer 412b Sidewall insulating layer 413 Insulating film 415 Interlayer insulating film 420 Transistor 421 Dopant 422a Electrode layer 422b Electrode layer 423 Insulating film 424a Electrode layer 424b Electrode layer 425a Electrode layer 425b Electrode layer 426 Insulating film 436 Base insulating layer 445 Conductive film 446 Insulating film 502 Electrode 504 Electrode 506 Electrode 508 Capacitor line 509 Word line 510 n-channel transistor 512 p-channel transistor 801 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Transistor 807 X decoder 808 Y decoder 811 Transistor 812 Storage capacitor 813 X decoder 814 Y decoder 901 RF circuit 902 Analog baseband circuit 903 Digital baseband circuit 904 Battery 905 Power supply circuit 906 Application processor 907 CPU
908 DSP
910 Flash memory 911 Display controller 912 Memory circuit 913 Display 914 Display unit 915 Source driver 916 Gate driver 917 Audio circuit 918 Keyboard 919 Touch sensor 950 Memory circuit 951 Memory controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display controller 957 Display 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash memory 1005 Audio circuit 1006 Keyboard 1007 Memory circuit 1008 Touch panel 1009 Display 1010 Display controller

Claims (5)

a first transistor including an oxide semiconductor in a channel formation region;
a second transistor including silicon in a channel formation region;
A capacitive element;
having
one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor;
a semiconductor device in which one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor,
a first conductive film having a region located above a channel formation region of the second transistor and electrically connected to one of a source and a drain of the first transistor;
an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor;
a second conductive film having a region located above the oxide semiconductor film and functioning as a gate of the first transistor;
a third conductive film having a region located above the oxide semiconductor film and electrically connected to one of a source and a drain of the first transistor;
a fourth conductive film having a region located above the oxide semiconductor film and electrically connected to the other of the source and the drain of the first transistor;
an insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, and a region disposed above the fourth conductive film;
a fifth conductive film having a region disposed above the insulating film and functioning as the other electrode of the capacitance element;
having
the third conductive film has a region in contact with the oxide semiconductor film,
the third conductive film has a region in contact with the first conductive film,
the third conductive film is spaced apart from the second conductive film in a plan view;
the fourth conductive film is spaced apart from the second conductive film in a plan view;
the first conductive film has a first region that does not overlap with the third conductive film;
the first region of the first conductive film overlaps with the fifth conductive film with the insulating film therebetween;
Semiconductor device. a first transistor including an oxide semiconductor in a channel formation region;
a second transistor including silicon in a channel formation region;
A capacitive element;
having
one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor;
one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor element;
A semiconductor device in which a signal is input to the other electrode of the capacitive element,
a first conductive film having a region located above a channel formation region of the second transistor and electrically connected to one of a source and a drain of the first transistor;
an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor;
a second conductive film having a region located above the oxide semiconductor film and functioning as a gate of the first transistor;
a third conductive film having a region located above the oxide semiconductor film and electrically connected to one of a source and a drain of the first transistor;
a fourth conductive film having a region located above the oxide semiconductor film and electrically connected to the other of the source and the drain of the first transistor;
an insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, and a region disposed above the fourth conductive film;
a fifth conductive film having a region disposed above the insulating film and functioning as the other electrode of the capacitance element;
having
the third conductive film has a region in contact with the oxide semiconductor film,
the third conductive film has a region in contact with the first conductive film,
the third conductive film is spaced apart from the second conductive film in a plan view;
the fourth conductive film is spaced apart from the second conductive film in a plan view;
the first conductive film has a first region that does not overlap with the third conductive film;
the first region of the first conductive film overlaps with the fifth conductive film with the insulating film therebetween;
Semiconductor device. a first transistor including an oxide semiconductor in a channel formation region;
a second transistor including silicon in a channel formation region;
A capacitive element;
having
one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor;
a semiconductor device in which one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor,
a first conductive film having a region located above a channel formation region of the second transistor and electrically connected to one of a source and a drain of the first transistor;
an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor;
a second conductive film having a region located above the oxide semiconductor film and functioning as a gate of the first transistor;
a third conductive film having a region located above the oxide semiconductor film and electrically connected to one of a source and a drain of the first transistor;
a fourth conductive film having a region located above the oxide semiconductor film and electrically connected to the other of the source and the drain of the first transistor;
an insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, and a region disposed above the fourth conductive film;
a fifth conductive film having a region disposed above the insulating film and functioning as the other electrode of the capacitance element;
having
the third conductive film has a region in contact with the oxide semiconductor film,
the fourth conductive film has a region in contact with the oxide semiconductor film,
the third conductive film has a region in contact with the first conductive film,
the third conductive film is spaced apart from the second conductive film in a plan view;
the fourth conductive film is spaced apart from the second conductive film in a plan view;
the first conductive film has a first region that does not overlap with the third conductive film;
the first region of the first conductive film overlaps with the fifth conductive film with the insulating film therebetween;
Semiconductor device. a first transistor including an oxide semiconductor in a channel formation region;
a second transistor including silicon in a channel formation region;
A capacitive element;
having
one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor;
one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor element;
A semiconductor device in which a signal is input to the other electrode of the capacitive element,
a first conductive film having a region located above a channel formation region of the second transistor and electrically connected to one of a source and a drain of the first transistor;
an oxide semiconductor film having a region located above the first conductive film and including a channel formation region of the first transistor;
a second conductive film having a region located above the oxide semiconductor film and functioning as a gate of the first transistor;
a third conductive film having a region located above the oxide semiconductor film and electrically connected to one of a source and a drain of the first transistor;
a fourth conductive film having a region located above the oxide semiconductor film and electrically connected to the other of the source and the drain of the first transistor;
an insulating film having a region disposed above the second conductive film, a region disposed above the third conductive film, and a region disposed above the fourth conductive film;
a fifth conductive film having a region disposed above the insulating film and functioning as the other electrode of the capacitance element;
having
the third conductive film has a region in contact with the oxide semiconductor film,
the fourth conductive film has a region in contact with the oxide semiconductor film,
the third conductive film has a region in contact with the first conductive film,
the third conductive film is spaced apart from the second conductive film in a plan view;
the fourth conductive film is spaced apart from the second conductive film in a plan view;
the first conductive film has a first region that does not overlap with the third conductive film;
the first region of the first conductive film overlaps with the fifth conductive film with the insulating film therebetween;
Semiconductor device. In any one of claims 1 to 4,
the third conductive film overlaps with the first conductive film with the oxide semiconductor film interposed therebetween;
Semiconductor device.

Images