JP2024057942A - Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

A silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device are provided, which are capable of reducing the contact resistance between a p-type semiconductor region and an n-type semiconductor region and an alloy layer.
[Solution] A silicon carbide semiconductor device comprises a silicon carbide substrate having a first main surface exposing a p-type semiconductor region and an n-type semiconductor region, an alloy layer provided on the first main surface and containing nickel, silicon and aluminum, a barrier layer provided on the alloy layer, and an electrode provided on the barrier layer and containing aluminum, wherein the alloy layer has a first alloy region provided on the p-type semiconductor region and a second alloy region provided on the n-type semiconductor region, the aluminum concentration of the first alloy region being higher than the aluminum concentration of the second alloy region, the barrier layer has a first barrier region provided on the first alloy region and a second barrier region provided on the second alloy region, and the thickness of the first barrier region is thinner than the thickness of the second barrier region.
[Selected Figure] Figure 1

Description

This disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

As one silicon carbide semiconductor device, a metal oxide semiconductor field effect transistor (MOSFET) has been disclosed, which is provided with a NiSi film that forms ohmic junctions with a p-type semiconductor region and an n-type semiconductor region.

JP 2019-071312 A

In conventional silicon carbide semiconductor devices with NiSi films, there is a need to reduce the contact resistance between the p-type semiconductor region and the NiSi film.

The present disclosure aims to provide a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device that can reduce the contact resistance between the p-type semiconductor region and the n-type semiconductor region and the alloy layer.

The silicon carbide semiconductor device disclosed herein comprises a silicon carbide substrate having a first main surface exposing a p-type semiconductor region and an n-type semiconductor region, an alloy layer containing nickel, silicon, and aluminum provided on the first main surface, a barrier layer provided on the alloy layer, and an electrode containing aluminum provided on the barrier layer, the alloy layer having a first alloy region provided on the p-type semiconductor region and a second alloy region provided on the n-type semiconductor region, the aluminum concentration of the first alloy region being higher than the aluminum concentration of the second alloy region, the barrier layer having a first barrier region provided on the first alloy region and a second barrier region provided on the second alloy region, and the thickness of the first barrier region being thinner than the thickness of the second barrier region.

The present disclosure provides a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can reduce the contact resistance between the p-type semiconductor region and the n-type semiconductor region and the alloy layer.

FIG. 1 is a plan view showing a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view showing the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view showing a silicon carbide semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view showing a silicon carbide semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view showing a silicon carbide semiconductor device according to the embodiment. FIG. 6 is a plan view showing a silicon carbide semiconductor device according to a modified example of the embodiment. FIG. 7 is a cross-sectional view showing a silicon carbide semiconductor device according to a modified example of the embodiment. FIG. 8 is a cross-sectional view showing a silicon carbide semiconductor device according to a modified example of the embodiment. FIG. 9 is a cross-sectional view showing a silicon carbide semiconductor device according to a modified example of the embodiment. FIG. 10 is a cross-sectional view (part 1) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 11 is a cross-sectional view (part 2) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 12 is a cross-sectional view (part 3) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 13 is a cross-sectional view (part 4) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment. FIG. 14 is a cross-sectional view (part 5) illustrating the method for manufacturing a silicon carbide semiconductor device according to the embodiment.

The form for implementing this is explained below.

[Description of the embodiments of the present disclosure]
First, the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface on which a p-type semiconductor region and an n-type semiconductor region are exposed, an alloy layer containing nickel, silicon, and aluminum provided on the first main surface, a barrier layer provided on the alloy layer, and an electrode containing aluminum provided on the barrier layer, the alloy layer having a first alloy region provided on the p-type semiconductor region and a second alloy region provided on the n-type semiconductor region, the aluminum concentration of the first alloy region being higher than the aluminum concentration of the second alloy region, the barrier layer having a first barrier region provided on the first alloy region and a second barrier region provided on the second alloy region, and the thickness of the first barrier region being thinner than the thickness of the second barrier region. In this case, the first alloy region having a high aluminum concentration forms an ohmic junction with the p-type semiconductor region, and the second alloy region having a low aluminum concentration forms an ohmic junction with the n-type semiconductor region. This reduces the contact resistance between the alloy layer and the p-type semiconductor region and the n-type semiconductor region.

[2] A silicon carbide semiconductor device according to another aspect of the present disclosure includes a silicon carbide substrate having a first main surface on which a p-type semiconductor region and an n-type semiconductor region are exposed, an alloy layer provided on the first main surface, a barrier layer provided on the alloy layer, and an electrode including aluminum provided on the barrier layer, the alloy layer having a first alloy region provided on the p-type semiconductor region and including nickel, silicon, and aluminum, and a second alloy region provided on the n-type semiconductor region and including nickel and silicon but not including aluminum, the barrier layer having a first barrier region provided on the first alloy region and a second barrier region provided on the second alloy region, the thickness of the first barrier region being thinner than the thickness of the second barrier region. In this case, the first alloy region including aluminum forms an ohmic junction with the p-type semiconductor region, and the second alloy region not including aluminum forms an ohmic junction with the n-type semiconductor region. This can reduce the contact resistance between the alloy layer and the p-type semiconductor region and the n-type semiconductor region.

[3] In [1] or [2], the first barrier region and the second barrier region may have a laminated structure of a titanium film and a titanium nitride film, and the thickness of the titanium nitride film in the first barrier region may be thinner than the thickness of the titanium nitride film in the second barrier region. In this case, it is easy to prevent the diffusion of aluminum into the alloy layer on the n-type semiconductor region while diffusing aluminum into the alloy layer on the p-type semiconductor region.

[4] A method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure includes the steps of preparing a silicon carbide substrate having a first main surface on which a p-type semiconductor region and an n-type semiconductor region are exposed, forming an alloy layer containing nickel and silicon on the p-type semiconductor region and the n-type semiconductor region, forming a barrier layer on the alloy layer, etching at least a part of the barrier layer formed on the p-type semiconductor region, and forming an electrode containing aluminum on the barrier layer after the etching step, thereby diffusing aluminum into at least the alloy layer formed on the p-type semiconductor region. In this case, a silicon carbide semiconductor device can be manufactured in which an alloy region with a high aluminum concentration forms an ohmic junction with the p-type semiconductor region, and an alloy region with a low aluminum concentration or no aluminum forms an ohmic junction with the n-type semiconductor region. This allows the contact resistance between the p-type semiconductor region and the n-type semiconductor region and the alloy layer to be reduced.

[5] In [4], the barrier layer may have a laminated structure of a titanium film and a titanium nitride film, and in the etching step, the titanium nitride film may be etched without etching the titanium film. In this case, it is easy to prevent the diffusion of aluminum into the alloy layer on the n-type semiconductor region while diffusing aluminum into the alloy layer on the p-type semiconductor region.

[6] In [4] or [5], the diffusing step may include a step of forming an aluminum film on the barrier layer, and a step of heat treating the aluminum film after the film forming step. In this case, the diffusion of aluminum into the barrier layer and the alloy layer is promoted.

[7] In [4] or [5], the diffusion step may include a step of forming an aluminum film on the barrier layer, and a step of cooling the aluminum film during the film formation step. In this case, cracks are generated in the thin parts of the barrier layer, making it easier for the barrier layer to diffuse aluminum. This promotes the diffusion of aluminum into the alloy layer on the p-type semiconductor region.

[Details of the embodiment of the present disclosure]
Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto.

(Silicon carbide semiconductor device)
A silicon carbide semiconductor device according to an embodiment will be described with reference to Figures 1 to 5. Figure 1 is a plan view showing a silicon carbide semiconductor device according to an embodiment. Figures 2 to 5 are cross-sectional views showing a silicon carbide semiconductor device according to an embodiment. Figure 2 corresponds to a cross-sectional view taken along line II-II in Figure 1. Figure 3 corresponds to a cross-sectional view taken along line III-III in Figure 1. Figure 4 corresponds to a cross-sectional view taken along line IV-IV in Figure 1. Figure 5 is an enlarged view of a portion of Figure 4.

As shown in Figures 1 to 5, the silicon carbide semiconductor device according to the embodiment is a so-called trench-type MOSFET 100. The MOSFET 100 mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70.

The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are composed of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type.

In the embodiment, a field effect transistor is formed as an example of a semiconductor element on the silicon carbide substrate 10. The silicon carbide epitaxial layer 40 mainly has a drift region 11, a body region 12, a source region 13, and a contact region 18.

The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has an n-type conductivity.

The body region 12 is provided on the drift region 11. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity.

The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 contains n-type impurities such as nitrogen or phosphorus, and has an n-type. The source region 13 constitutes the first main surface 1. The source region 13 is an example of an n-type semiconductor region.

The contact region 18 contains p-type impurities such as aluminum and has a p-type. The contact region 18 constitutes the first main surface 1. The contact region 18 penetrates the source region 13 and contacts the body region 12. The contact region 18 is an example of a p-type semiconductor region.

A plurality of gate trenches 5 are provided in the first main surface 1. The gate trenches 5 extend, for example, in a first direction parallel to the first main surface 1, and the plurality of gate trenches 5 are arranged in a second direction. The gate trenches 5 have a bottom surface 4 made of the drift region 11. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The gate trenches 5 have a side surface 3 that penetrates the contact region 18, the source region 13, and the body region 12 and continues to the bottom surface 4. The side surface 3 is, for example, perpendicular to a plane including the bottom surface 4.

The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts each of the contact region 18, the source region 13, the body region 12, and the drift region 11 at the side surface 3.

The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5.

The interlayer insulating film 83 contacts the gate insulating film 81 and the gate electrode 82. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. Contact holes 90 are formed in the interlayer insulating film 83 at regular intervals in the second direction. The contact holes 90 are provided so that the gate trench 5 is located between adjacent contact holes 90 in the second direction. The contact holes 90 extend in the first direction. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83.

The source electrode 60 contacts the first main surface 1. The source electrode 60 is electrically insulated from the gate electrode 82 by an interlayer insulating film 83. The source electrode 60 has an alloy layer 61, a metal layer 62, a barrier layer 63, and a source wiring 64.

The alloy layer 61 is provided in the contact hole 90. The alloy layer 61 is provided on the first main surface 1. The alloy layer 61 contacts the source region 13 and the contact region 18 at the first main surface 1. The alloy layer 61 is connected to the silicon carbide substrate 10 through the contact hole 90. The alloy layer 61 has a first alloy region 61a and a second alloy region 61b.

The first alloy region 61a is in contact with the contact region 18. The first alloy region 61a forms an ohmic junction with the contact region 18. The first alloy region 61a is made of a material containing, for example, nickel (Ni), silicon (Si), and aluminum. The first alloy region 61a is made of, for example, a NiSiAl alloy.

The second alloy region 61b is in contact with the source region 13. The second alloy region 61b forms an ohmic junction with the source region 13. The second alloy region 61b is made of a material containing nickel, silicon, and aluminum, for example. The second alloy region 61b is formed of, for example, a NiSiAl alloy. The second alloy region 61b may be made of a material containing nickel and silicon but not containing aluminum. The second alloy region 61b may be formed of, for example, a NiSi alloy.

The aluminum concentration of the first alloy region 61a is higher than the aluminum concentration of the second alloy region 61b. In this case, the first alloy region 61a, which has a high aluminum concentration, forms an ohmic junction with the contact region 18, and the second alloy region 61b, which has a low aluminum concentration, forms an ohmic junction with the source region 13. This reduces the contact resistance between the contact region 18 and the source region 13 and the alloy layer 61.

The metal layer 62 covers the upper and side surfaces of the interlayer insulating film 83. The metal layer 62 is formed, for example, from a Ni film.

The barrier layer 63 is provided on the alloy layer 61 and the metal layer 62. The barrier layer 63 covers the alloy layer 61 and the metal layer 62. The barrier layer 63 is in contact with the alloy layer 61 and the metal layer 62. The barrier layer 63 has a first barrier region 63a, a second barrier region 63b, and a third barrier region 63c.

The first barrier region 63a is provided on the first alloy region 61a. The first barrier region 63a is in contact with the first alloy region 61a. The first barrier region 63a has a laminated structure of a titanium film 63d and a titanium nitride film 63e, as shown in FIG. 5, for example. The first barrier region 63a may not include the titanium nitride film 63e and may be composed of only the titanium film 63d.

The second barrier region 63b is provided on the second alloy region 61b. The second barrier region 63b is in contact with the second alloy region 61b. The second barrier region 63b has a laminated structure of a titanium film 63f and a titanium nitride film 63g, as shown in FIG. 5, for example. The thickness of the titanium film 63f in the second barrier region 63b may be, for example, 5 nm. The thickness of the titanium nitride film 63g in the second barrier region 63b may be, for example, 100 nm.

The thickness of the first barrier region 63a is thinner than the thickness of the second barrier region 63b. The thickness of the titanium nitride film 63e in the first barrier region 63a may be thinner than the thickness of the titanium nitride film 63g in the second barrier region 63b. In this case, it is easy to diffuse aluminum into the first alloy region 61a while suppressing the diffusion of aluminum into the second alloy region 61b. The ratio of the thickness of the first barrier region 63a to the thickness of the second barrier region 63b may be, for example, 1:2 to 1:10.

The third barrier region 63c is provided on the metal layer 62. The third barrier region 63c covers the metal layer 62. The third barrier region 63c has a laminated structure of, for example, a titanium film and a titanium nitride film.

The source wiring 64 is provided on the barrier layer 63. The source wiring 64 covers the barrier layer 63. The source wiring 64 is in contact with the barrier layer 63. The source wiring 64 is made of a material containing, for example, aluminum. The source wiring 64 is an example of an electrode.

The drain electrode 70 contacts the second main surface 2. The drain electrode 70 contacts the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 forms an ohmic junction with the silicon carbide single crystal substrate 50.

As described above, in the MOSFET 100 according to the embodiment, a p-type contact region 18 and an n-type source region 13 are formed in a silicon carbide substrate 10. A first alloy region 61a having a high aluminum concentration is provided on the contact region 18, and a second alloy region 61b having a low aluminum concentration is provided on the source region 13. In this case, the first alloy region 61a having a high aluminum concentration forms an ohmic junction with the contact region 18, and the second alloy region 61b having a low aluminum concentration forms an ohmic junction with the source region 13. This reduces the contact resistance between the contact region 18 and the source region 13 and the alloy layer 61.

The aluminum concentration in the first alloy region 61a and the second alloy region 61b can be measured, for example, by energy dispersive X-ray spectroscopy (EDX).

In the above embodiment, the silicon carbide semiconductor device is a so-called trench type MOSFET 100, but is not limited to this. For example, the silicon carbide semiconductor device may be a so-called planar type MOSFET 200.

Figure 6 is a plan view showing a silicon carbide semiconductor device according to a modified embodiment. Figures 7 to 9 are cross-sectional views showing silicon carbide semiconductor devices according to modified embodiments. Figure 7 corresponds to a cross-sectional view taken along line VII-VII in Figure 6. Figure 8 corresponds to a cross-sectional view taken along line VIII-VIII in Figure 6. Figure 9 corresponds to a cross-sectional view taken along line IX-IX in Figure 6.

As shown in Figures 6 to 9, in the MOSFET 200, a gate trench 5 is not provided on the first main surface 1 of the silicon carbide substrate 10, and a gate insulating film 81 and a gate electrode 82 are formed in this order on the first main surface 1.

MOSFET 200 has a silicon carbide substrate 10. Silicon carbide substrate 10 includes silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 on silicon carbide single crystal substrate 50. Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1. Silicon carbide epitaxial layer 40 constitutes first main surface 1, and silicon carbide single crystal substrate 50 constitutes second main surface 2. Silicon carbide epitaxial layer 40 has drift region 11, p region 15, and n region 16. p region 15 and n region 16 are exposed at first main surface 1. p region 15 is an example of a p-type semiconductor region. n region 16 is an example of an n-type semiconductor region. Other configurations of MOSFET 200 may be similar to those of MOSFET 100.

The MOSFET 200 according to the modified embodiment also achieves the same effects as the MOSFET 100 according to the embodiment.

(Method of Manufacturing Silicon Carbide Semiconductor Device)
A method for manufacturing the MOSFET 100 according to the embodiment will be described. Figures 10 to 14 are cross-sectional views showing the method for manufacturing the MOSFET 100 according to the embodiment. Figures 10 to 14 correspond to cross-sectional views taken along line IV-IV in Figure 1.

First, as shown in FIG. 10, a silicon carbide substrate 10 is prepared having a first main surface 1 on which the source region 13 and the contact region 18 are exposed.

The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide epitaxial layer 40 mainly has a drift region 11, a body region 12, a source region 13, and a contact region 18. A plurality of gate trenches 5 (FIGS. 2 and 3) are provided on the first main surface 1. Each gate trench 5 is provided with a gate insulating film 81, a gate electrode 82, and an interlayer insulating film 83 (FIGS. 2 and 3).

Next, as shown in FIG. 11, a metal film (not shown) for the alloy layer 61 is formed on the first main surface 1 in contact with the source region 13 and the contact region 18, and a metal film for the drain electrode 70 is formed on the second main surface 2 in contact with the silicon carbide single crystal substrate 50. The metal film for the alloy layer 61 and the metal film for the drain electrode 70 are formed by, for example, a sputtering method. The metal film for the alloy layer 61 and the metal film for the drain electrode 70 are made of a material containing, for example, nickel.

Next, alloying annealing is performed. The metal film for the alloy layer 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900°C or lower and 1100°C or lower for about 5 minutes. As a result, at least a part of the metal film for the alloy layer 61 and at least a part of the metal film for the drain electrode 70 reacts with the silicon contained in the silicon carbide substrate 10 and becomes silicided. This forms the alloy layer 61 that forms an ohmic junction with the source region 13 and the contact region 18, and the drain electrode 70 that forms an ohmic junction with the silicon carbide single crystal substrate 50.

Next, as shown in FIG. 12, a barrier layer 63 is formed on the alloy layer 61. The barrier layer 63 is formed, for example, by a sputtering method. The barrier layer 63 has a laminated structure, for example, of a titanium film formed on the alloy layer 61 and a titanium nitride film formed on the titanium film.

13, a resist pattern 30 having an opening 30a is formed on the contact region 18. Specifically, a photoresist is applied on the contact region 18, and the resist pattern 30 having the opening 30a is formed by exposing the photoresist to light using an exposure device and developing the photoresist. After that, at least a part of the barrier layer 63 in the opening 30a of the resist pattern 30 is etched away by reactive ion etching (RIE) or the like. As a result, a thin barrier layer 63 (first barrier region 63a) is formed on the contact region 18, and a thick barrier layer 63 (second barrier region 63b) is formed on the source region 13. In the etching of the barrier layer 63, a part of the titanium nitride film is removed by etching without etching the titanium film. In this case, when forming the source wiring 64, it is easy to suppress the diffusion of aluminum into the alloy layer 61 on the source region 13 while diffusing aluminum into the alloy layer 61 on the contact region 18. In the etching of the barrier layer 63, the titanium nitride film and a part of the titanium film may be etched. After this, the resist pattern 30 is removed using an organic solvent or the like.

Next, as shown in FIG. 14, the source wiring 64 is formed. Specifically, the source wiring 64 is formed to cover the barrier layer 63. The source wiring 64 is formed, for example, by a sputtering method. The source wiring 64 is formed, for example, while heating the barrier layer 63. The source wiring 64 is made of a material containing aluminum, for example. The conditions for forming the source wiring 64 are such that the aluminum contained in the source wiring 64 diffuses into at least the alloy layer 61 on the contact region 18.

The thickness of the first barrier region 63a is thinner than the thickness of the second barrier region 63b. In this case, aluminum is likely to diffuse into the region of the alloy layer 61 that contacts the first barrier region 63a, but is unlikely to diffuse into the region of the alloy layer 61 that contacts the second barrier region 63b. Therefore, a NiSiAl alloy with a high aluminum concentration is formed in the region of the alloy layer 61 that contacts the first barrier region 63a, and a NiSiAl alloy with a low aluminum concentration or a NiSi alloy that does not contain aluminum is formed in the region of the alloy layer 61 that contacts the second barrier region 63b. In this way, a first alloy region 61a with a high aluminum concentration is formed on the contact region 18, and a second alloy region 61b with a low aluminum concentration is formed on the source region 13.

After the source wiring 64 is formed on the barrier layer 63, the source wiring 64 may be heat-treated at a temperature of, for example, 400° C. or higher and 500° C. or lower. In this case, the diffusion of aluminum into the barrier layer 63 and the alloy layer 61 is promoted.

When forming the source wiring 64, the source wiring 64 may be cooled during film formation. In this case, cracks may occur in the first barrier region 63a, which has a thin barrier layer 63, and the first barrier region 63a may be more likely to diffuse aluminum. This promotes the diffusion of aluminum into the alloy layer 61 (first alloy region 61a) on the contact region 18. For example, the source wiring 64 may be formed to a thickness that is half the target film thickness, then the source wiring 64 may be air-cooled, and then the source wiring 64 may be formed to a thickness that is the remaining half of the target film thickness.

In this manner, the silicon carbide semiconductor device 100 according to the embodiment can be manufactured.

As described above, according to the method for manufacturing the silicon carbide semiconductor device 100 according to the embodiment, first, at least a portion of the barrier layer 63 formed on the contact region 18 is etched. Next, a source wiring 64 is formed on the barrier layer 63, thereby diffusing aluminum into at least the alloy layer 61 formed on the contact region 18. In this case, a silicon carbide semiconductor device can be manufactured in which the first alloy region 61a having a high aluminum concentration forms an ohmic junction with the contact region 18, and the second alloy region 61b having a low aluminum concentration or no aluminum forms an ohmic junction with the source region 13. This reduces the contact resistance between the contact region 18 and the source region 13 and the alloy layer 61.

Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and variations are possible within the scope of the claims.

REFERENCE SIGNS LIST 1 first main surface 2 second main surface 3 side surface 4 bottom surface 5 gate trench 10 silicon carbide substrate 11 drift region 12 body region 13 source region 15 p region 16 n region 18 contact region 30 resist pattern 30a opening 40 silicon carbide epitaxial layer 50 silicon carbide single crystal substrate 60 source electrode 61 alloy layer 61a first alloy region 61b second alloy region 62 metal layer 63 barrier layer 63a first barrier region 63b second barrier region 63c third barrier region 63d titanium film 63e titanium nitride film 63f titanium film 63g titanium nitride film 64 source wiring 70 drain electrode 81 gate insulating film 82 gate electrode 83 interlayer insulating film 90 contact hole 100 silicon carbide semiconductor device

Claims (7)

a silicon carbide substrate having a first main surface from which a p-type semiconductor region and an n-type semiconductor region are exposed;
an alloy layer including nickel, silicon, and aluminum provided on the first main surface;
a barrier layer provided on the alloy layer;
an electrode including aluminum provided on the barrier layer;
Equipped with
the alloy layer has a first alloy region provided on the p-type semiconductor region and a second alloy region provided on the n-type semiconductor region;
a concentration of aluminum in the first alloy region is greater than a concentration of aluminum in the second alloy region;
the barrier layer having a first barrier region overlying the first alloy region and a second barrier region overlying the second alloy region;
The thickness of the first barrier region is less than the thickness of the second barrier region.
Silicon carbide semiconductor devices. a silicon carbide substrate having a first main surface from which a p-type semiconductor region and an n-type semiconductor region are exposed;
An alloy layer provided on the first main surface;
a barrier layer provided on the alloy layer;
an electrode including aluminum provided on the barrier layer;
Equipped with
The alloy layer is
a first alloy region disposed over the p-type semiconductor region and comprising nickel, silicon, and aluminum;
a second alloy region overlying the n-type semiconductor region, the second alloy region comprising nickel and silicon and no aluminum;
having
the barrier layer has a first barrier region overlying the first alloy region and a second barrier region overlying the second alloy region;
The thickness of the first barrier region is less than the thickness of the second barrier region.
Silicon carbide semiconductor devices. the first barrier region and the second barrier region have a laminated structure of a titanium film and a titanium nitride film,
a thickness of the titanium nitride film in the first barrier region is thinner than a thickness of the titanium nitride film in the second barrier region;
The silicon carbide semiconductor device according to claim 1 . preparing a silicon carbide substrate having a first main surface from which a p-type semiconductor region and an n-type semiconductor region are exposed;
forming an alloy layer containing nickel and silicon on the p-type semiconductor region and the n-type semiconductor region;
forming a barrier layer on the alloy layer;
Etching at least a portion of the barrier layer formed on the p-type semiconductor region;
forming an electrode containing aluminum on the barrier layer after the etching step, thereby diffusing aluminum into the alloy layer formed at least on the p-type semiconductor region;
having
A method for manufacturing a silicon carbide semiconductor device. the barrier layer has a laminated structure of a titanium film and a titanium nitride film,
In the etching step, the titanium nitride film is etched without etching the titanium film.
The method for manufacturing a silicon carbide semiconductor device according to claim 4 . The diffusing step comprises:
depositing an aluminum film on the barrier layer;
a step of heat treating the aluminum film after the film-forming step;
having
The method for manufacturing a silicon carbide semiconductor device according to claim 4 or 5. The diffusing step comprises:
depositing an aluminum film on the barrier layer;
cooling the aluminum film during the film-forming step;
having
The method for manufacturing a silicon carbide semiconductor device according to claim 4 or 5.

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