JP2024044298A - Periodic signal corrector and control circuit - Google Patents

Abstract

[Problem] To provide a periodic signal corrector capable of suppressing disturbance of a periodic signal due to delay, etc. [Solution] A periodic signal corrector A1 includes a signal input unit 11 that receives a periodic signal indicating timing, a correction unit 14 that corrects the input periodic signal to a corrected periodic signal, a reference setting unit 12 that sets a reference timing based on the timing indicated by the corrected periodic signal and a set period T, an error range setting unit 13 that sets an error range based on the reference timing, and a signal output unit 15 that outputs the corrected periodic signal. If the timing indicated by the periodic signal is within an error range based on the previous corrected periodic signal, the correction unit 14 sets the periodic signal to the corrected periodic signal, and if the timing indicated by the periodic signal is not within the error range, corrects the timing indicated by the periodic signal to be within the error range to generate the corrected periodic signal. [Selected Figure] Figure 1

Description

The present invention relates to a periodic signal corrector that corrects a periodic signal indicating timing, and a control circuit equipped with the frequency corrector.

For example, technology that synchronizes the internal phase of inverter devices and parallels multiple distributed power sources as voltage sources is an extremely important technology for business continuity planning during power outages and microgrid construction. . Generally known methods for synchronizing internal phases include a technique in which a management device synchronizes by sending a synchronization signal to each device, and a technique in which a specific device transmits a synchronization signal to other devices to synchronize them. . Furthermore, a method has been developed in which the internal phases of a plurality of devices are matched by each device transmitting and receiving internal phases through communication, rather than by a management device or a specific device. Patent Document 1 discloses that a plurality of distributed power sources each transmits and receives an internal phase to at least one other distributed power source, and generates an internal phase using a calculation result based on the generated internal phase and the received internal phase. discloses a technique for synchronizing the internal phases of each distributed power source.

By generating a synchronization pulse based on the internal phase synchronized using the technique described in Patent Document 1, a synchronization signal indicating the timing for synchronizing with another device can be generated. Each device can achieve phase synchronization by using synchronization signals based on mutually synchronized internal phases.

JP2015-027155A

However, when each device generates a synchronization signal based on the internal phase, there is a risk that random and extremely large delays will occur due to interrupt processing, etc. Even if it is possible to achieve high-precision synchronization of the internal phase through calculation processing, if a sudden delay occurs when generating the synchronization signal, the synchronization of each device will be disrupted.

The present invention was conceived under the above-mentioned circumstances, and an object of the present invention is to provide a periodic signal corrector capable of suppressing disturbances of periodic signals due to delays and the like.

In order to solve the above problems, the present invention takes the following technical measures.

A periodic signal corrector provided by a first aspect of the present invention includes: a signal input section that receives a periodic signal indicating timing; a correction section that corrects the input periodic signal into a corrected periodic signal; a reference setting section that sets a reference timing based on the timing indicated by the corrected periodic signal and a set period; an error range setting section that sets an error range based on the reference timing; and an error range setting section that outputs the corrected periodic signal. and a signal output section, the correction section converts the periodic signal into the corrected periodic signal when the timing indicated by the periodic signal is within the error range based on the previous corrected periodic signal, and If the timing indicated by is not within the error range, the timing indicated by the periodic signal is corrected to be within the error range and the corrected periodic signal is obtained.

In a preferred embodiment of the present invention, when the timing indicated by the periodic signal is after the error range, the correction section corrects the timing indicated by the periodic signal to the last timing within the error range.

In a preferred embodiment of the present invention, when the timing indicated by the periodic signal is earlier than the error range, the correction unit corrects the timing indicated by the periodic signal to the earliest timing within the error range.

The control circuit provided by the second aspect of the present invention comprises a periodic signal corrector provided by the first aspect of the present invention, and a synchronization signal generator that generates a synchronization signal as the periodic signal and inputs it to the signal input unit, the synchronization signal generator comprises an internal value generation unit that generates an internal value, a communication unit that communicates with at least one other synchronization signal generator, and a synchronization signal generation unit that generates the synchronization signal based on the internal value after convergence, the communication unit transmits the internal value generated by the internal value generation unit to at least one of the other synchronization signal generators, and the internal value generation unit generates the internal value using a calculation result based on the generated internal value and an internal value received by the communication unit from at least one of the other synchronization signal generators.

According to the present invention, when the timing indicated by the periodic signal is not within the error range, the correction section corrects the timing indicated by the periodic signal to be within the error range. Therefore, the periodic signal corrector according to the present invention can correct the timing indicated by the generated periodic signal to a timing within the error range. Thereby, the periodic signal corrector can suppress disturbance of the periodic signal due to delay or the like.

Other features and advantages of the invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

FIG. 2 is a block diagram showing the internal configuration of a control circuit including a periodic signal corrector according to the first embodiment. (a) is a block diagram showing an example of the internal configuration of a synchronization signal generator, and (b) is a diagram showing a communication state of a plurality of synchronization signal generators forming a network. 7 is a timing chart for explaining correction processing performed by the periodic signal corrector according to the first embodiment. It is an example of a flowchart for explaining correction processing performed by the periodic signal corrector according to the first embodiment. 10 is a timing chart for explaining a correction process performed by a periodic signal corrector according to a second embodiment. It is an example of a flowchart for explaining the correction process performed by the periodic signal corrector according to the second embodiment. 12 is a timing chart for explaining correction processing performed by a periodic signal corrector according to a third embodiment. 13 is an example of a flowchart for explaining a correction process performed by a periodic signal corrector according to the third embodiment.

The following describes in detail the embodiment of the present invention with reference to the drawings.

FIG. 1 is a block diagram showing the internal configuration of a control circuit B including a periodic signal corrector A1 according to the first embodiment. Control circuit B is a configuration for controlling a device (not shown), and operates the device in synchronization with other devices. Control circuit B generates a synchronization signal that is a periodic signal indicating timing for synchronizing with other devices. Control circuit B performs control based on the generated synchronization signal. The control circuit B has a correction function for suppressing the delay when a delay occurs in the generated synchronization signal. The control circuit B is mounted on, for example, an inverter device, and controls the inverter circuit. In this case, control circuit B causes the inverter circuit to output AC power that is synchronized with other inverter devices. Note that the device in which the control circuit B is mounted is not limited. The control circuit B includes a periodic signal corrector A1, a synchronization signal generator 2, and an I/O circuit 3.

The synchronization signal generator 2 generates a synchronization signal synchronized with another control circuit B and outputs it to the periodic signal corrector A1. The synchronization signal generator 2 is realized by, for example, a microcomputer. FIG. 2 is a diagram for explaining an example of the synchronization signal generator 2. As shown in FIG. FIG. 2(a) is a block diagram showing an example of the internal configuration of the synchronization signal generator 2. As shown in FIG. FIG. 2(b) is a diagram showing the communication state of a plurality of synchronization signal generators 2 configuring the communication system.

As shown in FIG. 2(b), the synchronization signal generator 2 of the control circuit B is communicating with the synchronization signal generator 2 of the other control circuit B, and all the synchronization signal generators 2 communicating with each other are The network is configured with. FIG. 2(b) shows a state in which five synchronization signal generators 2 constitute a network. Note that the number of synchronization signal generators 2 constituting the network is not limited. The solid line arrow shown in FIG. 2(b) indicates that mutual communication is being performed. In this embodiment, each synchronization signal generator 2 mutually communicates with all other synchronization signal generators 2. Note that each synchronization signal generator 2 does not need to communicate with all other synchronization signal generators 2. Each synchronization signal generator 2 communicates with at least one synchronization signal generator 2 (for example, one located nearby or one with which communication has been established) among the synchronization signal generators 2 constituting the network. Any state in which a communication path exists for any two synchronization signal generators 2 making up the network (hereinafter, this state will be referred to as a "connected state") is sufficient.

As shown in FIG. 2A, the synchronization signal generator 2 includes an internal value generation section 21, a communication section 22, and a synchronization signal generation section 23.

The internal value generation unit 21 generates an internal value X _i . In this specification, the internal value generated by itself (i-th synchronization signal generator 2) is expressed as X _i . When the number of synchronization signal generators 2 is n (n=5 in the example of FIG. 2(b)), i is a natural number from 1 to n. Details of the internal value generation unit 21 will be described later.

The communication unit 22 communicates with other synchronization signal generators 2. The communication section 22 receives the internal value X _i generated by the internal value generation section 21 and transmits it to the communication section 22 of the other synchronization signal generator 2 . Furthermore, the communication unit 22 outputs the internal value X _j received from the communication unit 22 of another synchronization signal generator 2 to the internal value generation unit 21 . In this specification, the internal value received from the j-th synchronization signal generator 2 among the other synchronization signal generators 2 is expressed as X _j . j is a natural number from 1 to n. Note that the communication method is not limited, and may be wired communication or wireless communication.

The internal value generation unit 21 generates and outputs an internal value X _i that changes over time. Further, the internal value generation section 21 updates the internal value X _i using the generated internal value X _i and the internal value X _j of another synchronization signal generator 2 inputted from the communication section 22 . Even if the internal value X _i and the internal value X _j are different, the internal value X _i and the internal value X _j converge to the same value by repeating the update process in the internal value generation unit 21. Thereby, the internal values X _i of each synchronization signal generator 2 are synchronized. As shown in FIG. 1A, the internal value generation section 21 includes a calculation section 211, a multiplier 212, an adder 213, and an integrator 214.

The calculation unit 211 performs calculation based on the following equation (1) every update period Δt. Note that the update period Δt is not limited. The internal value X _i and the internal value X _j change over time, and the values at time t are written as X _i (t) and X _j (t), respectively. The calculation unit 211 subtracts each internal value X _i generated by the internal value generation unit 21 from each internal value X _j input from the communication unit 22, and calculates a total difference value D _i by adding all the subtraction results. . The coefficient a _ij is set to "1" or "0". The coefficient a _ij is set to "1" for the internal value X _j that the communication unit 22 receives, and the coefficient a _ij is set to "0" for the internal value X _j that is not received. The calculation unit 211 outputs the calculated total difference value D _i to the multiplier 212 .

The multiplier 212 multiplies the difference total value D _i input from the calculation unit 211 by a predetermined coefficient ε and outputs the result to the adder 213. The coefficient ε is a value that satisfies 0<ε<1/d _max and is set in advance. d _max is the maximum value among all the synchronization signal generators 2 constituting the _network , among the number of other synchronization signal generators 2 with which the communication unit 22 communicates, i.e., the coefficient ε is used to suppress the value added to the integrator 214 from becoming too large (small), causing the internal value X _i to fluctuate too much.

The adder 213 adds the input from the multiplier 212 and a predetermined angular frequency ω ₀ and outputs the result as a corrected angular frequency ω _i to the integrator 214. The integrator 214 generates and outputs the internal value X i by integrating the corrected angular frequency ω _i input from the adder 213. The integrator 214 generates the internal value X _i by adding the corrected angular frequency ω _i to the internal value X _i generated previously. That is, the integrator 214 always generates the internal value X _i by adding the angular frequency ω ₀ to the internal value X _i . Furthermore, the integrator 214 updates the internal value X _i by adding the output from the multiplier 212 in addition to the angular frequency ω ₀ to the internal value X _i at the update timing for each update period Δt. Furthermore, the integrator 214 outputs the internal value X _i as a value in the range of (0≦X _i <2π). The integrator 214 outputs the internal value _{X i to} the synchronization signal generating unit 23, the communication unit 22, and the calculation unit 211.

The internal value generation unit 21 updates the internal value X _i at every update period Δt. By performing this update in each synchronizing signal generator 2, the internal values X _i of each synchronizing signal generator 2 converge to the same value. The internal value X _i changes with time, and can be thought of as a combination of a component that changes according to the angular frequency ω ₀ and a component that changes to compensate for the initial phase shift. As the latter converges to the same value Xα, the internal values X _i of each synchronizing signal generator 2 also converge to the same value. It has also been mathematically proven that the latter converge to the same value. Since the synchronization signal generation section 2 can converge the internal values X _i of each synchronization signal generator 2 to the same value through calculation by the internal value generation section 21, there is no need for a management device or a specific device to match the internal phases. do not.

The synchronization signal generating unit 23 generates a synchronization signal based on the internal value X _i generated by the internal value generating unit 21. For example, the synchronization signal generating unit 23 generates a pulse signal that rises at the timing when the internal value X _i is initialized to "0" as the synchronization signal. That is, the synchronization signal indicates the timing for synchronizing the rising timing of the pulse with another device. Note that the synchronization signal is not limited to this, and may be any signal that can indicate the synchronized timing. For example, the synchronization signal may be a pulse signal that falls at the timing when the internal value X _i is initialized to "0". The synchronization signal generating unit 23 outputs the generated synchronization signal to the periodic signal corrector A1.

Note that the synchronization signal generator 2 shown in FIG. 2(a) is an example, and the internal configuration of the synchronization signal generator 2 is not limited. The synchronization signal generator 2 may be any device that generates a synchronization signal synchronized with another synchronization signal generator 2.

The periodic signal corrector A1 corrects the synchronization signal input from the synchronization signal generator 2 and outputs it to the I/O circuit 3. The periodic signal corrector A1 outputs the synchronization signal as is if the delay of the synchronization signal is within an allowable error range. On the other hand, if the delay of the synchronizing signal exceeds the error range, the periodic signal corrector A1 corrects the synchronizing signal so that the delay falls within the error range and outputs the corrected signal. The periodic signal corrector A1 is realized by a programmable logic device such as a CPLD (Complex Programmable Logic Device), which can process simple calculations with high real-time performance. Note that the periodic signal corrector A1 is not limited to this. As shown in FIG. 1, the periodic signal corrector A1 includes a signal input section 11, a reference setting section 12, an error range setting section 13, a correction section 14, and a signal output section 15.

The signal input section 11 receives a synchronization signal input from the synchronization signal generator 2 and outputs it to the correction section 14 . The correction unit 14 corrects the synchronization signal input from the signal input unit 11 and outputs the corrected synchronization signal to the signal output unit 15. The signal output section 15 outputs the corrected synchronization signal input from the correction section 14 to the I/O circuit 3. Details of the correction unit 14 will be described later.

The reference setting section 12 receives the corrected synchronization signal from the correction section 14, and sets a reference timing based on the timing indicated by the corrected synchronization signal and a preset setting cycle T. Specifically, the reference setting unit 12 sets a timing after a set period T from the timing of the rise of a pulse, which is a synchronization signal, as the reference timing. The set period T is set to be the same as the period of the synchronization signal generated by the synchronization signal generation section 23.

The error range setting unit 13 sets an error range based on the reference timing set by the reference setting unit 12 and a preset error setting value α. Specifically, the error range setting unit 13 sets the error range between the reference timing and the timing that is the error setting value α after the reference timing. The error setting value α is a value for setting an error range in which delay is tolerable, and is set appropriately based on experiments or simulations.

The correction unit 14 corrects the synchronization signal input from the signal input unit 11 based on the error range set by the error range setting unit 13. Specifically, the correction unit 14 determines that the synchronization signal is not delayed or , determines that the delay is within an acceptable error range. In this case, the correction unit 14 generates and outputs the same synchronization signal as the input synchronization signal. Note that when the synchronization signal is first input, the reference timing is not set and the error range is not set, so the correction unit 14 generates and outputs the same synchronization signal as the input synchronization signal. On the other hand, if the timing of the rise of the pulse that is the synchronization signal is after the error range, the correction unit 14 determines that the delay of the synchronization signal is within the range that is not allowed. In this case, the correction unit 14 generates a pulse that rises at the last timing within the error range, that is, a timing that has elapsed by the error setting value α from the reference timing, and outputs it as a corrected synchronization signal.

Figure 3 is a timing chart for explaining the correction process performed by the periodic signal corrector A1. Figure 3(a) shows the synchronization signal input to the correction unit 14. Figure 3(b) shows the synchronization signal after correction output by the correction unit 14. The rising edge of each pulse in Figures 3(a) and (b) is indicated by an arrow. At time t0, the first pulse of the input synchronization signal rises, and the first pulse of the output synchronization signal also rises at the same timing. The reference timing after the set period T from this timing (time t0) is indicated by a dashed arrow. The period from the reference timing to the error setting value α is the error range. In Figure 3, the set error range is dotted. At time t1, the second pulse of the input synchronization signal rises, and since the timing of this rise is within the error range, the second pulse of the output synchronization signal also rises at the same timing. The period from the reference timing (dashed arrow) after the set period T of this timing (time t1) to the error setting value α is the next error range.

At time t2, the third pulse of the input synchronization signal rises, and the timing of this rise is after the error range. In other words, this is a range in which the delay of the synchronization signal is not allowed. Therefore, the third pulse of the synchronization signal to be output rises at time t2', which is the last timing within the error range, that is, the timing at which the error setting value α has elapsed from the reference timing. The period from the reference timing (broken line arrow) after the setting period T of this timing (time t2') to the elapse of the error setting value α is the next error range. At time t3, the fourth pulse of the input synchronizing signal rises, and since the rising timing is within the error range, the fourth pulse of the output synchronizing signal also rises at the same timing.

The I/O circuit 3 inputs and outputs signals from and to the outside of the control circuit B. The I/O circuit 3 outputs a control signal to the outside. The synchronization signal generated by the synchronization signal generator 2 has its delay corrected by the periodic signal corrector A1 and is input to the I/O circuit 3. The I/O circuit 3 outputs a control signal based on the synchronization signal with the delay corrected.

FIG. 4 is an example of a flowchart for explaining the correction processing performed by the periodic signal corrector A1. The correction process is started when control circuit B is activated.

First, it is determined whether or not the first pulse has been input (S1). Specifically, the correction unit 14 makes this determination based on the synchronization signal input from the signal input unit 11. The determination in step S1 is repeated until the first pulse is input (S1: NO). If the first pulse has been input (S1: YES), a pulse is output (S2). Specifically, the correction unit 14 outputs a pulse to the signal output unit 15 at the same timing as the pulse input from the signal input unit 11.

Next, the error range is set (S3). Specifically, the reference setting unit 12 sets the timing a set period T after the rising edge of the pulse output from the correction unit 14 as the reference timing, and the error range setting unit 13 sets the error range from the reference timing and the error setting value α. Next, it is determined whether a pulse has been input (S4). If a pulse has not been input (S4: NO), it is determined whether the error range has ended (S5). If the error range has not ended (S5: NO), the process returns to step S4, and the determinations of steps S4 and S5 are repeated.

In step S4, if a pulse is input before the error range ends (S4: YES), a pulse is output (S6). Specifically, the correction unit 14 outputs a pulse to the signal output unit 15 at the same timing as the pulse input from the signal input unit 11. On the other hand, in step S5, if the error range ends before a pulse is input (S5: YES), a pulse is output (S6). Specifically, the correction unit 14 outputs a pulse to the signal output unit 15 at the timing when the error range ends. After the pulse is output in step S6, the process returns to step S3 and steps S3 to S6 are repeated. Note that the correction process performed by the periodic signal corrector A1 is not limited to the one described above.

Next, the effects of the periodic signal corrector A1 will be explained.

According to the present embodiment, when the rising timing of the pulse that is the synchronization signal is after the error range, the correction unit 14 corrects the timing at the last timing within the error range, that is, at the timing when the error setting value α has elapsed from the reference timing. It generates a pulse that rises at , and outputs it as a corrected synchronization signal. Therefore, the periodic signal corrector A1 can correct the synchronization signal inputted from the synchronization signal generator 2 so that the rising edge of the pulse does not exceed the error range, and can suppress disturbance of the synchronization signal due to delay or the like. Thereby, the periodic signal corrector A1 can suppress disruption of synchronization even if a delay or the like occurs in the synchronization signal generated by the synchronization signal generator 2.

In addition, according to this embodiment, the error range setting unit 13 sets the error range between the reference timing and the timing that is the error setting value α after the reference timing. Therefore, the periodic signal corrector A1 can correct delays such as delays in the synchronization signal.

5 and 6 are diagrams for explaining the periodic signal corrector A2 according to the second embodiment. FIG. 5 is a timing chart for explaining the correction processing performed by the periodic signal corrector A2. FIG. 6 is an example of a flowchart for explaining the correction processing performed by the periodic signal corrector A2. The diagram showing the internal configuration of the periodic signal corrector A2 is the same as FIG. 1, so its description will be omitted.

The periodic signal corrector A1 according to the first embodiment can perform correction when the synchronization signal output from the synchronization signal generator 2 is delayed. However, depending on the shift characteristics of the synchronization signal, the synchronization signal may advance without delay. The periodic signal corrector A2 according to the second embodiment differs from the periodic signal corrector A1 in that it performs correction when the synchronization signal output from the synchronization signal generator 2 advances.

The periodic signal corrector A2 in the second embodiment outputs the synchronization signal as is if the lead of the synchronization signal is within the allowable error. On the other hand, if the lead of the synchronization signal is outside the allowable error, the periodic signal corrector A2 corrects the synchronization signal so that the lead falls within the allowable range and outputs the corrected synchronization signal. The functions of the signal input unit 11, reference setting unit 12, and signal output unit 15 of the periodic signal corrector A2 are similar to those of the signal input unit 11, reference setting unit 12, and signal output unit 15 of the periodic signal corrector A1.

The error range setting unit 13 sets the error range between the reference timing and the timing that precedes the reference timing by the error setting value β. The error setting value β is a value for setting the error range within which advance is acceptable, and is set appropriately based on experiments or simulations.

When the timing of the rising edge of the synchronization signal pulse is within an error range based on the rising edge of the synchronization signal pulse after the previous correction, the correction unit 14 determines that the synchronization signal is not advanced or that the advance is within an allowable error range. In this case, the correction unit 14 generates and outputs a synchronization signal that is the same as the input synchronization signal. Note that when the synchronization signal is first input, no reference timing is set and no error range is set, so the correction unit 14 generates and outputs a synchronization signal that is the same as the input synchronization signal. On the other hand, when the timing of the rising edge of the synchronization signal pulse is earlier than the error range, the correction unit 14 determines that the advance of the synchronization signal is within an unacceptable range. In this case, the correction unit 14 generates a pulse that rises at the earliest timing within the error range, that is, at a timing earlier than the reference timing by the error setting value β, and outputs it as the synchronization signal after correction.

FIG. 5 is a timing chart for explaining the correction processing performed by the periodic signal corrector A2. FIG. 5(a) shows a synchronization signal input to the correction unit 14. FIG. 5(b) shows the corrected synchronization signal output by the correction unit 14. The rising edge of each pulse in FIGS. 5(a) and 5(b) is indicated by an arrow. At time t0, the first pulse of the input synchronization signal rises, and the first pulse of the output synchronization signal also rises at the same timing. A reference timing after a set period T from this timing (time t0) is indicated by a broken line arrow. The period from the timing before the reference timing by the error setting value β to the reference timing is the error range. In FIG. 5, the set error range is dotted. At time t1, the second pulse of the input synchronizing signal rises, and since the rising timing is within the error range, the second pulse of the output synchronizing signal also rises at the same timing. The period from the timing before the reference timing (broken line arrow) by the error setting value β after the setting cycle T of this timing (time t1) to the reference timing is the next error range.

At time t2, the third pulse of the input synchronization signal rises, and the timing of this rise is before the error range. In other words, this is a range in which the advance of the synchronization signal is not allowed. Therefore, the third pulse of the synchronization signal to be output rises at the earliest timing within the error range, that is, at time t2', which is the timing before the reference timing by the error setting value β. The period from the timing before the reference timing (broken line arrow) by the error setting value β after the setting cycle T of this timing (time t2') to the reference timing is the next error range. At time t3, the fourth pulse of the input synchronizing signal rises, and since the rising timing is within the error range, the fourth pulse of the output synchronizing signal also rises at the same timing.

In the flowchart shown in FIG. 6, the same processes as those in the flowchart shown in FIG. 4 are given the same numbers and their explanations are omitted. Steps S1 to S3 are the same as those in FIG. 4.

After the error range is set in step S3, it is determined whether a pulse is input (S4). The determination in step S4 is repeated until a pulse is input (S4: NO). If a pulse is input (S4: YES), it is determined whether or not it is within the error range (S11). If it is within the error range (S11: YES), a pulse is output (S6). Specifically, the correction unit 14 outputs a pulse to the signal output unit 15 at the same timing as the pulse input from the signal input unit 11.

In step S11, if it is not within the error range (S11: NO), that is, if it is before the error range, it is determined whether or not the error range has started (S12). The determination in step S12 is repeated until the error range starts (S12: NO). If the error range has started (S12: YES), a pulse is output (S6). Specifically, the correction unit 14 outputs a pulse to the signal output unit 15 at the timing when the error range starts. Note that the correction processing performed by the periodic signal corrector A2 is not limited to that described above.

According to this embodiment, when the timing of the rise of the pulse that is the synchronization signal is before the error range, the correction unit 14 performs the correction at the earliest timing within the error range, that is, before the reference timing by the error setting value β. A pulse that rises at the timing of is generated and output as a corrected synchronization signal. Therefore, the periodic signal corrector A2 can correct the synchronization signal inputted from the synchronization signal generator 2 so that the rising edge of the pulse does not exceed the error range, and can suppress disturbances due to progression of the synchronization signal. Thereby, the periodic signal corrector A2 can suppress synchronization from being disrupted even if the synchronization signal generated by the synchronization signal generator 2 advances.

In addition, according to this embodiment, the error range setting unit 13 sets the error range between the reference timing and the timing that precedes the reference timing by the error setting value β. Therefore, the periodic signal corrector A2 can correct the advance of the synchronization signal.

FIGS. 7 and 8 are diagrams for explaining the periodic signal corrector A3 according to the third embodiment. FIG. 7 is a timing chart for explaining the correction process performed by the periodic signal corrector A3. FIG. 8 is an example of a flowchart for explaining the correction process performed by the periodic signal corrector A3. The diagram showing the internal configuration of the periodic signal corrector A3 is the same as FIG. 1, so the description is omitted.

The periodic signal corrector A3 according to the third embodiment differs from the periodic signal corrector A1 in that it performs correction whether the synchronization signal output from the synchronization signal generator 2 is delayed or advances.

The periodic signal corrector A3 according to the third embodiment outputs the synchronization signal as is if the delay or advance of the synchronization signal is within the allowable error. On the other hand, if the delay or advance of the synchronization signal is outside the allowable error, the periodic signal corrector A3 corrects the synchronization signal so that it falls within the allowable range and outputs it. The functions of the signal input unit 11, reference setting unit 12, and signal output unit 15 of the periodic signal corrector A3 are similar to those of the signal input unit 11, reference setting unit 12, and signal output unit 15 of the periodic signal corrector A1.

The error range setting unit 13 sets the error range between the timing that is the error setting value β before the reference timing and the timing that is the error setting value α after the reference timing.

When the timing of the rising edge of the pulse of the synchronization signal is within the error range based on the rising edge of the pulse of the synchronization signal after the previous correction, the correction unit 14 determines that the delay or advance of the synchronization signal is within the allowable error range. In this case, the correction unit 14 generates and outputs a synchronization signal that is the same as the input synchronization signal. Note that when the synchronization signal is first input, the reference timing is not set and the error range is not set, so the correction unit 14 generates and outputs a synchronization signal that is the same as the input synchronization signal. On the other hand, when the timing of the rising edge of the pulse of the synchronization signal is after the error range, the correction unit 14 determines that the delay of the synchronization signal is within the unallowable range. In this case, the correction unit 14 generates a pulse that rises at the last timing within the error range, that is, at the timing when the error setting value α has elapsed from the reference timing, and outputs it as the synchronization signal after correction. Also, when the timing of the rising edge of the pulse of the synchronization signal is before the error range, the correction unit 14 determines that the advance of the synchronization signal is within the unallowable range. In this case, the correction unit 14 generates a pulse that rises at the earliest timing within the error range, that is, at a timing that is the error setting value β earlier than the reference timing, and outputs it as the corrected synchronization signal.

FIG. 7 is a timing chart for explaining the correction processing performed by the periodic signal corrector A3. FIG. 7(a) shows a synchronization signal input to the correction unit 14. FIG. 7(b) shows the corrected synchronization signal output by the correction unit 14. The rising edge of each pulse in FIGS. 7(a) and 7(b) is indicated by an arrow. At time t0, the first pulse of the input synchronization signal rises, and the first pulse of the output synchronization signal also rises at the same timing. A reference timing after a set period T from this timing (time t0) is indicated by a broken line arrow. The period from the timing before the reference timing by the error setting value β to the timing after the reference timing by the error setting value α is the error range. In FIG. 7, the set error range is dotted. At time t1, the second pulse of the input synchronizing signal rises, and since the rising timing is within the error range, the second pulse of the output synchronizing signal also rises at the same timing. The period from the timing before the error setting value β of the reference timing (broken line arrow) after the setting cycle T of this timing (time t1) to the timing after the error setting value α of the reference timing is the next error range. be.

At time t2, the third pulse of the input synchronization signal rises, and the timing of this rise is after the error range. In other words, it is within the range where delay of the synchronization signal is not allowed. Therefore, the third pulse of the output synchronization signal rises at time t2', which is the last timing within the error range, that is, the timing that is the error setting value α after the reference timing.

Furthermore, at time t4, the fifth pulse of the input synchronization signal rises, and the timing of this rise is before the error range. In other words, this is a range in which the advance of the synchronization signal is not allowed. Therefore, the fifth pulse of the synchronization signal to be output rises at the earliest timing within the error range, that is, at time t4', which is the timing before the reference timing by the error setting value β.

In the flowchart shown in FIG. 8, the same processes in the flowchart shown in FIG. 4 or 5 are given the same numbers, and the description thereof is omitted. The flowchart shown in FIG. 8 is a modified version of the flowchart shown in FIG. 4, with the processing performed when step S4 is YES.

In step S4, if a pulse is input before the end of the error range (S4: YES), it is determined whether or not it is before the error range (S21). If it is before the error range (S21: YES), it is determined whether the error range has started (S12). The determination in step S12 is repeated until the error range starts (S12: NO). If the error range has started (S12: YES), a pulse is output (S6). Specifically, the correction unit 14 outputs a pulse to the signal output unit 15 at the timing when the error range starts.

In step S21, if it is not before the error range (S21: NO), that is, if it is within the error range, a pulse is output (S6). Specifically, the correction unit 14 outputs a pulse to the signal output unit 15 at the same timing as the pulse input from the signal input unit 11.

In step S5, if the error range ends before the pulse is input (S5: YES), the pulse is output (S6). Specifically, the correction unit 14 outputs a pulse to the signal output unit 15 at the timing when the error range ends. Note that the correction processing performed by the periodic signal corrector A3 is not limited to that described above.

According to the present embodiment, when the rising timing of the pulse that is the synchronization signal is after the error range, the correction unit 14 corrects the timing at the last timing within the error range, that is, at the timing when the error setting value α has elapsed from the reference timing. It generates a pulse that rises at , and outputs it as a corrected synchronization signal. In addition, when the timing of the rise of the pulse that is the synchronization signal is before the error range, the correction unit 14 rises at the earliest timing within the error range, that is, at the timing that is earlier than the reference timing by the error setting value β. Generates a pulse and outputs it as a corrected synchronization signal. Therefore, the periodic signal corrector A3 can correct the synchronization signal input from the synchronization signal generator 2 so that the rising edge of the pulse does not exceed the error range, and can suppress disturbances caused by delays or advances in the synchronization signal. . Thereby, the periodic signal corrector A3 can suppress disruption of synchronization even when the synchronization signal generated by the synchronization signal generator 2 is delayed or advanced.

Further, according to the present embodiment, the error range setting unit 13 sets the period from the timing before the reference timing error setting value β to the timing after the reference timing error setting value α as the error range. . Therefore, the periodic signal corrector A3 can correct the delay of the synchronization signal, and can also correct the advance of the synchronization signal.

In the above first to third embodiments, the periodic signal correctors A1 to A3 correct the synchronization signal generated by the synchronization signal generator 2, but this is not limited to the above. The periodic signal corrector A1 can also be used to correct disturbances caused by delays in periodic signals other than the synchronization signal. In other words, the periodic signal corrector A1 is configured to correct a periodic signal that has been disturbed by delays or the like to within an acceptable error range, regardless of synchronization with other devices.

The periodic signal corrector and control circuit of the present invention are not limited to the above-mentioned embodiment. The specific configuration of each part of the periodic signal corrector and control circuit of the present invention can be freely designed in various ways.

A1 to A3: periodic signal corrector, 11: signal input section, 12: reference setting section, 13: error range setting section, 14: correction section, 15: signal output section, 2: synchronization signal generator, 21: internal value Generation unit, 22: Communication unit, 23: Synchronization signal generation unit, B: Control circuit

Claims (4)

a signal input unit to which a periodic signal indicating timing is input;
a correction unit that corrects the input periodic signal into a corrected periodic signal;
a reference setting unit that sets a reference timing based on the timing indicated by the corrected periodic signal and a set period;
an error range setting unit that sets an error range based on the reference timing;
a signal output unit that outputs the corrected periodic signal;
Equipped with
the correction unit sets the periodic signal as the corrected periodic signal when the timing indicated by the periodic signal is within the error range based on the previous corrected periodic signal, and when the timing indicated by the periodic signal is not within the error range, corrects the timing indicated by the periodic signal to be within the error range and sets the corrected periodic signal.
Periodic signal corrector. When the timing indicated by the periodic signal is after the error range, the correction unit corrects the timing indicated by the periodic signal to the last timing within the error range.
2. The periodic signal corrector according to claim 1. When the timing indicated by the periodic signal is before the error range, the correction unit corrects the timing indicated by the periodic signal to the earliest timing within the error range.
The periodic signal corrector according to claim 1. A periodic signal corrector according to any one of claims 1 to 3,
a synchronization signal generator that generates a synchronization signal as the periodic signal and inputs it to the signal input section;
Equipped with
The synchronization signal generator is
an internal value generation unit that generates an internal value;
a communication unit that communicates with at least one other synchronization signal generator;
a synchronization signal generation unit that generates the synchronization signal based on the internal value after convergence;
Equipped with
The communication unit transmits the internal value generated by the internal value generation unit to at least one of the other synchronization signal generators,
The internal value generation unit generates the internal value using a calculation result based on the generated internal value and an internal value received by the communication unit from at least one of the other synchronization signal generators.
control circuit.

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