JP2023141264A - Device with communication function - Google Patents

Abstract

To provide a device that is able to suppress influence of delay or noise on synchronization of an internal value and is able to suppress an increase in time taken for the synchronization.SOLUTION: A device A is provided with an internal-value generation unit 31 that generates an internal value Xi and a communication unit 34 that communicates with at least one other device A. The communication unit 34 transmits the internal value, generated by the internal-value generation unit 31, to at least one of the other devices A. The internal-value generation unit 31 can be switched between a first phase in which the generated internal value Xi is updated by a first method using a calculation result based on the generated internal value Xi and an internal value Xj received by the communication unit 34 from the at least one of the other devices A and a second phase in which the generated internal value Xi and the received internal value Xj are closer to synchronization than in the first phase and in which the generated internal value Xi is updated by a second method different from the first method.SELECTED DRAWING: Figure 1

Description

The present invention relates to a device that has a communication function and can match internal values by transmitting and receiving internal values to and from other devices.

A method has been developed in which the internal values of a plurality of devices are matched by each device transmitting and receiving internal values through communication, instead of being matched by a management device that manages all of these devices. In this method, each device transmits and receives an internal value to at least one other device, and updates the internal value using a calculation result based on the generated internal value and the received internal value. By performing this process in each device, the internal values of each device converge to the same value. As an example of using this method, Patent Document 1 describes synchronizing the internal phases of inverter devices, and Patent Document 2 describes that by matching the compensation values of each inverter device, the amount of suppression of output active power is reduced. Patent Document 3 describes that each measuring device makes the internal average values based on the measured values coincide with each other to calculate the overall average value.

JP2015-027155A JP2015-084612A Japanese Patent Application Publication No. 2015-166901

Reza Olfati-Saber, J. Alex Fax, and Richard M. Murray, “Consensus and Cooperation in Networked Multi-Agent Systems”, Proceedings of the IEEE, Vol.95, No.1, (2007) Mehran Mesbahi and Magnus Egerstedt, “Graph Theoretic Methods in Multiagent Networks”, Princeton (2010)

However, in this method, communication delays, internal processing delays, noise, etc. have a large effect on the synchronization of internal values. For example, an internal value transmitted by a certain device may become an abnormal value in the receiving device due to a sudden delay or noise superimposed on the communication path. Furthermore, the generated internal value may become an abnormal value due to a delay in internal processing within the device. Each device updates its internal values using calculation results based on generated internal values and received internal values, so if an abnormal value is mixed in with the internal values used for calculation, the synchronization of the internal values will be disrupted. . For example, when a generated internal value becomes an abnormal value, first, the internal value updated in the device concerned deviates greatly from the internal value of other devices. Since the internal value of the device is sent to another device, the internal value of the device that receives it is also updated to an abnormal value. After that, the internal values of each device converge, but during this period, the synchronization is disrupted. Depending on the device, a problem may occur if the internal value deviates significantly from the internal value of another device, or if the state of disturbed synchronization continues for a certain amount of time. For example, in the case of the inverter device described in Patent Document 1, the inverter device may stop due to the synchronization of the internal phase, which is an internal value, being disrupted. On the other hand, if the specifications are made to be less susceptible to delay or noise, there is a problem in that it takes longer to synchronize.

The present invention has been devised under the circumstances described above, and provides a device that can suppress the influence of delay or noise on synchronization of internal values, and can also suppress the lengthening of time until synchronization. Its purpose is to provide.

In order to solve the above problems, the present invention takes the following technical measures.

A device provided by a first aspect of the present invention includes an internal value generation means for generating an internal value, and a communication means for communicating with at least one other device, and the communication means is configured to generate the internal value. The generating means transmits the generated internal value to at least one of the other devices, and the internal value generating means transmits the generated internal value and the communication means receives the generated internal value from the at least one of the other devices. In a first method using a calculation result based on an internal value, a first phase in which the generated internal value is updated, and the generated internal value and the received internal value are synchronized from the first phase. It is characterized in that the generated internal value is updated in a second phase in which the generated internal value is updated by a second method different from the first method.

In a preferred embodiment of the present invention, the internal value generating means subtracts each of the generated internal values from the received internal value, and multiplies a total difference value obtained by adding all the subtraction results by a first coefficient. Accordingly, the calculation result is calculated, and the first method performs updating by adding the calculation result to the generated internal value.

In a preferred embodiment of the present invention, the second method includes correcting the total difference value to a value within a first range, and multiplying the corrected total difference value by the first coefficient, Update is performed by adding to the generated internal value.

In a preferred embodiment of the present invention, the second method updates the generated internal value by adding a value obtained by multiplying the total difference value by a second coefficient smaller than the first coefficient to the generated internal value. I do.

In a preferred embodiment of the present invention, the second method leaves the generated internal value unchanged.

In a preferred embodiment of the present invention, the internal value generation means switches between the first phase and the second phase based on the total difference value.

In a preferred embodiment of the present invention, the internal value generation means switches from the first phase to the second phase when the total difference value remains within the second range for a predetermined number of times.

In a preferred embodiment of the present invention, the internal value generating means is configured such that the generated internal value and the received internal value are closer to synchronization than in the first phase and further out of synchronization than in the second phase. The state is further switched to a third phase in which the generated internal value is updated by a third method different from the first method and the second method.

According to the present invention, the internal value generation means performs the update using the second method in the second phase, which is closer to synchronization than the first phase. By using the second method, which takes longer to synchronize than the first method, but is less susceptible to delay or noise, the internal value generation means can be synchronized in the first phase away from synchronization. In the second phase, when synchronization approaches, updates are performed that are less susceptible to delay or noise. Thereby, the device according to the present invention can suppress the influence of delay or noise on synchronization of internal values, and can also suppress an increase in time until synchronization.

Other features and advantages of the invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

1 is a diagram for explaining a communication system according to a first embodiment, in which (a) is a diagram showing the communication state of a plurality of devices that constitute the communication system, and (b) is a block diagram showing the internal configuration of each device; FIG. It is a diagram. FIG. 3 is a diagram for explaining phase switching. (a) is an example of a flowchart for explaining the phase switching process performed by the phase switching unit, and (b) is an example of a flowchart for explaining the internal value update process performed by the internal value generation unit. FIG. 2 is a diagram showing simulation results in the communication system of FIG. 1. FIG. It is an example of the flowchart for demonstrating the update process of an internal value performed by the internal value generation part in a modification. It is an example of the flowchart for demonstrating the update process of an internal value performed by the internal value generation part in a modification.

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a diagram for explaining a communication system B including a device A according to the first embodiment. FIG. 1A is a diagram showing the communication status of a plurality of devices A that constitute a communication system B. FIG. FIG. 1(b) is a block diagram showing the internal configuration of each device A. In this embodiment, each device A is a distributed power source, and the communication system B synchronizes the internal phases of the inverter devices of the devices A (distributed power sources) connected in parallel with each other.

As shown in FIG. 1(a), each device A communicates with other devices A, and the entire communicating devices A constitute a network. FIG. 1(a) shows a state in which five devices A (A1 to A5) constitute a network. Note that although the actual network is composed of a larger number of devices A, an extremely small number of devices A is shown to simplify the explanation.

The solid arrows shown in FIG. 1(a) indicate that mutual communication is being performed. In this embodiment, each of the devices A1 to A5 is in mutual communication with all other devices A. Note that in the communication system B, it is not necessary for each of the devices A1 to A5 to mutually communicate with all other devices A. Each device A is communicating with at least one device A (for example, one located nearby or with which communication has been established) among the devices A making up the network, and forming the network. Any state in which a communication path exists between any two devices A (hereinafter, this state will be referred to as a "connected state") may be sufficient.

As shown in FIG. 1(b), in this embodiment, the device A is a distributed power source and includes a DC power source 1, an inverter circuit 2, and a control circuit 3. Device A converts DC power output from a DC power supply 1 into AC power using an inverter circuit 2 and outputs the converted AC power. A combination of the inverter circuit 2 and the control circuit 3 is an inverter device, which is called a power conditioner. Note that the configuration of device A is not limited.

The DC power supply 1 outputs DC power and includes, for example, a solar cell. Solar cells generate DC power by converting sunlight energy into electrical energy. The DC power supply 1 outputs the generated DC power to the inverter circuit 2. Note that the DC power source 1 is not limited to one that generates DC power using a solar cell. The inverter circuit 2 converts DC power input from the DC power supply 1 into AC power and outputs the AC power. The inverter circuit 2 converts DC power into AC power by switching each switching element on and off based on a PWM signal input from the control circuit 3. Note that the configuration of the inverter circuit 2 is not limited.

The control circuit 3 controls the inverter circuit 2, and is realized by, for example, a microcomputer. The control circuit 3 generates a PWM signal based on the input voltage, output voltage, output current, etc. of the inverter circuit 2 detected by each sensor provided in the device A, and outputs the PWM signal to the inverter circuit 2. The control circuit 3 includes an internal value generation section 31, a command signal generation section 32, a PWM signal generation section 33, and a communication section 34.

The internal value generation unit 31 generates an internal phase used to generate a command signal as an internal value _Xi . In this specification, the internal value generated by the own device (i-th device A) is expressed as X _i . When the number of devices A is n (n=5 in the example of FIG. 1(a)), i is a natural number from 1 to n. Details of the internal value generation section 31 will be described later.

The command signal generation section 32 generates a command signal for controlling the output voltage. The command signal generation unit 32 performs so-called three-phase/two-phase conversion processing (αβ conversion processing) and rotational coordinate conversion processing (dq conversion processing) on the three-phase voltage signal detected as the output voltage of the inverter circuit 2. Convert to axis component and q-axis component signals. Three-phase/two-phase conversion processing is a process that converts a three-phase AC signal into an equivalent two-phase AC signal, and converts a three-phase AC signal into a stationary orthogonal coordinate system (hereinafter referred to as a "stationary coordinate system"). By decomposing the signal into orthogonal α-axis and β-axis components and adding the components of each axis, an AC signal of the α-axis component and an AC signal of the β-axis component are converted. In addition, rotational coordinate conversion processing is processing that converts two-phase signals (α-axis component and β-axis component) of a stationary coordinate system into two-phase signals (d-axis component and q-axis component) of a rotating coordinate system. . The rotating coordinate system is an orthogonal coordinate system that has orthogonal d and q axes and rotates at a predetermined angular frequency ω ₀ . The rotational coordinate conversion process is performed based on the internal value X _i (internal phase) input from the internal value generation unit 31.

The command signal generation unit 32 extracts only the DC component from the d-axis component and the q-axis component of the voltage signal, performs control processing on each separately, and performs stationary coordinate transformation processing (inverse dq transformation processing) and dual Phase/three-phase conversion processing (inverse αβ conversion processing) is performed to convert into three compensation signals. The stationary coordinate conversion process is the opposite of the rotating coordinate conversion process, and the two-phase/three-phase conversion process is the opposite of the three-phase/two-phase conversion process. The stationary coordinate conversion process is performed based on the internal value X _i (internal phase) input from the internal value generation unit 31. The command signal generation section 32 generates three command signals from the sine wave signal generated based on the internal value X _i input from the internal value generation section 31 and the three compensation signals, and generates three command signals from the PWM signal generation section. Output to 33. The command signal generation unit 32 controls the input voltage of the inverter circuit 2, but a description thereof will be omitted. In this embodiment, a case has been described in which the apparatus A is a three-phase system, but it may be a single-phase system. In the case of a single-phase system, the command signal generation unit 32 may control a single-phase voltage signal obtained by detecting the output voltage of the inverter circuit 2.

The PWM signal generation section 33 generates a PWM signal. The PWM signal generation section 33 generates a PWM signal using a triangular wave comparison method based on the carrier signal and the command signal inputted from the command signal generation section 32. For example, a pulse signal that becomes a high level when the command signal is greater than the carrier signal and becomes a low level when the command signal is less than or equal to the carrier signal is generated as a PWM signal. The generated PWM signal is output to the inverter circuit 2. Note that the configuration of the PWM signal generation section 33 is not limited.

The communication unit 34 communicates with other devices A. The communication unit 34 receives the internal value X _i generated by the internal value generation unit 31 and transmits it to the communication unit 34 of the other device A. Further, the communication unit 34 outputs the internal value X _j received from the communication unit 34 of another device A to the internal value generation unit 31. In this specification, the internal value received from the j-th device A among the other devices A is expressed as X _j . j is a natural number from 1 to n. Note that the communication method is not limited, and may be wired communication or wireless communication.

The internal value generation unit 31 generates and outputs an internal value X _i that changes over time. Further, the internal value generation section 31 updates the internal value X _i using the generated internal value X _i and the internal value X _j of another device A inputted from the communication section 34 . Even if the internal value X _i and the internal value X _j are different, the internal value X _i and the internal value X _j converge to the same value by repeating the update process in the internal value generation unit 31. Thereby, the communication system B can synchronize the internal values X _i of each device A. In this embodiment, the internal value generation unit 31 is switched between the first phase and the second phase. In the second phase, the internal value X _i is closer to synchronization than in the first phase. The internal value generation unit 31 updates the internal value X _i using different methods depending on the phase. As shown in FIG. 1B, the internal value generation section 31 includes a calculation section 311, a phase switching section 315, a multiplier 312, an adder 313, and an integrator 314.

The calculation unit 311 performs calculation based on the following equation (1) every update period Δt. Although the update period Δt is not limited, it is, for example, about 1 second in this embodiment. The internal value X _i and the internal value X _j change over time, and the values at time t are written as X _i (t) and X _j (t), respectively. The calculation unit 311 subtracts each internal value X _i generated by the internal value generation unit 31 from each internal value X _j input from the communication unit 34, and calculates a total difference value D _i by adding all the subtraction results. . The coefficient _aij is set to "1" or "0". The coefficient a _ij is set to "1" for the internal value X _j that the communication unit 34 receives, and the coefficient a _ij is set to "0" for the internal value X _j that is not received. The calculation unit 311 outputs the calculated total difference value D _i to the phase switching unit 315.

The phase switching section 315 switches between the first phase and the second phase based on the total difference value D _i input from the calculation section 311 . The closer the internal value X _i and each internal value X _j become to synchronization, the closer the total difference value D _i approaches "0". The phase switching unit 315 uses the total difference value D _i as an index for determining the synchronization state, sets a state where the absolute value of the total difference value D _i is large and is not yet close to synchronization as a first phase, and sets the total difference value D i to a first phase. A state in which the absolute value of _i is small and synchronization is approaching is defined as a second phase. The phase switching unit 315 switches from the first phase to the second phase when the first condition is satisfied in the first phase. The first condition is a condition for determining that synchronization is approaching, and in this embodiment, the absolute value of the total difference value D _i is smaller than the threshold value Dx, that is, the total difference value D _i is (-Dx<D _i <Dx) has continued for a predetermined number of times _N1 . The threshold value Dx is set as a guideline for switching the phase. Note that the threshold value Dx is not limited and is appropriately set depending on the target synchronization accuracy, the number n of devices A, and the like. Further, the predetermined number of times _N1 is not limited, but in this embodiment, it is set to "2" or more in order to exclude the case where the threshold value Dx is instantaneously exceeded (in this embodiment, it is set to "2"). ).

FIG. 2 is a diagram for explaining phase switching when the internal value X _i and each internal value X _j approach synchronization. In FIG. 2, the total difference value D _i for each update period Δt is shown. From the state in which the total difference value D _i was large in the first phase, the total difference value D _i gradually decreased, and the state in which the total difference value D _i was smaller than the threshold value Dx was repeated twice, so that the first condition Assuming that the following is satisfied, the first phase is switched to the second phase. Note that although FIG. 2 shows a case where the total difference value D _i decreases from a large state, the total difference value D _i may also be a negative value. In this case, if the state in which the total difference value D _i is smaller than the first phase and the state in which the total difference value D _i is larger than (-Dx) is repeated twice, it is assumed that the first condition is satisfied. The first phase is switched to the second phase.

The phase switching unit 315 performs different processing depending on the phase. In the case of the first phase, the phase switching unit 315 outputs the total difference value D _i to the multiplier 312 as is. On the other hand, in the case of the second phase, the phase switching unit 315 corrects the total difference value D _i to a range of (T _L ≦D _i ≦T _H ). That is, when the total difference value D _i input _from the calculation unit 311 is smaller than the lower limit value TL, the total difference value D _i is corrected to T _L , and the total difference value D _i input from the calculation unit 311 becomes the upper limit value. If it is larger than T _H , the total difference value D _i is corrected to T _H. Then, the phase switching unit 315 outputs the corrected total difference value D _i to the multiplier 312 . The upper limit value T _H is set to a value smaller than the threshold value Dx, for example, a value about half of the threshold value Dx. Further, the lower limit value T _L is set to a value larger than (-Dx), for example, a value about half of (-Dx). Note that the upper limit value T _H and the lower limit value T _L are not limited. The upper limit value T _H and the lower limit value T _L are appropriately set so that the apparatus A is not affected (for example, does not stop) by the internal value X _i updated by the corrected total difference value D _i .

Further, the phase switching unit 315 switches from the second phase to the first phase when the second condition is satisfied in the second phase. The second condition is a condition for determining that synchronization has departed, and in this embodiment, a state in which the total difference value D _i output by the phase switching unit 315 is the upper limit value T _H or the lower limit value T _L , that is, This means that a state in which the total difference value D _i input from the calculation unit 311 is greater than or equal to the upper limit value T _H or less than or equal to the lower limit value T _L continues for a predetermined number of times N ₂ . Note that the predetermined number of times _N2 is not limited, but is, for example, "2" in this embodiment.

FIG. 3A is an example of a flowchart for explaining the phase switching process performed by the phase switching unit 315. The phase switching process is executed every update period Δt.

First, the total difference value D _i is acquired from the calculation unit 311 (S1). Next, it is determined whether the current phase is the first phase (S2). If it is the first phase (S2: YES), it is determined whether the absolute value of the total difference value D _i is smaller than the threshold value Dx (S3). If the absolute value of the total difference value D _i is smaller than the threshold value Dx (S3: YES), it is determined whether the determination is the _N1th time (S4). If the determination is the _N1th time (S4: YES), it is assumed that the first condition is satisfied, the first phase is switched to the second phase (S5), and the phase switching process ends. If the absolute value of the total difference value D _i is greater than or equal to the threshold value Dx (S3: NO), or if the determination that the absolute value of the total difference value D _i is smaller than the threshold value Dx is not the N _1st time (S4: NO), The phase switching process ends without switching the phase.

On the other hand, if it is not the first phase (S2: NO), that is, if it is the second phase, it is determined whether the corrected total difference value D _i is the upper limit value T _H or the lower limit value T _L (S6 ). When the corrected total difference value D _i is the upper limit value T _H or the lower limit value T _L (S6: YES), it is determined whether or not the determination is the N _second time (S7). If the determination is the N _second time (S7: YES), it is assumed that the second condition is satisfied, the second phase is switched to the first phase (S8), and the phase switching process ends. If the total difference value D _i is not the upper limit value _TH or the lower limit value _TL (S6: NO), or the determination that the total difference value D _i is the upper limit value _TH or the lower limit value _TL is not _{the second} time. In this case (S7: NO), the phase is not switched and the phase switching process ends. Note that the phase switching process performed by the phase switching unit 315 is not limited to that described above.

Multiplier 312 multiplies the total difference value D _i input from phase switching section 315 by a predetermined coefficient ε, and outputs the result to adder 313 . The coefficient ε is a value that satisfies 0<ε<1/d _max and is set in advance. d _max is the largest number among all the devices A that make up the communication system B, out of d _i which is the number of other devices A with which the communication unit 34 communicates. The coefficient ε is multiplied in order to prevent the value added to the integrator 314 from becoming too large (small) and the variation in the internal value X _i from becoming too large.

Adder 313 adds the input from multiplier 312 and a predetermined angular frequency ω ₀ and outputs the result to integrator 314 as a modified angular frequency ω _i . The integrator 314 integrates the corrected angular frequency ω _i input from the adder 313 to generate and output an internal value X _i . The integrator 314 generates the internal value X _i by adding the modified angular frequency ω _i to the previously generated internal value X _i . That is, the integrator 314 always generates the internal value X _i by adding the angular frequency ω ₀ to the internal value X _i . Further, the integrator 314 updates the internal value X _i by adding the output from the multiplier 312 to the internal value X _i in addition to the angular frequency ω ₀ at the update timing every update period Δt. Further, the integrator 314 outputs the internal value X _i as a value in the range of (-π<X _i ≦π). Note that the method of setting the range of the internal value X _i is not limited to this, and may be, for example, (0≦X _i <2π). Integrator 314 outputs internal value X _i to command signal generation section 32, communication section 34, and calculation section 311.

In the case of the first phase, the internal value X _i generated by the internal value generation unit 31 is expressed by the following equation (2) and the following equation (3). Equation (2) below represents the calculation at the update timing. Equation (3) below represents calculation between update timings. On the other hand, in the case of the second phase, the internal value X _i generated by the internal value generation unit 31 is expressed by the following equation (4) and the following equation (3). Equation (4) below represents the calculation at the update timing. The internal value X _i generated between update timings is the same as in the first phase, and is expressed by the following equation (3).

The internal value generation unit 31 updates the internal value X _i at every update period Δt. By performing this update in each device A, the internal values X _i of each device A converge to the same value. The internal value X _i changes with time, and can be thought of as a combination of a component that changes according to the angular frequency ω ₀ and a component that changes to compensate for the initial phase shift. As the latter converges to the same value X _α , the internal value X _i of each device A also converges to the same value. It has also been mathematically proven that the latter converges to the same value (see Non-Patent Documents 1 and 2). It has also been proven that the convergence value X _α is the arithmetic mean value of the initial values of the internal values X _i of each device A, as shown in equation (5) below. Equation (5) below indicates that the arithmetic average value is calculated by adding all the initial values of the internal values X ₁ to X _n of the devices A1 to An and dividing the sum by n.

FIG. 3B is an example of a flowchart for explaining the process of updating the internal value X _i performed by the internal value generation unit 31. The update process is executed every update cycle Δt.

First, the total difference value D _i is calculated (S11). Specifically, the calculation unit 311 calculates the total difference value D _i based on the above equation (1). Next, it is determined whether it is the first phase or not (S12). Specifically, the phase switching unit 315 determines whether the current phase is the first phase. If it is the first phase (S12: YES), the internal value X _i is updated (S13), and the update process ends. In this case, the internal value X _i is updated using the above equation (2).

On the other hand, if it is not the first phase (S12: NO), that is, if it is the second phase, it is determined whether the total difference value D _i is smaller than the lower limit T _L (S14). If the total difference value D _i is smaller than the lower limit value T _L (S14: YES), the total difference value D _i is corrected to the lower limit value T _L (S15), and the process proceeds to step S13. If the total difference value D _i is greater than or equal to the lower limit value T _L (S14: NO), it is determined whether the total difference value D _i is greater than the upper limit value T _H (S16). If the total difference value D _i is larger than the upper limit value _TH (S16: YES), the total difference value D _i is corrected to the upper limit value _TH (S17), and the process proceeds to step S13. If the total difference value D _i is less than or equal to the upper limit value _TH (S16: NO), the total difference value D _i is greater than or equal to the lower limit value _TL and less than or equal to the upper limit value _TH , so the process proceeds to step S13 with the total difference value D _i unchanged. move on. In other words, in the second phase, the internal value X _i is updated using the above equation (4). Note that the process of updating the internal value X _i performed by the internal value generation unit 31 is not limited to that described above.

In this embodiment, a case has been described in which the control circuit 3 is implemented as a digital circuit, but it may also be implemented as an analog circuit. Alternatively, the computer may function as the control circuit 3 by designing a program to perform the processing performed by each section and executing the program. Alternatively, the program may be recorded on a recording medium and read by a computer.

FIG. 4 is a diagram showing simulation results for communication system B in FIG. 1. This simulation is a simulation in which noise is mixed into the internal value X ₁ at time t0 in a state where the internal values X _i (i=1 to 5) are synchronized. It shows the change in X _i . FIG. 4(b) shows simulation results for five devices A. Each device A switches between the first phase and the second phase, but since they are in a synchronized state, they are in the second phase. Figure 4(a) shows the simulation results for comparison, and shows the case where five devices A are updated in the first phase without switching to the second phase (i.e. using the same method as before). This shows the simulation results for the case where the update was performed with

As shown in FIG. 4(a), if the update is performed in the first phase, in the update after time t0, the internal value X ₁ becomes an abnormal value, and the other internal values X _i There is a big difference. Then, by transmitting the internal value X ₁ to the other device A, the other internal values X _i also become abnormal values. After that, each internal value X _i converged and became synchronized, but since the internal value X ₁ deviated greatly from the other internal values X _i , it took a long time to converge, and the state of being out of synchronization continued for a long time. are doing. In the case of device A, the internal value X _i is used as the internal phase of the inverter device. Therefore, when the synchronization of the internal value X _i is disturbed, a circulating current flows between the inverter circuits 2 connected in parallel with each other, and the inverter device may be stopped due to overcurrent.

On the other hand, as shown in FIG. 4(b), when the update is performed in the second phase, the total difference value D _i calculated in the update after time t0 is corrected, so that _the internal value It does not deviate greatly from the internal value X _i . Therefore, the time it takes for each internal value X _i to converge and become synchronized is short, and the state in which the synchronization is disturbed is short. As described above, it can be understood that device A can suppress the influence of delay or noise on internal value synchronization in the second phase when synchronization approaches.

Next, the effects of device A will be explained.

According to this embodiment, the internal value generation unit 31 updates the internal value X _{i using the generated internal value X i} and the internal value X _j of the other device A received by _the communication unit 34 . The internal value generation unit 31 of each device A similarly updates, so that the internal values X _i of all devices A converge to the same value. Furthermore, the internal value generation unit 31 uses different updating methods depending on the phase that is switched depending on the synchronization state. In the second phase, which is closer to synchronization than the first phase, the internal value generation unit 31 updates the internal value X _i by the calculation expressed by the above equation (4). Since the total difference value D _i is corrected to the range (T _L ≦D _i ≦ _TH ), even if each internal value X _j or internal value X _i contains an abnormal value, the total difference value D _i is suppressed from becoming an abnormal value. Thereby, device A can suppress the influence of delay or noise on internal value synchronization in the second phase when synchronization approaches. Further, in the first phase, which is farther from synchronization than the second phase, the internal value generation unit 31 updates the internal value X _i by the calculation expressed by the above equation (2). Since the total difference value D _i is not corrected, synchronization can be brought closer to synchronization earlier than in the second phase. Thereby, device A can suppress an increase in time until synchronization. Note that since the first phase is far from synchronization, even if the total difference value D _i becomes an abnormal value, the effect on the synchronization of internal values is small.

Further, according to the present embodiment, in the case of the second phase, the phase switching unit 315 corrects the total difference value D _i to a range of (T _L ≦D _i ≦T _H ). Therefore, even if a delay or noise occurs in the second phase, device A can prevent the updated internal value X _i from changing significantly.

Further, according to the present embodiment, the phase switching unit 315 switches between the first phase and the second phase based on the total difference value D _i input from the calculation unit 311. The total difference value D _i approaches "0" as the internal value X _i and each internal value X _j approach synchronization, and therefore is suitable as an index for determining the synchronization state. Therefore, device A can appropriately switch between the first phase and the second phase.

Further, according to the present embodiment, the phase switching unit 315 controls the phase switching unit 315 when the state in which the total difference value D _i is within the range of (-Dx<D _i <Dx) continues for a predetermined number of times N ₁ . , switches from the first phase to the second phase. Therefore, device A can appropriately switch to the second phase when it approaches synchronization. Further, according to the present embodiment, in the second phase, when the state in which the total difference value D _i is the upper limit value T _H or the lower limit value T _L continues for a predetermined number of times N ₂ Switch from phase to first phase. Therefore, device A can appropriately switch to the first phase if it goes out of synchronization.

In the first embodiment, the component that changes to compensate for the initial phase shift of the internal value X _i of the device A is converged to the arithmetic mean value of the initial value of the internal value X _i of each device A. Although the description has been made regarding the case where the The convergence value X _α changes depending on the arithmetic expression set in the arithmetic unit 311. The arithmetic expression set in the arithmetic unit 311 is not limited.

Moreover, the first condition is not limited to what is described above. The first condition may be any condition that allows it to be determined that synchronization is approaching. The first condition may be, for example, that the absolute value of the total difference value D _i has become smaller than the threshold value Dx (i.e., N ₁ =1), or the absolute value of the moving average value of the total difference value D _i may be smaller than the threshold value Dx.

Moreover, the second conditions are not limited to those described above. The second condition may be any condition that allows it to be determined that synchronization has been lost.

Further, in the first embodiment, a case has been described in which the phase switching unit 315 corrects the total difference value D _i to a value within a predetermined range in the second phase, but the present invention is not limited to this.

For example, the coefficient ε by which the total difference value D _i is multiplied by the multiplier 312 may be set to different values in the first phase and the second phase. Specifically, the phase switching unit 315 outputs the total difference value D _i input from the calculation unit 311 as is to the multiplier 312 regardless of the phase. The multiplier 312 multiplies the total difference value D _i by a coefficient ε ₁ (for example, the same value as the coefficient ε) in the first phase, and multiplies the total difference value D _i by a coefficient ε smaller than ₁ in the second phase. Multiply by a factor ε ₂ . In this case, in the second phase, the change in the internal value X _i due to updating is smaller than in the first phase. Therefore, device A can suppress the influence of delay or noise on internal value synchronization in the second phase. Furthermore, in the first phase, the change in the internal value X _i due to updating is larger than in the second phase. Therefore, in the first phase, synchronization can be brought closer to synchronization earlier than in the second phase. Thereby, device A can suppress an increase in time until synchronization.

Further, in the second phase, no update may be performed. Specifically, in the first phase, the phase switching unit 315 outputs the total difference value D _i input from the calculation unit 311 as is to the multiplier 312, and in the second phase, it multiplies it by “0”. output to the device 312. That is, in the second phase, the internal value generation unit 31 does not update the internal value X _i and leaves the generated internal value X _i unchanged. In this case, in the second phase, the internal value X _i is not updated, so there is no change in the internal value X _i due to updating. Therefore, device A can suppress the influence of delay or noise on internal value synchronization in the second phase. Furthermore, in the first phase, the change in the internal value X _i due to updating is larger than in the second phase. Therefore, in the first phase, synchronization can be brought closer to synchronization earlier than in the second phase. Thereby, device A can suppress an increase in time until synchronization.

As a further modification, in the second phase, if the total difference value D _i is within a predetermined range, the phase switching unit 315 outputs the input total difference value D _i as it is to the multiplier 312, and “0” may be output to the multiplier 312 (skipping the update of the internal value X _i ) only when the value is outside the range. FIG. 5 is an example of a flowchart for explaining the process of updating the internal value X _i performed by the internal value generation unit 31 in the modified example. The flowchart of FIG. 5 is the same as the flowchart of FIG. 3(b) except that steps S15 and S17 are changed to steps S15' and S17'. In steps S15' and S17', the total difference value D _i is corrected to "0", and the process proceeds to step S13. In this modified example, in the second phase, when the total difference value D _i is outside the predetermined range, the total difference value D _i is corrected to "0", so that updating of the internal value X _i is skipped.

Further, in the first embodiment, a case has been described in which the phase switching unit 315 switches between the first phase and the second phase, but the present invention is not limited to this. The phase switching unit 315 may also switch to a third phase. In the third phase, the internal value X _i is closer to synchronization than in the first phase, and further away from synchronization than in the second phase. The phase switching section 315 switches between the first phase, the third phase, and the second phase based on the total difference value D _i input from the calculation section 311 . The conditions for switching each phase are not limited. In the case of the third phase, the phase switching unit 315 performs processing different from the first and second phases. _For example, the phase _switching unit 315 sets the total difference value _{D i} to a second _lower limit value _{T L2} (<T _L ) and the second upper limit value T _H2 (>T _H ) to the range of (T _L2 ≦D _i ≦T _H2 ).

FIG. 6 is an example of a flowchart for explaining the process of updating the internal value X _i performed by the internal value generation unit 31 in the modified example. The flowchart of FIG. 6 is the flowchart of FIG. 3(b) with steps S21 to S25 added. In the flowchart of the modification, if it is not the first phase (S12: NO), it is determined whether it is the second phase (S21). If it is the second phase (S21: YES), the process advances to step S12. On the other hand, if it is not the second phase (S21: NO), that is, if it is the third phase, it is determined whether the total difference value D _i is smaller than the second lower limit T _L2 (S22). If the total difference value D _i is smaller than the second lower limit value T _L2 (S22: YES), the total difference value D _i is corrected to the second lower limit value T _L2 (S23), and the process proceeds to step S13. If the total difference value D _i is greater than or equal to the second lower limit value T _L2 (S22: NO), it is determined whether the total difference value D _i is greater than the second upper limit value T _H2 (S24). If the total difference value D _i is larger than the second upper limit value T _H2 (S24: YES), the total difference value D _i is corrected to the second upper limit value T _H2 (S25), and the process proceeds to step S13. If the total difference value D _i is less than or equal to the second upper limit value T _H2 (S24: NO), the total difference value D _i is greater than or equal to the second lower limit value T _L2 and less than or equal to the second upper limit value T _{H2 .} The process then proceeds to step S13.

In the case of this modification, since the third phase is included, the update method can be changed in stages. Note that the number of phases that the phase switching unit 315 switches is not limited, and a plurality of phases may be set between the first phase and the second phase. The conditions for switching each phase are not limited, and the updating method in each phase is not limited. For example, the phase switching unit 315 may change the upper limit value T _H and lower limit value T _L for correcting the total difference value D _i for each phase. Further, the phase switching unit 315 may change the upper limit value T _H and the lower limit value T _L according to the total difference value D _i (or the moving average value), with phase switching being stepless.

Furthermore, in the first embodiment, each device A is a distributed power source, and the communication system B synchronizes the internal phases of the inverter devices of each device A (distributed power source) connected in parallel. However, the device according to the present invention is not limited to this. The present invention can be applied to any device that has a communication function and matches internal values by transmitting and receiving internal values with other devices that constitute a network. For example, when various timings are made to match or are shifted so that they do not match, the present invention makes it possible to suppress the amount of output active power and output reactive power by matching the internal compensation values of each inverter device that constitutes the power system. It can also be applied to the case where each measuring device matches the internal average value, maximum value, and minimum value based on the measured value. In these devices, the internal value generation unit 31 and the communication unit 34 are common to the device A, and include control means for performing control based on the internal value X _i generated by the internal value generation unit 31, calculation means for performing calculations, or It further includes a display means for displaying the information. Further, in these devices, the internal value X _i generated by the internal value generation unit 31 may change only when updated.

The device according to the invention is not limited to the embodiments described above. The specific configuration of each part of the device according to the present invention can be modified in various ways.

A, A1 to A5: Device, 31: Internal value generation section, 34: Communication section

Claims (8)

internal value generation means for generating an internal value;
communication means for communicating with at least one other device;
Equipped with
The communication means transmits the internal value generated by the internal value generation means to at least one of the other devices,
The internal value generating means includes:
A first phase in which the generated internal value is updated by a first method using a calculation result based on the generated internal value and an internal value received by the communication means from at least one of the other devices. and,
A second step in which the generated internal value and the received internal value are closer to synchronization than in the first phase, and the generated internal value is updated by a second method different from the first method. phase and
can be switched with
A device characterized by: The internal value generation means calculates the calculation result by subtracting each of the generated internal values from the received internal value and multiplying a total difference value obtained by adding all the subtraction results by a first coefficient,
The first method updates the generated internal value by adding the operation result to the generated internal value.
The device according to claim 1. The second method is to correct the total difference value to a value within a first range, and add a value obtained by multiplying the corrected total difference value by the first coefficient to the generated internal value. perform updates,
3. The device according to claim 2. The second method updates the generated internal value by adding a value obtained by multiplying the total difference value by a second coefficient smaller than the first coefficient to the generated internal value.
3. The device according to claim 2. The second method leaves the generated internal value as is.
3. The device according to claim 2. The internal value generation means switches between the first phase and the second phase based on the total difference value.
Apparatus according to any one of claims 2 to 5. The internal value generation means switches from the first phase to the second phase when the total difference value remains within a second range for a predetermined number of times.
7. Apparatus according to claim 6. The internal value generating means is in a state in which the generated internal value and the received internal value are closer to synchronization than in the first phase and further out of synchronization than in the second phase, and further switching to a third phase in which the generated internal value is updated by a third method different from the second method;
8. A device according to any one of claims 1 to 7.

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