JP2024035168A - RF module having a housing with a microfabricated interior using semiconductor manufacturing - Google Patents

Abstract

An exemplary RF module has a housing with a microfabricated interior using semiconductor manufacturing. An exemplary RF module includes metal traces on one plane that connect high frequency components and provide a reference ground. It includes a dielectric substrate having a. Other metal traces on other sides of the board also provide high frequency transmission lines and reference ground. The housing, made using semiconductor manufacturing techniques, has a conductive internal recess defined by an extending wall that is attached to the substrate and connected to a reference ground. A recess surrounds each component and provides electromagnetic shielding. The dimensional accuracy in the location and smoothness of walls and recesses due to semiconductor manufacturing techniques provides reproducible unit-to-unit RF characteristics of the RF module. One method of attaching the enclosure to the board uses a plurality of metal bond bumps extending outwardly from the wall to engage reference ground metal traces on the board. The applied pressure deforms the bond bump to form a metal-to-metal bond. [Selection diagram] Figure 1

Description

RELATED APPLICATIONS This application is part of U.S. patent application Ser. Part Continuation Application, the entire contents of which are incorporated herein by reference.

Embodiments of the present invention provide a semiconductor device having an enclosure comprised of microfabricated interiors that improves the performance of active and passive RF devices and provides manufacturability that results in reproducible performance results from unit to unit. The present invention relates to RF modules having active and/or passive devices made using manufacturing techniques.

Active devices and filters using high frequencies, ie, frequencies above 1 GHz, have been constructed using a variety of materials and techniques. However, it is difficult to manufacture devices and filters with high Q and low input loss that are stable over extreme temperatures. Additionally, it is difficult to package such high frequency devices and filters to design RF modules that provide the desired RF isolation and can be manufactured repeatedly with substantially the same performance characteristics. What is needed are devices and filters that substantially overcome these challenges, and methods for packaging such devices and filters.

It is an object of embodiments of the present invention to provide an RF module that substantially meets these challenges.

An exemplary RF module includes a dielectric substrate with metal traces on one surface that connect high frequency components and provide a reference ground. Other metal traces on other surfaces of the substrate also provide reference ground. The enclosure, made using semiconductor manufacturing techniques, has a conductive internal recess defined by an extending wall that is attached to the substrate and connected to a reference ground. The recesses each surround the components and provide electromagnetic shielding. The dimensional accuracy in the location and smoothness of the walls and recesses by the manufacturer of the enclosure using semiconductor technology provides reproducible unit-to-unit RF characteristics of the RF module. One method of attaching the enclosure to the board uses a plurality of metal bond bumps extending outwardly from the wall to engage reference ground metal traces on the board. The applied pressure and heat deforms the bond bump to form a metal-to-metal bond.

An exemplary method for manufacturing an implemented semiconductor technology housing that provides electromagnetic shielding of high frequency RF components disposed on a substrate when the housing engages the substrate is described. The coating is applied to an area on the main surface of the silicon wafer, which area defines where the walls of the recess will be placed. The layer of silicon not protected by the coating is etched away to a first depth, the first depth of silicon defining the bottom of each recess. The coating is removed and the entire exposed surface of the silicon wafer is preferably sputtered with gold so that the sputtered gold coats the edges of the walls, the bottom of the recess, and the sides of the walls. The gold-sputtered gold-covered areas are then plated with gold.

An exemplary enclosure is fabricated using semiconductor technology and includes an electronic RF-sensitive substrate disposed on a substantially planar dielectric substrate having metal wiring disposed on at least one major surface of the substrate. Provide electromagnetic shielding for components. RF sensitive components can include both filters and passive components, as well as active devices such as MMICs and digital chips. The housing is fabricated from a dielectric wafer having a microfabricated semiconductor fabricated interior including a recess defined between outwardly extending peripheral walls. The peripheral walls have substantially flat end regions that are parallel to each other and in the same plane. The recess is dimensioned to surround each electronic component and provide electromagnetic isolation for each electronic component when the flat end area of the housing engages the ground reference trace on the surface of the board. It is decided. A conductive metal coating is deposited on all interior surfaces of the housing, including the substantially flat end regions and recesses. The substantially flat end region is dimensioned to engage and electrically connect with the reference ground metal trace on the surface of the substrate such that, when engaged, the internal recess is connected to the reference ground metal trace. form part of the component and provide electromagnetic shielding for the component. Preferably, a reference ground metal trace on the front side of the substrate is connected to a ground plane on the back side of the substrate using through-wafer vias to enhance electromagnetic shielding. Overall, from bottom to top, the backside metal, the through-wafer vias, the ground metal traces on the front surface of the board, the bonding bumps, the conductive metal on the substantially flat end area of the housing, and the metal on the internal recess. Rization provides electromagnetic shielding (eg, a "Faraday cage") of the hermetically sealed component.

Features of exemplary embodiments of the invention will become apparent from the description, the claims, and the accompanying drawings.

FIG. 1 is an exploded perspective view of a filter according to an embodiment of the present invention. 2 shows an exploded view of a filter according to an embodiment of the invention, showing the relationship between elements and layers; FIG. Figure 3 shows a top view of metallization located on the top surface of the substrate relative to the bottom metallization. Figure 3 shows a bottom view of metallization located on the bottom side of the substrate relative to the top metallization. 1 shows a representative cross-sectional view of an assembled filter according to an embodiment of the invention. FIG. 2 illustrates an enlarged corner of an exemplary housing according to an embodiment of the present invention. Figure 3 shows an enlarged detail of the top metallization associated with the coupling of signals to and from the filter. FIG. 2 shows an exploded detail view of a structure supporting the transition between high performance external microstrip transmission line and suspended stripline in an embodiment of the invention. 3 illustrates processing steps for manufacturing an exemplary housing. 3 illustrates processing steps for manufacturing an exemplary housing. 3 illustrates processing steps for manufacturing an exemplary housing. 3 illustrates processing steps for manufacturing an exemplary housing. 3 illustrates processing steps for manufacturing an exemplary housing. 3 illustrates processing steps for manufacturing an exemplary housing. 3 illustrates processing steps for manufacturing an exemplary housing. 2 shows a graph illustrating performance characteristics of an exemplary filter over a frequency range, in accordance with an embodiment of the present invention. 1 illustrates an exemplary substrate for an RF module according to an embodiment of the invention. 12 shows another major surface of the embodiment of FIG. 11 with the back side metallization removed. 12 shows the embodiment of FIG. 11 with added parts. 2 illustrates an exemplary cover according to an embodiment of the present invention having channels and recesses disposed around each component on a substrate of an RF module to provide RF isolation for each; FIG. Figure 3 shows an exploded perspective view of an RF module according to the invention with the cover open; Figure 3 shows a perspective view of a fully assembled RF module according to the present invention with the cover engaged to the substrate. 3 is a graph of output performance of an exemplary RF module. 2 is a graph illustrating fundamental frequency suppression in the output of an exemplary RF module.

One aspect of the present invention lies in the recognition of the difficulties associated with reproducibly manufacturing conductive housings for the elements that make up an RF module, including substrates, filters, and active MMIC components. The conductive enclosure must provide an effective grounding structure for current flow along the entire surrounding interior wall. Recognizing these difficulties, reliable and repeatable fabrication is required to provide an effective continuous grounding structure around the perimeter of the assembled enclosure, as well as to interlock the top and bottom metallization ground traces. A housing design that can be used arises. Details regarding overcoming these difficulties will be appreciated by those skilled in the art upon consideration of the following description.

The exemplary embodiment of a diplexer is used as an example of a passive RF module to convey features and improvements related to embodiments of the present invention. A diplexer acts as a type of filter that separates the input signal at a single input into two separate outputs, one output containing the input signal having a frequency within a first frequency range, and the other The output of includes an input signal having a frequency within a second frequency range, the first and second frequency ranges being different. As used herein, "filter" refers to any type of frequency selective circuitry of RF, microwave, or millimeter wave type suitable for placement on a substrate that may be placed within an enclosure. For example, filters include diplexers, low-pass filters, high-pass filters, bandpass filters, multifunction filters, multiband filters, power dividers/combiners, resonators, couplers, spiral/coil/toroid inductors, metal-insulator-metal ( MIM) capacitors, interdigitated capacitors, vertical (i.e., via-to-via) capacitors, balances, attenuators, phase shifters, arbitrary interlayer transitions, same interlayer type to line type transitions, etc. Not limited.

FIG. 1 shows an exemplary embodiment 100 of a filter or diplexer having a two-piece housing consisting of a bottom housing 105 and a top housing 110. Substantially planar substrate 115 is sized to be enclosed like a sandwich between bottom housing 105 and top housing 110 in an operationally ready assembly. Substrate 115 has a top surface 120 that supports top metallization 125 and a bottom surface 130 that supports bottom metallization 135. Input port 140 receives an input signal at a frequency selection circuit that routes signals in one frequency range to output port 145 and routes frequencies in another frequency range to output port 150 . Bottom housing 105 includes an interior recessed area that is partially divided by a central longitudinal peninsula 155 that separates a recessed area 160 associated with output port 145 and a recessed area 165 associated with output port 150 . The upper circumferential surfaces of both the bottom housing 105 and the top surface of the peninsula 155 represent a reference ground (potential). Top housing 110 is substantially similar to the bottom housing except for a cutout 170 that is located adjacent input port 140 in the assembled position. Cutout 170 facilitates coupling of input signals by external probes or lines by providing mechanical support to input port 140 on substrate 115. Similarly, cutout portions in the upper housing opposite output ports 145 and 150 facilitate clearance for connections with these ports. When assembled, the peninsula 155 engages the substrate 115 on one surface, and the corresponding peninsula on the upper housing engages the substrate 115 on the other surface opposite the peninsula 155, When interconnected by through vias, they form two parallel recesses separated by two opposing peninsulas. A ground structure formed by two peninsulas and a through-substrate via serves as a microwave separation wall between two concave cavities (“channels”) in this exemplary filter. Note that the peninsula is the inner wall of the cover. The cover can also have "islands" in addition to peninsulas. When the inner and protruding surfaces of the cover are metallized, the islands and peninsulas are metallized simultaneously as well. They typically provide an "inner" interior wall for insulation, demodeling, field shaping, and impedance control purposes. Note that the interior walls, including those contributed by islands and peninsulas, recessed surfaces, protruding surfaces, and bond bumps of both covers and through-substrate vias are all part of the reference ground structure. When assembled, they form a single connected ground structure, or "Faraday cage", for a sealed stripline circuit. Islands and peninsulas can have any differently contoured periphery, which does not pose any difficulties in manufacturing technology.

The exemplary diplexer 100 directs an input signal having a frequency between 0.5 GHz and 10 GHz input at an input port 140 along a first path to a first output 145 and a frequency between 11 GHz and 20 GHz. It is designed to separate the input signal along a second path to a second output 150. The circuitry associated with the first and second paths provides low input loss for the signals to be coupled to each of the first and second outputs, while being coupled through each path. provides a substantially higher impedance for other signals that are not desired. At such frequencies, example circuits are implemented with capacitors, inductors, and respective metallization traces that function as transmission line equivalents to provide frequency selection.

FIG. 2 shows a representative exploded view of an exemplary filter (diplexer) 200, in which elements described in FIG. 1 are indicated and identified by the same reference numerals. Bottom layer 205 and top layer 210 represent conductive metal layers deposited on the inner surfaces of bottom housing 105 and top housing 110, respectively. The longitudinal periphery 215 of bottom layer 205 and the longitudinal periphery 220 of top layer 210 extend to the longitudinal edges of the inner surfaces of bottom housing 105 and top housing 110, respectively. Similarly, the longitudinal periphery 225 of bottom metallization 135 and the longitudinal periphery 230 of top metallization 125 extend to the longitudinal edges of the interior surfaces of bottom housing 105 and top housing 110, respectively. The peripheral portions 225 and 230 of the bottom and top metallization layers 135 and 125 on the substrate represent the metallization where a reference ground is desired. The top metallization layer also includes signal traces 126 that carry input signals to a reference ground. A plurality of through-metalization vias 240 along the longitudinal periphery of the substrate 120 provide an effective ground connection between mating regions of the mating bottom and top metallization layers 135 and 125, respectively. In order to establish effective grounding, via 240 must avoid the undesirable effects that occur within the empty cavity ("cavity") formed by the surrounding vias when energy at the resonant frequency of that cavity is coupled into the cavity. The spacing should be appropriate for the electromagnetic frequency under consideration in order to prevent moding at electromagnetic resonance. Typically, the via spacing is chosen to be a small fraction of the quarter wavelength (1/4 wavelength) of the highest frequency under consideration, such as 1/5 to 1/10 or less. For example, a spacing of 750 μm to 375 μm is sufficient to prevent moding at frequencies below 20 GHz. To enhance effective grounding, vias 240 are placed inside the substrate 120 and engage near the internal edges of the ground metallization on the bottom metal layer 135 and the opposing ground metallization on the top metal layer 125. It also engages the area. Bottom deposited metal layer 205 is continuous within the inner surface of bottom housing 105 . That is, a successively deposited metal layer is present on the top surface 106, the top 107 of the interior recess defining the interior cavity, and the substantially vertical sidewalls 108 between the surfaces 106 and 107. The top deposited metal layer 210 is also continuous as similarly described for the bottom deposited metal layer. The bottom housing 105 includes two longitudinal side walls 104 and two end walls 103 that are perpendicular to the side walls. Upper housing 110 includes two longitudinal side walls 111 and two end walls 112 perpendicular to side wall 111 . In the illustrated diplexer example, the open portion 113 of the end wall 112 extends substantially perpendicularly back inward from the outer edge of the end wall so as to be adjacent to the main interior recess.

3 and 4 show views of top and bottom surfaces 300 and 400 of the metallization disposed on the top and bottom of the substrate, respectively. When assembled, the peninsula 155 engages the ground metallization on the substrate 115 on one surface, and the corresponding peninsula on the upper housing engages the ground metallization on the substrate 115 on the other surface, opposite the peninsula 155. When engaged with the ground metallization above and interconnected by through-substrate vias, it forms two parallel recesses separated by two opposing peninsulas. The view seen in FIG. 4 shows a bottom view of the metallization on the bottom side of the substrate, with the view shown in FIG. 3 rotated 180° in the longitudinal direction. A ground potential peninsula 305 is located on the top metal layer directly above the ground potential peninsula 405 on the bottom metal layer. The plurality of through-hole vias 310 in the top metal layer correspond to and are substantially identical to the through-hole vias 410 in the bottom metal layer and provide connections through the substrate between the top metal layer and the bottom metal layer. Establish. The plurality of vias all extend along the width and length of the top metal peninsula and the bottom metal peninsula to establish a common ground potential between the top metal peninsula layer and the bottom metal peninsula layer. A U-shaped metal loop 315 at ground potential extends around and completely surrounds the input port 140. Similarly, U-shaped metal loops 320 and 325 at ground potential also surround each of the output ports 145 and 150. This U-shaped loop serves to minimize wave leakage in the cavity between the probe and the substrate in a direction opposite to the desired direction (to a suspended stripline). This is a characteristic of line transition. Note that in other transition designs, e.g., ribbon bonding or dual purpose (probing and wire bonding), it may not be necessary or desirable to utilize such a ground loop. . This ground loop enhances high performance broadband flow for probe measurements, but is not a necessary feature of current suspended stripline technology.

A general description of a circuit implemented by wiring as shown in FIG. 3 is provided. However, those skilled in the art will appreciate that this description applies to the particular exemplary diplexer and that various other types of filter elements can be deployed on the substrate to provide transmission lines, inductive components, capacitive components, dispersive components, and coupling components. It will be appreciated that a frequency selection circuit including components can be provided. Such components can be designed to provide a variety of functions, such as low-pass filters, high-pass filters, bandpass filters and notch filters, and can include multiple input and/or output ports. Can be done. In addition, active circuit elements, such as transistors, ICs, etc., may also be disposed on the support substrate housed within the housing. Input transition 350 facilitates wide bandwidth adaptation between microstrips included between the probe and stripline 355 shown in FIG. If both the microstrip line and the stripline have a transmission impedance of 50 ohms, a typical microstrip has a centerline conductor width of about 3 mils, while suspended stripline 355 is 60 mils. Additionally, the electromagnetic field within the microstrip is primarily contained below the microstrip line, while the electromagnetic field within the suspended stripline 355 extends in all directions transverse to the propagation direction, from the signal metal trace to the inner wall of the cover. . The transition section 350 uses a wedge-shaped metal cladding on the bottom of the substrate and a contoured metal lining in the adjacent cover to transition from a narrowly confined microstrip mode to a suspended strip line over a short distance. Helps fan out the field into a substantially larger cavity. The taper of the housing from a regular channel width to the size of the aperture 113 is designed to work in conjunction with the wedge-shaped metallization for the same purpose of helping widen the field for high-performance broadband transitions. Designed to. The neck-down matching section (see narrowed section in Figure 7) and tail-end section behind the probe pad also help achieve broadband performance up to 40 GHz. Region 360 represents a common signal junction where the input signal is coupled by transmission line 355 to two transmission lines coupled to the top and bottom selection circuits, respectively. Similarly, elements 360, 365 function as open stub transmission lines associated with tuning to provide a notched frequency response. Element 370 represents a connecting transmission line. The transmission line 355 and the circuit elements present on the peninsula 305 combine to provide a low-pass filter frequency response, e.g., signals from 0.5 GHz to 10 GHz are passed with low attenuation, while higher Signals with frequencies undergo substantial attenuation, ie they are blocked/reflected at the entrance of the channel due to the high impedance. Element 375 represents a bond line that provides a bandpass frequency response. The transmission line 355 and the circuit elements present below the peninsula 305 combine to provide the frequency response of a bandpass filter; for example, signals within 11 GHz to 20 GHz fall within the bandpass frequency range and have low attenuation. while signals outside the range, ie 0.5 GHz to 10 GHz, are substantially attenuated, ie blocked/reflected at the entrance of the channel due to high impedance.

As seen in FIG. 4, vias in the bottom metallization connect to the U-shaped ground loop to enhance effective grounding between the two metal layers. Top cavity 330 includes a plurality of metal traces 126 disposed within the top metal layer that function as selective frequency circuitry to output port 145, where the selective frequency circuitry operates for signals between 0.5 GHz and 10 GHz. It provides high impedance and substantial rejection for signals between 11 GHz and 20 GHz while providing low attenuation. Similarly, the bottom cavity 335 includes a plurality of metal traces 126 disposed within the top metal layer, which function to form a selective frequency circuit to the output port 150, the selective frequency circuit comprising: It provides high impedance and substantial attenuation for signals between 0.5 GHz and 10 GHz, and low attenuation for signals between 11 GHz and 20 GHz. Preferably, the substrate core is silicon carbide on which the precision metallization is placed, and the through-wafer vias, which can be fabricated using the same fabrication, are made of gallium nitride (GaN) high electron mobility transistors ( used in HEMT) manufacturing.

FIG. 5 shows a representative cross-section of an assembled filter according to an embodiment of the invention, the cross-section being taken at a location on the assembled filter where peninsula 155 is not present. The bottom housing 105 and the top housing 110 may be made from silicon with gold linings on the inner surfaces 205 and 210 that are plated. The gold-plated surfaces of the bottom and top housings engage bottom metallization 135 and top metallization 125, respectively. Conductive vias 240 through the substrate provide a continuous ground connection interconnecting the gold plated cavities of the bottom and top housings and the top and bottom metal layers to be at ground potential. Substrate 120 is preferably silicon carbide or another material that has properties that vary little with temperature to minimize variations in frequency response with changes in temperature. Suspended stripline circuits with large cross-sections filled with low-loss materials (air, silicon carbide) facilitate very high Q and low-loss filters with sharp band edges and rejection roll-off. enable.

FIG. 6 shows a typical enlarged corner of the bottom housing 105 with metal plating 205 disposed on the vertical sidewalls, as well as an upwardly facing plane. Coupling bumps 605 extend generally perpendicularly and outwardly from the upwardly facing plane along the periphery and along the interior peninsula. Bonding bumps 605 are spaced around the entire circumference of the bottom housing and engage bottom metallization 135 in the assembled position. The bonding bump also extends along the bottom housing peninsula 155 and engages the bottom metallization 405 in the assembled position. Similarly, bonding bumps extend perpendicularly and outwardly from the downwardly facing plane of the upper housing and engage ground metallization 125 and ground peninsula metallization 305. In this example, the bonding bumps are formed on the housing rather than on the substrate (or metallization on the substrate), although the bonding bumps could be formed on both sides of the substrate 115. The bonding process preferably uses high precision thermocompression bonding using a tool such as the FC-300 manufactured by SET to bond the gold plated bonding bumps to the gold plated metallization surface on the substrate. do. If the bonding bumps were placed on the substrate, the second side to be bonded would have a much higher density of bumps, resulting in a lower density of the substrate used for the other of the bottom and top casings. The opposing bonding bumps on the other side will not be crushed during the process of applying pressure to bond the first housing to the substrate.

FIG. 7 shows an enlarged detail 700 of the top metallization associated with ports 140, 145, and 150 used to couple signals to and from the filter. These three ports are designed for probe measurements. As an example, port 140 is a ground signal ground port used to couple input signals. As seen in this detail, the U-shaped ground metallization 315 continuously surrounds the input port center conductor 140 by 270°. In this example, external probe or interconnect 705 includes a center metal conductor (finger) 710 positioned to engage input port center conductor 140 and engage opposing legs of U-shaped ground metallization 315. It includes two opposing metal fingers 715 on either side of a central finger 710 arranged in such a manner. The structure of this port provides the necessary compensation features such as inductance and capacitance in the vicinity, which allows a smooth transition from the field within the probe onto the signal carrying traces on the board, and thus from the probe. Create short microstrips (ie, transmission lines with ground metallization on the backside of the substrate) and "transitions" to suspended striplines.

FIG. 8 shows an exploded detail view of a structure that supports the transition between a compact, high performance, broadband external microstrip line and a suspended strip line in an embodiment of the invention. The electromagnetic field at the probe tip is horizontal between the signal pin and the ground pin. In order to be subjected to the pressure of probe branding, the bottom cover must have no drilling in this area, and therefore microstrip type transmission lines, i.e. those with metallization (ground) on the back side of the substrate, Must be used close to the professional branding area. Vias 240 and ground loops 315 help "fold" or "bend" the essentially horizontal electromagnetic field at the probe tip relative to the essentially vertical electromagnetic field beneath the microstrip wiring. The neck down 805 next to the probe pad 140 and tail end piece 810 are both features that aid in impedance matching for broadband performance. Then, at the junction between the microstrip line and the strip line, the essentially vertical electromagnetic field concentrated below the microstrip line is Must fan out in all directions (downward, upward, sideways, etc.). This field fanout is supported by the following features: The wedge-shaped metallization 815 on the backside of the substrate can be thought of as a "diving board" that allows the concentrated microstrip electromagnetic field to gradually loosen and form a connection to a much larger ground structure within the stripline. The taper of both the top and bottom covers provides a landing surface for the closely spaced electromagnetic field near the microstrip line junction and gradually expands the landed electromagnetic field to larger cross-sections until it fills the complete channel dimension. do. The distance between the probe-to-microstrip transition and the microstrip-to-stripline transition is small and due to the strong interaction, these can be treated as a single transition, i.e., the probe-to-microstrip to stripline transition. Note that it should be visible and designed. Other transitions have also been designed for practical purposes, such as wire bonding, or wire bonding and probing. These transitions may have different dimensions or may have ground via configurations. However, essential field bending/expansion features such as wedges and tapered ground planes are still very effective.

9A-9G illustrate processing steps for manufacturing an exemplary housing associated with a filter, according to an embodiment of the invention. In this example, an exemplary cross-section of bottom housing 105 is shown including peninsular wall 155. In FIG. 9A, the process begins with a relatively thick (eg, 1 mm) silicon wafer 900. The next step, shown in FIG. 9B, is to pattern the top surface of the silicon wafer 900 with photoresist and use reactive ion etching (RIE) to microfabricate, i.e. extend outward, the areas of silicon to be removed. A bonding bump 905 is left. "Microfabrication" refers to the creation of dimensionally accurate, smooth surfaces by semiconductor etching followed by the deposition of metal layers. In the next step, shown in FIG. 9C, the photoresist is removed and an oxide layer 910 is deposited to a thickness sufficient to resist complete erosion during the silicon etch. A photoresist pattern 915 is then applied to create what will become three walls 917, and RIE is used to etch away the oxide 910 not protected by the photoresist, as shown in FIG. 9D. As shown in FIG. 9E, the photoresist 915 shown in FIG. 9D is removed and a deep RIE etch is used to remove the areas of silicon that form internal recesses 918 within the housing. In FIG. 9F, the oxide 910 is removed to reveal two longitudinal walls 920 along the longitudinal edges and a central longitudinal peninsula wall 925 forming two separated longitudinal recesses 932, 933. . The recesses are etched to a depth of 15 mils in exemplary diplexer embodiments and may be up to about 40 mils deep. Following this, a relatively thin layer of gold 930 is sputtered over all exposed upward facing surfaces, including the relevant edges of the walls, bonding bumps, vertical walls, and planar recesses. Therefore, the exposed ends of walls 920 and 925, as well as bond bumps and recessed areas, are all sputtered with gold. In the final step as shown in Figure 9G, all of the areas previously sputtered with gold are now plated with a thicker layer of gold. In this example, the bonding bumps have a diameter of 25 μm, a bump height of 1.6 μm, and are preferably spaced apart by a distance of 200 μm. Typically, the maximum spacing is about a quarter wavelength, but a tenth wavelength is preferred if feasible.

The excellent dimensional accuracy and surface smoothness of the internal recesses and internal surfaces of the housing, achieved by microfabrication, are critical to the ability to produce filters with highly reproducible properties and performance and low electrical losses. . Enclosures manufactured by conventional mechanical manufacturing techniques such as machining, EDM, and electroforming have tolerances in the range of 0.2 mil to 1 mil, which is consistent with the semiconductor techniques described herein. 1-2 orders of magnitude greater than the accuracy provided by . Additionally, surface roughness from machining can typically be five times that achieved by semiconductor technology, which results in additional RF signal loss. For example, compared to a machined copper housing having a peak-to-valley roughness of approximately 9.4 μm, the micromachined inner surface within the exemplary housing has a peak-to-valley roughness of less than 2 μm, or 1.3 μm. It has a certain quality. This provides over a 7x improvement in smoothness.

Although conductive epoxy pastes can be utilized to achieve silicon-SiC assembly, conductive pastes have some control issues such as oozing, thickness variations, voids, and poor electrical contact, as well as placement accuracy. provide techniques that are more difficult to implement.

Regarding the vias, 50 μm diameter metallized through-wafer vias connecting with ground metallization on opposing surfaces on the substrate are used to form high isolation electromagnetic via fences. Simulations have shown that the vias may be used to provide high isolation up to 100 GHz when spaced with a minimum pitch of 100 μm. The via fence and gold-plated silicon enclosure walls are effectively encased in their own electromagnetically shielded cavity to minimize cross-coupling of the individual elements of the two separated frequency circuits. to be able to be The through-wafer vias promote substantially continuous ground continuity for RF return currents between the top and bottom housings and allow for probe testing of the filter after manufacture. Note that the "walls" formed by the gold-plated silicon enclosure walls and via fences can be used not only to separate channels, but also to separate individual filter elements. . Traditional open-face printed filter designs are often longer because close coupling between filter elements introduces guesswork and repeated simulation cycles are unavoidable when fine-tuning the filter geometry. Requires a design cycle. Separation between individual filter elements eliminates such undesirable cross-coupling, thus allowing rapid development and compact layout.

As seen in Table 1, tight manufacturing tolerances design for first-pass success and manufacturing repeatability, especially for filters that require tight cutoff characteristics, high isolation requirements, and high repeatable performance. It is important for

FIG. 10 shows a graph showing performance characteristics over a frequency range of an exemplary filter (diplexer). This graph is plotted as dB for exemplary frequencies of interest, ie, frequencies from 0.5 GHz to 25 GHz. Line 1005 represents the output characteristics associated with a signal from output port 145 that exhibits very low loss for input signals between 0.5 GHz and 10 GHz, with a sharp attenuation at about 11 GHz, and from about 12 GHz to 24 GHz. It is attenuated by about 50dB. Line 1010 represents the projection characteristics of the signal at output port 145 using ANSYS' finite element frequency domain analysis tool "HFSS". It will be clear that there is a very close correspondence between the projected properties and the actual measured properties. This is due to the tight manufacturing tolerances mentioned above. Line 1015 is an output port that attenuates by at least 30 dB (and more at decreasing frequencies) from about 10 GHz to 0.5 GHz, increases sharply at about 11 GHz, and exhibits very low loss for signals between 11 GHz and 20 GHz. 150 represents the output characteristics associated with the signal from 150. Line 1020 represents the projection characteristic of the signal at output port 150 using the same HFSS model as above. It will be clear that here too there is a very close correspondence between the projected properties and the actual measured properties. A close correspondence between the properties projected by the model analysis and the actual measured properties of the fabricated diplexer on the first pass of manufacturing represents good design and manufacturing technique. Furthermore, the variation among the first diplexer units was excellent, with 7 out of 8 units showing almost the same performance.

Although the above exemplary implementations of the invention have been illustrated and described in detail herein, it will be apparent to those skilled in the art that various modifications, additions, substitutions, etc. can be made without departing from the spirit of the invention. It should be obvious. For example, other microwave circuits can be implemented, including those described in paragraph [18]. The silicon cavities can be of different heights and the bonding bumps can be fabricated using a variety of chip and wafer bonding techniques, including eutectic bonding such as indium-gold or gold-tin or copper pillar bonding. Can be done. Bonding bumps can be fabricated on the substrate 115 instead of silicon, and the assembly can be bonded as an entire wafer rather than in smaller filter-sized blocks. The height of the cavity is limited only by the manufacturing capabilities of the silicon etch tool. Silicon cavities with two different etching depths are possible and can be used in terahertz waveguide devices and in filters of the type described herein. Substrate 115 can be made from another material, such as 5 mil thick alumina, as long as there are conductive vias through the wafer.

FIG. 11 illustrates an exemplary substrate 1102 of an RF module 1100 (shown in FIG. 16) according to an embodiment of the invention. An exemplary RF module includes several monolithic microwave integrated circuits (MMICs), three filters, and an amplified two-fold (x2) frequency multiplier that can, for example, provide a local RF signal oscillator at its output. It consists of a chip attenuator that implements the

A planar insulating substrate 1102, such as single crystal silicon carbide, has top and bottom major surfaces, the top surface being shown in FIG. Topside metallization 1110 defines both signal and ground for RF signals that traverse elements disposed on substrate 1102. A plurality of internal metallization traces 1115, which are not connected to ground, provide transmission paths for RF signals and define electrical components, such as filters, transmission lines, and the like. A continuous, uninterrupted conductive ground path exists near the perimeter of the upper metallization 1110, which cooperates with the cover 1400 to provide an effective uninterrupted RF ground around the perimeter surrounding the internal electrical components. It can be observed that making it possible to provide a seal. The through-wafer vias 1195 in the substrate 1102 provide effective transmission across the major surface of the substrate because the spacing between adjacent vias is much less than a quarter wavelength, e.g., 0.1 wavelength, at the frequencies used in the RF module. Provide grounded fencing. Preferably, the substrate thickness and via spacing are selected such that the upper frequency limit exceeds the highest frequency signal or spurs generated within the module during operation. In addition to the RF isolation provided, such a seal also prevents dust and other contaminants in the external environment from entering the interior which could lead to degradation or failure of the RF module.

Ports that couple input and output signals present challenges with respect to maintaining RF isolation and preventing external contaminants from entering the interior of the RF module. The conductive input port 1120 must be connected to a first electrical component 1125, such as a filter, while still facilitating internal RF isolation and physical sealing. As seen in the exploded cross section shown in FIG. 12, a through-plated via 1130 connects the upper conductive input port 1120 to the lower metallization 1122, which connects a through-plated through via 1135 with the upper first electrical component 1125. . As seen in FIG. 11, a region 1137 above the top metallization 1122 is covered with ground metallization 1110. This area is continuous about the periphery of the top surface of the substrate while still allowing corresponding engagement with the conductive walls of the cover 1400 and allowing the input signal to be coupled to the corresponding first electrical component. Maintain a good RF ground and physical seal. A conductive output port 1140 is coupled to the last electrical component 1145, similar to the input port. Preferably, DC voltage is coupled to internal active components in a similar manner to facilitate uninterrupted RF grounding and physical sealing of the cover around the perimeter of the board 1105. Such routing of the RF signal path can be considered an inverted bridge.

The exemplary RF module 1100, an amplified x2 multiplier, uses a series low pass filter 1150 to filter the input RF signal at the base frequency, multiplied by x2, and amplified by the RF module. This filter provides low attenuation at the base frequency signal and substantial attenuation at the x2 frequency. Two GaAs high electron mobility transistor (HEMT) circuit dies 1155 and 1160 provide amplification of the base frequency RF signal, which is then bandpass filtered by filter 1165. The amplified base RF signal is coupled to an InP diode circuit die 1170 used as a frequency multiplier with its output coupled to an attenuator die 1172, followed by another GaAs HEMT amplifier 1175 whose output is It is connected to a bandpass filter 1180 before being coupled to signal output port 1140. Attenuator 1172 reduces reflections from amplifier die 1175 to multiplier die 1170, thus providing a better “matched” load to multiplier circuit 1170. Bandpass filter 1180 provides low attenuation to the x2 frequency signal, while providing substantial attenuation, e.g., 60 dB, to the base x1 frequency signal, thus its amplitude at the output port compared to the amplitude of the x2 frequency signal. minimize.

Each of the three amplifiers 1155, 1160, 1175 has a corresponding DC voltage input 1190 and a corresponding chip capacitor 1185 to minimize any RF signal on the DC input voltage. Preferably, three-dimensional or vertical "fences" 1195 formed from closely spaced in-line metal plated ground through-hole vias connecting the top and bottom conductive ground areas are located at the lateral edges of the three microstrip filters. located along the ground, providing an effective ground plane between the top and bottom grounds and providing high isolation for all other components. Similarly, vertical fence 1195 is preferably placed closely around the amplifier and multiplier diodes. Therefore, all components such as active components, i.e. amplifiers and multipliers, and passive components, i.e. filters and attenuators, are each encapsulated within a "cavity" to provide isolation from other components. Ru. Additionally, cavities are typically formed by machining a metal housing, making the cavity resonances as closely as possible to the contours (lateral periphery) of each chip/component, as the semiconductor manufacturing process delineates them as closely as possible. provides the smallest cavity (other than margin for manufacturing tolerances) that allows much higher frequencies to be obtained than can be achieved with much larger cavities. For example, amplifier ICs and diode multipliers are attached to their respective ground areas on the top surface with conductive epoxy or the like by automated pick-and-place tools, and signal/control lines are wire bonded to their respective conductor areas on the substrate 1102. can be done.

FIG. 12 shows the other major side of the board of FIG. 11, with the back side metallization removed to better show the plated through-hole vias connecting the back side ground metallization and the top side ground metallization. ing. In this view, a vertical fence 1195 consisting of closely spaced in-line plated through-hole vias can be more easily seen. Ground through-hole vias in the ground area where the amplifier and multiplier diode modules are attached enhance grounding.

FIG. 13 shows the embodiment of FIG. 11 with the addition of MMIC die components. That is, three amplifier circuit dies, an attenuator circuit die, and a multiplier diode circuit die are mounted with conductive epoxy and electrically connected to corresponding conductive pads by wire bonding. Any other separate components, such as bypass capacitors, are also attached, eg epoxidized and wire bonded. To increase the Q and minimize losses in the three filters, the three microstrip filters are preferably formed as part of the substrate fabrication and placed on the surface of the substrate at the same time as all of the rest of the front metallization. printed. Such "integrated" or "printed" filters reduce component count, save effort in chip mounting and wire bonding, and eliminate variations caused by chip mounting and wire bonding to obtain high accuracy in performance. Therefore, it is preferred as much as possible. Alternatively, the filter may be manufactured separately and bonded to the surface of the substrate.

FIG. 14 depicts an exemplary cover 1400 according to an embodiment of the invention, which, when attached to and engaged with the substrate 1102, provides RF and magnetic isolation of the components from each other and from the external environment. For this purpose, the substrate 1102 has recesses 1450-1480 with reference numbers arranged to individually surround corresponding components 1150-1180. Cover 1400 is preferably made of a silicon wafer 1405 having a flat surface 1410. The bottom 1415 and sidewalls 1420 of the recess, as well as the flat surface 1410, are plated with a conductive metal, such as gold.

Starting from the aforementioned inverted bridge structure at the RF INPUT, a continuous recessed channel snakes up to the inverted bridge structure at the RF OUTPUT. The continuous recess surrounds the mounted electronic components and integrated filters on the substrate and also surrounds the interconnections therebetween when the cover is installed. Since the cover provides electrical and magnetic isolation between the electrical elements, the layout of the elements may be folded to allow an RF module with minimal area. Regarding the direction of signal flow as seen in FIG. 1170, flows from left to right through amplifier 1175 and filter 1180, and finally rotates 180°. As best shown in FIG. 14, peninsulas 1430 and 1435, in combination with the RF ground provided by the board, provide signal isolation that allows the signal path to undergo two 180° rotations, and the electrical Minimize the area occupied by parts. In this exemplary embodiment, three MMIC chips 1170, 1172, and 1175 are placed adjacent to each other with the minimum spacing allowed by semiconductor manufacturing, and the wires are bonded to each other without passing through intermediate wiring on the substrate. Ru. Such "chip-to-chip" bonding can be used to save space. Compared to machined housings, it is unlikely, if not impossible, to achieve the level of necking down (abrupt, controlled physical transition) of 1472. Therefore, in a machined housing, the three MMICs 1470, 1472, and 1475 are placed together in a single common, larger cavity that is likely to result in an undesirable lower resonant frequency associated with the cavity. likely to be placed. The techniques shown in this embodiment of the invention allow what would have been a single larger cavity within the machined housing to be divided into separate smaller cavities, thus , provides semiconductor control tolerances that avoid concerns associated with larger cavities, such as lower resonant frequencies.

FIG. 15 shows an exploded perspective view of the RF module 1100 with the cover 1400 shown in a position ready for assembly and engagement with the top surface of the substrate 1102. It will be appreciated that the recesses in the cover are aligned to provide a seal around the respective electrical components.

FIG. 16 shows a perspective view of a final assembled RF module 1100 according to the invention, with cover 1400 engaged with substrate 1102. Of course, it is important that the metallization on 1410 of cover 1400 physically and electrically engages the respective top metallization 1110 of substrate 1102 to provide electromagnetic isolation for the electrical components. This engagement also provides a continuous physical seal around the perimeter of the RF module to protect against ingress of external contaminants. This bonding is preferably accomplished using a precision chip bonder to form a gold-gold thermocompression bond between abutting surface platings on the substrate and the cover. Preferably, at least one of the surfaces of the two abutment surfaces includes bond bumps as described above to enhance the formation of a thermocompression bond. Alternatively, another technique, such as a conductive epoxy, can be used to conductively bond the cover to the ground metallization of the substrate. The chip bonder provides acceptable placement accuracy of the cover to the substrate, for example 0.5 mil.

RF modules are fabricated using semiconductor wafer manufacturing processes. This process is dimensionally much larger than covers made by other processes, such as bending sheets of metal or mechanically drilling/removing metal from blocks of metal to form cavities. produce parts that are precise and reproducible, especially but not limited to covers. The substrate may utilize a silicon carbide wafer with a front (top) side conductive plating of 3.5 um gold with dimensional accuracy of 0.5 um linewidth. The backside substrate process was performed by thinning the substrate to 254um and using inductively coupled plasma to etch through-wafer vias with a diameter of 150um, followed by patterning 3.5um of gold plating with dimensional accuracy of 2um linewidth. may be obtained.

The cover may consist of a 40 mil thick silicon wafer that is micromachined and plated with gold. The recesses (cavities) can be deep reactive ion etched (DRIE) using photolithography to a depth of 25 mils by patterning a silicon dioxide masking layer with etch selectivity greater than 100:1. can. After completion of the DRIE etch, which can provide nearly vertical and smooth sidewalls of the recess, the entire surface of the etched cover that will eventually engage the substrate can be plated with 3.5 um of gold. Cover 1400, which is part of RF module 1100, can be manufactured using the same or similar process as described with respect to FIG.

Covers utilized to provide electromagnetic isolation with microfabricated interiors created using semiconductor manufacturing provide reproducible dimensional tolerances limited only by semiconductor manufacturing tolerances. Dimensional tolerances are an important consideration when designing circuits with active and passive electrical components operating at high frequencies, eg, frequencies of 1 GHz and above. Being able to more accurately determine the height-to-width dimensions and volume of each recess associated with each electronic component means that the manufactured high-frequency module will have substantially the same characteristics as those contemplated by the design model. It means that you can. High frequency RF modules manufactured according to the microfabrication processes described herein will likely not require coordination between units to obtain the designed characteristics.

FIG. 17 is a graph 1700 of output performance of an example RF module 1100. The y-axis shows the output in dBm and the x-axis shows the output and input frequencies of the x2 frequency multiplication RF module in gigahertz. If the input frequency is 16 GHz, the output frequency is 32 GHz for the x2 frequency multiplier. As shown at 1705, the power output at 32 GHz is approximately +10 dBm, with substantially constant power output between 27 GHz and 40 GHz. At frequencies below 24 GHz and above 42 GHz, the power output will be found to be less than 60 dBm. Line 1710 represents the power output characteristics of each of the five different RF modules 1100. The respective power outputs between 24 GHz and 42 GHz are close enough to be viewed as a single line. As shown, there are small, insignificant differences in each RF module below and above these frequencies.

FIG. 18 is a graph 1800 showing suppression of the 16 GHz fundamental frequency at the output of an example RF module. As shown at 1805 in the graph, the 16 GHz input fundamental frequency is less than -70 dBm at the output of the RF module. As discussed with respect to FIG. 17, the five different RF modules represented by the five respective lines seen in this graph exhibit only small, insignificant levels of difference. As shown in the figure. Referring to FIGS. 17 and 18, the very similar performance of the five differently manufactured x2 frequency doubling RF modules is due to the precision of the components, especially the filters, the reproducible exact dimensions of each recess within the housing, and the The physical alignment of the recess to the component demonstrates reproducible performance achieved without individual adjustment of the RF module.

Although the exemplary RF module 1100 provides an amplified x2 frequency multiplier, various other types of RF modules using active, passive, or active and passive electrical components benefit from microfabricated fabrication. It is clear that it will be received. For example, wideband or limited bandwidth RF amplifiers, RF mixers, and high speed switching circuits can benefit from the reproducible electromagnetic shielding between units provided by such an enclosure. Additionally, additional shielding protection is employed by using a second casing to create a sandwich with the board to add shielding for components present on both major surfaces, and both surfaces of the board. can be done. High frequency circuits, e.g. circuits operating at frequencies higher than 1 GHz, must use targeted microfabrication manufacturing processes because as operating frequencies increase, the influence of physical dimensions on the associated RF electromagnetic fields becomes increasingly important. Deriving improved and reproducible unit-to-unit performance when the module is constructed. Another advantage is that the module can be probe tested before it is incorporated into the next assembly. Other advantages compared to modules using machined covers are lower cost (fewer parts, no adjustments), smaller size and weight, and faster assembly.

The module design is simplified and reduces the time and cost for NRE (Non-Repetitive Engineering), primarily due to the highly accurate and predictable configuration of the modules. For example, traditionally, the most time-consuming part of filter design is the iterations used to compensate for undesirable mutual coupling between filter elements through the air and substrate. In contrast, in an exemplary semiconductor RF module, each filter element resides within its own individual cavity and is isolated from adjacent elements. This structure virtually eliminates interconnections between parts, allowing designs to proceed faster, for example, from days to hours. Another reason for the lower NRE cost is the predictable performance of the interconnects between components. For example, in a conventional machined housing, two MMIC chips are connected to each other through a piece of substrate epoxidized to the bottom of the housing that carries a length of transmission line, with each end of the transmission line A wire bond is formed on the In contrast, in an exemplary semiconductor RF module, the interconnect lines are "printed" onto the surface of the substrate, which eliminates additional substrate variations and variations in the placement of such substrates. Wire bonds formed on an automated assembly line using a numerically programmed wire bonder produce highly reproducible wire profiles, which, when combined with a high-precision printing line, create It enables the development of design models that can capture the entire MMIC chip to the transmission line and simulate it with high accuracy. Other design models, such as probe-to-board transitions, dive-under transitions (as embodied by 1120, 1130, 1122, 1135, 1125), 90 degree bends, transmission line jogs, in-line series (blocking) Capacitors and the like can also be developed once and used repeatedly with predictable performance. The ability to accurately model interconnections that have been difficult to predict to known and repeatable characteristics puts the design flow in a "modular" regime and greatly reduces design time.

The scope of the invention is defined in the following claims.

Claims (18)

a flat dielectric substrate,
metal wiring arranged on both of the two main surfaces of the dielectric substrate and functioning as a reference ground;
at least one frequency selection circuit and at least one active semiconductor component disposed on one of the two main surfaces;
another metal interconnect disposed on at least one main surface of the dielectric substrate and connecting the at least one frequency selection circuit and the at least one active semiconductor component;
the at least one frequency selective circuit and the at least one active semiconductor component having at least first and second internal recesses dimensioned to surround and provide electromagnetic isolation; A casing having an interior made of semiconductor,
The casing is attached to the one main surface of the dielectric substrate,
the housing has an outwardly extending peripheral wall including a flat end region parallel to the dielectric substrate;
all internal surfaces of the housing, including the flat end region and the internal recess of the housing, have a deposited conductive metal coating;
the flat end region and the metal wiring on the one main surface of the dielectric substrate engage so that the internal recess functions as a reference ground;
the casing;
An RF module realized by semiconductor technology, comprising:
The housing connects the flat end region and the dielectric substrate such that the internal recess functions as the reference ground to provide electromagnetic isolation for the at least one frequency selection circuit and the at least one active semiconductor component. an RF module attached to said dielectric substrate by a metal-to-metal conductive bond between metal traces on one major surface of the RF module. further comprising a plurality of metal bond bumps extending outwardly from the metal wiring on the one major surface and at least one of the flat end regions;
the metal bond bump engages both each of the reference ground metal traces on the one major surface and the flat end region on the major surface of the housing;
the metal bond bump is compressed by bond pressure to strengthen a metal-to-metal conductive bond and establish a common reference ground with the deposited conductive metal coating on the interior of the housing;
RF module according to claim 1. In order to provide a continuous seal of the interior of the RF module against contamination from the external environment of the RF module, the housing includes a surface of the one major surface of the dielectric substrate around its periphery. 2. The RF module of claim 1, having a first elongated continuous peripheral wall that engages the metal trace disposed near a periphery and has a corresponding planar end region. the housing further comprises at least one projecting longitudinal peninsula wall having one of the flat end regions;
The at least one protruding longitudinal peninsular wall is a reference ground and connects any frequency selective circuitry and active semiconductor components on one side of the at least one longitudinal peninsular wall to the other side of the at least one longitudinal peninsular wall. electromagnetically isolated from other frequency selection circuits and active semiconductor components on the side of the
RF module according to claim 1. The at least one projecting longitudinal peninsular wall has a first signal path on one longitudinal side of the at least one projecting longitudinal peninsular wall and a first signal path on the other longitudinal side of the at least one projecting longitudinal peninsular wall. electromagnetically separating the second signal path;
enabling the first signal path and the second signal path to meander in the front-back direction, and minimizing the total area of the dielectric substrate required for the RF module;
RF module according to claim 4. a plurality of conductive through-hole vias arranged to connect metal wiring on both main surfaces of the dielectric substrate functioning as the reference ground;
a plurality of rows of conductive vias, each row of conductive vias adjacent to each other and spaced apart by less than 0.1 wavelength of an RF signal in the RF module, the rows of conductive vias being spaced apart by less than 0.1 wavelength of an RF signal in the RF module; , a plurality of rows of conductive vias disposed in the dielectric substrate near at least some of the peripheral edges of the at least one frequency selective circuit and the at least one active semiconductor component;
The RF module according to claim 1, further comprising: The casing is
the internal recess that is microfabricated by semiconductor;
a metal having a peak-to-valley roughness of less than 2 μm deposited within the semiconductor microfabricated interior;
comprising a dielectric wafer having a
RF module according to claim 1. Semiconductor technology implementation for providing electromagnetic shielding of RF-sensitive electronic components located on a flat dielectric substrate, having a metal trace serving as a reference ground located on at least one major surface The casing is made of
a dielectric wafer having a microfabricated semiconductor interior;
an internal recess defined between internal, outwardly extending peripheral walls, said peripheral walls having flat end regions parallel to and coplanar with each other, each of said recesses defining said recesses within said housing; dimensioned to surround the electronic component and provide electromagnetic isolation when the flat end region of the body engages one major surface of the dielectric substrate;
a conductive metal coating deposited on all internal surfaces of the housing, including the flat end region and the recess;
A casing comprising:
The flat end region is dimensioned to engage the metal trace on the one major surface of the dielectric substrate, and when engaged, the recess within the interior becomes part of the reference ground. form,
Housing. further comprising a plurality of metal bond bumps extending outwardly from the flat end region;
each of the plurality of metal bond bumps is sized to engage the metal trace on the one major surface serving as the reference ground;
The metal bonding bump is. compressible under bonding pressure and strengthens the metal-to-metal conductive bond;
The housing according to claim 8. The housing has a corresponding flat end region around its periphery dimensioned to engage the metal wiring disposed near the periphery of the one major surface of the dielectric substrate. a first continuously extending peripheral wall having;
the housing, when engaged with the dielectric substrate, provides a continuous seal of the interior of the RF module against contamination from an environment external to the RF module;
The housing according to claim 8. further comprising at least one projecting longitudinal peninsula wall having one of said flat end regions;
The at least one protruding longitudinal peninsula wall includes a signal path on one side of the longitudinal peninsular wall and a signal path on one side of the longitudinal peninsular wall when the housing is attached to the dielectric substrate. It is arranged so as to electromagnetically isolate a part of the other side,
enabling the signal path to meander in the front-back direction and minimizing the total area of the dielectric substrate;
The housing according to claim 8. 9. The housing of claim 8, wherein the recess in the interior comprises semiconductor micromachined deposited metal having a peak-to-valley roughness of less than 2 μm. A method of manufacturing a semiconductor technology packaging housing that provides electromagnetic shielding for high frequency RF components disposed on a substrate in which the housing engages the substrate, the method comprising:
applying a coating to an area on the main surface of the silicon wafer that defines the area where the walls of the recess will be located;
etching away the layer of silicon not protected by the coating to a first depth, the first depth of silicon defining each of the bottoms of the recesses;
remove the coating,
sputtering the entire exposed surface of the silicon wafer with gold such that the sputtered gold covers the edges of the walls, the bottom of the recess, and the sides of the wall;
plating the sputtered gold covered area with gold;
Methods that include. applying another coating to an area on the main surface of the silicon wafer that defines the area where the walls of the recess will be located, the other coating representing a small isolated area along the wall where the bonding bump will be located;
etching away the first layer of silicon not protected by the another coating to a second depth, the second depth of silicon defining the top of the wall;
removing said another coating;
The sputtering and the plating are also applied to bonding bumps,
further comprising the step of, performed before the step of claim 13.
14. The method according to claim 13. 14. The method of claim 13, wherein the plated gold surface within the recess has a peak-to-valley roughness of less than 2 μm. 15. The method of claim 14, wherein the bonding bump to bonding bump spacing is less than 1/5 of a quarter wavelength of the highest frequency in use. 14. The method of claim 13, wherein the etching is a reactive ion etching. 14. The method of claim 13, wherein the etching is a deep reactive ion etch.