JP2024031449A - Power conversion device and control method of power conversion device - Google Patents

Abstract

To prevent an expansion failure at the time of a short circuit current protection.SOLUTION: A semiconductor power conversion device comprises: a first driving circuit that drives a first semiconductor switching element; a second driving circuit that drives a second semiconductor switching element connected to the first semiconductor switching element in series; and a communication circuit that is capable of isolated bi-directional communications between the first driving circuit and the second driving circuit, and transmits, in the case where a first failure detection signal indicating that the first semiconductor switching element is failed or a second failure detection signal indicating that the second semiconductor switching element is in failed, the signal to the other driving circuit. The first driving circuit brings the first semiconductor switching element into an off state in the case where the second failure detection signal is transmitted from the second driving circuit, and the second driving circuit bring the second semiconductor switching element into an off state in the case where the first failure detection signal is input from the first driving circuit.SELECTED DRAWING: Figure 1

Description

Embodiments of the present invention relate to a power conversion device and a method of controlling the power conversion device.

In recent years, power semiconductor elements using wide-gap semiconductors have been put into practical use, and the breakdown voltage of the elements is increasing. Due to higher voltage resistance, unipolar elements such as MOSFETs can now be applied to fields where bipolar elements such as IGBTs were previously applied, enabling high-speed operation and contributing to further loss reduction and high-frequency switching. ing.
When using such a power semiconductor element as a switching element, a short-circuit protection operation is implemented in which the on-voltage drop of the switching element is observed, and if the on-voltage exceeds a threshold, it is determined that an overcurrent has occurred and the device enters a protective operation. Ta.
In this short circuit protection operation, a failure signal is output to a control device that outputs an on/off control signal to the switching element.
In response to this, the control device stops the operation of other healthy elements.

JP 2021-065039 Publication

However, in the conventional technology, when applied to a switching element that can be turned on and off at high speed in 1 μs or less, such as a MOSFET using a wide gap semiconductor such as SiC, the operation of other healthy elements is stopped via the control device. However, the signal transmission is slow and there is a possibility that the signal will not be delivered in time.
As a technique to solve the above problem, it has been proposed to turn off the other arm when a short-circuit failure is detected in one arm, but in general, the ground potential of the gate drive circuit that turns on and off the upper and lower arms of a semiconductor power conversion device is Since the gate drive circuits are different, it is not possible to simply connect the gate drive circuits of the upper and lower arms, and there is a risk that the configuration will become complicated.

The present invention has been made in view of the above, and an object of the present invention is to provide a power conversion device and a control method that can prevent extended failures when protecting against short circuit current.

The semiconductor power conversion device of the embodiment includes a first drive circuit that drives a first semiconductor switching element, a second drive circuit that drives a second semiconductor switching element connected in series to the first semiconductor switching element, and a first drive circuit that drives a second semiconductor switching element connected in series to the first semiconductor switching element. Insulated bidirectional communication is possible between the circuit and the second drive circuit, and a first failure detection signal indicating that the first semiconductor switching element has failed or a second failure detection signal indicating that the second semiconductor switching element has failed is transmitted. a communication circuit that transmits the signal to the other drive circuit when the signal is input, and the first drive circuit turns off the first semiconductor switching element when the second failure detection signal is transmitted from the second drive circuit. , the second drive circuit turns off the second semiconductor switching element when the first failure detection signal is input from the first drive circuit.

FIG. 1 is a schematic configuration diagram of a semiconductor power conversion device according to an embodiment. FIG. 2 is an explanatory diagram of a configuration example of a gate drive circuit. FIG. 3 is an explanatory diagram of a configuration example of a transmission data output circuit in the first gate drive circuit. FIG. 4 is an explanatory diagram of a configuration example of an inter-arm insulation communication circuit.

Next, preferred embodiments will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram of a semiconductor power conversion device according to an embodiment.
For ease of understanding, FIG. 1 will be described using a semiconductor power conversion device equipped with a single-phase half-bridge inverter as an example, but the invention is not limited to this. For example, a semiconductor power conversion device equipped with a three-phase half-bridge inverter is illustrated. It is also possible to apply it in the same way.

The semiconductor power conversion device 10 of the embodiment is roughly divided into a gate control circuit 11, a first gate drive circuit 12, a second gate drive circuit 13, a first N-channel MOS transistor 14, a second N-channel MOS transistor 15, and a first failure. It includes a detection circuit 16, a second failure detection circuit 17, an inter-arm insulation communication circuit 18, and a controller 19.

In the above configuration, the gate control circuit 11 controls the first gate drive circuit 12 and the second gate drive circuit 13 under the control of the controller 19.

The gate control circuit 11 outputs the first gate drive control signal DS1 to the first gate drive circuit 12, and receives the first failure detection signal E1X from the first gate drive circuit 12.

Further, the gate control circuit 11 outputs a second gate drive control signal DS2 to the second gate drive circuit 13, and receives a second failure detection signal E2X from the second gate drive circuit 13.

The first gate drive circuit 12 drives the first N-channel MOS transistor 14 based on the first gate drive control signal DS1 input from the gate control circuit 11.

The second gate drive circuit 13 drives the second N-channel MOS transistor 15 based on the second gate drive control signal DS2 input from the gate control circuit 11.

Here, specific examples of the first gate drive circuit 12 and the second gate drive circuit 13 will be described.
The first gate drive circuit 12 and the second gate drive circuit 13 have similar configurations, and the first gate drive circuit 12 will be described as an example.

FIG. 2 is an explanatory diagram of a configuration example of a gate drive circuit.
The first gate drive circuit 12 includes a photocoupler 51, an AND circuit 52, a complementary output circuit 53, a NOT circuit 54, a gate resistor 55, and a pull-down switch (pull-down transistor) 56.

The photocoupler 51 includes an LED 51A to which the first gate drive control signal DS1 is input, and a phototransistor 51B which is a light receiving element that performs photoelectric conversion and outputs the resultant signal as a gate drive signal.

The output terminal of the photocoupler 51 is connected to the first input terminal of the AND circuit 52, the first failure detection signal E1X is input to the second input terminal, and the transmitted signal E1X is input to the third input terminal. A second failure detection signal E2X is input.

The complementary output circuit 53 includes an NPN transistor 53A whose collector terminal is connected to a high potential side power supply, whose base terminal is connected to the output terminal of the AND circuit 52, and whose emitter terminal is connected to the emitter terminal of the NPN transistor 53A, and whose collector terminal is connected to the output terminal of the AND circuit 52. is connected to a low potential side power supply, and a PNP transistor 53BA whose base terminal is connected to the output terminal of the AND circuit 52.

The NOT circuit 54 negates the output of the AND circuit 52 and outputs the result.
The gate resistor 55 suppresses rapid fluctuations in the voltage at the gate terminal of the first N-channel MOS transistor 14, thereby stabilizing the operation of the first N-channel MOS transistor 14.

The pull-down switch 56 is turned on when the output of the NOT circuit 54 becomes "H" level, and connects the gate terminal of the first N-channel MOS transistor 14 to the low-potential side power supply. The gate terminal of the transistor 14 is reliably brought to the "L" level, the gate potential of the first N-channel MOS transistor 14 is fixed, and the first N-channel MOS transistor 14 is turned off to protect the first N-channel MOS transistor 14.
In the above description, the pull-down switch 56 is connected (short-circuited) to the low-potential side power supply, but it can also be connected (short-circuited) to the low-potential side terminal of the first N-channel MOS transistor 14. be.

FIG. 3 is an explanatory diagram of a configuration example of a transmission data output circuit in the first gate drive circuit.
FIG. 3A shows a configuration example of a transmission data output circuit that outputs transmission data in positive logic.

More specifically, the transmission data output circuit 12A has the first failure detection signal E1 inputted to one input terminal, and the power supply voltage drop detection signal LP of the first gate drive circuit 12 inputted to the other input terminal. , an OR circuit 12A1 which takes the logical sum of the first failure detection signal E1 and the power supply voltage drop detection signal LP and outputs the result as the first failure detection signal E1X.

Generally, when an abnormality occurs in the first N-channel MOS transistor 14 and the second N-channel MOS transistor 15, which are semiconductor switching elements, the power supply circuit voltage disappears in the first gate drive circuit 12 and the second gate drive circuit 13. There are many. That is, the power supply voltage drop detection signal LP becomes "H" level.

By adopting such a configuration, in the first gate drive circuit 12, the first failure detection signal E1 and the power supply voltage drop detection signal LP are logically summed to indicate a positive logic (if "H", a failure occurs). By outputting the first failure detection signal E1X as the first failure detection signal E1X (detection), it is possible to output the first failure detection signal E1X that is more suitable for the actual situation in a positive logic circuit configuration.

FIG. 3B shows a configuration example of a transmission data output circuit that outputs transmission data in negative logic.
More specifically, the transmission data output circuit 12A has the first failure detection signal E1 inputted to one input terminal, and the power supply voltage drop detection signal LP of the first gate drive circuit 12 inputted to the other input terminal. , a NOR circuit 12A2 that performs the logical sum of the first failure detection signal E1 and the power supply voltage drop detection signal LP and outputs the result as a first failure detection signal E1X.

Generally, when an abnormality occurs in the first N-channel MOS transistor 14 and the second N-channel MOS transistor 15, which are semiconductor switching elements, the power supply circuit voltage disappears in the first gate drive circuit 12 and the second gate drive circuit 13. There are many. That is, the power supply voltage drop detection signal LP becomes "H" level.

By adopting such a configuration, the first gate drive circuit 12 calculates the negative logic (in the case of "L" By outputting the first failure detection signal E1X (failure detection), the failure state can be reliably output even if the power supply voltage decreases and it becomes difficult to send an "H" level signal. This makes it possible to output the first failure detection signal E1X that is more in line with the actual situation.

The first N-channel MOS transistor 14 has a source terminal connected to the high potential side power supply PH, a drain terminal connected to the output terminal OUT, a gate terminal connected to the first gate drive circuit 12, and a first gate drive control signal DS1. is input and on/off control is performed.

The second N-channel MOS transistor 15 has a source terminal connected to the low potential side power supply PL, a drain terminal connected to the output terminal OUT, a gate terminal connected to the second gate drive circuit 13, and a second gate drive control signal DS2. is input and on/off control is performed.

The first failure detection circuit 16 includes a first backflow prevention diode 21 , a first voltage dividing circuit 22 , a first buffer circuit 23 , a first comparator 24 , and a first latch circuit 25 .
The first backflow prevention diode 21 has an anode terminal connected to the source terminal of the first N-channel MOS transistor 14 .

The first voltage dividing circuit 22 includes a first resistive element 22A, one end of which is connected to the cathode of the first backflow prevention diode 21, one end of which is connected to the other end of the first resistive element 22A, and the other end of which is connected to the low potential side power supply. A second resistance element 22B connected to PL.

The first buffer circuit 23 directly outputs the output voltage of the first voltage dividing circuit 22 to the first comparator 24 .
The first comparator 24 compares the output voltage of the first buffer circuit 23 with a first reference voltage Vref1 and outputs a first failure detection signal E1 to the first latch circuit 25.

The first latch circuit 25 takes in the first failure detection signal E1, which is the output of the first comparator 24, at a predetermined timing under the control of the controller, holds it, and outputs it to the first gate drive circuit 12.

The second failure detection circuit 17 includes a second backflow prevention diode 31, a second voltage dividing circuit 32, a second buffer circuit 33, a second comparator 34, and a second latch circuit 35.
The second backflow prevention diode 31 has an anode terminal connected to the drain terminal of the second N-channel MOS transistor 15.

The second voltage dividing circuit 32 includes a first resistive element 32A having one end connected to the cathode of the second backflow prevention diode 31, one end connected to the other end of the first resistive element 32A, and the other end connected to the low potential side power supply. A second resistance element 32B connected to PL.
The second buffer circuit 33 directly outputs the output voltage of the second voltage dividing circuit 32 to the second comparator 34 .

The second comparator 34 compares the output voltage of the second buffer circuit 33 with the second reference voltage Vref2 and outputs a second failure detection signal E2 to the second latch circuit 35.

The second latch circuit 35 takes in the second failure detection signal E2, which is the output of the second comparator 34, at a predetermined timing under the control of the controller, holds it, and outputs it to the second gate drive circuit 13.

Next, the inter-arm insulation communication circuit 18 will be explained.
FIG. 4 is an explanatory diagram of a configuration example of an inter-arm insulation communication circuit.
The inter-arm insulation communication circuit 18 includes a first optical coupler 18A that transmits the first failure detection signal E1X from the first gate drive circuit 12 to the second gate drive circuit, and a first gate from the second gate drive circuit 13. A second optical coupler 18B that transmits a second failure detection signal E2X to the drive circuit 12 is provided.

According to the above configuration, since the transmission of the first failure detection signal E1 and the second failure detection signal E2 is performed in an insulated state via the inter-arm insulated communication circuit 18, the first gate drive circuit 12 and the second gate drive Communication can be reliably performed without being affected by the difference in potential level at which the circuit 13 is operating.

In this case, since a high voltage is applied to the main circuit of the semiconductor power conversion device including the first N-channel MOS transistor 14 and the second N-channel MOS transistor 15, a high dielectric strength voltage (for example, a device with a DC 1500 V) is applied according to standards such as JIS. In this case, a dielectric strength voltage of 5400 VAC/1 minute) is required.

On the other hand, this is because the gate control circuit 11 is a low-voltage circuit composed of a low-voltage integrated circuit or the like. Therefore, the photocoupler 51 that insulates the two is required to have the same dielectric strength performance as the main circuit.

On the other hand, the inter-arm isolated communication circuit 18 shown in FIG. 4 is not required to have the same dielectric strength performance as the main circuit.

This is because both the transmitting side and the receiving side are high voltage circuits, and only the maximum rated voltage of the first N-channel MOS transistor 14 and the second N-channel MOS transistor 15 (for example, 3300 V for a 1500 V DC device) is applied. Because there is. Generally, the rated voltages of the first N-channel MOS transistor 14 and the second N-channel MOS transistor 15 are lower than the withstand voltages of the first N-channel MOS transistor 14 and the second N-channel MOS transistor 15.
Therefore, there is no problem even if the dielectric strength performance of the inter-arm insulated communication circuit 18 is lower than the dielectric strength voltages of the first gate drive circuit 12 and the second gate drive circuit 13.
As a result, the inter-arm insulation communication circuit 18 can be configured simply and compactly.

Next, the operation of the embodiment will be explained.
The gate control circuit 11 outputs a first gate drive control signal DS1 to the first gate drive circuit 12 under the control of the controller 19.

Thereby, the LED 51A of the photocoupler 51 of the first gate drive circuit 12 performs electro-optical conversion based on the input first gate drive control signal DS1, and lights the first gate drive control signal DS1 to the phototransistor 51B. Transmit as.
Thereby, the phototransistor 51B performs photoelectric conversion and outputs the first gate drive control signal DS1 to the first input terminal of the AND circuit 52.

At this time, the first failure detection signal E1X is input from the first latch circuit 25 to the second input terminal of the AND circuit 52, and the first failure detection signal E1X is input to the third input terminal via the inter-arm insulation communication circuit 18. A second failure detection signal E2X transmitted from the second gate drive circuit 13 is input.

In this case, assuming that the first failure detection signal E1X and the second failure detection signal E2X are negative logic signals, both are at the "H" level when no failure is detected.

Therefore, when no failure is detected, the AND circuit 52 outputs a signal at the "H" level when the first gate drive control signal DS1 becomes "H" level, and the first gate drive control signal DS1 becomes "H" level. When the level becomes "L", a signal of "L" level is output. In other words, this is equivalent to outputting the first gate drive control signal DS1 as is.

When the first gate drive control signal DS1 is at "H" level, the NPN transistor 53A of the complementary output circuit 53 is turned on.
At this time, the PNP transistor 53B of the complementary output circuit 53 is turned off.

Furthermore, the output of the NOT circuit 54 is at the "L" level. Therefore, the pull-down switch 56 is in an off state.
Therefore, an "H" level signal is applied from the complementary output circuit 53 to the gate terminal of the first N-channel MOS transistor 14 via the gate resistor 55, and the first N-channel MOS transistor 14 is turned on.

On the other hand, when the first gate drive control signal DS1 is at "L" level, the NPN transistor 53A of the complementary output circuit 53 is turned off.
At this time, the PNP transistor 53B of the complementary output circuit 53 is turned on.

Furthermore, the output of the NOT circuit 54 is at the "H" level. Therefore, the pull-down switch 56 is in the on state.
Therefore, an "L" level signal is applied from the complementary output circuit 53 to the gate terminal of the first N-channel MOS transistor 14 via the gate resistor 55, and the first N-channel MOS transistor 14 is turned off.

Further, the first failure detection signal E1X is at the "L" level when a failure is detected in the first failure detection circuit 16.
Therefore, when a failure is detected in the first failure detection circuit 16, the AND circuit 52 always outputs " Outputs an L” level signal.

As a result, the NPN transistor 53A of the complementary output circuit 53 is turned off, and the PNP transistor 53B of the complementary output circuit 53 is turned on, regardless of the level of the first gate drive control signal DS1 and the signal level of the second failure detection signal E2X. becomes.

Further, the output of the NOT circuit 54 is always at the "H" level regardless of the level of the first gate drive control signal DS1. Therefore, the pull-down switch 56 is always in the on state.

Therefore, an "L" level signal is applied from the complementary output circuit 53 to the gate terminal of the first N-channel MOS transistor 14 via the gate resistor 55, so that the first N-channel MOS transistor 14 is always in an off state.
That is, when a failure is detected, the first failure detection signal E1X immediately goes to the "L" level and turns off the first N-channel MOS transistor 14.

At this time, the first failure detection signal E1X is also output to the inter-arm insulation communication circuit 18, and the inter-arm insulation communication circuit 18 connects the first optical coupler 18A from the first gate drive circuit 12 to the second gate drive circuit. The first failure detection signal E1X is transmitted via the first failure detection signal E1X.

As a result, when a failure is detected in the first failure detection circuit 16, the first failure detection signal E1X of "L" level is input to the AND circuit 52 of the second gate drive circuit 13. , the AND circuit 52 of the second gate drive circuit 13 outputs an "L" level signal regardless of the signal level of the second gate drive control signal DS2 and the signal level of the second failure detection signal E2X.

As a result, regardless of the level of the first gate drive control signal DS1 and the signal level of the second failure detection signal E2X, the NPN transistor 53A of the complementary output circuit 53 of the second gate drive circuit 13 is turned off, and the complementary output circuit 53 The PNP transistor 53B is turned on.

Further, the output of the NOT circuit 54 of the second gate drive circuit 13 is always at the "H" level regardless of the level of the first gate drive control signal DS1. Therefore, the pull-down switch 56 is in the on state.

Therefore, an “L” level signal is applied from the complementary output circuit 53 of the second gate drive circuit 13 to the gate terminal of the second N-channel MOS transistor 15 via the gate resistor 55, and the second N-channel MOS transistor 15 Turns off.

That is, when the first failure detection signal E1X becomes "L" level, the first failure detection signal E1X is transmitted via the first optical coupler 18A, the second N-channel MOS transistor 15 is also turned off, and the first N-channel MOS transistor 15 is turned off. The influence of failure of the MOS transistor 14 can be avoided.

In parallel with the above operation, the gate control circuit 11 outputs a second gate drive control signal DS2 to the second gate drive circuit 13 under the control of the controller 19.

Thereby, the LED 51A of the photocoupler 51 of the second gate drive circuit 13 performs electro-optical conversion based on the input second gate drive control signal DS2, and lights the second gate drive control signal DS2 to the phototransistor 51B. Transmit as.
Thereby, the phototransistor 51B performs photoelectric conversion and outputs the second gate drive control signal DS2 to the first input terminal of the AND circuit 52.

At this time, the second failure detection signal E2X is input from the second latch circuit 35 to the third input terminal of the AND circuit 52, and the second failure detection signal E2X is input to the second input terminal via the inter-arm insulation communication circuit 18. A first failure detection signal E1X transmitted from the first gate drive circuit 12 is input.

Then, when no failure is detected, the AND circuit 52 outputs a signal at the "H" level when the second gate drive control signal DS2 becomes "H" level, and the second gate drive control signal DS2 becomes "H" level. When the level becomes "L", a signal of "L" level is output. In other words, this is equivalent to outputting the second gate drive control signal DS2 as is.

When the second gate drive control signal DS2 is at "H" level, the NPN transistor 53A of the complementary output circuit 53 is turned on.
At this time, the PNP transistor 53B of the complementary output circuit 53 is turned off.

Furthermore, the output of the NOT circuit 54 is at the "L" level. Therefore, the pull-down switch 56 is in an off state.
Therefore, an "H" level signal is applied from complementary output circuit 53 to the gate terminal of second N-channel MOS transistor 15 via gate resistor 55, and second N-channel MOS transistor 15 is turned on.

On the other hand, when the second gate drive control signal DS2 is at "L" level, the NPN transistor 53A of the complementary output circuit 53 is turned off.

At this time, the PNP transistor 53B of the complementary output circuit 53 is turned on, and the output of the NOT circuit 54 is at the "H" level. Therefore, the pull-down switch 56 is in the on state.

Therefore, an "L" level signal is applied from the complementary output circuit 53 to the gate terminal of the second N-channel MOS transistor 15 via the gate resistor 55, and the second N-channel MOS transistor 15 is turned off.

Further, the second failure detection signal E2X is at the "L" level when a failure is detected in the second failure detection circuit 17.
Therefore, when a failure is detected in the second failure detection circuit 17, the AND circuit 52 always outputs " Outputs an L” level signal.

As a result, the NPN transistor 53A of the complementary output circuit 53 is turned off, and the PNP transistor 53B of the complementary output circuit 53 is turned on, regardless of the level of the second gate drive control signal DS2 and the signal level of the first failure detection signal E1X. becomes.

Further, the output of the NOT circuit 54 is always at the "H" level regardless of the level of the second gate drive control signal DS2. Therefore, the pull-down switch 56 is always on.

Therefore, an "L" level signal is applied from the complementary output circuit 53 to the gate terminal of the second N-channel MOS transistor 15 via the gate resistor 55, so that the second N-channel MOS transistor 15 is always in an off state.

That is, when a failure is detected, the second failure detection signal E2X immediately goes to the "L" level and turns off the second N-channel MOS transistor 15.
At this time, the second failure detection signal E2X is also output to the inter-arm insulation communication circuit 18, and the inter-arm insulation communication circuit 18 connects the second optical coupler from the second gate drive circuit 13 to the first gate drive circuit 12. A second failure detection signal E2X is transmitted via 18B.

As a result, when a failure is detected in the second failure detection circuit 17, the second failure detection signal E2X of "L" level is input to the AND circuit 52 of the first gate drive circuit 12. , the AND circuit 52 of the first gate drive circuit 12 outputs an "L" level signal regardless of the signal level of the first gate drive control signal DS1 and the signal level of the first failure detection signal E1X.

As a result, regardless of the level of the first gate drive control signal DS1 and the signal level of the first failure detection signal E1X, the NPN transistor 53A of the complementary output circuit 53 of the first gate drive circuit 12 is turned off, and the complementary output circuit 53 The PNP transistor 53B is turned on.

Furthermore, the output of the NOT circuit 54 of the first gate drive circuit 12 is always at the "H" level, regardless of the level of the first gate drive control signal DS1. Therefore, the pull-down switch 56 is in the on state.

Therefore, an “L” level signal is applied from the complementary output circuit 53 of the first gate drive circuit 12 to the gate terminal of the first N-channel MOS transistor 14 via the gate resistor 55, and the first N-channel MOS transistor 14 Turns off.

That is, when the second failure detection signal E2X becomes "L" level, the second failure detection signal E2X is transmitted via the second optical coupler 18B, the first N-channel MOS transistor 14 is also turned off, and the second N-channel MOS transistor 14 is turned off. The influence of failure of the MOS transistor 15 can be avoided.

As described above, the first N-channel MOS transistor 14 and the second N-channel MOS transistor 15 forming the opposing arm can be protected at high speed without relying on an external control device (for example, the controller 19). , it is possible to prevent the spread of failure in the semiconductor power conversion device 10, and it is possible to improve reliability.

In the above description, a photocoupler is used to ensure electrical insulation, but it is possible to ensure electrical insulation using a pulse transformer, an optical fiber, or the like.
Although several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the invention described in the claims and its equivalents.

10 Semiconductor power conversion device 11 Gate control circuit 12 First gate drive circuit 12A Transmission data output circuit 13 Second gate drive circuit 14 First N-channel MOS transistor 15 Second N-channel MOS transistor 16 First failure detection circuit 17 Second failure detection circuit 18 Inter-arm insulation communication circuit 18A First optical coupler 18B Second optical coupler 19 Controller 21 First backflow prevention diode 22 First voltage divider circuit 22A First resistance element 22B Second resistance element 23 First buffer circuit 24 First comparator 25 First latch circuit 31 Second backflow prevention diode 32 Second voltage divider circuit 32A First resistance element 32B Second resistance element 33 Second buffer circuit 34 Second comparator 35 Second latch circuit 51 Photocoupler 51A LED
51B Phototransistor 52 AND circuit 53 Complementary output circuit 53A NPN transistor 53B PNP transistor 53BA PNP transistor 54 NOT circuit 55 Gate resistor 56 Pull-down switch 12A1 OR circuit 12A2 NOR circuit LP Power supply voltage drop detection signal OUT Output terminal PH High potential side power supply PL Low Potential side power supply DS1 First gate drive control signal DS2 Second gate drive control signal E1 First failure detection signal E1X First failure detection signal E2 Second failure detection signal E2X Second failure detection signal Vref1 First reference voltage Vref2 Second reference Voltage

Claims (5)

a first drive circuit that drives a first semiconductor switching element;
a second drive circuit that drives a second semiconductor switching element connected in series to the first semiconductor switching element;
Insulated bidirectional communication is possible between the first drive circuit and the second drive circuit, and a first failure detection signal indicating that the first semiconductor switching element has failed or that the second semiconductor switching element has failed. a communication circuit that transmits the second failure detection signal to the other drive circuit when the second failure detection signal is input;
The first drive circuit turns off the first semiconductor switching element when the second failure detection signal is transmitted from the second drive circuit,
The second drive circuit turns off the second semiconductor switching element when the first failure detection signal is transmitted from the first drive circuit.
Semiconductor power conversion device. a first failure detection circuit that outputs the first failure detection signal when the voltage of the first semiconductor switching element exceeds a first threshold;
a second failure detection circuit that outputs the second failure detection signal when the voltage of the second semiconductor switching element exceeds a second threshold;
The semiconductor power conversion device according to claim 1, comprising: The first failure detection circuit outputs the first failure detection signal even when the voltage of the power supply that drives the first semiconductor switching element is below a predetermined threshold voltage,
The second failure detection circuit outputs the second failure detection signal even when a voltage of a power source that drives the second semiconductor switching element is below a predetermined threshold voltage.
The semiconductor power conversion device according to claim 2. The first failure detection signal and the second failure detection signal are generated as negative logic signals,
A semiconductor power conversion device according to any one of claims 1 to 3. A method for controlling a power conversion device comprising: a first drive circuit that drives a first semiconductor switching element; and a second drive circuit that drives a second semiconductor switching element connected in series to the first semiconductor switching element. hand,
transmitting information to the other drive circuit that the first semiconductor switching element has failed or that the second semiconductor switching element has failed;
Turning the first semiconductor switching element into an OFF state when it is transmitted that the first semiconductor switching element has failed;
turning the second semiconductor switching element into an OFF state when it is transmitted that the second semiconductor switching element has failed;
A method for controlling a power converter equipped with the following.

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