JP2024024991A - electronic components - Google Patents

Abstract

The present invention reduces stress applied to a capacitor in an electronic component having a structure in which a capacitor is provided on a substrate. SOLUTION: An electronic component 100 includes a capacitor C1 including a lower electrode pattern 35, an upper electrode pattern 41, and a dielectric film 12 located between these, and a capacitor C1 that overlaps a signal terminal S1 in plan view and is connected to the signal terminal S1. It includes a connected conductor pattern 51 and a connection pattern 58 that connects the upper electrode pattern 41 and the conductor pattern 51. The connection pattern 58 connects the upper electrode pattern 41 and the conductor pattern 51 not by the shortest distance but by a detour. This makes it possible to relieve the stress applied from the conductor pattern 51 to the upper electrode pattern 41 via the connection pattern 58. [Selection diagram] Figure 5

Description

TECHNICAL FIELD The present disclosure relates to electronic components, and particularly to electronic components including capacitors provided on a substrate.

Patent Document 1 discloses a surface-mounted chip-type electronic component that includes a capacitor provided on a substrate.

JP2022-094391A

In this type of electronic component, it is important to design the capacitor so that strong stress is not applied to it.

The present disclosure describes a technique for reducing stress applied to a capacitor in an electronic component having a structure in which a capacitor is provided on a substrate.

An electronic component according to one aspect of the present disclosure includes a substrate, a terminal electrode, a capacitor provided on the substrate and including a lower electrode pattern, an upper electrode pattern, and a dielectric film located between these, and a terminal in a plan view. It includes a conductor pattern that overlaps with the electrode and is connected to the terminal electrode, and a connection pattern that connects the upper electrode pattern and the conductor pattern. and connect.

According to the present disclosure, it is possible to alleviate the stress applied from the conductor pattern to the upper electrode pattern via the connection pattern.

In the present disclosure, the lower electrode pattern is formed on the first conductor layer provided on the substrate, the upper electrode pattern is formed on the second conductor layer provided on the substrate, and the conductor pattern and the connection pattern are , the connection pattern is formed in the third conductor layer provided on the substrate, and the connection pattern is formed in the first via hole provided in the first interlayer insulating film located between the second conductor layer and the third conductor layer. The conductor pattern is connected to the terminal electrode through the second via hole provided in the second interlayer insulating film covering the third conductor layer, and the connection pattern is connected to the upper electrode pattern through the first conductor layer. The first via hole and the second via hole may be arranged so as to avoid the virtual pattern connecting the second via hole at the shortest distance, thereby forming a clearance region in which no connection pattern exists on at least a portion of the virtual pattern. According to this, it becomes possible to more effectively relieve stress applied to the upper electrode pattern. In this case, the clearance area may divide the virtual pattern in the width direction. According to this, the stress applied to the upper electrode pattern can be alleviated even more effectively.

In the present disclosure, the connection pattern includes a first partial pattern connected to the upper electrode pattern and a second partial pattern connecting the upper electrode pattern and the conductor pattern, and the extending direction of the second partial pattern is bent or curved. It doesn't matter if you do. According to this, the stress applied to the upper electrode pattern can be alleviated due to the springiness of the connection pattern. In this case, the angle at the bent portion of the second partial pattern may be greater than or equal to 90° and less than or equal to 150°. According to this, the stress applied to the upper electrode pattern can be alleviated even more effectively.

An electronic component according to an aspect of the present disclosure further includes an inductor that is provided on a substrate and includes a winding pattern connected to a capacitor, and the upper electrode pattern is located outside the winding pattern in a plan view. I don't mind. According to this, it becomes possible to arrange the capacitor while avoiding interference with the winding pattern.

As described above, the present disclosure provides a technique for reducing stress applied to a capacitor in an electronic component having a structure in which a capacitor is provided on a substrate.

FIG. 1 is a schematic perspective view showing the appearance of an electronic component 100 according to an embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view of the electronic component 100. FIG. 3 is an equivalent circuit diagram of the electronic component 100. FIG. 4 is a schematic plan view showing the pattern shapes of the conductor layers M1 and MM. FIG. 5 is a schematic plan view showing the pattern shape of the conductor layer M2. FIG. 6 is a schematic plan view showing the pattern shape of the conductor layer M3. FIG. 7 is a schematic plan view showing the pattern shapes of the conductor layers M4 and M5. FIG. 8 is a schematic partial cross-sectional view showing a state in which the electronic component 100 is mounted on the circuit board 80. FIG. 9 is a schematic plan view for explaining the shape of the connection pattern 58. FIG. 10 is a schematic plan view for explaining the shape of the connection pattern 58 according to a modified example.

Hereinafter, embodiments of the technology according to the present disclosure will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic perspective view showing the appearance of an electronic component 100 according to an embodiment of the technology according to the present disclosure. Further, FIG. 2 is a schematic cross-sectional view of the electronic component 100.

The electronic component 100 according to the present embodiment is a surface-mounted high-pass filter, and as shown in FIG. It includes signal terminals S1 and S2 and ground terminals G1 and G2 formed on the surface of the interlayer insulating film 20. As shown in FIG. 2, the surface of the substrate 10 is covered with a planarizing layer 11, and a plurality of conductor layers M1 to M4, MM covered with an interlayer insulating film 20 are provided on the planarizing layer 11. . Signal terminals S1, S2 and ground terminals G1, G2 are formed on the conductor layer M5 located at the top layer. Interlayer insulating film 20 includes four interlayer insulating films 21 to 24.

The material for the substrate 10 may be any material that is chemically and thermally stable, generates little stress, and can maintain surface smoothness, and is not particularly limited, such as silicon single crystal, alumina, Sapphire, aluminum nitride, MgO single crystal, SrTiO ₃ single crystal, surface oxidized silicon, glass, quartz, ferrite, etc. can be used. As the planarization layer 11, alumina, silicon oxide, or the like can be used.

FIG. 3 is an equivalent circuit diagram of the electronic component 100 according to this embodiment.

As shown in FIG. 3, the electronic component 100 according to the present embodiment includes capacitors C1, C2, C4, and C5 connected in series between signal terminal S1 and signal terminal S2, and capacitors C1, C2, C4, and C5 connected in parallel to capacitors C1 and C2. Connection of the connected capacitor C3, the capacitor C6 connected in parallel to the capacitors C4 and C5, the inductor L1 connected between the connection point of the capacitors C1 and C2 and the ground terminal G1, and the capacitors C4 and C5. It has an inductor L2 connected between the point and the ground terminal G2. With this circuit configuration, the electronic component 100 according to this embodiment functions as a high-pass filter. The frequency characteristics of the high-pass filter are basically determined by the capacitance of the capacitors C1 to C6 and the inductance of the inductors L1 and L2.

The structure of the conductor layers M1 to M5 and MM included in the electronic component 100 will be described below. Note that the line AA shown in FIGS. 4 to 7 indicates the cross-sectional position of FIG. 2.

The conductor layer M1 is the lowest conductor layer, and includes conductor patterns 31 to 34, winding patterns 35 and 36, lower electrode patterns 37 and 38, and a dummy pattern 39, as shown in FIG. The conductor patterns 31 to 34 are provided at positions overlapping the signal terminals S1 and S2 and the ground terminals G1 and G2, respectively, in plan view. The winding patterns 35 and 36 are patterns that rotate approximately one turn, and constitute a part of the inductors L1 and L2, respectively. Lower electrode patterns 37 and 38 are arranged between conductor pattern 31 and conductor pattern 32. Among these, the lower electrode pattern 37 is connected to the conductor pattern 31 and the lower electrode pattern 38 is connected to the conductor pattern 32. The dummy pattern 39 is arranged between the conductor pattern 33 and the conductor pattern 34, and is not connected to any conductor pattern. The conductor patterns 31 to 34 and the winding patterns 35 and 36 are connected to the upper conductor layer M2 via via holes 31a to 36a provided in the interlayer insulating film 21, respectively.

As shown in FIG. 2, the surface of the conductor layer M1 is covered with a dielectric film 12 made of silicon nitride or the like, and the conductor layer MM is provided on the dielectric film 12. As shown in FIG. 4, conductor layer MM includes upper electrode patterns 41-46. Of these, the upper electrode patterns 41 and 42 are provided at positions overlapping a part of the winding pattern 35, and the upper electrode patterns 44 and 45 are provided at positions overlapping a part of the winding pattern 36. The upper electrode pattern 41 is provided at a position overlapping with one end of the winding pattern 35, and the upper electrode pattern 45 is provided at a position overlapping with one end of the winding pattern 36. The portions of the winding patterns 35 and 36 that overlap with the upper electrode patterns 41, 42, 44, and 45 function as lower electrodes. As a result, the winding pattern 35, the upper electrode pattern 41, and the dielectric film 12 constitute a capacitor C1, and the winding pattern 35, the upper electrode pattern 42, and the dielectric film 12 constitute a capacitor C2. Similarly, the winding pattern 36, the upper electrode pattern 44, and the dielectric film 12 constitute a capacitor C4, and the winding pattern 36, the upper electrode pattern 45, and the dielectric film 12 constitute a capacitor C5. Further, the upper electrode patterns 43 and 46 are provided at positions overlapping with the lower electrode patterns 37 and 38, respectively. As a result, the lower electrode pattern 37, the upper electrode pattern 43, and the dielectric film 12 constitute a capacitor C3, and the lower electrode pattern 38, the upper electrode pattern 46, and the dielectric film 12 constitute a capacitor C6. The upper electrode patterns 41 to 46 are connected to the upper conductor layer M2 via via holes 41a to 46a provided in the interlayer insulating film 21, respectively.

The conductor layer M2 is located above the conductor layer M1 via the interlayer insulating film 21, and includes conductor patterns 50 to 54, 57, connection patterns 58, 59, and winding patterns 55, 56, as shown in FIG. I'm here. The conductor patterns 51 to 54 are connected to the conductor patterns 31 to 34 of the conductor layer M1 via via holes 31a to 34a provided in the interlayer insulating film 21, respectively. The winding patterns 55 and 56 are patterns that revolve around one turn, and constitute a part of the inductors L1 and L2, respectively. One end of the winding patterns 55, 56 is connected to the other end of the winding patterns 35, 36 of the conductor layer M1 via via holes 35a, 36a provided in the interlayer insulating film 21, respectively. The conductor pattern 57 is commonly connected to the upper electrode patterns 42, 43, 44, and 46 of the conductor layer M1 via via holes 42a, 43a, 44a, and 46a provided in the interlayer insulating film 21. The connection pattern 58 is a pattern that protrudes from the conductor pattern 51 toward the winding pattern 55, and is connected in-plane to the conductor pattern 51 and connected to the conductor layer M1 through the via hole 41a provided in the interlayer insulating film 21. is connected to the upper electrode pattern 41 of. The connection pattern 59 is a pattern that protrudes from the conductor pattern 52 toward the winding pattern 56, and is connected in-plane to the conductor pattern 52 and connected to the conductor layer M1 through the via hole 45a provided in the interlayer insulating film 21. is connected to the upper electrode pattern 45 of. The conductive pattern 50 is a pattern that connects the conductive pattern 53 and the conductive pattern 54, and serves to short-circuit the ground terminals G1 and G2. A dummy pattern 39 is present at a position overlapping with the conductor pattern 50, thereby ensuring flatness. The conductor patterns 51 to 54 and the winding patterns 55 and 56 are connected to the upper conductor layer M3 through via holes 51a to 56a provided in the interlayer insulating film 22, respectively.

The conductor layer M3 is located above the conductor layer M2 via the interlayer insulating film 22, and includes conductor patterns 61 to 64 and winding patterns 65 and 66, as shown in FIG. The conductor patterns 61 to 64 are connected to the conductor patterns 51 to 54 of the conductor layer M2 via via holes 51a to 54a provided in the interlayer insulating film 22, respectively. The winding patterns 65 and 66 are patterns that rotate approximately 0.5 turns, and constitute a part of the inductors L1 and L2, respectively. One end of the winding patterns 65, 66 is connected to the other end of the winding patterns 55, 56 of the conductor layer M2 via via holes 55a, 56a provided in the interlayer insulating film 22, respectively. The other ends of the winding patterns 65 and 66 are connected to conductor patterns 63 and 64, respectively. The conductor patterns 61 to 64 are connected to the upper conductor layer M4 via via holes 61a to 64a provided in the interlayer insulating film 23, respectively.

The conductor layer M4 is located above the conductor layer M3 via the interlayer insulating film 23, and includes conductor patterns 71 to 74, as shown in FIG. The conductor patterns 71 to 74 are connected to the conductor patterns 61 to 64 of the conductor layer M3 via the via holes 61a to 64a provided in the interlayer insulating film 23, respectively, and are connected to the conductor patterns 61 to 64 provided in the interlayer insulating film 24, respectively. It is connected to the upper conductor layer M5 via 74a. Conductor layer M5 includes signal terminals S1 and S2 and ground terminals G1 and G2. Signal terminals S1, S2 and ground terminals G1, G2 are connected to conductor patterns 71-74 of conductor layer M4 via via holes 71a-74a provided in interlayer insulating film 24, respectively. The conductor layers M1 to M5 and MM described above are all made of a good conductor such as Cu (copper). The surfaces of the signal terminals S1, S2 and the ground terminals G1, G2 may be subjected to surface treatment to improve wettability with solder.

With the above pattern structure, the winding patterns 35, 55, 65, and 75 constitute the inductor L1, and the winding patterns 36, 56, 66, and 76 constitute the inductor L2. Here, the winding directions of the inductors L1 and L2 starting from the ground terminals G1 and G2 are opposite to each other, so that current flows in the same direction in adjacent sections of the inductors L1 and L2 on the same conductor layer.

FIG. 8 is a schematic partial cross-sectional view showing a state in which the electronic component 100 according to this embodiment is mounted on a circuit board 80.

A land pattern 81 is provided on the circuit board 80. FIG. 8 shows a portion where the land pattern 81 and the signal terminal S1 are connected via the solder 82 and the surrounding area thereof. Although not shown, the other signal terminals S2 and ground terminals G1 and G2 are also connected to their corresponding land patterns via solder. When mounting the electronic component 100 on the circuit board 80, the solder 82 is reflowed. During reflow, the electronic component 100 is heated to about 260° C., so when the temperature returns to room temperature after reflow, stress occurs inside the electronic component 100 due to the difference in coefficient of thermal expansion of each member. . In particular, since silicon nitride forming the dielectric film 12 and polyimide forming the interlayer insulating film 20 have a large difference in coefficient of thermal expansion, strong stress is likely to be applied to the dielectric film 12.

Specifically, as the temperature decreases after reflow, polyimide, which has a large coefficient of thermal expansion, contracts, but since the signal terminals S1 and S2 and the ground terminals G1 and G2 are fixed to the circuit board 80, stress does not occur. The conductor patterns 31, 51, 61, and 71 are not opened, but are pulled inward as shown by F1. This is because the conductor patterns 31, 51, 61, and 71 overlap the signal terminal S1 in plan view and are connected to each other via the via hole. When the conductor pattern 51 is pulled inward, the connection pattern 58 located on the same conductor layer M2 is also pulled, as indicated by the symbol F2. Since the connection pattern 58 is connected to the upper electrode pattern 41 through the via hole 41a provided in the interlayer insulating film 21, a force in the peeling direction acts on the upper electrode pattern 41, as shown by reference symbol F3. Here, if the force in the peeling direction indicated by the symbol F3 is strong, a gap is generated between the upper electrode pattern 41 and the dielectric film 12, and the capacitance of the capacitor C1 is reduced.

In order to suppress such a phenomenon, in this embodiment, the tensile stress applied to the upper electrode pattern 41 is alleviated by bending or curving the connection patterns 58 and 59 instead of straight lines, as shown in FIG. ing. In other words, the connection patterns 58 and 59 may be formed not in a straight line but in a non-linear shape including bent or curved portions. Hereinafter, the shape of the connection pattern 58 will be explained in more detail.

FIG. 9 is a schematic plan view for explaining the shape of the connection pattern 58.

As shown in FIG. 9, the connection pattern 58 is a pattern that is integrated with the conductor pattern 51, but the conductor pattern covers a portion overlapping with the via hole 51a provided in the interlayer insulating film 22 and a substantially rectangular area located around the portion. 51, the other portions constitute a connection pattern 58. The connection pattern 58 includes a first partial pattern 58A that is connected to the upper electrode pattern 41 via a via hole 41a provided in the interlayer insulating film 21, and a second partial pattern 58B that connects the conductor pattern 51 and the first partial pattern 58A. including.

As shown in FIG. 9, the extending direction of the second partial pattern 58B is not linear but bent or curved. In other words, the connection pattern 58 does not connect the upper electrode pattern 41 and the conductor pattern 51 linearly over the shortest distance, but connects them in a detour. More specifically, the via hole 51a connected to the conductor pattern 51 and the via hole 41a connected to the upper electrode pattern 41 are not connected at the shortest distance by the connection pattern 58, but the via hole 51a and the via hole 41a are connected linearly at the shortest distance. The connection pattern 58 is arranged avoiding the virtual pattern 91 that connects to. As a result, a clearance region 92 in which the connection pattern 58 does not exist is formed on the virtual pattern 91.

The second partial pattern 58B of the connection pattern 58 has a section 58B1 extending perpendicularly to the connection side of the substantially rectangular conductor pattern ₅₁ and extends in a direction different from the extending direction of the section _58B1 . It has a section _58B2 . In the example shown in FIG. 9, the extending directions of the section _58B1 and the section _58B2 change at the bent portion 58C. The angle formed by the extending direction of the section _58B1 and the extending direction of the section _58B2 is θ ₀ .

With such a configuration, the influence of the stress indicated by the symbol F1 in FIG. 8 on the upper electrode pattern 41 is alleviated by the detour shape of the connection pattern 58. This reduces the tensile stress indicated by the symbol F3 in FIG. 8, making it difficult for the upper electrode pattern 41 to peel off. In other words, if the connection pattern 58 is formed along the virtual pattern 91 that linearly connects the via hole 51a and the via hole 41a at the shortest distance, the stress indicated by the symbol F1 in FIG. 8 is directly transmitted to the upper electrode pattern 41. A relatively strong tensile stress is applied to the In contrast, in this embodiment, since the connection pattern 58 is detoured to avoid the virtual pattern 91, the tensile stress applied to the upper electrode pattern 41 is significantly reduced due to the springiness of the connection pattern 58 having the detour shape. eased.

In order to more effectively relieve the tensile stress applied to the upper electrode pattern 41, a larger clearance area 92 may be ensured. For example, as shown in FIG. 9, clearance regions 92 may be formed to divide the virtual pattern 91 in the width direction. As a result, the stress coupling between the via hole 51a and the via hole 41a is sufficiently weakened, so that the tensile stress applied to the upper electrode pattern 41 is significantly alleviated. Further, the angle θ ₀ of the bent portion 58C may be set to an appropriate range that enhances the stress relaxation effect. For example, the angle θ ₀ of the bent portion 58C may be set to 150° or less so that the stress relaxation effect is enhanced by reducing the angle θ ₀ of the bent portion 58C. However, if the angle θ ₀ of the bent portion 58C is too small, the shape of the connection pattern 58 will become complicated and the occupied area will increase, so the angle θ ₀ may be set to 90° or more.

Furthermore, when defining a virtual line 93 perpendicular to _the diagonal _line D shown in _FIG . The angle θ ₂ formed by the existing direction B2 may be smaller. Here, the diagonal line D is a straight line that connects the corner formed by the side surfaces 101 and 102 of the substrate 10 and the corner formed by the side surfaces 103 and 104 of the substrate 10 in a plan view from the stacking direction. . The side surfaces 101 and 103 are parallel surfaces located on the long side, and the side surfaces 102 and 104 are parallel surfaces located on the short side. The imaginary line 93 and the extending direction _B2 of the section 58B2 may substantially coincide with each other. In the example shown in FIG. 9, the virtual line 93 and the extending direction _B2 of the section 58B2 do not completely match, but since the difference between the two is small, the entire section of the section _58B2 overlaps the virtual line 93. Can be done.

FIG. 10 is a schematic plan view for explaining the shape of the connection pattern 58 according to a modified example.

In the modification shown in FIG. 10, a section _58B2 included in the second partial pattern 58B has a curved shape. That is, the extending direction of the section _58B2 gradually changes from the section _58B1 toward the first partial pattern 58A. Even with such a shape, the influence of stress applied to the conductor pattern 51 is less likely to be applied to the upper electrode pattern 41. In this case, the smaller the radius of curvature R on the inner peripheral side of the section _58B2 , the higher the stress relaxation effect. Therefore, the radius of curvature R may be, for example, twice or less the distance W between the first partial pattern 58A and the conductive pattern 51.

The shape of the connection pattern 58 has been described above, but the shape of the connection pattern 59 is axisymmetric with the connection pattern 58, and the same effect as the connection pattern 58 can be obtained.

As described above, in the electronic component 100 according to the present embodiment, since the connection pattern 58 connecting the upper electrode pattern 41 and the conductor pattern 51 has a detour shape, the conductor pattern 31 connected to the signal terminal S1 , 51, 61, 71 is less likely to be affected by the stress applied to the upper electrode pattern 41. Similarly, since the connection pattern 59 connecting the upper electrode pattern 45 and the conductor pattern 52 has a detour shape, the influence of stress applied to the conductor patterns 32, 52, 62, 72 connected to the signal terminal S2 is reduced. It becomes difficult to join the upper electrode pattern 45. This makes it difficult for the upper electrode patterns 41 and 45 to peel off after reflow, making it possible to suppress a decrease in the capacitance of the capacitors C1 and C5 due to the peeling of the upper electrode patterns 41 and 45.

Although the embodiments of the technology according to the present disclosure have been described above, the technology according to the present disclosure is not limited to the above embodiments, and various changes can be made without departing from the spirit thereof. It goes without saying that this is included within the scope of the technology according to the present disclosure. For example, in the above embodiment, the connection pattern 58 includes one bent portion 58C, but there may be two or more bent portions 58C.

10 Substrate 11 Flattening layer 12 Dielectric film 20-24 Interlayer insulation film 31-34 Conductor pattern 31a-36a Via hole 35, 36 Winding pattern 37, 38 Lower electrode pattern 39 Dummy pattern 41-46 Upper electrode pattern 41a-46a Via hole 50 to 54, 57 Conductor patterns 51a to 56a Via holes 55, 56 Winding patterns 58, 59 Connection pattern 58A First part pattern 58B Second part pattern 58B ₁ , 58B ₂ section 58C Bend part 61 to 64 Conductor pattern 61a to 64a Via hole 65, 66 Winding patterns 71 to 74 Conductor patterns 71a to 74a Via hole 80 Circuit board 81 Land pattern 82 Solder 91 Virtual pattern 92 Clearance area 93 Virtual line 100 Electronic components 101 to 104 Side surface B1 Extending direction B2 Extending direction C1 to C6 Capacitor D Diagonal F1 to F3 Stress G1, G2 Ground terminal L1, L2 Inductor M1 to M5, MM Conductor layer R Radius of curvature S1, S2 Signal terminal W Distance θ ₀ to θ ₂ angle

Claims (8)

A substrate and
a terminal electrode;
A capacitor provided on the substrate and including a lower electrode pattern, an upper electrode pattern, and a dielectric film located between these, and a conductor pattern that overlaps with and is connected to the terminal electrode in plan view. and a connection pattern connecting the upper electrode pattern and the conductor pattern,
The connection pattern is an electronic component in which the upper electrode pattern and the conductor pattern are connected in a detour rather than through the shortest distance. The lower electrode pattern is formed on a first conductor layer provided on the substrate,
The upper electrode pattern is formed on a second conductor layer provided on the substrate,
The conductor pattern and the connection pattern are formed on a third conductor layer provided on the substrate,
The connection pattern is connected to the upper electrode pattern via a first via hole provided in a first interlayer insulating film located between the second conductor layer and the third conductor layer,
The conductor pattern is connected to the terminal electrode via a second via hole provided in a second interlayer insulating film covering the third conductor layer,
The connection pattern is arranged avoiding a virtual pattern that connects the first via hole and the second via hole at the shortest distance, so that at least a part of the virtual pattern has a clearance area where the connection pattern does not exist. The electronic component according to claim 1, wherein: is formed. The electronic component according to claim 2, wherein the clearance area divides the virtual pattern in the width direction. The connection pattern includes a first partial pattern connected to the upper electrode pattern, and a second partial pattern connecting the first partial pattern and the conductor pattern,
The electronic component according to claim 1, wherein the second partial pattern is bent or curved in an extending direction. The electronic component according to claim 4, wherein the angle at the bent portion of the second partial pattern is 90° or more and 150° or less. further comprising an inductor provided on the substrate and including a winding pattern connected to the capacitor,
The electronic component according to any one of claims 1 to 5, wherein the upper electrode pattern is located outside the winding pattern in plan view. The electronic component according to any one of claims 1 to 3, wherein the connection pattern is formed in a non-linear shape. A substrate and
a terminal electrode;
A capacitor provided on the substrate and including a lower electrode pattern, an upper electrode pattern, and a dielectric film located between these, and a conductor pattern that overlaps with and is connected to the terminal electrode in plan view. and a connection pattern connecting the upper electrode pattern and the conductor pattern,
In the electronic component, the connection pattern connects the upper electrode pattern and the conductor pattern by a non-linearly formed wiring including at least one bent part or curved part.

Images