JP2024018948A - Attenuator and measurement device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an attenuator and a measurement device capable of reducing parasitic capacitance.

SOLUTION: An attenuator includes a substrate, a metal component, a first surface mount component disposed on one surface of the substrate, a second surface mount component disposed on the other surface of the substrate, and a one surface side pad which is provided on the one surface of the substrate and to which one terminal of the first surface mount component is bonded. The attenuator is provided on the other surface of the substrate, is arranged at a position overlapping with the one surface side pad in a thickness direction of the substrate, and has the other surface side pad to which one terminal of the second surface mount component is bonded. The attenuator includes conduction means for conducting the one surface mount component and the other surface mount component to connect the first surface mount component and the second surface mount component in series.

SELECTED DRAWING: Figure 4

COPYRIGHT: (C)2024,JPO&INPIT

Description

The present invention relates to an attenuator and a measuring device.

Patent Document 1 discloses a voltage detection circuit. The voltage detection circuit includes a plurality of surface mount resistors connected in series. Each surface mount resistor is mounted on a printed wiring board.

The printed wiring board is provided with pads to which surface-mounted components such as surface-mounted resistors are soldered. One surface mount component and the other surface mount component of two adjacent surface mount components are connected in series by this pad.

JP 2021-197090 Publication

This pad is soldered to one terminal of one adjacent surface mount component and one terminal of the other surface mount component. Therefore, it is necessary for the pad to secure an area for soldering both one terminal of one surface mount component and one terminal of the other surface mount component.

A parasitic capacitance is generated between the pad and a metal component such as the casing of the measuring device. This parasitic capacitance can deteriorate the frequency characteristics of an attenuator comprised of surface mount components soldered to pads.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an attenuator and a measuring device that can reduce the parasitic capacitance between a pad and a metal component.

An attenuator and a measuring device equipped with an attenuator according to an aspect of the present invention include a substrate, a metal component, a first surface mount component disposed on one surface of the substrate, and a first surface mount component disposed on the other surface of the substrate. The device includes a second surface mount component, and a one surface pad provided on the one surface of the substrate and to which one terminal of the first surface mount component is bonded. An attenuator and a measurement device including the attenuator are provided on the other surface of the substrate, are arranged at a position overlapping with the first surface pad in the thickness direction of the substrate, and are located on one of the second surface mount components. It has a pad on the other side to which the terminal is bonded. The attenuator and the measuring device including the attenuator include a conduction unit that connects the first surface mount component and the second surface mount component in series by connecting the first surface side pad and the other surface side pad to each other.

In this embodiment, the pads on one side and the pads on the other side are connected through the conductive means, so compared to pads that require simultaneous bonding of one terminal of each of two surface mount components adjacent to the same side. Therefore, the area of each pad can be reduced. Therefore, the parasitic capacitance that occurs between the electrically integrated pads on one side and the pads on the other side and the metal components is reduced by the area required to simultaneously bond one terminal of each of the two surface mount components on the same surface. This makes it possible to reduce the parasitic capacitance that occurs between the pad and the metal component.

Therefore, it is possible to reduce the parasitic capacitance generated in the attenuator.

FIG. 1 is a block diagram showing a measuring device equipped with an attenuator according to the first embodiment. FIG. 2 is a diagram showing an attenuation circuit of an attenuator according to the first embodiment. FIG. 3 is a diagram showing an attenuation circuit of an attenuator according to a modified example. FIG. 4 is a plan view showing the inside of the attenuator according to the first embodiment. FIG. 5 is a sectional view taken along line VV in FIG. 4. FIG. 6 is a diagram showing an attenuator according to the second embodiment, and is a diagram corresponding to a cross-sectional view taken along line VV in FIG. 4.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

<First embodiment>
First, with reference to FIGS. 1 to 5, an attenuator 10 according to a first embodiment and a measuring device 12 equipped with the attenuator 10 inside will be described. FIG. 1 is a block diagram showing a measuring device 12 that includes an attenuator 10 according to the first embodiment.

This measuring device 12 is a device that measures high voltage. An example of the measuring device 12 that measures high voltage is a wattmeter.

The measuring device 12 includes an attenuator 10 . The measuring device 12 attenuates the measured voltage with an attenuator 10 .

Here, a high voltage probe having a built-in attenuator 10 may be connected to the measuring device 12. Further, the high voltage probe connected to the measuring device 12 includes, for example, a differential probe that measures a voltage difference from a ground voltage.

The attenuator 10 includes, for example, the following attenuation circuits 20 and 50 (see FIGS. 2 and 3).

(attenuation circuit)
FIG. 2 is a diagram showing the attenuation circuit 20 of the attenuator 10 according to the first embodiment.

As shown in FIG. 2, the attenuator 10 includes an attenuation circuit 20. The attenuation circuit 20 is composed of an inverting amplifier circuit using an operational amplifier 22. A non-inverting input terminal 24 of the operational amplifier 22 is connected to a reference potential 26.

A feedback resistor 32 is connected between the output terminal 28 and the inverting terminal 30 of the operational amplifier 22. A measurement voltage is input to the inverting terminal 30 via the input circuit 34 .

The input circuit 34 is composed of a plurality of surface mount components 40 connected in series. As the surface mount component 40, for example, a passive element can be mentioned. Passive elements include surface mount resistors, surface mount capacitors, surface mount inductances, and the like. In the first embodiment, the surface mount component 40 includes a surface mount resistor 42 and a surface mount capacitor 44 connected in parallel.

The input circuit 34 is composed of a plurality of surface mount components 40 connected in series. This increases the impedance of the input circuit 34. Further, the input circuit 34 is composed of a plurality of surface mount components 40 arranged in series. This increases the creepage distance formed between the input and output of the input circuit 34.

The DC resistance of this input circuit 34 is set to, for example, several tens of MΩ. Further, the DC resistance of the feedback resistor 32 is set to, for example, several kΩ.

Thereby, the attenuation circuit 20 attenuates the measurement voltage input to the input terminal 46 and outputs it from the output terminal 48 . The output voltage from the output terminal 28 is output to the next circuit.

(Modified example of attenuator)
FIG. 3 is a diagram showing an attenuation circuit 50 of the attenuator 10 according to a modification. FIG. 3 shows a modification of the attenuation circuit 20 described above.

As shown in FIG. 3, the attenuation circuit 50 according to the modification is configured with a voltage dividing circuit.

The attenuation circuit 50 includes an input circuit 34 into which a measurement voltage is input, and a voltage dividing resistor 52 provided between the output of the input circuit 34 and the reference potential 26.

Since the input circuit 34 is configured in the same manner as described above, it is given the same reference numeral as described above and a description thereof will be omitted.

The DC resistance of the input circuit 34 is set to several tens of MΩ. Further, the voltage dividing resistor 52 is set to several kilohms.

Thereby, the attenuation circuit 50 attenuates the measurement voltage input to the input terminal 46 and outputs it from the output terminal 48 . The output voltage from the output terminal 28 is output to the next circuit.

Next, each of the attenuation circuits 20 and 50 will be explained using FIGS. 4 and 5.

FIG. 4 is a plan view showing the inside of the attenuator 10 according to the first embodiment. FIG. 5 is a sectional view taken along line VV in FIG. 4.

4 and 5 are diagrams in which components other than the input circuit 34 and the surface mount capacitor 44 forming the input circuit 34 are omitted to make the explanation easier to understand. Further, the surface mount resistor 42 constituting the surface mount component 40 is shown as a first surface mount component 66, which is mounted on one surface 64 of a substrate 62, which will be described later. Furthermore, the surface mount resistor 42 mounted on the other surface 70 of the substrate 62 is shown as a second surface mount component 72. Further, in FIG. 5, the thickness of the substrate 62 is shown enlarged to make the explanation easier to understand.

As shown in FIGS. 4 and 5, the attenuator 10 includes a metal housing 60, which is an example of a metal component. The housing 60 is electrically connected to the reference potential 26 of the attenuation circuits 20, 50 (see FIGS. 2 and 3).

A rectangular substrate 62 is provided inside the casing 60. The board 62 is composed of a printed wiring board.

A plurality of first surface mount components 66, which are part of the surface mount resistors 42 constituting the surface mount components 40 of the input circuit 34, are arranged on one surface 64 of the board 62. On the other surface 70 of the board 62, a plurality of second surface mount components 72, which are other surface mount resistors 42 constituting the surface mount component 40 of the input circuit 34, are arranged. One surface 64 of the substrate 62 constitutes, for example, a component surface, and the other surface 70 of the substrate 62 constitutes a solder surface.

The first surface mount component 66 and the second surface mount component 72 are comprised of the surface mount resistor 42. The surface mount resistor 42 is composed of a chip surface mount resistor (chip resistor) that is a surface mount resistor. The first surface mount component 66 and the second surface mount component 72 constitute the surface mount resistor 42 of the input circuit 34.

Note that, as described above, the surface mount capacitor 44 constituting the surface mount component 40 of the input circuit 34 is not shown in FIGS. 4 and 5.

The first surface mount component 66 is formed into a rectangular plate shape. The first surface mount component 66 includes a first side component body 80 and terminals 82 provided at one end and the other end of the first side component body 80 in the longitudinal direction.

The second surface mount component 72 is formed into a rectangular plate shape. The second surface mount component 72 includes a second side component body 86 and terminals 88 provided at one end and the other end of the other side component body 86 in the longitudinal direction.

The surface mount components 66 and 72 are arranged on the substrate 62 such that the longitudinal direction of each surface mount component 66 and 72 matches the longitudinal direction 90 of the substrate 62. As a result, each of the first surface mount components 66 and each of the second surface mount components 72 are aligned along the virtual straight line 92 extending in the longitudinal direction 90 of the board 62 at the center of the board 62 in the width direction. It is located in

Each first surface mount component 66 is arranged in a row in the longitudinal direction 90 of the board 62 at intervals. The second surface mount components 72 are arranged in a row in the longitudinal direction 90 of the substrate 62 at intervals.

A second surface mount component 72 disposed on the other surface 70 of the substrate 62 is arranged between first surface mount components 66 disposed at intervals on one surface 64 of the substrate 62. . As a result, the first surface mount component 66 and the second surface mount component 72 are arranged along the virtual straight line 92 and alternately in the direction in which the virtual straight line 92 extends.

Note that in the first embodiment, a case will be described in which the first surface mount component 66 and the second surface mount component 72 are arranged in series along the virtual straight line 92; It is not limited to.

For example, the surface mount components 66 and 72 may be arranged such that the longitudinal direction of the first surface mount component 66 and the longitudinal direction of the second surface mount component 72 are different from each other.

On one side 64 of the substrate 62, one side pads 100 to which one terminal 82 of the first surface mount component 66 is bonded are provided at intervals. One terminal 82 of the first surface mount component 66 is bonded to each one-side pad 100 by solder. Each one-side pad 100 is formed to have a width that is necessary and sufficient for joining one terminal 82 of the first surface mount component 66 by soldering, and waste is suppressed.

On the other surface 70 of the substrate 62, other surface pads 102 to which one terminal 88 of the second surface mount component 72 is bonded are provided at intervals. One terminal 88 of the second surface mount component 72 is bonded to each other side pad 102 by solder. Each pad 102 on the other side is formed to have a width that is necessary and sufficient for one terminal 88 of the second surface mount component 72 to be joined by solder, and waste is suppressed.

In addition, in FIG. 5, one terminal 82 of the first surface mount component 66 located on the one end 110 side of the longitudinal direction 90 of the board 62 is soldered to an input pad 112 that constitutes an input of the input circuit 34. . Further, one terminal 88 of the second surface mount component 72 located on the other end 114 side in the longitudinal direction 90 of the board 62 is soldered to the output pad 116 that constitutes the output of the input circuit 34.

The one side pad 100 and the other side pad 102 are arranged at positions overlapping each other in the thickness direction 120 of the substrate 62.

Overlapping with each other means not only that the one side pad 100 and the other side pad 102 exactly overlap in the thickness direction 120 of the substrate 62, but also when a part of the one side pad 100 and a part of the other side pad 102 overlap each other. Including cases where they overlap.

The pads 100 on one side and the pads 102 on the other side, which are arranged to overlap with each other, are electrically connected to each other through a through hole 130 as a conductive means formed in the substrate 62. A through hole 130 is provided in each pad 100, 102, and each pad 100, 102 is comprised of a land around the through hole 130.

In addition, in the first embodiment, a case will be described in which a through hole 130 is provided in each pad 100, 102 to constitute a conduction means for electrically connecting both pads 100, 102 arranged at positions overlapping each other. is not limited to this.

For example, in the first embodiment, each pad 100, 102 may be electrically connected through a through hole provided at a different location from each pad 100, 102. In this case, each pad 100, 102 constitutes a pad without a through hole.

(action and effect)
Next, the effects of the first embodiment will be explained.

The attenuator 10 and the measuring device 12 including the attenuator 10 in the first embodiment include a substrate 62, a casing 60 that is a metal component, and a first surface mount component 66 disposed on one surface 64 of the substrate 62. A second surface mount component 72 is provided on the other surface 70 of the substrate 62. The attenuator 10 and the measurement device 12 including the attenuator 10 include a one-side pad 100 provided on one side 64 of the substrate 62 and to which one terminal 82 of the first surface mount component 66 is bonded. The attenuator 10 and the measuring device 12 including the attenuator 10 are provided on the other surface 70 of the substrate 62, are arranged at a position overlapping with the first surface pad 100 in the thickness direction 120 of the substrate 62, and are mounted on the second surface mounting surface. A pad 102 on the other side is provided to which one terminal 88 of the component 72 is bonded. The attenuator 10 and the measuring device 12 equipped with the attenuator 10 are electrically conductive means that connect the first surface mount component 66 and the second surface mount component 72 in series by electrically connecting the pad 100 on one side and the pad 102 on the other surface. A through hole 130 is provided.

In this configuration, the first surface mount component 66 is disposed on one surface 64 of the substrate 62, and the second surface mount component 72 connected in series to the first surface mount component 66 is disposed on the other surface 70 of the substrate 62. Placed. A one-side pad 100 to which one terminal 82 of the first surface mount component 66 is bonded by solder is provided on one surface 64 of the board 62, and one surface pad 100 to which one terminal 88 of the second surface mount component 72 is bonded by solder. The other side pad 102 is provided on the other side 70 of the substrate 62.

Therefore, each of the pads 100 on one side and the pads 102 on the other side is different from a pad to which one terminal of each of two adjacent surface mount components must be simultaneously soldered on the same side of the board. The area of pads 100 and 102 can be reduced.

The pad 100 on one side and the pad 102 on the other side are electrically connected through a through hole 130 serving as a conduction means, and the pad 100 on the one side and the pad 102 on the other side are electrically integrated by the through hole 130. Further, the one-side pad 100 and the other-side pad 102 are arranged at positions overlapping each other in the thickness direction 120 of the substrate 62.

Therefore, the area of the pad 100 on one side and the pad 102 on the other side that are electrically integrated can be made smaller than the area of the pad to which one terminal of each of the two surface mount components is simultaneously bonded. . As a result, one terminal of each of the two surface mount components simultaneously connects the parasitic capacitance 140 (see FIG. 5) that occurs between the pad 100 on one side and the pad 102 on the other side and the casing 60, which is a metal component. This makes it possible to reduce the parasitic capacitance that occurs between the pad and the housing 60.

Therefore, the parasitic capacitance 140 occurring in the attenuator 10 can be reduced.

Furthermore, by suppressing the parasitic capacitance 140 that occurs in the input circuit 34 of the attenuator 10, it is possible to reduce the amplitude error of the output signal output from the attenuator 10 and suppress the phase shift, thereby improving frequency characteristics. be able to.

Note that each pad 100, 102 is constituted by a land formed on the substrate 62. This land is made of copper foil or the like, and the thickness of the land is, for example, 100 μm or less.

Therefore, the thickness of each pad 100, 102 is very small compared to the area of each pad 100, 102, and the distance between the periphery of each pad 100, 102 and the surface of the housing 60 opposite to the periphery is The parasitic capacitance that occurs can be ignored.

Further, the first surface mount component 66 is arranged on one surface 64 of the substrate 62, and the second surface mount component 72 is arranged on the other surface 70 of the substrate 62. As a result, the position of one terminal 82 of the first surface mount component 66 and the position of one terminal 88 of the second surface mount component 72 connected in series are arranged to overlap in the thickness direction 120 of the board 62. can do.

Therefore, due to the structure in which all of the surface mount components are installed on the same surface of the board, each terminal of the surface mount components connected in series must be shifted in the in-plane direction. The mounting area of the surface mount components 66 and 72 can be suppressed. Thereby, the area of the substrate 62 can be reduced, and the size of the attenuator 10 can be reduced.

Further, the attenuator 10 of the first embodiment has a plurality of first surface mount components 66 and a plurality of second surface mount components 72, and the first surface mount component 66 and the second surface mount component 72 have a plurality of second surface mount components 72. are arranged alternately and connected in series.

According to this configuration, the surface mount components 66 and 72 connected in series can be arranged alternately on one surface 64 and the other surface 70 of the substrate 62.

This makes it possible to reduce the mounting area of each surface mount component 66, 72 while increasing the creepage distance formed between the input and output of the input circuit 34 that each surface mount component 66, 72 constitutes. .

Further, in the first embodiment, the plurality of first surface mount components 66 and the plurality of second surface mount components 72 are arranged along the virtual straight line 92.

According to this configuration, compared to the case where each surface mount component 66, 72 is arranged in a meandering manner, for example, with respect to the virtual straight line 92, one terminal 82, 88 of each surface mount component 66, 72 can be The insulation distance to the casing 60 located on the side of each surface mount component 66, 72 can be increased.

<Second embodiment>
FIG. 6 is a diagram illustrating an attenuator 200 according to the second embodiment, in which the same or equivalent parts as in the first embodiment are given the same reference numerals, explanations are omitted, and only different parts will be explained. This attenuator 200 differs from the first embodiment in that a plurality of holes are formed in the substrate 62.

FIG. 6 is a diagram showing an attenuator 200 according to the second embodiment, and FIG. 6 shows a cross-sectional view corresponding to the cross section taken along line VV in FIG. 4.

In the substrate 62 of the attenuator 200 according to the second embodiment, one-side holes 210 are formed between adjacent one-side pads 100. Each one-side hole 210 penetrates the substrate 62.

The one-side hole 210 is formed in a rectangular shape and has a length that reaches from near the edge of one adjacent one-side pad 100 to near the edge of the other one-side pad 100. Further, the width dimension of the first side hole 210 is set to be the same as the length of the first side pad 100 in the longitudinal direction.

Further, an input side hole 212 having the same shape as the first side hole 210 is formed between the input pad 112 and the first side pad 100.

Further, in the substrate 62, a hole 220 on the other side is formed between the adjacent pads 102 on the other side. Each other side hole 220 penetrates the substrate 62.

The other side hole 220 is formed in a rectangular shape and has a length that reaches from near the edge of one adjacent other side pad 102 to near the edge of the other other side pad 102. Further, the width of the other side hole 220 is set to be the same as the length of the other side pad 102 in the longitudinal direction.

Further, an output side hole 222 having the same shape as the other side hole 220 is formed between the output pad 116 and the other side pad 102.

In the second embodiment, one side holes 210 are formed between all adjacent one side pads 100, and other side holes 220 are formed between all adjacent other side pads 102. However, the second embodiment is not limited to this configuration.

For example, in the second embodiment, a hole penetrating the substrate 62 may be formed at at least one location between adjacent pads 100 on one side or between pads 102 on the other side.

Similarly to the first embodiment, in the substrate 62, the pads 100 on one side and the pads 102 on the other side, which are arranged at positions overlapping with each other, are electrically connected to each other through the through holes 130, which serve as conduction means, formed in the substrate 62. Ru.

Further, in the second embodiment, a case has been described in which the conduction means is constituted by the through hole 130 that conducts the one side pad 100 and the other side pad 102 arranged at positions overlapping each other. It is not limited to.

For example, the conduction means for electrically connecting the one side pad 100 and the other side pad 102 is connected to an end 210a on the one end 110 side or an end 210b on the other end 114 side of the inner wall of the one side hole 210 formed in the substrate 62. It may be constructed by plating or pasting a conductor. Further, the conduction means for electrically connecting the one side pad 100 and the other side pad 102 is an end 220a on the one end 110 side of the inner wall of the other side hole 220 formed in the substrate 62 or an end 220b on the other end 114 side. It may be constructed by plating or pasting a conductor. In these cases, the through hole 130 provided between the pad 100 on one side and the pad 102 on the other side can be eliminated.

In addition, another hole different from the holes 210 and 220 is formed in the substrate 62, and the inner wall of this other hole is plated or a conductor is pasted, so that pads on one side are arranged at positions overlapping with each other. 100 and the pad 102 on the other side may be configured as a conductive means.

(action and effect)
Next, the effects of the second embodiment will be explained.

In the second embodiment as well, with respect to the same or equivalent parts as in the first embodiment, the same effects as in the first embodiment can be achieved.

The attenuator 200 in the second embodiment also includes a first side hole 210, which is a hole penetrating the substrate 62, in at least one place between the adjacent first side pads 100 or between the adjacent second side pads 102, and another hole 210, which is a hole penetrating the substrate 62. A surface side hole 220 is formed.

According to this configuration, the other side hole 220 penetrating the substrate 62 is formed in a portion of the substrate 62 where the first surface mount component 66 provided between the adjacent one side pads 100 is located. Therefore, even if the substrate 62 absorbs moisture and the dielectric constant of the substrate 62 changes, changes in the parasitic capacitance 232 occurring between the first surface mount component 66 and the lower surface 230 of the housing 60 can be suppressed. be able to.

Further, a hole 210 on one side passing through the substrate 62 is formed in a portion of the substrate 62 where the second surface mount component 72 provided between the adjacent pads 102 on the other side is located. Therefore, even if the substrate 62 absorbs moisture and the dielectric constant of the substrate 62 changes, changes in the parasitic capacitance 236 occurring between the second surface mount component 72 and the upper surface 234 of the housing 60 can be suppressed. be able to.

Therefore, it is possible to suppress changes in frequency characteristics caused by changes in parasitic capacitance due to changes in humidity.

Although the embodiments of the present invention have been described above, the above embodiments merely show a part of the application examples of the present invention, and are not intended to limit the technical scope of the present invention to the specific configurations of the above embodiments. do not have.

In each embodiment, a case has been described in which the attenuators 10 and 200 are provided inside the measuring device 12, but each embodiment is not limited to this.

For example, the attenuators 10 and 200 are not limited to those provided inside the measuring device 12, but may be of an external type provided outside the measuring device 12.

In each of the embodiments, a case has been described in which the metal component is configured with a metal housing 60, but each embodiment is not limited to this configuration. For example, the metal component may consist of a metal shield or chassis connected to reference potential 26.

10, 200 Attenuator 12 Measuring device 34 Input circuit 62 Board 64 One side 66 First surface mount component 70 Other surface 72 Second surface mount component 92 Virtual straight line 100 Pad on one side 102 Pad on other side 120 Thickness direction 130 Through hole (Conduction means)

Claims (8)

A substrate and
metal parts and
a first surface mount component disposed on one surface of the substrate;
a second surface mount component disposed on the other surface of the substrate;
a one-side pad provided on the one surface of the substrate and to which one terminal of the first surface mount component is bonded;
a second surface pad provided on the other surface of the substrate, located at a position overlapping with the first surface pad in the thickness direction of the substrate, and to which one terminal of the second surface mount component is bonded;
conduction means for connecting the first surface mount component and the second surface mount component in series by electrically connecting the one surface side pad and the other surface side pad;
An attenuator comprising: The attenuator according to claim 1,
having a plurality of the first surface mount components and a plurality of the second surface mount components;
The first surface mount component and the second surface mount component are arranged alternately and connected in series,
Attenuator. The attenuator according to claim 2,
The plurality of first surface mount components and the plurality of second surface mount components are arranged along a virtual straight line,
Attenuator. The attenuator according to claim 2 or 3,
A hole penetrating the substrate is formed at at least one location between the adjacent pads on the first side or between the pads on the other side.
Attenuator. A measuring device comprising the attenuator according to claim 1. The measuring device according to claim 5,
having a plurality of the first surface mount components and a plurality of the second surface mount components;
The first surface mount component and the second surface mount component are arranged alternately and connected in series,
measuring device. The measuring device according to claim 6,
The plurality of first surface mount components and the plurality of second surface mount components are arranged along a virtual straight line,
measuring device. The measuring device according to claim 6 or claim 7,
A hole penetrating the substrate is formed at at least one location between the adjacent pads on the first side or between the pads on the other side.
measuring device.

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