JP2024017038A - sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sensor capable of improving robustness at wire breaking.

SOLUTION: A sensor includes N sensor circuits and an interface circuit. The output of a Kth sensor circuit has a serial connection input to a K+1th sensor circuit. The output of the Kth interface circuit has a serial connection input to a K-1th interface circuit. Each of the N sensor circuits completes a detection operation by inverting an output signal after the detection time proportional to a detection amount has elapsed since an input signal is inverted. Each of the N interface circuits inverts the output signal in response to the inversion of the output signal of the corresponding sensor circuit. In response to the completion of the detection operation of the Kth sensor circuit, the detection operation of the K+1th sensor circuit is started. Signals indicating N detection times detected by first to Nth sensor circuits are continuously output from a first interface circuit.

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2024,JPO&INPIT

Description

The technology disclosed in this specification relates to a sensor that can improve robustness in the event of wire breakage.

Patent Document 1 discloses a sensor system including a sensor array having a plurality of sensors arranged in a two-dimensional array, and an XY decoder. Multiple sensors can be read out by scanning the sensor array with an XY decoder.

Japanese Patent Application Publication No. 2004-258018

Detection signals from a plurality of sensors may be serially output using one signal line. In this case, if a disconnection failure occurs in any part of the signal line, there is a possibility that the detection signals of all the sensors cannot be output.

One aspect of the sensor disclosed in this specification includes N sensor circuits (N is a natural number of 2 or more), N interface circuits provided corresponding to each of the N sensor circuits, It is a sensor equipped with. The N sensor circuits have a serial connection in which the sensor output logic signal of the Kth (K is a natural number from 1 to N-1) sensor circuit is input as the sensor input logic signal of the K+1th sensor circuit. ing. The N interface circuits have a serial connection through which the interface output logic signal of the Kth interface circuit is input as the interface input logic signal of the K-1th interface circuit. Each of the N sensor circuits starts a detection operation in response to the inversion of the sensor input logic signal, and outputs the sensor after a detection time proportional to the detection amount of the sensor circuit has elapsed since the sensor input logic signal was inverted. This circuit completes the detection operation by inverting the logic signal. Each of the N interface circuits is a circuit that inverts the interface output logic signal in response to inversion of the sensor output logic signal of the corresponding sensor circuit. When the sensor output logic signal of the Kth sensor circuit is inverted and the sensing operation of the Kth sensor circuit ends, the sensing operation of the K+1th sensor circuit is started. The first interface circuit outputs an interface output logic signal that continuously outputs a signal indicating N detection times detected by the first to Nth sensor circuits.

In this sensor, the detection operation of the sensor circuit can be propagated to subsequent stages, such as the K-th, K+1-th, and so on. Further, the operation of outputting the interface output logic signal indicating the detection time can be propagated to the previous stage side, such as the Kth, K-1th, and so on. Then, the interface output logic signal indicating the detection time of all the sensor circuits can be serially output from the first interface circuit. That is, the advancing direction of the detection operation and the propagation direction of the detection signal can be made opposite to each other. As a result, even if a disconnection occurs on the serial connection path of N sensor circuits or a disconnection occurs on the serial connection path of N interface circuits, the sensor circuit on the previous stage than the disconnection part will Output can be serially output. Since all sensor circuits will not be unable to output detection signals due to a disconnection failure, it is possible to improve robustness in the event of a disconnection.

The sensor output logic signal output from the K-th sensor circuit and the interface output logic signal output from the K+1-th interface circuit may be input to the K-th interface circuit. The interface output logic signal output from the Kth interface circuit may be input to the K-1th interface circuit. In response to the sensor output logic signal of the Kth sensor circuit being inverted and the detection operation of the Kth sensor circuit being completed, the interface output logic signal indicating the detection time detected by the Kth sensor circuit becomes K. The signal may be output from the th interface circuit to the K-1th interface circuit.

It may further include N first resistor sections provided corresponding to each of the N interface circuits. Each of the N interface circuits may include a logic circuit. The output terminal of the K-th sensor circuit and the output terminal of the K+1-th logic circuit may be connected to the input terminal of the K-th logic circuit. The connection path between the input terminal of the K-th logic circuit and the output terminal of the K+1-th logic circuit may be connected to the first predetermined voltage portion via the K-th first resistance section.

It may further include N second resistor sections provided corresponding to each of the N sensor circuits. A connection path between the output terminal of the Kth sensor circuit and the input terminal of the K+1th sensor circuit may be connected to the second predetermined voltage portion via the Kth second resistance section.

Each of the N sensor circuits may include a variable capacitance. The detected amount may be a variable capacitance. The detection time may be a time proportional to the capacitance of the variable capacitor.

Each of the N sensor circuits may include a diode element. The detected amount may be a reverse leakage current value of a diode element. The detection time may be a time inversely proportional to the reverse leakage current value.

Each of the N sensor circuits may include a variable resistance. The detected amount may be a resistance value of a variable resistor. The detection time may be a time proportional to the resistance value of the variable resistor.

1 is a block diagram schematically showing a sensor 1 of Example 1. FIG. FIG. 3 is a circuit configuration diagram of a sensor circuit SC(K). FIG. 3 is a waveform diagram illustrating the operation of the sensor circuit SC(K). FIG. 2 is a waveform diagram illustrating the normal operation of the sensor 1. FIG. FIG. 3 is a waveform diagram illustrating the operation when the sensor 1 is disconnected. FIG. 2 is a block diagram schematically showing a sensor 100 of a comparative example. FIG. 2 is a block diagram schematically showing a sensor 1a according to a second embodiment.

(Configuration of sensor 1)
FIG. 1 shows a sensor 1 according to a first embodiment. The sensor 1 is an example of an A/D conversion circuit that converts various physical quantities into digital values. The sensor 1 includes an input/output circuit IO and N sensor units SU(1) to SU(N) (N is a natural number of 2 or more).

The input/output circuit IO includes an input buffer IB, an output buffer OB, and a NOR circuit NR(0). The start signal ST input to the input/output circuit IO is input to the sensor circuit SC(1) via the input buffer IB. A start signal ST and an output signal DO(1) are input to the NOR circuit NR(0). The serial output signal Sout output from the NOR circuit NR(0) is output to the outside via the output buffer OB. The input/output circuit IO inverts the serial output signal Sout when the start signal ST or the output signal DO(1) is inverted. The start signal ST is a signal that performs on/off control of the sensor 1. During the period when the start signal ST is at a low level, the sensor 1 performs a detection operation. The sensor 1 stops while the start signal ST is at a high level.

A positive power line PL and a negative power line NL are arranged in the input/output circuit IO and the sensor units SU(1) to SU(N). The positive power supply line PL is connected to the power supply voltage section VDD and supplies a power supply voltage (eg, 3.3V). The positive power supply line PL is connected to the reference voltage site GND and supplies a reference voltage (eg, 0V).

Each of the N sensor units SU(1) to SU(N) includes a sensor circuit SC(1) to SC(N), a NOR circuit NR(1) to NR(N), and a resistance element RD(1) to RD. (N), and resistance elements RU(1) to RU(N). NOR circuits NR(1) to NR(N) are provided corresponding to sensor circuits SC(1) to SC(N), respectively. A sensor array 20 is configured by sensor circuits SC(1) to SC(N). A start signal ST is input to the first stage sensor circuit SC(1). The output signal OS(1) output from the sensor circuit SC(1) is input to the second stage sensor circuit SC(2). Similarly, in the sensor array 20, the output signal of the previous stage sensor circuit is inputted as the input signal of the next stage sensor circuit. That is, the output signal OS(K) of the Kth sensor circuit SC(K) (K is a natural number from 1 to N-1) is input as the sensor input logic signal of the K+1st sensor circuit SC(K+1). , has a serial connection.

The output circuit 30 includes NOR circuits NR(0) to NR(N). The start signal ST is input to the NOR circuit NR(0), and the output signal DO(1) is input to the NOR circuit NR(0). The output signal OS(1) and the output signal DO(2) are input to the NOR circuit NR(1). An output signal DO(1) is output from the NOR circuit NR(1). The output signal DO(1) is a logic signal expressed by the following formula.

Similarly, the K-th NOR circuit NR(K) receives the output signal OS(K) output from the K-th sensor circuit SC(K) and the output signal OS(K) output from the K+1-th NOR circuit NR(K+1). An output signal DO(K+1) is input. The output signal DO(K) output from the K-th NOR circuit NR(K) is input to the K-1th NOR circuit NR(K-1). That is, it has a serial connection in which the output signal DO(K) of the K-th NOR circuit NR(K) is input as an input logic signal to the K-1th NOR circuit NR(K-1). The output signal DO(K) is a logic signal expressed by the following formula.

As can be seen from the above equation, the NOR circuit NR (K) receives the signal when the output signal OS (K) input from the sensor circuit SC (K) is inverted, or when the output signal OS (K) is input from the next stage NOR circuit NR (K+1). When the output signal OS(K+1) is inverted, the output signal OS(K) is inverted. In other words, the NOR circuit NR(K) is disabled during the period when the high level output signal OS(K) is input, and the output is fixed at the low level. On the other hand, it is enabled during the period when the low level output signal OS(K) is input. Then, it operates as a NOT circuit that inverts the output signal OS(K+1) inputted from the subsequent stage to generate an output signal OS(K), and outputs the generated output signal OS(K) to the previous stage.

The output signal OS(N) output from the N-th sensor circuit SC(N) is input to the N-th NOR circuit NR(N), which is the final stage. The output signal DO(N) output from the NOR circuit NR(N) is input to the N-1th NOR circuit NR(N-1). The output signal DO(N) is a logic signal expressed by the following formula.

A serial output signal Sout is output from the NOR circuit NR(0) of the input/output circuit IO, which is the first stage. The serial output signal Sout is a logic signal expressed by the following formula.

A connection path CP(1) between the output terminal of the NOR circuit NR(2) and the input terminal of the NOR circuit NR(1) is connected to the negative power supply line NL via the resistance element RD(1). Similarly, the connection path CP(K) between the output terminal of the NOR circuit NR(K+1) and the input terminal of the NOR circuit NR(K) is connected to the negative power supply line NL via the resistance element RD(K). ing. Further, the input terminal of the NOR circuit NR(N) is connected to the negative power supply line NL via the resistance element RD(N). Resistance elements RD(1) to RD(N) function as pull-down resistors. When the connection paths CP(1) to CP(N) are disconnected, the input voltages of the NOR circuits NR(1) to NR(N) are set to low level by each of the resistance elements RD(1) to RD(N). Can be fixed. Thereby, it is possible to prevent the input of the NOR circuit NR in the disconnected portion from being in a floating state and malfunctioning. Therefore, it becomes possible to reliably invalidate the sensor unit SU in the disconnected portion. Furthermore, by fixing it to a low level, when a disconnection fault occurs in the connection path CP (K), the inversion of the output signal OS (K) output from the sensor circuit SC (K) is controlled by the NOR circuit NR (K). It can be propagated to the output signal DO(K) output from.

A connection path SP(1) between the output terminal of the sensor circuit SC(1) and the input terminal of the sensor circuit SC(2) is connected to the positive power supply line PL via a resistance element RU(1). Similarly, the connection path SP(K) between the output terminal of the sensor circuit SC(K) and the input terminal of the sensor circuit SC(K+1) is connected to PL via the resistive element RU(K). Further, the output terminal of the sensor circuit SC(N) is connected to the positive power supply line PL via the resistance element RU(N). Resistance elements RU(1) to RU(N) function as pull-up resistors. Each of the resistive elements RU(1) to RU(N) sets the output voltage of the sensor circuit SC(1) to SC(N) to a high level when the connection path SP(1) to SP(N) is disconnected. Can be fixed. Therefore, it is possible to prevent malfunctions.

(Configuration and operation of sensor circuit SC(K))
The circuit configuration of the K-th sensor circuit SC(K) will be described using FIG. 2. Here, K is a natural number greater than or equal to 1 and less than or equal to N-1. The sensor circuit SC(K) includes a pMOS transistor TP, an nMOS transistor TN, a resistance element RN, a variable capacitance element CN(K), and a Schmitt trigger inverter SI. Resistance element RN has a fixed resistance value R0. The variable capacitance element CN (K) has a capacitance value CV (K) to be detected.

The output signal OS (K-1) output from the previous stage sensor circuit SC (K-1) is input to the gate terminals of the pMOS transistor TP and the nMOS transistor TN. The source terminal and back gate terminal of the pMOS transistor TP are connected to the power supply voltage site VDD. The source terminal and back gate terminal of the nMOS transistor TN are connected to the reference voltage site GND. One end of the resistance element RN is connected to the drain terminal of the pMOS transistor TP. The other end of the resistance element RN is connected to the drain terminal of the nMOS transistor TN at a connection node NN. Connection node NN is connected to one end of variable capacitance element CN (K) and an input terminal of Schmitt trigger inverter SI. The other end of variable capacitance element CN (K) is connected to reference voltage site GND. A voltage signal AN(K) is input to the input terminal of the Schmitt trigger inverter SI. The positive power supply terminal of the Schmitt trigger inverter SI is connected to the power supply voltage site VDD, and the negative power supply terminal is connected to the reference voltage site GND.

The operation of the sensor circuit SC(K) will be explained using the waveform diagram of FIG. 3. At a time before time t(K-1), the output signal OS(K-1) input to the sensor circuit SC(K) is at a high level, the pMOS transistor TP is in the off state, and the nMOS transistor TN is in the on state. state. At this time, the voltage signal AN(K) is 0 [V], and the output signal OS(K) output from the Schmitt trigger inverter SI is at a high level.

When the output signal OS (K-1) switches from high level to low level at time t (K-1), the pMOS transistor TP turns on, the nMOS transistor TN turns off, and charging of the variable capacitance element CN (K) starts. Therefore, the voltage signal AN(K) starts to rise. At this time, assuming that the on-resistance of the pMOS transistor TP is sufficiently smaller than the resistance value R0 of the resistance element RN and can be ignored, the voltage signal AN(K) increases with the slope of "VDD/(R0×CV(K))". (see area A1).

When the voltage signal AN(K) reaches the rising logic threshold voltage VT1 of the Schmitt trigger inverter SI at time t(K), the output signal OS(K) is inverted from high level to low level (see arrow Y1). The detection time DT(K) from time t(K-1) to t(K) is a time proportional to "R0×CV(K)". Therefore, the detection time DT (K) becomes an output corresponding to the capacitance value CV (K) that is the detection target. Thereafter, the voltage signal AN(K) increases until it reaches the power supply voltage VDD.

That is, the sensor circuit SC(K) is a circuit that starts a detection operation in response to the inversion of the output signal OS(K-1), which is an input logic signal. Then, after the input logic signal is inverted and a detection time DT (K) proportional to the capacitance value CV (K), which is the detection amount, has elapsed, the output signal OS (K), which is the output logic signal, is inverted. This circuit ends the detection operation at .

After time t(K), while the output signal OS(K-1) maintains the low level, the voltage signal AN(K) maintains the power supply voltage VDD, and the output signal OS(K) remains at the low level. maintain. Then, at time tres, when the output signal OS (K-1) switches from low level to high level, the pMOS transistor TP is turned off and the nMOS transistor TN is turned on. Since the on-resistance of the nMOS transistor TN is sufficiently small, the charge accumulated in the variable capacitance element CN (K) is instantly discharged, and the voltage signal AN (K) changes to 0 [V] (see arrow Y2). In response to this, the output signal OS(K) output from the Schmitt trigger inverter SI is inverted from low level to high level (see arrow Y3).

(Normal operation of sensor 1)
The normal operation of the sensor 1 will be explained using the waveform diagram of FIG. 4. In FIG. 4, a case where the number of connected sensor units SU is an even number (that is, a case where N is an even number) will be described. At a time before time t(0) in FIG. 4, the start signal ST is at a high level and the sensor 1 is in an off state. When the sensor 1 is in the off state, the output signal OS(1) of the first stage sensor circuit SC(1) is at a high level. As shown in FIG. 1, since the input of each sensor circuit is the output of the preceding sensor circuit, the output signals OS(1) to OS(N) of all sensor circuits are also at high level. Further, as can be seen from the output circuit 30 in FIG. 1, the output signals DO(1) to DO(N) of all the NOR circuits NR are at a low level. Further, the serial output signal Sout is at a low level.

When the start signal ST is switched from high level to low level at time t(0), the detection operation in sensor 1 is started. In response to the transition of the start signal ST to low level, charging of the variable capacitance element CN(1) in the first stage sensor circuit SC(1) is started. At the same time, the serial output signal Sout output from the NOR circuit NR(0) is inverted from low level to high level (arrow Y10).

When the output signal OS(1) of the first stage sensor circuit SC(1) switches from high level to low level at time t(1), the output signal DO(1) output from the NOR circuit NR(1) becomes high level. (arrow Y11), the serial output signal Sout is inverted from high level to low level (arrow Y12). The detection time DT(1) between both edges of the serial output signal Sout is a time proportional to the capacitance value CV(1) of the detection target of the first stage sensor circuit SC(1). Further, in response to the output signal OS(1) switching to low level at time t(1), charging of the variable capacitance element CN(2) in the second stage sensor circuit SC(2) is started.

Similarly, when the output signal OS(2) of the second stage sensor circuit SC(2) switches from high level to low level at time t(2), the output signal DO output from the NOR circuit NR(2) (2) switches to high level (arrow Y13). Therefore, since the output signal DO(1) output from the NOR circuit NR(1) switches to low level (arrow Y14), the serial output signal Sout is inverted from low level to high level (arrow Y15). The detection time DT(2) between both edges of the serial output signal Sout is a time proportional to the capacitance value CV(2) of the detection target of the second stage sensor circuit SC(2). Further, at time t(2), charging of the variable capacitance element CN(3) in the third stage sensor circuit SC(3) is started.

Similarly, when the output signal OS (K) of the previous stage sensor circuit SC (K) switches from high level to low level, the K+1st inversion occurs in the serial output signal Sout, and at the same time, the next stage sensor circuit SC Charging of variable capacitance element CN (K+1) in (K+1) is started. In this way, the detection operation is passed from the previous stage to the subsequent stage in the order in which they are serially connected.
It also indicates the detection time detected by the sensor circuit SC(K) in response to the inversion of the output signal OS(K) of the sensor circuit SC(K) and the completion of the detection operation of the sensor circuit SC(K). Output signal DO(K) is output from NOR circuit NR(K) to NOR circuit NR(K-1). In this way, the detection time is passed from the latter stage to the former stage in the order in which they are serially connected.

Then, at time t(N), when the output signal OS(N) of the Nth sensor circuit SC(N), which is the final stage, switches from high level to low level, the output is output from the NOR circuit NR(N). The signal DO(N) switches to high level (arrow Y16). Since this edge inversion propagates from NOR circuit NR(N-1) to NOR circuit NR(0), serial output signal Sout is inverted to high level (arrow Y17). This completes one detection operation of the N sensor circuits SC(1) to SC(N). The serial output signal Sout is a signal that continuously outputs signals indicating N detection times DT(1) to DT(N) detected by N sensor circuits SC(1) to SC(N). becomes.

Thereafter, at an arbitrary time tres, when the start signal ST is switched from low level to high level, all of the output signals OS(1) to OS(N) are reset to the initial high level (area A2). Furthermore, all of the output signals DO(1) to DO(N) and the serial output signal Sout are reset to the initial state low level (area A3). That is, the sensor 1 is turned off by the transition of the start signal ST to a high level.

As described above, in the sensor 1 of this embodiment, the detection operation of the K+1th sensor circuit can be started in response to the completion of the detection operation of the Kth sensor circuit. Therefore, the detection operation can proceed autonomously in the order in which the serially connected sensor circuits SC(1) to SC(N) are arranged. Since N sensor signals can be read from N sensor circuits without providing a scan circuit such as an XY decoder, the circuit scale of the sensor 1 can be reduced.

(Operation when sensor 1 is disconnected)
The operation when the sensor 1 is disconnected will be described using the waveform diagram in FIG. 5. In this embodiment, as shown in disconnection area BA in FIG. explain. When the connection path CP(1) is disconnected, the signal CP(1) of the connection path CP(1) input to the NOR circuit NR(1) is fixed at a low level by the resistance element RD(1). .

The operation up to time t(1) is the same as the normal operation shown in FIG. 4, so the explanation will be omitted. When the output signal OS(1) of the first stage sensor circuit SC(1) switches from high level to low level at time t(1), the output signal DO(1) output from the NOR circuit NR(1) becomes high level. (arrow Y21), the serial output signal Sout is inverted from high level to low level (arrow Y22). As a result, the detection time DT(1) is outputted by the serial output signal Sout.

At time t(2), the output signal OS(2) of the sensor circuit SC(2) switches from high level to low level, and as a result, the output signal DO(2) is also inverted. However, the signal CP(1) input to the NOR circuit NR(1) is not inverted (arrow Y23 ). Therefore, since the output signal DO(1) output from the NOR circuit NR(1) is not inverted (arrow Y24), the serial output signal Sout is also not inverted (arrow Y25).

As explained above, when the connection path CP(K) of the NOR circuit NR(K) is disconnected, the Propagation of output signals DO(K+1) to DO(N) is blocked by NOR circuit NR(K). As a result, only the detection times DT(1) to DT(K) on the previous stage than the NOR circuit NR(K) in which the disconnection has occurred are outputted as the serial output signal Sout.

(assignment)
The problem will be explained using the sensor 100 of the comparative example shown in FIG. The sensor 100 of the comparative example has a different configuration of the output circuit 130 from the sensor 1 of the present example (FIG. 1). Specifically, instead of NOR circuits NR(1) to NR(N), NAND circuits ND(1) to ND(N) are provided. In the output circuit 130 of the comparative example, the serial output signal Sout is output from the final stage sensor unit SU(N). Furthermore, in the sensor 100, descriptions of the resistance elements RU and RD, the positive power line PL, and the negative power line NL are omitted. The other operational details of the sensor 100 are the same as those of the sensor 1, so a description thereof will be omitted.

In the sensor 100 of the comparative example, the propagation direction of the output signal OS of the sensor array 20 and the propagation direction of the output signal DO of the output circuit 130 are both the same direction from the front stage to the rear stage side. Therefore, the serial output signal Sout is output from the final stage sensor unit SU(N). Therefore, if a disconnection fault occurs in any of the connection paths CP(1) to CP(N-1), the output circuit 130 on the downstream side of the disconnection will inevitably become inoperable, so the entire detection time will be DT(1) to DT(N) will no longer be obtained.

(effect)
In the sensor 1 of this embodiment, the output signal OS that starts the detection operation of the sensor circuit can be propagated from the previous stage to the subsequent stage, such as the Kth, K+1th, and so on. Furthermore, the output signal DO indicating the detection time can be propagated from the later stage to the earlier stage, such as the Kth, K-1st, and so on. Therefore, both the input of the start signal ST and the output of the serial output signal Sout can be combined on the first NOR circuit NR(1) side. As a result, even if a disconnection fault occurs in any of the connection paths CP(1) to CP(N-1) and the output circuit 30 on the downstream side of the disconnection becomes inoperable, the It is possible to output all the detection times DT detected by the sensor circuit SC on the previous stage than the disconnection part by using the output circuit 30 on the previous stage side. In other words, when a disconnection fault occurs in the connection path CP(K), the detection time DT(1) to DT detected by the sensor circuits SC(1) to SC(K-1) on the previous stage than the disconnection part (K) can be output as a serial output signal Sout. It becomes possible to improve robustness in the event of wire breakage.

In the technology of this specification, the sensor 1 can be configured by serially connecting sensor units SU(1) to SU(N) having the same structure. Therefore, an additional sensor unit SU can be added to the final stage sensor unit SU (N), or it can be separated by an intermediate stage sensor unit SU (K). Since the number of connected stages of the sensor units SU can be changed freely, the degree of freedom in designing the sensor 1 can be increased.

FIG. 7 shows a sensor 1a according to a second embodiment. The output circuit 30 (FIG. 1) of Example 1 was an example of a circuit configuration including NOR circuits NR(0) to NR(N). On the other hand, the output circuit 30a (FIG. 7) of the second embodiment is an example of a circuit configuration including NAND circuits NDa(0) to NDa(N). Note that the same reference numerals are given to the parts having the same contents as those in the first embodiment, and the explanation thereof will be omitted. Further, parts unique to the second embodiment are distinguished by adding "a" to the end of the reference numerals.

The output circuit 30a includes NAND circuits NDa(1) to NDa(N) and inverters INVa(0) to INVa(N). The start signal ST is inputted to the NAND circuit NDa(K) via the inverter INVa(0), and the output signal DO(1) is also inputted thereto. The output signal OS (K) output from the K-th sensor circuit SC (K) is input to the K-th NAND circuit NDa (K) via the inverter INVa (K), and the K-th NAND circuit NDa (K) is also input to the K-th NAND circuit NDa (K). An output signal DO(K+1) output from NR(K+1) is input. The output signal DO(K) output from the K-th NAND circuit NDa(K) is input to the K-1th NAND circuit NDa(K-1). The output signal DO(K) is a logic signal expressed by the following formula.

A serial output signal Sout is output from the NAND circuit NDa(0) of the input/output circuit IO, which is the first stage. The serial output signal Sout is a logic signal expressed by the following formula.

A connection path CP(K) between the output terminal of the NAND circuit NDa(K+1) and the input terminal of the NAND circuit NDa(K) is connected to the positive power supply line PL via the resistance element RUa(K). Resistance elements RUa(1) to RUa(N) function as pull-up resistors. When the connection paths CP(1) to CP(N) are disconnected, the input voltages of the NAND circuits NDa(1) to NDa(N) are set to high level by each of the resistance elements RUa(1) to RUa(N). Can be fixed. Therefore, it is possible to prevent malfunctions.

The operation of the output circuit 30a of the second embodiment is the same as that of the output circuit 30 of the first embodiment, and therefore a description thereof will be omitted. The sensor 1a of the second embodiment can also provide the same effects as the sensor 1 of the first embodiment.

Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The techniques described in the claims include various modifications and changes to the specific examples illustrated above. Further, the technical elements described in this specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims as filed. Furthermore, the techniques illustrated in this specification or the drawings can achieve multiple objectives simultaneously, and achieving one of the objectives has technical utility in itself.

(Modified example)
In the operation example shown in FIG. 5, the case where the number of connected sensor units SU is an even number (N is an even number) has been described. In this case, the serial output signal Sout is inverted to low level at time t(N). On the other hand, when the number of connected sensor units SU is an odd number (N is an odd number), the serial output signal Sout is inverted to a high level at time t(N). That is, the only difference between an even number and an odd number of connection stages is the direction of inversion of the final edge of the serial output signal Sout.

In the operation example shown in FIG. 5, a case has been described in which a disconnection occurs in the connection path CP(K) of the NOR circuit NR(K). Similarly, even if a disconnection occurs in the connection path SP(K) of the sensor circuit SC(K), the output signal OS(K) can be fixed at a high level by the resistive element RU(K). Thereby, only the detection time DT on the previous stage side of the sensor circuit SC(K) in which the disconnection has occurred can be outputted as the serial output signal Sout.

In the sensor circuit SC(K) of FIG. 2, a case has been described in which the capacitance of the variable capacitance element CN is used as the physical quantity to be detected, but it is not limited to this form, and various physical quantities can be used as the detection target. It is. For example, the detection target may be the detection current of the photodiode PD or the resistance value of the variable resistance element.

The NOR circuit NR and NAND circuit ND are examples of an interface circuit. The output signal OS is an example of a sensor output logic signal. Output signal DO is an example of an interface output logic signal. The serial output signal Sout is an example of an interface output logic signal output from the first interface circuit. Resistance element RD is an example of a first resistance section. The reference voltage portion GND is an example of a first predetermined voltage portion. Resistance element RU is an example of a second resistance section. The power supply voltage portion VDD is an example of a second predetermined voltage portion.

Aspects of the present technology are listed below.
[Aspect 1]
A sensor comprising N sensor circuits (N is a natural number of 2 or more) and N interface circuits provided corresponding to each of the N sensor circuits,
The N sensor circuits are serially connected such that the sensor output logic signal of the Kth sensor circuit (K is a natural number from 1 to N-1) is input as the sensor input logic signal of the K+1st sensor circuit. It has
The N interface circuits have a serial connection through which an interface output logic signal of the K-th interface circuit is input as an interface input logic signal of the K-1-th interface circuit,
Each of the N sensor circuits starts a detection operation in response to the inversion of the sensor input logic signal, and has a detection time proportional to the detection amount of the sensor circuit after the sensor input logic signal is inverted. A circuit that terminates the detection operation by inverting the sensor output logic signal after the elapsed time,
Each of the N interface circuits is a circuit that inverts the interface output logic signal in response to inversion of the sensor output logic signal of the corresponding sensor circuit,
In response to the sensor output logic signal of the Kth sensor circuit being inverted and the sensing operation of the Kth sensor circuit being completed, the sensing operation of the K+1st sensor circuit is started;
The first interface circuit outputs the interface output logic signal that continuously outputs a signal indicating the N detection times detected by the first to Nth sensor circuits. , sensor.
[Aspect 2]
The sensor output logic signal output from the K-th sensor circuit and the interface output logic signal output from the K+1-th interface circuit are input to the K-th interface circuit,
The interface output logic signal output from the K-th interface circuit is input to the K-1-th interface circuit,
the interface output indicating the sensing time detected by the Kth sensor circuit in response to the sensor output logic signal of the Kth sensor circuit being inverted and the sensing operation of the Kth sensor circuit being completed; The sensor according to aspect 1, wherein a logic signal is output from the Kth said interface circuit to the K-1th said interface circuit.
[Aspect 3]
further comprising N first resistor sections provided corresponding to each of the N interface circuits,
Each of the N interface circuits includes a logic circuit,
An output terminal of the Kth sensor circuit and an output terminal of the K+1st logic circuit are connected to the input terminal of the Kth logic circuit,
Aspect 1, wherein a connection path between the input terminal of the K-th logic circuit and the output terminal of the K+1-th logic circuit is connected to a first predetermined voltage portion via the K-th first resistance section. Or the sensor described in 2.
[Aspect 4]
further comprising N second resistance sections provided corresponding to each of the N sensor circuits,
Aspect 1, wherein a connection path between the output terminal of the Kth sensor circuit and the input terminal of the K+1st sensor circuit is connected to a second predetermined voltage portion via the Kth second resistor section. The sensor described in any one of ~3.
[Aspect 5]
Each of the N sensor circuits has a variable capacitance,
The detected amount is the capacitance of the variable capacitor,
The sensor according to any one of aspects 1 to 4, wherein the detection time is a time proportional to the capacitance of the variable capacitor.
[Aspect 6]
Each of the N sensor circuits includes a diode element,
The detected amount is a reverse leakage current value of the diode element,
The sensor according to any one of aspects 1 to 4, wherein the detection time is a time inversely proportional to the reverse leakage current value.
[Aspect 7]
Each of the N sensor circuits includes a variable resistance,
The detected amount is a resistance value of the variable resistor,
The sensor according to any one of aspects 1 to 4, wherein the detection time is a time proportional to a resistance value of the variable resistor.

1: Sensor SC(1) to (N): Sensor circuit NR(1) to (N): NOR circuit OS(1) to (N): Output signal DO(1) to (N): Output signal DT(1 ) to (N): Detection time Sout: Serial output signal

Claims (7)

A sensor comprising N sensor circuits (N is a natural number of 2 or more) and N interface circuits provided corresponding to each of the N sensor circuits,
The N sensor circuits are serially connected such that the sensor output logic signal of the Kth sensor circuit (K is a natural number from 1 to N-1) is input as the sensor input logic signal of the K+1st sensor circuit. It has
The N interface circuits have a serial connection through which an interface output logic signal of the K-th interface circuit is input as an interface input logic signal of the K-1-th interface circuit,
Each of the N sensor circuits starts a detection operation in response to the inversion of the sensor input logic signal, and has a detection time proportional to the detection amount of the sensor circuit after the sensor input logic signal is inverted. A circuit that terminates the detection operation by inverting the sensor output logic signal after the elapsed time,
Each of the N interface circuits is a circuit that inverts the interface output logic signal in response to inversion of the sensor output logic signal of the corresponding sensor circuit,
In response to the sensor output logic signal of the Kth sensor circuit being inverted and the sensing operation of the Kth sensor circuit being completed, the sensing operation of the K+1st sensor circuit is started;
The first interface circuit outputs the interface output logic signal that continuously outputs a signal indicating the N detection times detected by the first to Nth sensor circuits. , sensor. The sensor output logic signal output from the K-th sensor circuit and the interface output logic signal output from the K+1-th interface circuit are input to the K-th interface circuit,
The interface output logic signal output from the K-th interface circuit is input to the K-1-th interface circuit,
the interface output indicating the sensing time detected by the Kth sensor circuit in response to the sensor output logic signal of the Kth sensor circuit being inverted and the sensing operation of the Kth sensor circuit being completed; The sensor of claim 1, wherein a logic signal is output from the Kth interface circuit to the K-1th interface circuit. further comprising N first resistor sections provided corresponding to each of the N interface circuits,
Each of the N interface circuits includes a logic circuit,
An output terminal of the Kth sensor circuit and an output terminal of the K+1st logic circuit are connected to the input terminal of the Kth logic circuit,
A connection path between an input terminal of the K-th logic circuit and an output terminal of the K+1-th logic circuit is connected to a first predetermined voltage portion via the K-th first resistance section. 2. The sensor according to 1 or 2. further comprising N second resistance sections provided corresponding to each of the N sensor circuits,
A connection path between the output terminal of the K-th sensor circuit and the input terminal of the K+1-th sensor circuit is connected to a second predetermined voltage portion via the K-th second resistor section. 1. The sensor according to 1. Each of the N sensor circuits has a variable capacitance,
The detected amount is the capacitance of the variable capacitor,
The sensor according to claim 1, wherein the detection time is a time proportional to the capacitance of the variable capacitor. Each of the N sensor circuits includes a diode element,
The detected amount is a reverse leakage current value of the diode element,
The sensor according to claim 1, wherein the detection time is a time inversely proportional to the reverse leakage current value. Each of the N sensor circuits includes a variable resistance,
The detected amount is a resistance value of the variable resistor,
The sensor according to claim 1, wherein the detection time is a time proportional to a resistance value of the variable resistor.

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