JP3759740B2 - Data holding circuit - Google Patents

Description

  The present invention relates to a data holding circuit such as a latch circuit, and more particularly to a data holding circuit that reduces the occurrence of soft errors due to α rays and neutrons.

  Conventionally, in semiconductor devices used in outer space and aircraft, the occurrence of soft errors due to radiation such as α rays and neutrons has been a problem. In recent years, higher integration and lower voltage of semiconductor devices have been promoted, and accordingly, generation of soft errors due to radiation can no longer be ignored in semiconductor devices used on the ground. If semiconductor devices are further miniaturized in the future, it is clear that even in semiconductor devices used on the ground, there is a concern about an increase in the occurrence rate of soft errors due to radiation, and the influence cannot be ignored. Against this background, countermeasures for soft errors are required in semiconductor devices in various fields.

  In memories, etc., correction is performed over several clocks by using redundant bits to detect the occurrence of soft errors, using correction codes, or by majority voting by module multiplexing. Countermeasures against soft errors are also demanded in logic circuits that are becoming finer and faster. A data holding circuit such as a latch circuit has a large influence of a soft error in a logic circuit. Even if the data of the combinational circuit is temporarily inverted, the range of influence is limited because it returns to the original data again unless the previous data is inverted, but the retained data is inverted and held as it is Then, the inverted data propagates and affects a wide range. For this reason, in particular, countermeasures against soft errors in the data holding circuit are required, and the present invention does not require a correction module, and relates to countermeasures against soft errors in the data holding circuit that corrects within one clock cycle.

  In the MOS transistor, due to its structure, the soft error from the high logic level (data: 1) to the low logic level (data: 0) in the NMOS, and the low logic level (data: 0) to the high logic level (data: 1 in the PMOS). ) Only a soft error occurs. In the following description, data is represented by 0 and 1.

  Non-Patent Document 1 and Patent Document 1 describe countermeasures against soft errors in a data holding circuit, but both circuits generate only errors of 1 → 0 in the NMOS as described above and 0 → 1 in the PMOS. Focusing on the features, the node that holds the latched data is divided into a part consisting only of NMOS and a part consisting only of PMOS, so that the same data is held and the held data is corrected mutually. It has become. Since they are the same data, a soft error occurs only in one side and does not occur in the other. Therefore, one data in which an error has occurred is corrected with the other data having no error.

  However, in these circuit configurations, there is a problem that the operation speed is slow because the NMOS side node and the PMOS side node are connected in a feedback manner. Further, since a large number of transistors are used, there is a problem that the configuration is complicated and the circuit scale becomes large.

  Further, since the feedback path is always in operation, there is a problem that if a glitch caused by the generation of charge is inverted longer than the delay time of the feedback path, a node error is propagated to other holding nodes. .

  In order to solve such problems, Patent Document 2 by the present applicant describes a data holding circuit as shown in FIG. This data holding circuit includes a conventional input gate circuit TFG that takes in and holds input data D in synchronization with clocks CK and CKB, and an inverter Inv1 having a CMOS configuration in which the data held in the input gate circuit is applied to the gate. This data holding circuit is characterized in that a pull-up path constituted by P-channel transistors P0 and P1 and a pull-down path constituted by N-channel transistors N0 and N1 are further provided. When a soft error occurs in the data held in the data holding node DH of the data holding circuit, it is corrected with the data of the data holding node PDH in the pull-up path and the data holding node NDH in the pull-down path. Further, when a soft error occurs in the data of the data holding node PDH of the pull-up path or the data holding node NDH of the pull-down path, the P channel transistor P1 or the N channel transistor N1 is turned off and the correction function does not work. The data held in the node DH is not affected.

  In the data holding circuit of FIG. 1, P-channel transistors P51 and P52 and N-channel transistors N51 and N52 are further provided so as to mutually correct the data of the data holding node PDH of the pull-up path or the data holding node NDH of the pull-down path. It is a static type that feeds back. Thereby, the data of the data holding nodes PDH and NDH are stably held.

  In the conventional example of FIG. 1, PDH data is corrected by data held in NDH and DH, and NDH is corrected by data held in PDH and DH. However, even if a soft error occurs in each data holding node. It has a configuration that does not affect others. Specifically, PDH is connected to a low-potential power supply through two transistors, a P-channel transistor P51 and an N-channel transistor N52, and NDH connects two transistors, an N-channel transistor N51 and a P-channel transistor P52. Via a high potential power source. For example, when DH is at a high level (H) and PDH and NDH are at a low level (L), P51 and N52 are turned on, PDH is connected to a low potential power source, and PDH is statically held at L.

  When DH is L and PDH and NDH are H, P51 and N52 are turned off. Here, even if a soft error in which DH changes from L to H occurs and N52 is turned on, P51 does not turn on, so PDH does not change to L. Similarly, even if a soft error occurs in which NDH changes from H to L, N52 remains off, so PDH does not change to L. Since PDH is connected only to the P-channel transistor, PDH itself does not change from H to L. The same applies to NDH.

K. Joe Hass, Jody W. Gambles: "Mitigating Single Event Upsets From Combinational Logic" 7th NASA Symposium on VLSI Design 1998 US Patent 6,026,011 JP 2003-273709 A

  However, in the data holding circuit of FIG. 1, since PDH is connected to a low potential power source through two transistors P51 and N52, there is a problem that even when PDH is L, the level is not sufficiently low. . Further, since all the PDHs are connected to the P-channel transistors, there is a problem that there is a leak when PDH is L, and the data holding time is insufficient. There is a similar problem with NDH.

  In addition, the data holding circuits described in Non-Patent Document 1, Patent Document 1 and Patent Document 2 can improve resistance to soft errors caused by α rays generated individually in each data holding node. The resistance to soft errors caused by neutrons generated at the same time cannot be improved. In order to solve this problem, Patent Document 2 describes a layout in which the drains of transistors that hold data that may simultaneously cause a soft error are arranged apart from each other. However, the area allocated to one data holding circuit in the logic circuit block is limited, and it is not possible to sufficiently improve a soft error that occurs simultaneously at a plurality of data holding nodes only by improving the layout. There was a problem.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems and further improve the tolerance of a data holding circuit against a soft error.

  To achieve the above object, the data holding circuit according to the first aspect of the present invention includes a data holding unit that takes in and holds input data in a data holding node in synchronization with a clock, and outputs the held data. A pull-up control signal is applied directly to the gate, and a first gate circuit composed of a P-channel transistor that captures and holds input data as a pull-up control signal in a first correction data holding node in synchronization with the pull-up control signal. A first correction circuit having a first P channel transistor for pulling up the data held in the data holding node to a high level when the control signal is at a low level, and input data as a pull-down control signal in synchronization with the clock. 2 A second gate composed of an N-channel transistor is stored in the correction data holding node. And a first N-channel transistor for pulling down the data held in the data holding node to a low level when the pull-down control signal is directly applied to the gate and the pull-down control signal is at a high level. The first correction data holding node is connected to the low-potential power source by one stage of the second N-channel transistor, and the second correction data holding node is set by one stage of the second P-channel transistor. Each is connected to a high potential power source. A first correction control circuit that controls the second N-channel transistor to be conductive (ON) when the data held in the data holding node is at a high level, and the second P-channel transistor receives the data held in the data holding node. A second correction control circuit is further provided for controlling to turn on (turn on) at a low level.

  With this configuration, since the first correction data holding node is connected to the low-potential power supply by the one-stage second N-channel transistor, the potential of the first correction data holding node can be made sufficiently low. Similarly, since the second correction data holding node is connected to the high potential power source by the second P channel transistor in one stage, the potential of the second correction data holding node can be sufficiently set to the H level.

  However, in this configuration, since the first correction data holding node is directly connected to the low potential power supply by the second N channel transistor, the potential of the first correction data holding node becomes H when a soft error occurs in the second N channel transistor. May change from L to L and affect the data holding node. Therefore, the second N-channel transistor has a size as small as possible in order to reduce the possibility of radiation entering the portion of the second N-channel transistor. Since the second P-channel transistor connecting the second correction data holding node to the high potential power supply has the same problem, the size is reduced.

  If the gates of the second N-channel transistor and the second P-channel transistor are directly connected to the data holding node, there arises a problem that a soft error of the data holding node immediately affects the first and second correction data holding nodes. Therefore, the second N-channel transistor and the second P-channel transistor are controlled by the data of the data holding node through the first and second correction control circuits. Specifically, in the first correction control circuit, the gate of the second N-channel transistor is connected to the data holding node via the third P-channel transistor, and in the second correction control circuit, the gate of the second P-channel transistor is connected to the third N-channel. The transistor is connected to the data holding node through the transistor. The third P-channel transistor is controlled by the potential of the pull-down path, and the third N-channel transistor is controlled by the potential of the pull-up path. Thus, even if a soft error occurs in the data holding node, the first and second correction data holding nodes are not affected.

  In addition, when the third P-channel transistor and the third N-channel transistor are off, the gates of the second N-channel transistor and the second P-channel transistor are in a floating state, which causes a problem of instability. Therefore, in the first correction control circuit, the gate of the second N-channel transistor is connected to the low potential power supply via the fourth N-channel transistor, and in the second correction control circuit, the gate of the second P-channel transistor is connected via the fourth P-channel transistor. Connect to a high potential power supply. The fourth N-channel transistor is controlled by the potential of the second correction data holding node, and the fourth P-channel transistor is controlled by the potential of the first correction data holding node.

  With the above configuration, when the first correction data holding node is at the L level, the second N-channel transistor is turned on, so that the first correction data holding node is connected to the low potential power source and is stable. However, when the first correction data holding node is at the H level, the second N-channel transistor is off and the first correction data holding node is in a floating state. Therefore, when a soft error occurs in the second N-channel transistor and it turns on, the first correction data holding node changes from H level to L level, and the first P channel transistor turns on and affects the data holding node. Therefore, the first correction data holding node is connected to the high potential power supply by the fifth P channel transistor. The gate of the fifth P-channel transistor is connected to the gate of the second N-channel transistor. As a result, the second N-channel transistor and the fifth P-channel transistor operate complementarily, and the first correction data holding node is stabilized. For the same reason, the second correction data holding node is connected to the low potential power source by the fifth N-channel transistor, and the gate of the fifth N-channel transistor is connected to the gate of the second P-channel transistor.

  Further, since the first correction data holding node is connected to the second N-channel transistor, a soft error that changes from H level to L level may occur. The first P-channel transistor is turned off when the first correction data holding node is at the H level, but may be turned on when the first correction data holding node is changed to the L level to change the data holding node. Therefore, the second N-channel transistor is connected to the first correction data holding node via the resistance element. As a result, the possibility that the first correction data holding node changes to the L level when the first correction data holding node is at the H level is significantly lower than when the first correction data holding node is directly connected to the second N-channel transistor. For the same reason, the second P-channel transistor is connected to the second correction data holding node via the resistance element.

  Further, when the first correction data holding node is at L level, the gate of the second N-channel transistor is at H level. Since the gate of the second N-channel transistor is connected to the fourth N-channel transistor, a soft error that changes from H level to L level may occur. When such a soft error occurs, the fifth P-channel transistor May turn on and change the first correction data holding node from the L level to the H level. Even if such a change occurs, only the first P-channel transistor is turned off and the first correction circuit is disconnected, but such a state is not preferable. Therefore, the fifth P-channel transistor is connected to the first correction data holding node via the resistance element. As a result, the possibility of changing to the H level when the first correction data holding node is at the L level is reduced. For the same reason, the fifth N-channel transistor is connected to the second correction data holding node through the resistance element.

  The resistance element is preferably composed of a diffused resistor, a resistor connected to the first correction data holding node uses a P-type diffused resistor, and a resistor connected to the second correction data holding node is an N-type diffused resistor. Consist of resistors.

  In addition, the P channel transistor constituting the gate circuit of the first correction data holding node has a longer gate length than the other P channel transistors, and the N channel transistor constituting the second correction data holding node is more than the other N channel transistors. A long gate length is desirable. As a result, the leakage of the first and second correction data holding nodes can be reduced.

  Further, in order to further improve the resistance against soft errors, a capacitive element is connected to at least one of the data holding node, the first correction data holding node, the second correction data holding node, the second N channel transistor, and the second N channel transistor. May be.

  Although the first aspect of the present invention has been described above, in the configuration of the first aspect, soft errors that have occurred individually at each node do not propagate and are corrected immediately. Since the soft error generated by the α ray is limited for each node, in other words, the first mode can improve the resistance against the soft error caused by the α ray. However, since soft errors due to neutrons are not limited to errors at each node as semiconductor technology becomes smaller in the future, there is a concern that they may occur at a plurality of adjacent nodes. Soft error tolerance is not enough. The configurations described in Non-Patent Document 1, Patent Documents 1 and 2, and the like do not have sufficient resistance against soft errors that occur in a plurality of nodes.

  The second aspect of the present invention can improve resistance to soft errors that occur in such a plurality of nodes. The data holding circuit according to the second aspect of the present invention further includes an error recovery circuit that is activated by a disturbance such as radiation and changes from a high impedance state to a state that outputs data according to the output of the data holding circuit, Feedback is provided so as to correct the state of the data holding circuit based on the output of the error recovery circuit.

  An error recovery circuit according to a second aspect of the present invention includes an N-channel transistor and a first minute current source, and includes a first sensor circuit that is activated by a disturbance, a P-channel transistor, and a second minute current source, A second sensor circuit that is activated by a disturbance; and a switch that changes an output from a high impedance state to a state that outputs data according to input data when the first and second sensor circuits are activated. It is characterized by that.

  The switch circuit of the error recovery circuit includes a plurality of nodes that output a plurality of different data corresponding to input data so that the states of a plurality of portions of the data holding circuit can be corrected.

  The sensitivity with which the first and second sensor circuits are activated with respect to radiation is set to be higher than the sensitivity with which the data retention node changes the retention data with respect to radiation.

  The error recovery circuit according to the second aspect can be added to any data holding circuit. The error recovery circuit is provided near the center of the data holding circuit.

  When the second mode is applied to the data holding circuit of the first mode, the error recovery circuit of the second mode is provided in the data holding circuit of the first mode, and the output of the data holding node is an error. A plurality of output data of the error recovery circuit switch that are input as input data of the recovery circuit are fed back to the data holding node, the first correction data holding node, and the second correction data holding node of the data holding circuit. .

  According to the second aspect of the present invention, when a soft error occurs in a plurality of nodes such as neutrons, a soft error occurs in the data holding node, the first correction data holding node, and the second correction data holding node of the data holding circuit. Before being generated and propagating the output of the data holding circuit to the error recovery circuit, the error recovery circuit is quickly activated to output data corresponding to the output of the data holding circuit before the soft error occurs. The output of the error recovery circuit is fed back to the data holding node, the first correction data holding node, and the second correction data holding node of the data holding circuit so as to maintain these nodes in the state before the soft error occurs. Therefore, a normal state is maintained.

  Although there is a concern that the output of the data holding circuit changed due to the soft error is propagated to the error recovery circuit, this problem can be prevented by setting the time constant of the error recovery circuit to an appropriate value. For example, the time constant for activating the error recovery circuit is set to be approximately equal to the pulse period due to the neutron soft error, and during the period in which an error occurs in the data holding circuit, the data in the data holding circuit is fed back from the error recovery circuit. Force data to be stored correctly. In other words, the data holding circuit sets a time constant so as not to generate a soft error. The time constant of the error recovery circuit can be set with a minute current source.

  It should be noted that the sensitivity for activating the error recovery circuit is preferably set higher than the sensitivity at which the data holding circuit changes the stored data with respect to radiation, but in that case, the error recovery circuit frequently (mainly by alpha rays) An error will occur. However, the data output when the error recovery circuit is activated is data when the data holding circuit is in a normal state, and even if it is fed back, each part of the data holding circuit is the same data, and there is a particular problem. Absent.

  As described above, according to the first aspect of the present invention, even if a soft error occurs, it is corrected and the final output signal can be maintained at a normal value, and the data holding is performed so that the soft error does not propagate to the next stage. A circuit is obtained.

  Further, according to the second aspect of the present invention, it is possible to obtain a data holding circuit that can correct even if soft errors occur simultaneously in a plurality of nodes.

  FIG. 2 is a diagram showing the configuration of the data holding circuit according to the first embodiment of the present invention. As shown in the figure, the data holding circuit of the first embodiment includes data having a clock synchronous inverter CKIInv that takes input data D into a data holding node DH in synchronization with clocks CK and CKB, and an inverter Inv1 that outputs data Q. A holding unit 1, a first gate circuit composed of a P-channel transistor P0 that takes in and holds input data D as a pull-up control signal in the first correction data holding node PDH in synchronization with the clock, and a pull-up control signal A first correction circuit 2 having a first P-channel transistor P1 applied directly to the gate and pulling up the data held in the data holding node DH to a high level when the pull-up control signal is at a low level, and in synchronization with the clock The second correction data holding node ND using the input data D as a pull-down control signal A second gate circuit composed of an N-channel transistor N0 that captures and holds the data, and a pull-down control signal is directly applied to the gate, and when the pull-down control signal is high, the data held in the data holding node DH is set to low level And a second correction circuit 3 having a first N-channel transistor N1 to be pulled down. Since this configuration is described in Patent Document 2, description thereof is omitted. In addition to the above configuration, the data holding circuit according to the first embodiment has a second N-channel transistor N2 that connects the first correction data holding node PDH to a low potential power source, and a second correction data holding node NDH that uses a high potential power source. The second P-channel transistor P2 to be connected, the third P-channel transistor P3 to connect the gate of the second N-channel transistor N2 to the data holding node DH, and the third N-channel transistor to connect the gate of the second P-channel transistor P2 to the data holding node DH N3, a fourth N-channel transistor N4 that connects the gate of the second N-channel transistor N2 to the low-potential power supply, and a fourth P-channel transistor P4 that connects the gate of the second P-channel transistor P2 to the high-potential power supply.

  The gate of the third P-channel transistor P3 is connected to the second correction data holding node NDH, the gate of the third N-channel transistor N3 is connected to the first correction data holding node PDH, and the gate of the fourth N-channel transistor N4 is connected to the second correction data holding node PDH. Connected to the holding node NDH, the gate of the fourth P-channel transistor P4 is connected to the first correction data holding node PDH. The gate of the second N-channel transistor N2 is represented by a first auxiliary node PDH2, and the gate of the second P-channel transistor P2 is represented by a second auxiliary node NDH2. Further, the part constituted by P3 and N4 corresponds to the first correction control circuit, and the part constituted by N3 and P4 corresponds to the second correction control circuit. Further, the clock synchronous inverter CKINv in FIG. 2 shows a state constituted by transistors.

  FIG. 3 shows a state where input data of L level (0) is taken. In the figure, a portion indicated by a thin line indicates an off state, and a thick line indicates an on state. As shown in the figure, the data holding node DH and the first auxiliary node PDH2 are at the H level (1). The output Q, the first correction data holding node PDH, the second correction data holding node NDH, and the second auxiliary node NDH2 are zero. Transistors P1, N2, P3, P4 and inverter Invo are on. Transistors N1, P2, N3 and N4 are off.

  As shown in FIG. 3, in the data holding circuit of the first embodiment, when the first correction data holding node PDH is 0, it is connected to the low potential power source only by the second N-channel transistor N2, so the first correction data The potential of holding node PDH can be made sufficiently low. Although not shown, when the input data D is 1, the transistors N1, P2, N3, and N4 are turned on, the transistors P1, N2, P3, and P4 are turned off, and the second correction data holding node NDH is Since only the second P-channel transistor P2 is connected to the high potential power supply, the potential of the second correction data holding node NDH can be made sufficiently high.

  Next, consider a case where a soft error occurs in each node in the state of FIG. In this case, a soft error may occur in the data holding node DH, the first correction data holding node PDH, the second correction data holding node NDH, the first auxiliary node PDH2, and the second auxiliary node NDH2, that is, all nodes. is there.

  FIG. 4A shows a case where a soft error occurs in the data holding node DH, and DH changes from 1 to 0 and the output Q changes from 0 to 1. Due to this change, the first auxiliary node PDH2 changes from 1 to 0, and N2 is turned off, but PDH remains at 0. Further, since N4 is off, even if DH changes from 1 to 0, the second auxiliary node NDH2 is not affected, and NDH2 remains 1 and does not change.

  FIG. 4A changes due to a DH soft error, but PDH remains 0. Therefore, as shown in FIG. 4B, P1 is on, and DH changes from 0 to 1 again. The output Q returns to 0.

  FIG. 5 is a time chart showing the above change, and DH and Q change due to a DH soft error. However, since PDH and NDH do not change, the original state is restored within a short time.

  FIG. 6A shows a case where a soft error occurs in the first correction data holding node PDH and PDH changes from 0 to 1. Due to this change, P1 is turned off, but N1 is also turned off, so DH remains at 1.

  Even if PDH changes as shown in FIG. 6A, N2 remains on. Therefore, as shown in FIG. 6B, PDH returns from 0 to 0 again, and P1 turns on again.

  FIG. 7 is a time chart showing the above change. PDH changes due to PDH soft error, but DH, Q, and NDH do not change.

  Next, the value of NDH is determined and held by N0, but is also held by P2. When it is determined and held only by N0, it is only necessary to consider the occurrence of a soft error from 0 to 1 of NDH as described above. Therefore, the size of P2 is made very small compared to other transistors, particularly P0, to reduce the possibility of a soft error in which PDH changes from 1 to 0 due to radiation. Similarly, the size of N2 is made very small compared to other transistors, particularly P0, to reduce the possibility of a soft error in which PDH changes from 0 to 1 due to radiation.

  Further, it is desirable that the gate length of P0 and N0 is longer than that of other transistors in order to reduce the possibility that PDH and NDH change due to leakage.

  Further, the first auxiliary node PDH2 is determined and held by P3, but since it is connected to the low potential power source by N4, a soft error from 1 to 0 may occur. However, even if PDH2 changes from 1 to 0, only N2 is turned off and PDH and DH are not affected.

  Further, since the second auxiliary node NDH2 is determined and held by N3, a soft error from 1 to 0 may occur. However, since NDH2 is connected to the high potential power source by P4, P2 is Before turning on, NDH2 returns from 0 to 1.

  The case where the input data D is 0 has been described above. However, when D, PDH and NDH are 1 and DH is 0, the same applies to the case where a soft error occurs in DH and NDH, and the description is omitted. .

  In the configuration of the first embodiment, when PDH is at L level (0), since N2 is on, PDH is connected to a low potential power source and is stable. However, when PDH is at H level (1), N2 is off and PDH is in a floating state. As described above, N2 is reduced in size so that a soft error does not occur, but the occurrence of a soft error cannot be reduced to zero. If a soft error occurs and N2 is turned on, PDH changes from the H level to the L level, and P1 is turned on to affect the data holding node. The data holding circuit of the second embodiment solves this problem.

  FIG. 8 is a diagram showing the configuration of the data holding circuit of the second embodiment of the present invention. The difference from the first embodiment is that P5 is connected between the PDH and the high potential power supply, and the NDH and the low potential power supply are connected. N5 is connected between them. The gate of P5 is connected to PDH2, and the gate of N5 is connected to NDH2.

  FIG. 9A shows a case where D, PDH, NDH and Q are 1 and DH, PDH2 and NDH2 are 0 in the second embodiment. As shown in the figure, since N4 is on, PDH2 is 0 and P5 is also on. In this state, even if a soft error in which PDH changes from 1 to 0 due to N2, PDH is connected to the high potential power supply by P5, so the soft error is canceled and P1 is not turned on. Therefore, DH does not change and Q does not change.

  FIG. 9B shows a case where D, PDH, NDH and Q are 0 and DH, PDH2 and NDH2 are 1 in the second embodiment. In this case, N5 works to hold NDH.

  FIG. 10 is a diagram showing the resistance against the soft error of the data holding circuit of the second embodiment in comparison with the conventional example. In this figure, the horizontal axis indicates the power supply voltage Vdd, the vertical axis indicates the amount of charge collected in the drain, and the case where the correct data is 10 ns after the occurrence of noise (soft error) due to radiation is considered normal (Pass). The case where the data is incorrect was regarded as an error (Fail). In the figure, the solid line indicates the range in which an error occurs when the output Q is 0 in the data holding circuit of the second embodiment, and the broken line indicates the range in which an error occurs when the output Q is 1 in the data holding circuit of the second embodiment. The alternate long and short dash line indicates a range where an error occurs when the output Q is 0, and the alternate long and two short dashes line indicates a range where an error occurs when the output Q is 1. It can be seen that even when the charge amount is 10 fC or more, which is conventionally determined as Fail, it is Pass.

  FIG. 11 is a diagram showing the configuration of the data holding circuit according to the third embodiment of the present invention. The resistance element R1 is between PDH and N2, the resistance element R2 is between NDH and P2, and between PDH and P5. The second embodiment is different from the second embodiment in that the resistance element R3 is connected to the resistance element R4 between NDH and N5.

  In the configuration of the second embodiment, since the PDH is connected to N2, a soft error from 1 to 0 may occur. As described above, in the second embodiment, the provision of P5 makes it difficult for PDH to change from 1 to 0. However, such a soft error cannot be completely prevented. P1 is off when PDH is 1, but turns on when it changes to 0, changing DH from 0 to 1. Therefore, N2 is connected to PDH via the resistance element R1. As a result, even if radiation is incident when PDH is 1, carriers generated by the radiation flow to N2 through the resistance element, so that it is difficult for the potential to change, and the possibility that PDH changes from 1 to 0 is second. This is significantly lower than when PDH is directly connected to N2 as in the embodiment. For the same reason, the possibility that NDH is changed from 1 to 0 by the resistance element R2 is significantly lower than that in the second embodiment.

  Further, when PDH is 1, PDH2 is 0. When a soft error occurs in which PDH2 changes from 0 to 1, N2 is turned on and works to change PDH to 0. However, because of R1, the time constant of this change is large, and before PDH changes to 0 Since PDH2 returns to 0 and N2 is turned off, the original state is maintained. R2 performs the same function.

  Further, in the configuration of the second embodiment, when DH and PDH2 are 1, PDH is 0. When DH changes from 1 to 0 due to a soft error, PDH2 changes similarly. In addition, since PDH2 is connected to N4, a soft error that changes from 1 to 0 may occur. When such a soft error occurs, P5 is turned on and PDH is changed from 0 to 1. Even if such a change occurs, only P1 is turned off and PDH is disconnected. However, if a soft error has occurred in DH as described above, this will not be corrected immediately. Therefore, P5 is connected to PDH via the resistance element R3. As a result, even if P5 is turned on, PDH does not change from 0 to 1 immediately, the possibility that PDH changes due to a soft error is reduced, and DH is also corrected immediately. Similarly, the resistance element R4 reduces the possibility that NDH changes from 1 to 0.

  The resistance elements R1 to R4 are preferably configured by diffusion resistors, the resistance elements R1 and R3 connected to the PDH are configured using P-type diffusion resistors, and the resistance elements R2 and R4 connected to the NDH are N-type Consists of diffused resistors. For example, if the noise due to soft error is a pulse of 100 ps and the capacitance of the node is 100 fF, the resistance value of the resistance element may be 1 kΩ, and this resistance element is made small by a polysilicon resistance or a diffused resistance. It is possible.

  The data holding circuits of the first to third embodiments of the present invention have been described above. However, these data holding circuits have a feature that soft errors generated individually at each node, mainly PDH and NDH, do not propagate. , There is a feature that an error generated in DH is corrected immediately. Since the soft error occurring in the α-ray is limited for each node, in other words, the data holding circuits of the first to third embodiments can improve the resistance against the soft error due to the α-ray. However, as the power supply voltage decreases, the error correction time increases, and the probability of other node errors occurring within the correction time also increases.Furthermore, soft errors due to neutrons are not limited to each node, but at multiple adjacent nodes. As a result, even the data holding circuits of the first to third embodiments are not sufficiently resistant to soft errors. The configurations described in Non-Patent Document 1, Patent Documents 1 and 2, and the like do not have sufficient resistance against soft errors that occur in a plurality of nodes.

  FIG. 12 is a diagram showing the configuration of the data holding circuit according to the fourth embodiment of the present invention. As shown in the figure, the data holding circuit of the fourth embodiment has a configuration in which an error recovery circuit 11 is added to the data holding circuit 10 of the second embodiment.

  The error recovery circuit 11 includes an N-channel transistor 11 and a first minute current source 7, and includes a first sensor circuit 5 that is activated by a disturbance such as radiation, a P-channel transistor P11, and a second minute current source 8. When the second sensor circuit 6 that is activated by disturbance and the first and second sensor circuits 5 and 6 are activated, the output is changed from a high impedance state to a state in which data corresponding to the input data is output. A changing switch circuit. The switch circuit includes a first-stage inverter composed of P-channel transistors P12 and P13 and N-channel transistors N12 and N13, and a second-stage inverter composed of P-channel transistors P14 and P15 and N-channel transistors N14 and N15. And have. The outputs of the first sensor circuit 5 and the second sensor circuit 6 are applied to the gates of P13 and P15 and N13 and N15, respectively. The input of the first stage inverter is connected to the output Q of the data holding circuit 10, and the output of the first stage inverter is input to the second stage inverter and also connected to the data holding node DH of the data holding circuit 10. ing. The output of the second stage inverter is connected to the first and second correction data holding nodes PDH and NDH of the data holding circuit 10.

  The sensitivity with which the first and second sensor circuits 5 and 6 are activated with respect to the radiation is set to be higher, that is, more sensitive than the sensitivity with which the data holding node 10 changes the held data with respect to the radiation.

  In FIG. 12, the error recovery circuit 11 is shown to be provided beside the data holding node 10, but it is desirable to provide it near the center of the data holding node 10. As a result, when a neutron affecting the data holding node 10 is incident, the error recovery circuit 11 is reliably activated and works to hold normal data.

  In the data holding circuit of the fourth embodiment, when there is no disturbance such as radiation, the error recovery circuit 11 is inactive, and the outputs of the first and second stages are in a high impedance state. When a soft error occurs at a plurality of nodes of the data holding circuit due to neutrons or the like, the first and second sensor circuits 5 and 6 of the error recovery circuit 11 are more sensitive, so they are always activated, and the output of the data holding circuit 10 Activates before Q changes. Therefore, before the output Q of the data holding circuit 10 is propagated to the error recovery circuit 11, the first and second sensor circuits 5 and 6 are activated, the first and second stage inverters are activated, and a soft error occurs. An output corresponding to the output Q before changing is generated.

  Since the output of the error recovery circuit corresponding to the state before changing due to the soft error is fed back to the data holding node, the first correction data holding node, and the second correction data holding node of the data holding circuit, the values of these nodes It works so as not to change, and if the value of the node is changing, it is restored. Even if there is a node whose value has not changed, there is no problem because it is just the same data. In this way, the state of each node of the data holding circuit 10 is maintained in a normal state before the soft error occurs.

  Although there is a concern that the internal data held in the data holding circuit 10 is inverted due to a soft error and the output Q is propagated to the error recovery circuit 11 with a certain time constant, the data is set by setting the time constant of the error recovery circuit. The holding circuit can be prevented from being inverted.

  For example, when the pulse period generated by a neutron soft error is about 100 ps to 150 ps, the time constant is set from 100 ps to 150 ps depending on the resistance value, current value, and node capacitance value of the micro current source of the error recovery circuit, and data is retained. A counter pulse that forcibly blocks the error is given by feedback during the period when the error is expected to occur in the circuit, and the data holding circuit has a time constant set so that no error pulse is generated, that is, no soft error is generated. .

  Further, after this series of recovery operations, a single error may occur in the data holding circuit, but the single error can be dealt with only by the data holding circuits of the first to third embodiments. By that time, the error recovery circuit has sufficiently returned to the inactive state and does not affect the data holding circuit.

  Since the sensitivity for activating the error recovery circuit 11 is set higher than the sensitivity with which the data holding circuit changes the held data with respect to radiation, the error recovery circuit 11 frequently causes soft errors (mainly due to α rays). Will occur. However, the data output when the error recovery circuit 11 is activated is data when the data holding circuit 10 is in a normal state, and the same data is obtained even if it is fed back or each part of the data holding circuit is corrected. There is no particular problem.

  According to the present invention, since the reliability of the data holding circuit is improved, the data holding circuit includes a semiconductor device used in a situation that is easily affected by radiation such as outer space and an aircraft, and a large number of data holding circuits. When used in a large computer that requires high reliability, it is possible to prevent malfunctions of the semiconductor device and the computer and improve the reliability and safety of the device.

It is a figure which shows the structure of the prior art example of the data holding circuit which improved the tolerance with respect to a soft error. It is a figure which shows the structure of the data holding circuit of 1st Example of this invention. It is a figure explaining operation | movement of the data holding circuit of 1st Example. It is a figure explaining operation | movement of the data holding circuit of 1st Example. It is a time chart which shows the operation | movement of the data holding circuit of 1st Example. It is a figure explaining operation | movement of the data holding circuit of 1st Example. It is a time chart which shows the operation | movement of the data holding circuit of 1st Example. It is a figure which shows the structure of the data holding circuit of 2nd Example of this invention. It is a figure explaining operation | movement of the data holding circuit of 2nd Example. It is a figure which shows the improvement of the soft error tolerance of the data holding circuit of 2nd Example compared with a prior art example. It is a figure which shows the structure of the data holding circuit of 3rd Example of this invention. It is a figure which shows the structure of the data holding circuit of 4th Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Data holding part 2 ... 1st correction circuit 3 ... 2nd correction circuit 5 ... 1st sensor circuit 6 ... 2nd sensor circuit 7 ... 1st minute current source 8 ... 2nd minute current source 10 ... Data holding circuit 11 ... Error recovery circuit

Claims (11)

A data holding unit that captures and holds input data in a data holding node in synchronization with a clock, and outputs the held data;
A first gate circuit composed of a P-channel transistor that captures and holds input data as a pull-up control signal in a first correction data holding node in synchronization with a clock; and the pull-up control signal is applied directly to the gate; A first correction circuit having a first P-channel transistor for pulling up data held in the data holding node to a high level when a pull-up control signal is at a low level;
A second gate circuit composed of an N-channel transistor that captures and holds input data as a pull-down control signal in a second correction data holding node in synchronization with the clock; and the pull-down control signal is directly applied to the gate, A second correction circuit having a first N-channel transistor for pulling down the data held in the data holding node to a low level when the control signal is at a high level;
A second N-channel transistor connected between the first correction data holding node and a low potential power source;
A second P-channel transistor connected between the second correction data holding node and a high potential power source;
A first correction control circuit for conducting the second N-channel transistor when the data held in the data holding node is at a high level;
A data holding circuit comprising: a second correction control circuit for conducting the second P-channel transistor when data held in the data holding node is at a low level. The first correction control circuit includes:
A third P-channel transistor connected between the data holding node and the gate of the second N-channel transistor and controlled by the potential of the second correction data holding node;
The fourth N-channel transistor connected between the gate of the second N-channel transistor and a low-potential power supply and controlled by the potential of the second correction data holding node;
The second correction control circuit is
The third N-channel transistor connected between the data holding node and the gate of the second P-channel transistor and controlled by the potential of the first correction data holding node;
2. The data holding circuit according to claim 1, further comprising: a fourth P channel transistor connected between a gate of the second P channel transistor and a high potential power source and controlled by a potential of the first correction data holding node. A fifth P-channel transistor connected between the first correction data holding node and a high-potential power supply and controlled by the gate potential of the second N-channel transistor;
3. The data holding circuit according to claim 1, further comprising: a fifth N-channel transistor connected between the second correction data holding node and a low-potential power source and controlled by a gate potential of the second P-channel transistor.   Between the first correction data holding node and the second N-channel transistor, between the second correction data holding node and the second P-channel transistor, and between the first correction data holding node and the fifth P-channel transistor. The data holding circuit according to claim 3, further comprising a resistance element connected to at least one of the second correction data holding node and the fifth N-channel transistor.   The resistive element is a diffused resistor, a P-type diffused resistor when connected to the first correction data holding node, and an N-type diffused resistor when connected to the second correction data holding node. The data holding circuit according to claim 4. The P-channel transistor constituting the first gate circuit has a gate length longer than other P-channel transistors,
6. The data holding circuit according to claim 1, wherein the N-channel transistor constituting the second gate circuit has a gate length longer than that of other N-channel transistors.   7. The capacitive element is connected to at least one of the data holding node, the first correction data holding node, the second correction data holding node, the second N-channel transistor, and the second N-channel transistor. The data holding circuit according to claim 1. A data holding unit;
A data holding circuit comprising an error recovery circuit,
The error recovery circuit is
A first sensor circuit comprising an N-channel transistor and a first minute current source and activated by a disturbance;
A second sensor circuit comprising a P-channel transistor and a second minute current source and activated by a disturbance;
A switch that changes from a high impedance state to a state that outputs data according to input data when the first and second sensor circuits are activated;
The output of the data holding unit is input as the input data of the error recovery circuit,
The output of the switch of the error recovery circuit is fed back to the data holding unit,
The data holding circuit, wherein the first and second sensor circuits are activated with respect to radiation with higher sensitivity than the sensitivity with which the data holding unit changes the held data with respect to radiation.   The data holding circuit according to claim 8, wherein the switch circuit includes a plurality of nodes that output a plurality of different data according to the input data.   The data holding circuit according to claim 8 or 9, wherein the error recovery circuit is provided near a center of the data holding unit. A data holding circuit according to any one of claims 1 to 5,
A first sensor circuit activated by a disturbance comprising an N-channel transistor and a first minute current source; a second sensor circuit activated by a disturbance comprising a P-channel transistor and a second minute current source; A switch that changes from a high-impedance state to a state that outputs data corresponding to input data when the second sensor circuit is activated, and the switch circuit includes a plurality of switches corresponding to the input data. It has an error recovery circuit with multiple nodes that output different data,
The output of the data holding unit is input as the input data of the error recovery circuit,
A data holding circuit that feeds back a plurality of output data of the switch of the error recovery circuit to the data holding node, the first correction data holding node, and the second correction data holding node of the data holding circuit.

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