JP2024015126A - semiconductor equipment - Google Patents

Abstract

An imaging device having a light source is provided. [Solution] An imaging device having a light emitting device and a photoelectric conversion device in pixels, in which a pixel circuit outputs third data obtained by multiplying acquired first data and second data (weighting). Has a function. By calculating the third data externally, more detailed information on the subject for a specific wavelength can be obtained. Further, by collectively reading out a plurality of pixels given appropriate weights, it is also possible to output difference data between pixels, and external calculations can be omitted. [Selection diagram] Figure 3

Description

One aspect of the present invention relates to an imaging device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. More specifically, the technical fields of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, lighting devices, power storage devices, storage devices, imaging devices, and driving methods thereof. , or their manufacturing method.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Furthermore, storage devices, display devices, imaging devices, and electronic devices may include semiconductor devices.

2. Description of the Related Art A technique for configuring a transistor using an oxide semiconductor thin film formed on a substrate is attracting attention. For example, Patent Document 1 discloses an imaging device in which a pixel circuit uses a transistor that includes an oxide semiconductor and has an extremely low off-state current.

Japanese Patent Application Publication No. 2011-119711

Imaging devices are used not only as means for imaging visible light, but also for various purposes. For example, it is used for personal authentication, failure analysis, medical diagnosis, security applications, etc. In these applications, in addition to visible light, short-wavelength light such as X-rays, long-wavelength light such as infrared light, etc. are used depending on the purpose.

Natural light or indoor light may be used as visible light and infrared light, but it is also common to use a dedicated light source. Light bulb-shaped lamps, LEDs, lasers, and the like are used as light sources, but there are challenges in making them smaller and thinner when used in combination with imaging devices.

Therefore, one object of one aspect of the present invention is to provide an imaging device having a light source. Another object of the present invention is to provide an imaging device that includes a thin light source and captures an image of light emitted from the light source reflected from a subject. Alternatively, one of the objects is to provide an imaging device having a thin infrared light source. Another object of the present invention is to provide an imaging device capable of performing product-sum calculations on a plurality of pixels.

Alternatively, one of the objects is to provide an imaging device with low power consumption. Alternatively, one of the objects is to provide an imaging device that can perform imaging at high speed. Alternatively, one of the purposes is to provide a highly reliable imaging device. Alternatively, one of the purposes is to provide a new imaging device. Alternatively, one of the objects is to provide a method for operating the above imaging device. Alternatively, one of the purposes is to provide a new semiconductor device or the like.

Note that the description of these issues does not preclude the existence of other issues. Note that one embodiment of the present invention does not need to solve all of these problems. Note that issues other than these will naturally become clear from the description, drawings, claims, etc., and it is possible to extract issues other than these from the description, drawings, claims, etc. It is.

One aspect of the present invention relates to a thin imaging device having a light source. Alternatively, the present invention relates to an imaging device capable of performing calculations.

One aspect of the present invention includes a first pixel, a second pixel, a first correlated double sampling circuit, a second correlated double sampling circuit, and an A/D conversion circuit, The first pixel and the second pixel each include a light emitting device and a photoelectric conversion device, the first pixel is electrically connected to the first correlated double sampling circuit, and the second pixel is electrically connected to the first correlated double sampling circuit. is electrically connected to the first correlated double sampling circuit, the first correlated double sampling circuit is electrically connected to the second correlated double sampling circuit, and the second correlated double sampling circuit is electrically connected to the first correlated double sampling circuit. is electrically connected to the A/D conversion circuit, and the first pixel, the second pixel, the first correlated double sampling circuit, and the second correlated double sampling circuit have a metal oxide in the channel forming region. This is an imaging device having a transistor.

The first pixel and the second pixel each include a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, The first pixel and the second pixel each further include a first capacitor, a second capacitor, and a memory circuit, and one of the source and drain of the first transistor is connected to the photoelectric conversion device. the other of the source or drain of the first transistor is electrically connected to one electrode of the first capacitor; the source or drain of the second transistor is electrically connected to one of the source or drain of the third transistor; One of the drains is electrically connected to one electrode of the second capacitor, one electrode of the second capacitor is electrically connected to the gate of the fourth transistor, and the source or One of the drains is electrically connected to one of the source or drain of the fifth transistor, the other of the source or drain of the fifth transistor is electrically connected to the first correlated double sampling circuit, and the other of the source or drain of the fifth transistor is electrically connected to the first correlated double sampling circuit. The other electrode of the second capacitor can be electrically connected to a memory circuit.

The memory circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, and the memory circuit further includes a third capacitor and a sixth transistor. one of the source or drain of is electrically connected to one electrode of the third capacitor, one electrode of the third capacitor is electrically connected to the gate of the seventh transistor, and the seventh transistor is electrically connected to one of the source or drain of the eighth transistor, and the other of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the ninth transistor. and one of the source or drain of the ninth transistor can be electrically connected to the other electrode of the second capacitor.

The other of the source or drain of the fifth transistor included in the first pixel and the other source or drain of the fifth transistor included in the second pixel are electrically connected, and The gate of the fifth transistor and the gate of the fifth transistor included in the second pixel may be electrically connected.

The first wavelength<the second wavelength, and the light-emitting devices of the first pixel and the second pixel emit near-infrared light including the first wavelength and the second wavelength, The photoelectric conversion device included in the pixel may have an absorption edge wavelength shorter than the second wavelength, and the photoelectric conversion device included in the second pixel may have an absorption edge wavelength equal to or longer than the second wavelength.

Further, the first wavelength < the second wavelength, the light emitting device included in the first pixel emits near-infrared light having a peak at the first wavelength, and the light emitting device included in the second pixel emits near-infrared light having a peak at the first wavelength. The photoelectric conversion device of the first pixel emits near-infrared light having a peak at a second wavelength, and the absorption edge wavelength is shorter than the second wavelength. The end may be configured to have a wavelength equal to or longer than the second wavelength.

Further, the first wavelength < the second wavelength, the light emitting device included in the first pixel emits near-infrared light having a peak at the first wavelength, and the light emitting device included in the second pixel emits near-infrared light having a peak at the first wavelength. The photoelectric conversion device that emits near-infrared light having a peak at the second wavelength and that the first pixel and the second pixel have may have an absorption edge wavelength equal to or longer than the second wavelength. In this configuration, the first pixel is provided with a first optical filter layer that selectively transmits light at a first wavelength and its vicinity, and the second pixel is provided with a first optical filter layer that selectively transmits light at a first wavelength and its vicinity. A second optical filter layer that selectively transmits the light may be provided.

The first pixel, the second pixel, the first correlated double sampling circuit, and the second correlated double sampling circuit each include a first flexible substrate and a second correlated double sampling circuit opposite to the first flexible substrate. can be provided between the flexible substrate and the flexible substrate.

The metal oxide preferably contains In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

By using one embodiment of the present invention, an imaging device having a light source can be provided. Alternatively, it is possible to provide an imaging device that includes a thin light source and captures an image of light emitted from the light source reflected from a subject. Alternatively, an imaging device having a thin infrared light source can be provided. Alternatively, it is possible to provide an imaging device capable of performing product-sum calculations on a plurality of pixels.

Alternatively, an imaging device with low power consumption can be provided. Alternatively, it is possible to provide an imaging device that can capture images at high speed. Alternatively, a highly reliable imaging device can be provided. Alternatively, a new imaging device can be provided. Alternatively, a method for operating the imaging device described above can be provided. Alternatively, a new semiconductor device or the like can be provided.

FIG. 1 is a block diagram illustrating an imaging device. 2A to 2C are diagrams illustrating a pixel array. FIG. 3 is a diagram illustrating a pixel circuit. FIG. 4A is a diagram illustrating the rolling shutter method. FIG. 4B is a diagram illustrating the global shutter method. FIG. 5 is a diagram illustrating the readout circuit. FIG. 6 is a timing chart illustrating the operation of the imaging device. FIG. 7 is a block diagram illustrating the imaging device. 8A to 8C are diagrams illustrating a light emitting device and a photoelectric conversion device. 9A to 9C are diagrams illustrating pixel circuits. FIGS. 10A to 10C are diagrams illustrating pixel circuits. FIGS. 11A to 11C are diagrams illustrating pixel circuits. 12A to 12C are diagrams illustrating a pixel circuit. 13A and 13B are diagrams illustrating a pixel circuit. 14A to 14C are diagrams illustrating the configuration of a pixel, a photoelectric conversion device, and a light emitting device of an imaging device. FIG. 15 is a diagram illustrating a pixel configuration of an imaging device. 16A to 16D are diagrams illustrating transistors. 17A1, FIG. 17A2, FIG. 17B1, and FIG. 17B2 are diagrams illustrating electronic equipment. 18A and 18B are diagrams illustrating an electronic device.

Embodiments will be described in detail using the drawings. However, those skilled in the art will easily understand that the present invention is not limited to the following description, and that the form and details thereof can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the contents described in the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions may be designated by the same reference numerals in different drawings, and repeated explanation thereof may be omitted. Note that hatching for the same elements constituting a figure may be omitted or changed as appropriate between different drawings.

Furthermore, even if a single element is shown in the circuit diagram, the element may be composed of a plurality of elements as long as there is no functional inconvenience. For example, a plurality of transistors that operate as switches may be connected in series or in parallel. In some cases, a capacitor (also referred to as a capacitive element) may be divided and placed at multiple positions.

Further, one conductor may have multiple functions such as wiring, electrode, and terminal, and in this specification, multiple names may be used for the same element. Furthermore, even if elements are shown to be directly connected on the circuit diagram, the elements may actually be connected via multiple conductors, and this specification In this document, even such a configuration is included in the category of direct connection.

(Embodiment 1)
In this embodiment, an imaging device that is one embodiment of the present invention will be described with reference to drawings.

One embodiment of the present invention is an imaging device that includes a light emitting device and a photoelectric conversion device in a pixel. The light emitted by the light emitting device and reflected by the subject is received by the photoelectric conversion device. Since an EL element is used as the light emitting device, a thin imaging device with a light source can be constructed.

Further, a configuration in which a plurality of EL elements with different emission wavelengths are provided, and a configuration in which a plurality of photoelectric conversion devices with different light reception wavelengths are provided can also be adopted. Therefore, object information for a plurality of wavelengths can be obtained.

Further, the imaging device has a function of outputting third data obtained by multiplying the first data acquired by the pixel by the second data (weight). By calculating the third data externally, more detailed information on the subject for a specific wavelength can be obtained. Further, by collectively reading out a plurality of pixels given appropriate weights, it is also possible to output difference data between pixels, and external calculations can be omitted.

Furthermore, by using an element that emits infrared light as a light-emitting device, it can be used for biometric authentication, measurement of physical activity, analysis of defects in industrial products, selection of agricultural products, etc. Furthermore, by using a pixel circuit that can capture images using a global shutter method, it is possible to obtain distortion-free images even when the subject is in motion.

<Imaging device>
FIG. 1 is a block diagram illustrating an imaging device according to one embodiment of the present invention. The imaging device includes a pixel array 21 having pixels arranged in a matrix, a circuit 22 (row driver) having a function of selecting a row of the pixel array 21, and a circuit 23 having a function of reading data from the pixel circuit 10. and a circuit 28 for supplying a power supply potential. A pixel circuit 10 and a light emitting device 11 are provided in the pixel.

The circuit 23 is a readout circuit, which includes a circuit 24 (first CDS circuit) for performing correlated double sampling processing on the output data of the pixel circuit 10, and a circuit 24 (first CDS circuit) for performing correlated double sampling processing on the output data of the circuit 24. A circuit 25 (second CDS circuit) for performing this, a circuit 26 (such as an A/D conversion circuit) having a function of converting analog data output from the circuit 25 into digital data, and a pixel array 21 for reading data. A circuit 27 (column driver) having a function of selecting a column can be included. The circuit 23 can also be provided with a current source circuit or the like.

Note that a configuration may be adopted in which the pixel circuit 10 and the light emitting device 11 do not overlap. For example, as shown in FIG. 2A, the pixel circuits 10 and the light emitting devices 11 may be alternately arranged at regular intervals. Further, as shown in FIG. 2B, the pixel circuits 10 and the light emitting devices 11 may be arranged alternately in each row. As a modification of the configuration shown in FIG. 2B, the light emitting device 11 may extend in one direction as shown by the broken line.

Further, as shown in FIG. 2C, a configuration may be adopted in which the light emitting device 11 is arranged between two adjacent pixel circuits 10. In this case, the light emitting device 11 is arranged with a region overlapping the wiring connected to the pixel circuit 10. Note that although FIGS. 2A to 2C illustrate the same number of light emitting devices 11 as the pixel circuits 10, the number of light emitting devices 11 may be different from the number of pixel circuits 10.

<Pixel circuit>
FIG. 3 is a circuit diagram illustrating a pixel circuit 10 that can be used in an imaging device according to one embodiment of the present invention. The pixel circuit 10 can include a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, a transistor 106, a capacitor 107, a capacitor 108, and a memory circuit 30. Note that a configuration may be adopted in which the capacitor 107 is not provided.

One electrode (cathode) of the photoelectric conversion device 101 is electrically connected to one of the source and drain of the transistor 102. The other of the source and drain of transistor 102 is electrically connected to one electrode of capacitor 107. One electrode of the capacitor 107 is electrically connected to one of the source and drain of the transistor 103. The other one of the source and the drain of the transistor 103 is electrically connected to one of the source and the drain of the transistor 104. One of the source and drain of transistor 104 is electrically connected to one electrode of capacitor 108. One electrode of capacitor 108 is electrically connected to the gate of transistor 105. One of the source and drain of transistor 105 is electrically connected to one of the source and drain of transistor 106. The other electrode of capacitor 108 is electrically connected to memory circuit 30 .

The memory circuit 30 can include a transistor 110, a transistor 111, a transistor 112, a transistor 113, and a capacitor 114.

One of the source and drain of transistor 110 is electrically connected to one electrode of capacitor 114. One electrode of capacitor 114 is electrically connected to the gate of transistor 112. One of the source and drain of the transistor 112 is electrically connected to one of the source and the drain of the transistor 111. The other one of the source and drain of transistor 112 is electrically connected to one of the source and drain of transistor 113. One of the source and drain of transistor 113 is electrically connected to the other electrode of capacitor 108.

Here, a wiring connecting the other of the source or drain of the transistor 102, one electrode of the capacitor 107, and one of the source or drain of the transistor 103 is referred to as a node FD1. A wiring connecting the other of the source or drain of transistor 103, one of the source or drain of transistor 104, one electrode of capacitor 108, and the gate of transistor 105 is defined as node FD2.

Node FD1 can function as a charge storage section. Node FD2 can function as a charge detection section.

Further, in the memory circuit 30, a wiring connecting one of the source or drain of the transistor 110, one electrode of the capacitor 114, and the gate of the transistor 112 is referred to as a node NW1. A wiring connecting the other of the source or drain of transistor 112, one of the source or drain of transistor 113, and the other electrode of capacitor 108 is defined as node NW2.

Node NW1 can function as a data holding node. Node NW2 can function as a data read node.

The other electrode (anode) of the photoelectric conversion device 101 is electrically connected to the wiring 121. A gate of the transistor 102 is electrically connected to the wiring 124. A gate of the transistor 103 is electrically connected to the wiring 125. The other source or drain of the transistor 104 and the other source or drain of the transistor 105 are electrically connected to the wiring 122. A gate of the transistor 104 is electrically connected to the wiring 126. A gate of the transistor 106 is electrically connected to a wiring 127. The other of the source and drain of the transistor 106 is electrically connected to the wiring 123. The other electrode of the capacitor 107 is electrically connected to a reference potential line such as a GND wiring, for example.

Further, in the memory circuit 30, the other of the source and drain of the transistor 110 is electrically connected to the wiring 133. The other of the source and drain of the transistor 111 is electrically connected to the wiring 134. The other of the source and drain of the transistor 113 is electrically connected to the wiring 135. The other electrode of the capacitor 114 is electrically connected to a reference potential line such as a GND wiring, for example.

The wirings 124, 125, 126, 127, 136, 137, and 138 can function as signal lines that control conduction of each transistor.

The wirings 121 and 122 can have a function as a power supply line. In the configuration shown in FIG. 3, the cathode side of the photoelectric conversion device 101 is electrically connected to the transistor 102, and the node FD1 and node FD2 are reset to a high potential to operate, so the wiring 122 is connected to a high potential ( (potential higher than that of the wiring 121).

In the memory circuit 30, the transistor 112 and the transistor 113 operate as source followers, and can read the potential of the node NW1 to the node NW2. The wiring 134 and the wiring 135 can have a function as a power supply line for operating the transistor 112, and the wiring 134 is set at a high potential (higher potential than the wiring 135).

The wiring 123 can function as an output line. The wiring 133 in the memory circuit can function as a signal line for data (weight) writing.

A photodiode can be used as the photoelectric conversion device 101. In one aspect of the present invention, imaging is performed using infrared rays. Therefore, the photoelectric conversion device 101 uses a photodiode that can photoelectrically convert at least light in the infrared region.

For example, a photodiode having an organic photoconductive film in the photoelectric conversion layer can be used. The organic photoconductive film is a thin film and can be bent if the supporting substrate is flexible. Therefore, it is suitable for forming a flexible imaging device. Furthermore, it is easy to increase the size of the imaging device. Note that a photoconductor having an organic photoconductive film may be used as the photoelectric conversion device 101.

Further, a pn junction type photodiode using single crystal silicon for the photoelectric conversion portion, a pin type photodiode using polycrystalline silicon or microcrystalline silicon for the photoelectric conversion layer, etc. can also be used. Alternatively, a photodiode including a material such as a compound semiconductor that can photoelectrically convert light in the infrared region may be used.

Note that many of the materials that can be used for the photodiode or photoconductor have sensitivity in the visible light region, so images in visible light can also be acquired. Note that when acquiring an infrared light image, if visible light becomes noise, it is preferable to provide an infrared transmission filter (a filter that blocks visible light) between the photoelectric conversion device 101 and the subject.

The transistor 102 has a function of controlling the potential of the node FD1. Transistor 103 has a function of controlling the potential of node FD2. Transistor 104 has a function of resetting the potentials of node FD1 and node FD2. The transistor 105 functions as a source follower circuit and can output the potential of the node FD2 to the wiring 123 as image data. The transistor 106 has a function of selecting a pixel that outputs image data.

For the transistors 102, 103, and 104, transistors in which a metal oxide is used in a channel formation region (hereinafter referred to as an OS transistor) are preferably used. OS transistors have a characteristic of extremely low off-state current. By using OS transistors for the transistors 102, 103, and 104, the period during which charges can be held at the nodes FD1 and FD2 can be extremely long. Therefore, it is possible to apply a global shutter method in which charge is accumulated simultaneously in all pixels without complicating the circuit configuration or operation method.

<Operation mode of imaging device>
FIG. 4A is a diagram schematically showing the operating method of the rolling shutter method, and FIG. 4B is a diagram schematically showing the global shutter method. En represents the exposure (accumulation operation) of the n-th column (n is a natural number), and Rn represents the read-out operation of the n-th column. 4A and 4B show operations from the first line (Line[1]) to the Mth line (Line[M]) (M is a natural number).

The rolling shutter method is an operation method that sequentially performs exposure and data readout, and is a method in which the readout period of one row overlaps the exposure period of another row. Since the readout operation is performed immediately after exposure, imaging can be performed even with a circuit configuration in which the data retention period is relatively short. However, since one frame of image is composed of data without imaging simultaneity, distortion occurs in the image when imaging a moving object.

On the other hand, the global shutter method is an operation method in which all pixels are exposed simultaneously, data is held in each pixel, and data is read out row by row. Therefore, even when imaging a moving object, an image without distortion can be obtained.

When a pixel circuit uses a transistor with a relatively high off-state current, such as a transistor whose channel formation region uses Si (hereinafter referred to as a "Si transistor"), a rolling shutter method is used because the data potential tends to flow out from the charge storage section. . In order to realize the global shutter method using Si transistors, it is necessary to separately provide a memory circuit, etc., and furthermore, complicated operations must be performed at high speed. On the other hand, when an OS transistor is used in the pixel circuit, there is almost no leakage of data potential from the charge storage section, so a global shutter method can be easily implemented.

It is also preferable to use OS transistors for the transistor 110, the transistor 111, the transistor 112, and the transistor 113 in the memory circuit 30. By using an OS transistor as the transistor 110, the potential of the node NW1 can be held for an extremely long time. Therefore, if the data is the same, it is possible to reduce the frequency of writing to the node NW1.

Furthermore, by using OS transistors for the transistors 111, 112, and 113, the potential of the node NW2 can be maintained for an extremely long time. Since the potential of the node NW2 can be held for a long period of time, the potential of the node FD2 is stabilized, so that reliable data can be read from the pixel circuit 10.

Note that OS transistors may also be applied to other transistors included in the pixel circuit 10. Alternatively, an arbitrary combination of OS transistors and Si transistors may be applied. Alternatively, all transistors may be OS transistors. Alternatively, all transistors may be Si transistors. Examples of the Si transistor include a transistor containing amorphous silicon, a transistor containing crystalline silicon (typically, low-temperature polysilicon, single crystal silicon, etc.), and the like.

An EL element can be used for the light emitting device 11. As the EL element, an element that emits infrared light can be used. In particular, an EL element that emits near-infrared light having a peak at a wavelength of 700 nm or more and 2500 nm or less is preferable. For example, since light with a wavelength of 760 nm or around 760 nm is easily absorbed by deoxyhemoglobin in veins, the position of a vein can be detected by receiving reflected light from a palm or finger and creating an image. This effect can be used as biometric authentication.

Furthermore, by comparing the amount of light received at a wavelength at which deoxyhemoglobin absorbs a large amount and light at a wavelength at which oxyhemoglobin absorbs a large amount (for example, 940 nm), a region in which neural activity is active in the living body can be detected. This function can be used for analysis of brain function, etc. Similarly, the blood oxygen concentration can also be measured by comparing the amount of light received at a wavelength that is absorbed by deoxyhemoglobin and light at a wavelength that is absorbed by oxyhemoglobin. Note that if the target of infrared light absorption is glucose in the blood, the blood sugar level can also be measured.

In addition, near-infrared light of an appropriate wavelength can be used to perform non-destructive inspections such as inspecting foreign objects in foods and analyzing defects in industrial products. In addition, when combined with the global shutter method, highly accurate sensing is possible even when the subject is moving.

In analyzing brain function, it is necessary to place a relatively large-area imaging device (sensor) in close contact with the head, so the imaging device must be flexible or have a curved surface that matches the shape of the head. It is preferable that the image pickup device is formed with the following characteristics. In order to impart flexibility to an imaging device, a method is used in which the imaging device is first completed on a hard substrate and then transferred to a soft substrate.

At this time, since an organic resin such as polyimide is used as a buffer layer for separating the imaging device from the hard substrate, the process temperature of transistors and the like may be limited. Therefore, the electrical characteristics and reliability of the transistor may be deteriorated. Furthermore, forming a transistor using polycrystalline silicon requires laser irradiation, and laser damage to the buffer layer and peripheral members may cause peeling defects.

Therefore, when forming a flexible imaging device, it is preferable to use an OS transistor. Since OS transistors can be formed at relatively low temperatures and do not require a laser irradiation process, they do not have the above problems and can be said to be suitable for flexible imaging devices.

Further, by using an EL element as the light emitting device 11, a thin imaging device with a light source can be realized, which can be easily installed in various devices, and portability can be improved.

<Readout circuit>
FIG. 5 is a diagram illustrating the circuit 23 connected to a specific column of the pixel array 21. A current source circuit 29 is electrically connected to the wiring 123 through which data is output from the pixel circuit 10 . Further, a circuit 24 (first CDS circuit), a circuit 25 (second CDS circuit), a circuit 26 (A/D conversion circuit), and a circuit 27 (shift register) are connected to the wiring 123 in this order.

The circuit 24 can have a configuration including a transistor 141 and a capacitor 143. Further, the circuit 25 can have a configuration including a transistor 142 and a capacitor 144.

One electrode of the capacitor 143 is electrically connected to the wiring 123. The other electrode of capacitor 143 is electrically connected to one of the source and drain of transistor 141. One of the source and drain of the transistor 141 is electrically connected to one electrode of the capacitor 144. The other electrode of capacitor 144 is electrically connected to one of the source and drain of transistor 142. One of the source or drain of transistor 142 is electrically connected to circuit 26 . Circuit 26 is electrically connected to circuit 27. The circuit 26 can include, for example, a comparator, a counter, an output section (OUT), and the like.

Here, a wiring connecting the other electrode of the capacitor 143, one of the source or drain of the transistor 141, and one electrode of the capacitor 144 is referred to as a node NC1. The wiring connecting the other electrode of capacitor 144, one of the source or drain of transistor 142, and circuit 26 is designated as node NC2.

The other of the source or drain of the transistor 141 and the other of the source or drain of the transistor 142 are electrically connected to a wiring that can supply a reference potential (V _CDS ).

<Output data of imaging device>
In the imaging device according to one embodiment of the present invention, third data obtained by multiplying first data acquired by a pixel by second data (weight) can be output. The third data can be generated using the pixel circuit 10, the circuit 24, and the circuit 25, and unnecessary components are removed. Next, I will explain it.

The third data includes data without exposure (D _r ) output by the pixel circuit 10, data obtained by adding weight to data without exposure (D _r+w ), data with exposure (D _r+x ), and data with exposure. It is generated using weighted data (D _r+x+w ).

When the pixel circuit 10 outputs _Dr , a current proportional to the function of equation (1) flows through the wiring 123. Here, r is the reset potential, V _th is the threshold voltage of the transistor 105, and r corresponds to the potential of the node FD2 at the time of reading.

(r-V _th ) ² (1)

When the pixel circuit 10 outputs Dr _+w , a current proportional to the function of equation (2) flows through the wiring 123. Here, w is a weight, and r+w corresponds to the potential of the node FD2 at the time of reading.

(r+w-V _th ) ² (2)

When the pixel circuit 10 outputs Dr _+x , a current proportional to the function of equation (3) flows through the wiring 123. Here, x is the amount of change in potential due to exposure, and r+x corresponds to the potential of node FD2 at the time of reading.

(r+x−V _th ) ² (3)

When the pixel circuit 10 outputs Dr _+x+w , a current proportional to the function of equation (4) flows through the wiring 123. r+x+w corresponds to the potential of node FD2 during reading.

(r+x+w-V _th ) ² (4)

Here, the amount of change (difference) in the presence or absence of weighting is calculated for the case without exposure and the case with exposure. Specifically, equation (2) - equation (1) and equation (4) - equation (3) are calculated.

(r+w−V _th ) ² −(r−V _th ) ² =w(2r+w−2V _th ) (5)

(r+x+w-V _th ) ² -(r+x-V _th ) ² =w(2r+2x+w-2V _th ) (6)

Furthermore, when formulas (6) to (5) are calculated, the solution becomes 2wx as shown in formula (7).

w(2r+2x+w-2V _th )-w(2r+w-2V _th )=2wx (7)

That is, information regarding the product of exposure data (x) and weight (w) can be extracted. The operation of outputting data corresponding to the above equations (1) to (4) can be performed by the pixel circuit 10. The calculation operation of data corresponding to equations (5) and (6) can be mainly performed by the circuit 24. The calculation operation of data corresponding to equation (7) can be mainly performed by the circuit 25.

<Operation of imaging device>
Next, an example of specific operations of the pixel circuit 10, the circuit 24, and the circuit 25 will be explained using the timing chart of FIG. Note that in the explanation of timing charts in this specification, a high potential is expressed as "H" and a low potential is expressed as "L". It is assumed that "L" is always supplied to the wirings 121, 123, and 135, and "H" is always supplied to the wirings 122, 134.

Although the operation of the light emitting device 11 will not be discussed here, it is assumed that the light emitting device 11 is supplied with a power supply potential for appropriately emitting light at least during the storage operation period.

In period T1, the potential of the wiring 124 is "H", the potential of the wiring 125 is "H", the potential of the wiring 126 is "H", the potential of the wiring 127 is "L", the potential of the wiring 136 is "H", and the potential of the wiring 125 is "H". When the potential of the wiring 137 is "L", the potential of the wiring 138 is "H", the potential of the wiring 151 is "L", and the potential of the wiring 152 is "L", the transistors 102, 103, and 104 are conductive, and the nodes FD1 and The potential “H” (r: reset potential) of the wiring 122 is supplied to the node FD2 (reset operation).

Furthermore, in the memory circuit 30, the transistor 113 becomes conductive, and the potential "L" of the wiring 135 is written to the node NW2. At this time, "rL" is held in the capacitor 108. Further, the transistor 110 becomes conductive, and the potential "w" supplied from the wiring 133 is written to the node NW1. Note that writing of the weight to the node NW1 is not limited to the period T1, and may be performed before the weight is read to the node NW2.

In period T2, the potential of the wiring 124 is "H", the potential of the wiring 125 is "L", the potential of the wiring 126 is "L", the potential of the wiring 127 is "L", the potential of the wiring 136 is "L", and the potential of the wiring 125 is "L". When the potential of the wiring 137 is set to "L", the potential of the wiring 138 is set to "H", the potential of the wiring 151 is set to "L", and the potential of the wiring 152 is set to "L", the transistors 103 and 104 become non-conductive, and the potential of the wiring 152 becomes "L". Reset potential "r" is held. Further, the potential of the node FD1 changes by the potential of the exposure amount "x" according to the operation of the photoelectric conversion device 101, and becomes "r+x" (accumulation operation).

In period T3, the potential of the wiring 124 is "L", the potential of the wiring 125 is "L", the potential of the wiring 126 is "L", the potential of the wiring 127 is "L", the potential of the wiring 136 is "L", and the potential of the wiring 125 is "L". When the potential of the wiring 137 is "L", the potential of the wiring 138 is "H", the potential of the wiring 151 is "L", and the potential of the wiring 152 is "L", the transistor 102 becomes non-conductive, and the potential of the node FD1 is determined. and retained. Further, the transistor 110 becomes non-conductive, and the potential of the node NW1 is maintained.

At this time, by using OS transistors with low off-state current as the transistors 102, 103, 104, and 110, it is possible to suppress unnecessary charge outflow from the nodes FD1, FD2, and NW1, and each data retention time can be extended.

In period T4, the potential of the wiring 124 is "L", the potential of the wiring 125 is "L", the potential of the wiring 126 is "L", the potential of the wiring 127 is "H", the potential of the wiring 136 is "L", and the potential of the wiring 125 is "L". When the potential of the wiring 137 is "L", the potential of the wiring 138 is "H", the potential of the wiring 151 is "H", and the potential of the wiring 152 is "H", the transistor 106 becomes conductive, and the source follower operation of the transistor 105 causes the transistor 106 to conduct. A current proportional to a function (r−V _th ) ² containing the potential “r” of the node FD2 flows through the wiring 123 (read operation 1). This operation corresponds to the above-mentioned equation (1).

Further, the transistor 141 of the circuit 24 and the transistor 142 of the circuit 25 are turned on, and the reference potential "V _CDS " is written to the node NC1 and the node NC2, respectively.

In period T5, the potential of the wiring 124 is "L", the potential of the wiring 125 is "L", the potential of the wiring 126 is "L", the potential of the wiring 127 is "H", the potential of the wiring 136 is "L", and the potential of the wiring 125 is "L". When the potential of the wiring 137 is "H", the potential of the wiring 138 is "L", the potential of the wiring 151 is "L", and the potential of the wiring 152 is "H", in the memory circuit 30, the transistor 111 is conductive and the transistor 113 is conductive. The transistor 112 becomes non-conductive, and the source follower operation of the transistor 112 causes the potential "w" of the node NW1 to be read to the node NW2.

At this time, the potential of the node FD2 becomes "r-L+w" due to the capacitive coupling of the capacitor 108. Here, if "L"=0V, the potential of the node FD2 becomes "r+w". Therefore, due to the source follower operation of the transistor 105, a current proportional to a function (r+w−V _th ) ² including “r+w” flows through the wiring 123. This operation corresponds to the above-mentioned equation (2).

Further, in the circuit 24, the transistor 141 becomes non-conductive. At this time, when “V _CDS ”=0V, the potential of the node NC1 becomes (r+w−V _th ) ² −(r−V _th ) ² =w(2r+w−2V _th ) due to the capacitive coupling of the capacitor 143. This operation corresponds to the above-mentioned equation (5).

In period T6, the potential of the wiring 124 is "L", the potential of the wiring 125 is "H", the potential of the wiring 126 is "L", the potential of the wiring 127 is "H", the potential of the wiring 136 is "L", and the potential of the wiring 125 is "H". When the potential of the wiring 137 is "L", the potential of the wiring 138 is "H", the potential of the wiring 151 is "H", and the potential of the wiring 152 is "L", the transistor 103 becomes conductive, and the potential of the node FD1 is transferred to the node FD2. The potential of "r+x" is read out. Therefore, due to the source follower operation of the transistor 105, a current proportional to a function (r+x−V _th ) ² including “r+x” flows through the wiring 123. This operation corresponds to the above-mentioned equation (3).

Further, in the memory circuit 30, the transistor 111 becomes non-conductive, the transistor 113 becomes conductive, and the potential "L" of the wiring 135 is written to the node NW2. At this time, “r+x−L” is held in the capacitor 108.

Further, the transistor 141 of the circuit 24 becomes conductive, and the reference potential "V _CDS " is written to the node NC1. Further, the transistor 142 of the circuit 25 becomes non-conductive. Therefore, the potential of the node NC2 becomes "V _CDS -w (2r+w-2V _th )" due to the capacitive coupling of the capacitor 144. That is, if "V _CDS "=0V, the potential of the node NC2 becomes "-w(2r+w-2V _th )".

In period T7, the potential of the wiring 124 is "L", the potential of the wiring 125 is "H", the potential of the wiring 126 is "L", the potential of the wiring 127 is "H", the potential of the wiring 136 is "L", and the potential of the wiring 125 is "L". When the potential of the wiring 137 is "H", the potential of the wiring 138 is "L", the potential of the wiring 151 is "L", and the potential of the wiring 152 is "L", in the memory circuit 30, the transistor 111 is conductive and the transistor 113 is conductive. The transistor 112 becomes non-conductive, and the source follower operation of the transistor 112 causes the potential "w" of the node NW1 to be read to the node NW2.

At this time, the potential of the node FD2 becomes "r+x-L+w" due to the capacitive coupling of the capacitor 108. Here, if "L"=0V, the potential of the node FD2 becomes "r+x+w". Therefore, due to the source follower operation of the transistor 105, a current proportional to a function (r+x+w−V _th ) ² including “r+x+w” flows through the wiring 123. This operation corresponds to the above-mentioned equation (4).

Further, in the circuit 24, the transistor 141 becomes non-conductive. At this time, when “V _CDS ”=0V, the potential of the node NC1 becomes (r+x+w−V _th ) ² −(r+x−V _th ) ² =w(2r+2x+w−2V _th ) due to the capacitive coupling of the capacitor 143. This operation corresponds to the above-mentioned equation (6).

Further, the transistor 142 of the circuit 25 becomes non-conductive. At this time, when “V _CDS ”=0V, the potential of the node NC2 becomes w(2r+2x+w−2V _th )−w(2r+w−2V _th )=2wx due to the capacitive coupling of the capacitor 144. This operation corresponds to the above-mentioned equation (7). Therefore, information regarding the product of exposure data (x) and weight (w) can be extracted from the circuit 25.

The above is an example of specific operations of the pixel circuit 10, the circuit 24, and the circuit 25.

<Modified example of imaging device>
An imaging device according to one embodiment of the present invention may have a configuration shown in a block diagram shown in FIG. The imaging device shown in FIG. 7 differs from the imaging device shown in FIG. 1 in that a plurality of pixel circuits 10 share a readout gate line (wiring 128) and an output line (wiring 123). Although FIG. 7 shows an example in which four pixels share wiring such as an output line, the number is not limited as long as it is two or more and can equally divide the total number of pixels.

With this configuration, information on the product of exposure data (x) and weight (w) obtained from a plurality of pixels can be read out all at once. That is, a sum-of-products operation can be performed using a plurality of pixels. Each of the plurality of pixels can output data multiplied by an arbitrary weight. Therefore, by multiplying a portion of a plurality of pixels by a weight having an inverted sign, it is possible to obtain the difference from other pixels without extracting data to the outside.

The imaging device can also be operated according to the timing chart shown in FIG. 6 and its explanation. The derived functions are shown below. Note that when the number of pixels to be read out at once is 4, n is an integer from 1 to 4.

The current read out to the wiring 123 at time T4 is proportional to Σ _n (r−V _th ) ² .

The current read out to the wiring 123 at time T5 is proportional to Σ _n (r+w _n −V _th ) ² .

The current read out to the wiring 123 at time T6 is proportional to Σ _n (r+x _n -V _th ) ² .

The current read out to the wiring 123 at time T7 is proportional to Σ _n (r+x _n +w _n −V _th ) ² .

Then, at the end of time T7, the circuit 25 can obtain Σ _n (x _n +w _n ).

<Light-emitting device and imaging device>
Next, combinations of light emitting devices and photoelectric conversion devices that each pixel can have will be described. 8A to 8C are diagrams illustrating the first pixel 160, the second pixel 170, and the subject 180. The first pixel 160 and the second pixel 170 can be applied to pixels included in the pixel array 21. Note that when one pixel is regarded as a square, the size of one side is 1 mm or less, preferably 100 μm or less.

FIG. 8A shows a configuration in which the first pixel 160 has a photoelectric conversion device 101a, the second pixel 170 has a photoelectric conversion device 101b, and both pixels have a light emitting device 11a. Part of the light emitted from the light emitting device 11a is absorbed by the subject 180, and the light reflected by the subject 180 is received by each pixel. Note that the arrows shown in the figure indicate part of the optical path.

When there are two central wavelengths to be imaged, wavelengths A and B (wavelength A<wavelength B), the light emitting device 11a includes an EL element that emits light with a broad wavelength distribution including wavelengths A and B. Can be used. Here, the absorption edge wavelength of the photoelectric conversion device 101a can be shorter than the wavelength B, and the absorption edge wavelength of the photoelectric conversion device 101b can be greater than or equal to the wavelength B.

As the photoelectric conversion device 101a, a photodiode whose photoelectric conversion layer is made of a semiconductor material whose absorption edge wavelength is near wavelength A can be used. As the photoelectric conversion device 101b, a photodiode whose photoelectric conversion layer is made of a semiconductor material whose absorption edge wavelength is near wavelength B can be used.

Alternatively, the photoelectric conversion layer of both the photoelectric conversion devices 101a and 101b may be formed of a semiconductor material sensitive to a wavelength range including wavelength A and wavelength B. At this time, an optical filter that transmits wavelength A and its vicinity may be provided on the photoelectric conversion device 101a, and an optical filter that transmits wavelength B and its vicinity may be provided on the photoelectric conversion device 101b.

With such a combination, the first pixel 160 can obtain information about light near wavelength A and light having a shorter wavelength. Further, in the second pixel 170, information about light near wavelength B and light having a shorter wavelength can be obtained. That is, by taking the difference between the information obtained at the first pixel 160 and the information obtained at the second pixel 170, data at wavelength B and its vicinity can be extracted.

By using the imaging device shown in FIG. 1, it is possible to output data obtained by multiplying image data acquired at each pixel by a weight. Therefore, by extracting the data to the outside and calculating the difference, only information about wavelength B and its vicinity can be obtained.

Furthermore, if the imaging device shown in FIG. 7 is used, it is possible to obtain only information on the wavelength B and its vicinity by adding appropriate weights to the pixels used in the difference calculation and reading them out all at once.

Note that although the above example uses light of two wavelengths, a configuration may be adopted that uses light of more wavelengths.

FIG. 8B shows a configuration in which the first pixel 160 has a photoelectric conversion device 101a and a light emitting device 11b, and the second pixel 170 has a photoelectric conversion device 101b and a light emitting device 11b. An EL element that emits light having a peak at wavelength A can be used as the light emitting device 11b. An EL element that emits light having a peak at wavelength B can be used as the light emitting device 11c.

In the configuration shown in FIG. 8B, since the wavelength distribution of the light source is not broad, information on light having a peak at wavelength A can be directly acquired by the photoelectric conversion device 101a. Further, information on light having a peak at wavelength B can be directly acquired by the photoelectric conversion device 101b.

FIG. 8C shows a configuration in which the first pixel 160 has a light emitting device 11b, the second pixel 170 has a light emitting device 11c, and both pixels have a photoelectric conversion device 101b. The absorption edge wavelength of the photoelectric conversion device 101b is set to be equal to or greater than the wavelength B, and the first pixel 160 and the second pixel 170 are operated with a time difference (T1, T2). With this operation, at T1, information on light having a peak at wavelength B can be directly acquired by the photoelectric conversion device 101b included in the pixel 170. Furthermore, at T2, information on light having a peak at wavelength A can be directly acquired by the photoelectric conversion device 101b included in the pixel 160.

Note that in the configurations shown in FIGS. 8B and 8C, it is not always necessary to perform a difference calculation, but noise components of unnecessary wavelengths may be reduced by performing a difference calculation.

<Example of pixel modification>
FIG. 9A is a circuit diagram illustrating a pixel circuit 10 and a light emitting device 11 that can be provided in a pixel of an imaging device according to one embodiment of the present invention. The pixel circuit 10 has the same configuration as shown in FIG.

In this pixel, there is no electrical connection between the pixel circuit 10 and the light emitting device 11, so the input potential to the light emitting device 11 and the timing of light emission can be independently controlled. One electrode of the light emitting device 11 is electrically connected to the wiring 130. The wiring 130 has a function of supplying a forward bias to the light emitting device 11 and supplying a potential for causing the light emitting device 11 to emit light. The other electrode of the light emitting device 11 is electrically connected to a reference potential line such as a GND wiring, for example.

FIG. 9B shows a configuration in which one electrode of the light emitting device 11 is electrically connected to the wiring 122. If the reset potential of the nodes FD1 and FD2, the power supply potential supplied to the transistor 105, and the input potential of the light emitting device 11 can be made common, this configuration can be adopted.

Further, as shown in FIG. 9C, a transistor 109 may be added to the configuration of FIG. 9B. One of the source and drain of transistor 109 is electrically connected to one electrode of light emitting device 11 . The other of the source and drain of the transistor 109 is electrically connected to the wiring 122. A gate of the transistor 109 is electrically connected to the wiring 124. With this structure, the light emission period can be limited to only the period when the transistor 102 is conductive, and power consumption can be reduced. The period during which the transistor 102 needs to be conductive is only the reset operation period and the storage operation period for the node FD1, and unnecessary light emission during the read operation period and the like can be suppressed.

In addition, if the reset potentials of the nodes FD1 and FD2 are too high with respect to the appropriate potential input to the light emitting device 11, as shown in FIG. Resistance element 115 may be electrically connected. The resistance element 115 acts as a current limiting resistor, can limit the current flowing through the light emitting device 11, and can improve the reliability of the light emitting device 11. The resistance value of the resistive element 115 may be selected appropriately according to the electrical characteristics of the light emitting device 11.

Note that as shown in FIG. 10B, the transistor 109 shown in FIG. 9C may be operated in place of the resistive element 115. In this structure, the gate of the transistor 109 is electrically connected to the wiring 131. Therefore, by varying the potential of the wiring 131, the illuminance and timing of light emission of the light emitting device 11 can be arbitrarily controlled, and power consumption can be suppressed.

Further, as shown in FIG. 10C, a transistor 109 is provided, the other of the source or drain of the transistor 109 is electrically connected to the wiring 130, and the gate of the transistor 109 is electrically connected to the wiring 124. It may be a configuration. In this configuration, the input potential to the light emitting device 11 is controlled by the wiring 130, and the timing of light emission is controlled by the wiring 124.

Note that although FIGS. 9A to 9C and FIGS. 10A to 10C show configurations in which the cathode of the photoelectric conversion device 101 is electrically connected to the transistor 102, as shown in FIGS. 11A to 11C and FIGS. 12A to 12C, Alternatively, the anode of the photoelectric conversion device 101 may be electrically connected to the transistor 102.

In the configurations shown in FIGS. 11A to 11C and 12A to 12C, one electrode of the photoelectric conversion device 101 is electrically connected to the wiring 122, and the other electrode of the photoelectric conversion device 101 is connected to the source or drain of the transistor 102. electrically connected to one side. Further, the other of the source and drain of the transistor 104 is electrically connected to the wiring 132.

The wiring 132 can function as a power supply line or a reset potential supply line. In the configurations shown in FIGS. 11A to 11C and 12A to 12C, the nodes FD1 and FD2 are reset to a low potential to operate, so the wiring 132 is at a low potential (lower potential than the wiring 122). .

For a description of the light emitting device 11 shown in FIGS. 11A to 11C and FIGS. 12A to 12C and its connection form with peripheral elements, reference can be made to the description of FIGS. 9A to 9C and FIGS. 10A to 10C.

The OS transistor included in the imaging device may have a back gate. FIG. 13A shows a configuration in which the back gate is electrically connected to the front gate, which has the effect of increasing on-current. FIG. 13B shows a configuration in which the back gate is electrically connected to a wiring that can supply a constant potential, and the threshold voltage of the transistor can be controlled.

Alternatively, a configuration may be adopted in which each transistor can perform an appropriate operation, such as by combining FIGS. 13A and 13B. Furthermore, the pixel circuit may include a transistor that is not provided with a back gate. Note that the structure in which a back gate is provided in a transistor can be applied to all the pixel circuits and peripheral circuits shown in this embodiment.

This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

(Embodiment 2)
In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

FIG. 14A illustrates the structure of a pixel included in the imaging device. The pixel can have a layered structure including a layer 510 having the light emitting device 11 and the photoelectric conversion device 101, and a layer 520 having the transistor and the like forming the pixel circuit 10. Note that each layer has a supporting substrate.

As the light emitting device 11 included in the layer 510, a light emitting device (EL element) that uses electroluminescence can be used. An EL element has a layer containing a luminescent compound (EL layer) between a pair of electrodes. When a potential difference greater than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the light-emitting substance contained in the EL layer emits light.

Further, EL elements are classified depending on whether the light emitting material is an organic compound or an inorganic compound, and the former is generally called an organic EL element and the latter an inorganic EL element.

In an organic EL element, by applying a voltage, electrons are injected from one electrode and holes are injected from the other electrode into the EL layer. When these carriers (electrons and holes) recombine, the luminescent organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to this mechanism, such a light emitting device is called a current excitation type light emitting device.

The EL layer can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

Inorganic EL devices are classified into dispersed type inorganic EL devices and thin film type inorganic EL devices depending on their device configurations. A dispersion type inorganic EL device has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. A thin film type inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and the light emission mechanism is localized light emission using inner shell electron transition of metal ions.

FIG. 14B shows the configuration of the light emitting device 11 (EL element). The EL layer 300 can be composed of multiple layers such as a layer 330, a light emitting layer 320, and a layer 340. The layer 330 can include, for example, a layer containing a substance with high electron injection properties (electron injection layer), a layer containing a substance with high electron transport properties (electron transport layer), and the like. The light-emitting layer 320 includes, for example, a light-emitting compound. The layer 340 can include, for example, a layer containing a substance with high hole injection property (hole injection layer) and a layer containing a substance with high hole transport property (hole transport layer).

The EL layer 300 provided between the electrode 311 and the electrode 312 can function as a single light emitting unit. Note that a plurality of light emitting layers may be provided between the layer 330 and the layer 340. Note that by using a light-transmitting conductive film for either the electrode 311 or the electrode 312, the light emission direction is determined.

The light emitting device 11 can emit light of various wavelengths depending on the material forming the EL layer 300. In one embodiment of the present invention, the EL layer 300 is made of a material that emits light having a peak in near-infrared light (wavelengths from 720 to 2500 nm). For example, materials that emit light at wavelengths of 720 nm, 760 nm, 850 nm, 900 nm, 940 nm, and around these wavelengths may be used depending on the purpose.

Note that in one embodiment of the present invention, the EL layer 300 preferably includes an organometallic iridium complex that emits near-infrared light as a light-emitting material (also referred to as a guest material or dopant material). The organometallic iridium complex preferably has a dimethylphenyl skeleton and a quinoxaline skeleton. The organometallic iridium complex is typically bis{4,6-dimethyl-2-[3-(3,5-dimethylphenyl)-2-quinoxalinyl-κN]phenyl-κC}(2, 2′,6,6′-tetramethyl-3,5-heptanedionato-κ ² O,O′)iridium(III) (abbreviation: Ir(dmdpq) ₂ (dpm)), etc. can be used. By using the above organometallic iridium complex, it is possible to provide an imaging device with high quantum efficiency or luminous efficiency.

Further, as the substance (i.e., host material) used to make the organometallic iridium complex into a dispersed state, examples include 2,3-bis(4-diphenylaminophenyl)quinoxaline (abbreviation: TPAQn), an aryl compound such as NPB, In addition to compounds having an amine skeleton, carbazole derivatives such as CBP, 4,4',4''-tris(carbazol-9-yl)triphenylamine (abbreviation: TCTA), and bis[2-(2'-hydroxy) phenyl)pyridinato]zinc (abbreviation: Znpp ₂ ), bis[2-(2-hydroxyphenyl)benzoxazolato]zinc (abbreviation: Zn(BOX) ₂ ), bis(2-methyl-8-quinolinolato) (4 Metal complexes such as -phenylphenolato)aluminum(III) (abbreviation: BAlq) and tris(8-quinolinolato)aluminum(III) (abbreviation: Alq ₃ ) are preferred. Further, a polymer compound such as PVK can also be used.

The material (host material) used to disperse the organometallic iridium complex is N-(1,1'-biphenyl-4-yl)-N-[4-(9-phenyl-9H-). It is preferable to use carbazol-3-yl)phenyl]-9,9-dimethyl-9H-fluoren-2-amine (abbreviation: PCBBiF).

Note that by forming the light-emitting layer 320 containing the above-mentioned organometallic iridium complex (guest material) and the above-mentioned host material, it is possible to obtain near-infrared phosphorescence with high luminous efficiency from the EL layer 300. I can do it.

As the photoelectric conversion device 101 included in the layer 510, a photodiode, a photoconductor, or the like can be used. For example, the photoelectric conversion device 101 can be a stack of a layer 531, a layer 540, and a layer 532, as shown in FIG. 14C.

The photoelectric conversion device 101 shown in FIG. 14C is an example of an organic photoconductive film, and the layers 531 and 532 correspond to electrodes, and one of them has translucency so that light can be introduced into the photoelectric conversion section. The layer 540 corresponds to a photoelectric conversion section and includes a layer 541, a layer 542, and a layer 542.

One of the layers 541 and 543 of the photoelectric conversion section can be a hole transport layer, and the other can be an electron transport layer. Further, the layer 542 can be a photoelectric conversion layer.

As the hole transport layer, for example, molybdenum oxide or the like can be used. As the electron transport layer, for example, fullerenes such as C60 and C70, or derivatives thereof can be used.

As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used. Examples of materials for the photoelectric conversion layer include organic semiconductor materials such as copper (II) phthalocyanine (CuPc) and tetraphenyldibenzoperiflanthene (DBP).

Further, as the photoelectric conversion device 101, a pn junction photodiode formed using single crystal silicon, a pin junction photodiode formed using a thin film such as single crystal silicon, microcrystalline silicon, or polycrystalline silicon is used. It's okay. Single crystal silicon, microcrystalline silicon, and polycrystalline silicon are sensitive to infrared light and are suitable for detecting infrared light.

The layer 520 is mainly provided with elements such as transistors included in the pixel circuit 10. Further, some or all of the transistors included in the peripheral circuit described in Embodiment 1 may be included. It is preferable to use an OS transistor as the transistor.

As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, it is an oxide semiconductor containing indium, and for example, CAAC-OS or CAC-OS, which will be described later, can be used. The atoms that make up the crystal of CAAC-OS are stable, making it suitable for transistors and other devices where reliability is important. Further, since CAC-OS exhibits high mobility characteristics, it is suitable for transistors and the like that are driven at high speed.

Since the energy gap of the semiconductor layer is large, the OS transistor exhibits an extremely low off-current characteristic of several yA/μm (current value per 1 μm of channel width). Further, OS transistors have characteristics different from Si transistors, such as not causing impact ionization, avalanche breakdown, short channel effects, etc., and can form highly reliable circuits with high breakdown voltage. Further, variations in electrical characteristics due to non-uniformity of crystallinity, which is a problem in Si transistors, are less likely to occur in OS transistors.

The semiconductor layer included in the OS transistor is, for example, In--M containing indium, zinc, and M (one or more of metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). - The film can be expressed as a Zn-based oxide. In-M-Zn-based oxides can typically be formed by sputtering. Alternatively, it may be formed using an ALD (atomic layer deposition) method.

The atomic ratio of metal elements in a sputtering target used to form an In-M-Zn-based oxide by sputtering preferably satisfies In≧M and Zn≧M. The atomic ratio of metal elements in such a sputtering target is In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1: 2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1: 7, In:M:Zn=5:1:8 etc. are preferable. Note that the atomic ratio of each of the semiconductor layers to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

As the semiconductor layer, an oxide semiconductor with low carrier density is used. For example, the semiconductor layer has a carrier density of 1×10 ¹⁷ /cm ³ or less, preferably 1×10 ¹⁵ /cm ³ or less, more preferably 1×10 ¹³ /cm ³ or less, more preferably 1×10 ¹¹ /cm ³ or less, more preferably less than 1×10 ¹⁰ /cm ³ , and 1×10 ⁻⁹ /cm ³ or more can be used. Such an oxide semiconductor is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor can be said to have low defect level density and stable characteristics.

Note that the composition is not limited to these, and a material having an appropriate composition may be used depending on the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. In addition, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the carrier density, impurity concentration, defect density, atomic ratio of metal elements and oxygen, interatomic distance, density, etc. of the semiconductor layer be appropriate. .

When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor that constitutes the semiconductor layer, oxygen vacancies increase and the oxide semiconductor becomes n-type. For this reason, the concentration of silicon or carbon (concentration obtained by secondary ion mass spectrometry (SIMS)) in the semiconductor layer is set to 2×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁷ atoms. / ^cm3 or less.

Further, when alkali metals and alkaline earth metals combine with an oxide semiconductor, they may generate carriers, which may increase the off-state current of the transistor. For this reason, the concentration of the alkali metal or alkaline earth metal (concentration obtained by SIMS) in the semiconductor layer is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

Further, when nitrogen is contained in the oxide semiconductor forming the semiconductor layer, electrons as carriers are generated, the carrier density increases, and the semiconductor layer is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, the nitrogen concentration (concentration obtained by SIMS) in the semiconductor layer is preferably 5×10 ¹⁸ atoms/cm ³ or less.

Further, if hydrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, it reacts with oxygen bonded to metal atoms to become water, which may cause oxygen vacancies to be formed in the oxide semiconductor. If a channel formation region in an oxide semiconductor contains oxygen vacancies, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen is inserted into oxygen vacancies function as donors, and electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.

A defect in which hydrogen is present in an oxygen vacancy can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Therefore, in oxide semiconductors, evaluation is sometimes made based on carrier concentration rather than donor concentration. Therefore, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied is sometimes used instead of a donor concentration as a parameter of an oxide semiconductor. That is, the "carrier concentration" described in this specification and the like can sometimes be translated into "donor concentration."

It is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably 5×10 ¹⁸ atoms/cm It is less than ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ . By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be provided.

Further, the semiconductor layer may have a non-single crystal structure, for example. Non-single crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c-axis, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single crystal structures, the amorphous structure has the highest density of defect levels, and the CAAC-OS has the lowest density of defect levels.

For example, an oxide semiconductor film having an amorphous structure has a disordered atomic arrangement and does not have a crystalline component. Alternatively, the oxide film having an amorphous structure has, for example, a completely amorphous structure and does not have a crystal part.

Note that even if the semiconductor layer is a mixed film having two or more of the following: an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. good. The mixed film may have, for example, a single-layer structure or a laminated structure including two or more of the above-mentioned regions.

The structure of a CAC (Cloud-Aligned Composite)-OS, which is one embodiment of a non-single-crystal semiconductor layer, will be described below.

CAC-OS is, for example, a structure of a material in which elements constituting an oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. The mixed state is also called mosaic or patch.

Note that the oxide semiconductor preferably contains at least indium. In particular, it is preferable to include indium and zinc. Also, in addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from these may be included.

For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide may be particularly referred to as CAC-IGZO among CAC-OS) is indium oxide (hereinafter, InO _X1 (X1 is a real number greater than 0), or indium zinc oxide (hereinafter, In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z2 are real numbers greater than 0)), and gallium. oxide (hereinafter referred to as GaO _X3 ( _X3 is a real number larger than ₀ )), or gallium zinc _oxide (hereinafter referred to as Ga ), _the material separates into _a mosaic _- like structure, and the mosaic-like _InO be.

That is, CAC-OS is a complex oxide semiconductor having a configuration in which a region whose main component is GaO _X3 and a region whose main component is In _X2 Zn _Y2 O _Z2 or InO _X1 are mixed. Note that, in this specification, for example, the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. Assume that the In concentration is higher than that in region 2.

Note that IGZO is a common name and may refer to one compound made of In, Ga, Zn, and O. As a typical example, it is expressed as InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _(1+x0) Ga _(1-x0) O ₃ (ZnO) _m0 (-1≦x0≦1, m0 is an arbitrary number) Examples include crystalline compounds.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

On the other hand, CAC-OS relates to the material composition of an oxide semiconductor. CAC-OS is a material composition containing In, Ga, Zn, and O, with some regions observed as nanoparticles containing Ga as the main component and some nanoparticles containing In as the main component. This refers to a configuration in which regions observed in a shape are randomly distributed in a mosaic shape. Therefore, in CAC-OS, crystal structure is a secondary element.

Note that the CAC-OS does not include a stacked structure of two or more types of films with different compositions. For example, a structure consisting of two layers of a film mainly composed of In and a film mainly composed of Ga is not included.

Note that a clear boundary may not be observed between the region where GaO _X3 is the main component and the region where In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component.

In addition, instead of gallium, select from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium. When the CAC-OS contains one or more of the metal elements, the CAC-OS will have a region observed in the form of nanoparticles mainly composed of the metal element and a region mainly composed of In. A configuration in which regions observed in the form of particles are randomly dispersed in a mosaic pattern.

The CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. Furthermore, when forming the CAC-OS by sputtering, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the film-forming gas. good. Further, the lower the flow rate ratio of oxygen gas to the total flow rate of film forming gas during film formation, the better. For example, it is preferable to set the flow rate ratio of oxygen gas to 0% or more and less than 30%, preferably 0% or more and 10% or less. .

CAC-OS has the characteristic that no clear peaks are observed when measured using a θ/2θ scan using the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. have That is, it can be seen from the X-ray diffraction measurement that no orientation in the a-b plane direction or the c-axis direction of the measurement region is observed.

Furthermore, in the electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), CAC-OS has a ring-shaped area with high brightness (ring area) and a ring-shaped area with high brightness. Multiple bright spots are observed in the area. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure with no orientation in the plane direction and the cross-sectional direction.

Furthermore, for example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) reveals that _GaO It can be confirmed that the region and the region whose main component is In _X2 Zn _Y2 O _Z2 or InO _X1 are unevenly distributed and have a mixed structure.

CAC-OS has a structure different from that of IGZO compounds in which metal elements are uniformly distributed, and has different properties from IGZO compounds. In other words, in CAC-OS, a region in which GaO _X3 is the main component and a region in which _InX2 Zn _Y2 O _Z2 or _InO It has a mosaic-like structure.

Here, the region where In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component is a region with higher conductivity than the region where GaO _X3 or the like is the main component. In other words, conductivity as an oxide semiconductor is developed by carriers flowing through _a region where _InX2ZnY2OZ2 or _InOX1 is _the main component. Therefore, by distributing regions containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component in a cloud shape in the oxide semiconductor, high field effect mobility (μ) can be achieved.

On the other hand, a region whose main component is GaO _X3 or the like has higher insulation than a region whose main component is In _X2 Zn _Y2 O _Z2 or InO _X1 . In other words, by distributing regions containing GaO _X3 or the like as a main component in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

Therefore, when CAC-OS is _used in a semiconductor device, _the insulation caused by _{GaO X3} and _the conductivity caused by In On-current (I _on ) and high field-effect mobility (μ) can be achieved.

Furthermore, semiconductor devices using CAC-OS have high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

It is preferable to use a flexible substrate as the support substrate included in the layer 510 and the layer 520. Since the support substrate has flexibility, a flexible imaging device can be configured. For example, it becomes easy to attach the imaging device closely to a part of the living body.

Materials for the flexible support substrate include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, Polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetra Fluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. can be used.

Furthermore, the supporting substrate of the layer 520 may be a semiconductor substrate such as a silicon wafer, a glass substrate, a ceramic substrate, a metal substrate having an insulating surface, or the like. It is preferable that these substrates be processed to be thin enough to have flexibility. Depending on the application, a support substrate that does not have flexibility may be used.

As the supporting substrate of the layer 510, a substrate that is transparent to light of the wavelength to be used can be selected from the above materials.

Note that when a semiconductor substrate such as a silicon wafer is used as the support substrate of the layer 520, a circuit for driving a pixel circuit, an image signal readout circuit, an image processing circuit, and the like can be provided on the semiconductor substrate. Specifically, some or all of the transistors included in the circuits (pixel circuit 10, circuits 22, 23, 28, etc.) described in Embodiment 1 can be provided on the support substrate. With this configuration, the elements constituting the pixel circuit and the peripheral circuits can be distributed over multiple layers, and the elements can be provided overlapping each other or the elements and the peripheral circuits, thereby reducing the area of the imaging device. be able to.

FIG. 15 is a diagram illustrating an example of a cross section of the pixel shown in FIG. 14A. Layer 510 has the EL element shown in FIG. 14B as light emitting device 11. Furthermore, the photoelectric conversion device 101 includes an organic photoconductive film shown in FIG. 14C. The layer 520 includes OS transistors, and in FIG. 15, the transistor 102 connected to the photoelectric conversion device 101 and the transistor 109 connected to the light emitting device 11 are illustrated using the configuration shown in FIG. 9C as an example.

In the light emitting device 11, the electrode 312 corresponds to the reference potential line (GND) shown in FIG. 9C. In the photoelectric conversion device 101, the layer 532 corresponds to a power line (wiring 121).

FIG. 16A shows details of the OS transistor. The OS transistor shown in FIG. 16A has a self-aligned structure in which a source electrode 205 and a drain electrode 206 are formed by providing an insulating layer on a stack of an oxide semiconductor layer and a conductive layer, and providing a trench that reaches the semiconductor layer. be.

The OS transistor can have a structure including a channel formation region, a source region 203, and a drain region 204 formed in the oxide semiconductor layer 207, as well as a gate electrode 201 and a gate insulating film 202. At least a gate insulating film 202 and a gate electrode 201 are provided in the groove. An oxide semiconductor layer 208 may be further provided in the groove.

The OS transistor may have a self-aligned structure in which a source region 203 and a drain region 204 are formed in the semiconductor layer using the gate electrode 201 as a mask, as shown in FIG. 16B.

Alternatively, as shown in FIG. 16C, a non-self-aligned top-gate transistor having a region where the source electrode 205 or the drain electrode 206 and the gate electrode 201 overlap may be used.

Although the transistors 102 and 109 have a structure having a back gate 535, they may have a structure without a back gate. The back gate 535 may be electrically connected to the front gate of a transistor provided oppositely, as shown in the cross-sectional view of the transistor in the channel width direction shown in FIG. 16D. Note that although FIG. 16D shows the transistor in FIG. 16A as an example, the same applies to transistors with other structures. Further, a configuration may be adopted in which a fixed potential different from that of the front gate can be supplied to the back gate 535.

Planarization films 551 and 552 are provided over the transistors 102 and 109. The light emitting device 11 (electrode 311, EL layer 300, electrode 312) and the photoelectric conversion device 101 (layer 531, layer 540, layer 532) are formed on the surface where the uneven portions caused by the transistors and contact portions are flattened by the flattening films 551 and 552. will be provided.

For the electrode 311 and the layer 531, a low-resistance conductive film such as metal can be used. For example, tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni) ), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), alloys thereof, or metal nitrides thereof. .

A light-transmitting conductive film that transmits near-infrared light can be used for the electrode 312 and the layer 532. For example, the electrode 312 and the layer 532 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium A light-transmitting conductive material such as zinc oxide or indium tin oxide added with silicon oxide can be used.

In the pixel configuration shown in FIG. 15, light 601 is emitted to the outside from the light emitting device 11 included in the layer 510, and the reflected light 602 is received by the photoelectric conversion device 101 included in the layer 510.

A protective layer 553 may be provided on the light emitting device 11 and the photoelectric conversion device 101 to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting device 11 and the photoelectric conversion device 101. As the protective layer 553, it is preferable to use an inorganic insulating film such as silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like.

Further, it is preferable that a sealing layer 570 is provided between the protective layer 553 and the substrate 582 for sealing. For the sealing layer 570, in addition to an inert gas such as nitrogen or argon, ultraviolet curing resin or thermosetting resin can be used, such as PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, etc. A resin such as PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Furthermore, the sealing layer 570 may contain a desiccant.

Further, between the protective layer 553 and the substrate 582, it is preferable to provide a light shielding layer 571 at and near the boundary between the light emitting device 11 and the photoelectric conversion device 101. A part of the light emitted from the light emitting device 11 may be scattered or reflected by the sealing layer 570, the protective layer 553, the substrate 582, etc., and may be received by the photoelectric conversion device 101. By providing the light shielding layer 571, it is possible to prevent the photoelectric conversion device 101 from receiving such stray light that does not contain useful information. The light shielding layer 571 is preferably formed of a metal with a high reflectance of light of the wavelength to be used, a resin with a high absorption rate, or the like.

Substrates 581 and 582 are supporting substrates. When flexible substrates are used as the substrates 581 and 582, a layer 591 is preferably provided between the substrate 581 and a region where a transistor or the like is provided. Further, a layer 592 is preferably provided between the substrate 582 and the region where the sealing layer 570 is provided.

It is difficult to directly form structures (such as transistors) that require high formation temperatures and precise alignment on a flexible substrate, so these are first formed on a hard substrate and then transferred to a flexible substrate. It is common to transpose. The layers 591 and 592 are buffer layers for peeling off the structure from the hard substrate, and can be made of a resin such as polyimide that is heat resistant and has a small coefficient of linear expansion. Note that the layer 591 may function as a supporting substrate without providing the substrate 581. Alternatively, the layer 592 may function as a supporting substrate without providing the substrate 582.

This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

(Embodiment 3)
In this embodiment, an example of an electronic device that can use an imaging device according to one embodiment of the present invention will be described.

FIG. 17A1 is an infrared spectroscopy device for analyzing brain function. As shown in FIG. 17A2, it is attached to the human body so as to cover the head. The imaging device 912 of one embodiment of the present invention has flexibility and can be attached to the inner curved surface of the helmet-shaped housing 911. Note that the imaging device 912 may be attached not to the entire inner surface of the housing 911 but only to a necessary portion. Further, the infrared spectrometer can include a data recording memory, a control LSI, a battery, and the like. Data retrieval and power supply can be performed via external interface 913.

This infrared spectrometer detects neural activity in the cerebral cortex by comparing (taking the difference) the absorbance of infrared light, where oxyhemoglobin has an absorption peak, and the absorbance of infrared light, where deoxyhemoglobin has an absorption peak. can do. Since it is possible to know the active areas and intensity of brain activity, it can be used for understanding and researching injuries and diseases. Since the imaging device 912 of one embodiment of the present invention includes a light source and is thin, a thin and lightweight infrared spectroscopic device can be formed.

FIG. 17B1 is an infrared spectroscopy device for analyzing brain functions that has the same basic function as FIG. 17A1 but has a different shape and purpose. The infrared spectrometer has two imaging devices 922 built into a band 921, a battery 923, and a wireless communication unit 924. As shown in FIG. 17B2, the band 921 is attached to a part of the human body's head using its elasticity. Band 921 is made of an elastic body such as resin or metal. Power can be supplied from a battery 923, and data can be transmitted and received via a wireless communication unit 924. The infrared spectroscopy device is small and lightweight, and can be used to detect activity in specific areas of the brain.

FIG. 18A is a blood oximeter. A finger is placed on a detection section 932 provided in a housing 931, and an image is captured by an imaging device 934 disposed directly below the detection section 932. The imaging results are displayed on a display section 933 provided at the top of the housing 931. This blood oxygen concentration meter can calculate the oxygen concentration in the blood from the difference in absorbance between oxyhemoglobin and deoxyhemoglobin with respect to light of two different wavelengths. Since the imaging device 912 of one embodiment of the present invention has a light source and is thin, a thin and lightweight blood oxygen concentration meter can be formed.

FIG. 18B shows a food sorting device, which includes a housing 941, operation buttons 942, a display section 943, a light-shielding hood 944, and the like. By closely contacting the light-shielding hood 944 provided around the light-receiving section to the food to be inspected, such as fruit, and taking an image, it is possible to detect foreign objects, insects, cavities or rot inside the food, etc. Furthermore, an infrared spectrum can be obtained from the difference between a plurality of detected infrared lights, and the sugar content of foodstuffs can also be detected. Food sorting equipment can sort out defective products and grades, and determine the harvest period. Since the imaging device 945 of one embodiment of the present invention provided in the light receiving portion does not require a light source, a food sorting device that is thin, lightweight, and highly portable can be formed at low cost.

This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

10: pixel circuit, 11: light emitting device, 11a: light emitting device, 11b: light emitting device, 11c: light emitting device, 21: pixel array, 22: circuit, 23: circuit, 24: circuit, 25: circuit, 26: circuit, 27: circuit, 28: circuit, 29: current source circuit, 30: memory circuit, 101: photoelectric conversion device, 101a: photoelectric conversion device, 101b: photoelectric conversion device, 102: transistor, 103: transistor, 104: transistor, 105 : Transistor, 106: Transistor, 107: Capacitor, 108: Capacitor, 109: Transistor, 110: Transistor, 111: Transistor, 112: Transistor, 113: Transistor, 114: Capacitor, 115: Resistance element, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 127: Wiring, 128: Wiring, 130: Wiring, 131: Wiring, 132: Wiring, 133: Wiring, 134: Wiring, 135: Wiring, 136: Wiring, 137: Wiring, 138: Wiring, 141: Transistor, 142: Transistor, 143: Capacitor, 144: Capacitor, 151: Wiring, 152: Wiring, 160: Pixel, 170: Pixel, 180: Subject, 201: Gate electrode, 202: Gate insulating film, 203: Source region, 204: Drain region, 205: Source electrode, 206: Drain electrode, 207: Oxide semiconductor layer, 208: Oxide semiconductor layer, 300: EL layer, 311: electrode, 312: electrode, 320: light emitting layer, 330: layer, 340: layer, 510: layer, 520: layer, 531: layer, 532: layer, 535: back gate, 540: layer, 541: layer, 542: layer, 543: layer, 551: planarizing film, 552: planarizing film, 553: protective layer, 570: sealing layer, 571: light shielding layer, 581: substrate, 582: substrate, 591: layer, 592: layer, 601: Light, 602: Reflected light 911: Housing, 912: Imaging device, 913: External interface, 921: Band, 922: Imaging device, 923: Battery, 924: Wireless communication unit, 931: Housing, 932: Detection section, 933: display section, 934: imaging device, 941: housing, 942: operation button, 943: display section, 944: light-shielding hood, 945: imaging device,

Claims (2)

comprising first to ninth transistors, a photoelectric conversion device, and a first capacitor,
One of the source or drain of the first transistor is electrically connected to one electrode of the photoelectric conversion device,
The other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor,
The other of the source or drain of the second transistor is electrically connected to the gate of the fourth transistor,
One of the source or drain of the third transistor is electrically connected to the gate of the fourth transistor,
The other of the source or drain of the third transistor is electrically connected to the first wiring,
One of the source or drain of the fourth transistor is electrically connected to one of the source or drain of the fifth transistor,
The other of the source or drain of the fourth transistor is electrically connected to the first wiring,
The other of the source or drain of the fifth transistor is electrically connected to a second wiring,
One of the source or drain of the sixth transistor is electrically connected to the gate of the seventh transistor,
The other of the source or drain of the sixth transistor is electrically connected to a third wiring,
One of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the eighth transistor,
The other of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the ninth transistor,
The other of the source or drain of the eighth transistor is electrically connected to a fourth wiring,
The other of the source or drain of the ninth transistor is electrically connected to a fifth wiring,
one electrode of the first capacitor is electrically connected to the gate of the fourth transistor,
the other electrode of the first capacitor is electrically connected to the other of the source or drain of the seventh transistor;
Semiconductor equipment. In claim 1,
having a second capacitor and a third capacitor;
one electrode of the second capacitor is electrically connected to the other of the source or drain of the first transistor,
one electrode of the third capacitor is electrically connected to the gate of the seventh transistor;
Semiconductor equipment.

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