JP2024002645A - Wiring board and method for manufacturing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the characteristics of wiring boards and the efficiency of wiring board manufacturing.

SOLUTION: A wiring board of the embodiment includes an insulating layer 31 having a first surface 31a, and a conductor layer 1 having a portion formed over the first surface 31a of the insulating layer 31. The insulating layer 31 has a void 311 opening on the first surface 31a. The conductor layer 1 includes: a first conductor pattern 11 formed entirely over the first surface 31a; and a second conductor pattern 12 having a portion formed inside the void 311 and not overlapping the first conductor pattern 11 in plan view, wherein a thickness of the second conductor pattern 12 is greater than a thickness of the first conductor pattern 11.

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2024,JPO&INPIT

Description

The present invention relates to a wiring board and a method for manufacturing a wiring board.

Patent Document 1 discloses a circuit board in which a circuit layer is formed by a metal layer filling an opening provided in a dielectric layer, and a method for manufacturing the same.

Japanese Patent Application Publication No. 2007-221089

In the circuit board disclosed in Patent Document 1, all circuit patterns included in the circuit layer are formed within openings provided in the dielectric layer. In the circuit board of Patent Document 1, each circuit pattern may not have the desired thickness or thickness uniformity. Therefore, desired electrical characteristics may not be obtained in the circuit board. Further, in the method for manufacturing a circuit board disclosed in Patent Document 1, the efficiency of forming a circuit pattern may be low.

The wiring board of the present invention includes a first insulating layer having a first surface and a second surface opposite to the first surface, and a portion of the first insulating layer formed on the first surface. A conductor layer. The first insulating layer has a gap opening on the first surface, and the conductor layer includes a first conductor pattern formed entirely on the first surface and an inside of the gap. a second conductor pattern having a portion formed in a shape that does not overlap with the first conductor pattern in plan view, the thickness of the second conductor pattern being greater than the thickness of the first conductor pattern. .

The method for manufacturing a wiring board of the present invention includes preparing a first insulating layer, and a conductor layer having a portion located on the surface of the first insulating layer and including a first conductor pattern and a second conductor pattern. It includes forming and. Forming the conductor layer includes providing a metal layer covering the surface of the first insulating layer, and forming the first conductor pattern on the surface by partially removing the metal layer. forming a void in the first insulating layer that opens to the surface of the first insulating layer; and filling the void with a conductive film including a plating film, thereby increasing the conductivity in the void. The method includes forming the second conductor pattern including a portion made of a film to have a thickness greater than that of the first conductor pattern.

According to embodiments of the present invention, good electrical characteristics may be obtained in a wiring board. Further, it is considered that a wiring board having such good electrical characteristics can be efficiently manufactured.

FIG. 1 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention. FIG. 2 is a plan view partially showing an example of one surface of a core substrate in the wiring board of FIG. 1; FIG. 2 is a plan view partially showing an example of the other surface of the core substrate in the wiring board of FIG. 1; FIG. 3 is a cross-sectional view showing a modified example of the wiring board according to the embodiment. FIG. 3 is a cross-sectional view showing a modified example of the wiring board according to the embodiment. FIG. 3 is a cross-sectional view showing a part of another example of the core board in the wiring board of one embodiment. FIG. 3 is a cross-sectional view showing another example of the core board in the wiring board of one embodiment. 1 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. 1 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. 1 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. 1 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. FIG. 1 is a plan view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. 1 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. FIG. 1 is a plan view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention. 1 is a cross-sectional view showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention.

A wiring board of one embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a wiring board 100, which is an example of a wiring board according to an embodiment. 2A and 2B respectively show a plan view (top view) from one surface 10a side and a plan view (bottom view) from the other surface 10b side of the core substrate 10 included in the wiring board 100 of FIG. has been done. Note that the wiring board 100 is only an example of the wiring board of this embodiment. The laminated structure of the wiring board of this embodiment and the number of conductive layers and insulating layers are not limited to the laminated structure of the wiring board 100 in FIG. 1 and the number of conductive layers and insulating layers included in the wiring board 100. . In addition, in each of the drawings referred to in the following description, certain parts may be enlarged to make it easier to understand the disclosed embodiments, and each component may differ in size and length. They may not be drawn to exact proportions.

As shown in FIG. 1, the wiring board 100 of this embodiment includes a core board layer 50 consisting of the core board 10, a buildup layer 51, a buildup layer 52, and a solder resist layer 61 covering the buildup layer 51. and a solder resist layer 62 covering the buildup layer 52. The core board 10 has one surface 10a and the other surface 10b, which are two surfaces orthogonal to the thickness direction of the wiring board 100. The buildup layer 51 is laminated on one surface 10a of the core substrate 10, and the buildup layer 52 is laminated on the other surface 10b of the core substrate 10. Each of the buildup layers 51 and 52 is one or more sets (two sets in the example of FIG. 1) that are alternately laminated on the surface of the core substrate layer 50 (one side 10a or the other side 10b of the core substrate 10). It is composed of a conductor layer 5a and an insulating layer 5b. A via conductor 5c is formed in each buildup layer, penetrating the insulating layer 5b and connected to the conductor layer 5a. The core board 10 in the example of FIG. 1 is located at the center layer of a hierarchical structure of an insulating layer and a conductor layer that the wiring board 100 has. The core substrate 10 provides rigidity to the wiring board 100 and supports the buildup layer 51 and the buildup layer 52 during manufacturing and use of the wiring board 100.

The core substrate 10 includes a core layer 30, an insulating layer 31 (first insulating layer), an insulating layer 32 (second insulating layer), a conductor layer 1 (first conductor layer), and a conductor layer 2 (second conductor layer). layer), an insulating layer 33 and an insulating layer 34. The core layer 30, the insulating layers 31 to 34, the conductor layer 1, and the conductor layer 2 each constitute a part of the core substrate layer 50. The core layer 30 is an insulating layer formed of an insulating material like the insulating layer 31 and the like. However, since the core layer 30 is located at the center of the core substrate 10 and the wiring board 100 in the thickness direction of the wiring board 100, it is particularly referred to as a "core layer."

Furthermore, in the description of the method of this embodiment, the side of the wiring board 100 that is far from the core layer 30 in the thickness direction is also referred to as the "outside", "upper side", "upper", or simply "upper". On the other hand, the side closer to the core layer 30 is also referred to as "inner", "lower", or "lower", or simply "lower". Furthermore, in each conductor layer, the conductor pattern included in each conductor layer, and each insulating layer, the surface facing the opposite side to the core layer 30 is also referred to as the "upper surface", and the surface facing the core layer 30 side is also referred to as the "lower surface". It is called. Further, the thickness direction of the wiring board 100 is also referred to as the "Z direction."

The core board 10 further includes through-hole conductors 4 that penetrate the entire core board 10 in the thickness direction of the wiring board 100. That is, the through-hole conductor 4 penetrates the core layer 30, the insulating layers 31 to 34, the conductor layer 1, and the conductor layer 2. The conductor layer 5a in the buildup layer 51 and the conductor layer 5a in the buildup layer 52 are electrically connected by the through-hole conductor 4. In the wiring board 100, the core board 10 is a laminate made up of insulating layers (including the core layer 30) and conductor layers, which are penetrated by the through-hole conductors 4.

The core layer 30 has one surface 30a, which is the surface on the one surface 10a side of the core substrate 10, and the other surface 30b, which is the surface on the opposite side to the one surface 30a. The insulating layer 31 is laminated on one surface 30a of the core layer 30. The insulating layer 31 has a first surface 31a that is a surface on the one side 10a side of the core substrate 10, and a second surface 31b that is a surface on the opposite side to the first surface 31a and is a surface on the core layer 30 side. are doing. The insulating layer 31 has a void 311 open to its first surface 31a. In the example of FIG. 1, the void 311 penetrates the insulating layer 31 and communicates with a recess 30c provided on one surface 30a of the core layer 30.

The insulating layer 32 is laminated on the first surface 31a of the insulating layer 31. A surface 32a of the insulating layer 32 facing in the opposite direction to the insulating layer 31, a surface (top surface) of the conductor layer 1 facing the opposite direction to the core layer 30, and a surface of the through-hole conductor 4 on the insulating layer 31 and insulating layer 32 sides. One surface 10a of the core substrate 10 is constituted by the end surface 4a.

The insulating layer 33 is laminated on the other surface 30b of the core layer 30, and the insulating layer 34 is laminated on the insulating layer 33. In the example of FIG. 1, the conductor layer 2 is formed entirely on the insulating layer 33. The insulating layer 34 is provided on the surface of the insulating layer 33 that is not covered with the conductor layer 2. The other surface 10b of the core substrate 10 is constituted by the surfaces of the conductor layer 2 and the insulating layer 34 facing in the direction opposite to the core layer 30, and the end surface 4b of the through-hole conductor 4 on the insulating layer 34 side. The surface of the conductor layer 2, the surface of the insulating layer 34, and the end surface 4b of the through-hole conductor 4, which respectively constitute the other surface 10b of the core substrate 10, are located on substantially the same plane. That is, the other surface 10b of the core substrate 10 is substantially flat.

In addition, in this disclosure, two or more surfaces (for example, "front surface," "end surface," "upper surface," or "lower surface," etc.) "located on the same plane" refers to the modulus between those two or more surfaces. This means that the difference in position in the linear direction is 3 μm or less.

The conductor layer 1 has a portion formed on the first surface 31a of the insulating layer 31 and a portion formed inside the insulating layer 31. The conductor layer 1 may include any conductor pattern, but includes at least a first conductor pattern 11 and a second conductor pattern 12 formed in a region that does not overlap with the first conductor pattern 11 in plan view. . Note that in the wiring board of the embodiment, each conductor layer may include conductor patterns that at least partially overlap each other in a side view. In other words, a plurality of conductor patterns having mutually overlapping portions in side view may belong to the same conductor layer. As shown in FIG. 1, the first conductor pattern 11 and the second conductor pattern 12 each overlap with each other in a side view (for example, in a side view from a viewpoint located on the right or left side of the wiring board 100 in FIG. 1). have. Therefore, the first conductor pattern 11 and the second conductor pattern 12 belong to the conductor layer 1, which is a single conductor layer. Note that "planar view" means viewing the wiring board of the embodiment from a line of sight parallel to its thickness direction. Moreover, "side view" means viewing the wiring board of the embodiment toward the side with a line of sight perpendicular to the thickness direction of the wiring board of the embodiment.

The first conductor pattern 11 is formed entirely on the first surface 31a of the insulating layer 31. Therefore, the side surfaces of the first conductor pattern 11 are covered with the insulating layer 32 laminated on the first surface 31a of the insulating layer 31. On the other hand, a portion of the second conductor pattern 12 in the thickness direction is formed inside the gap 311 that the insulating layer 31 has. That is, the second conductor pattern 12 includes a portion formed inside the void 311. In the example of FIG. 1, the second conductor pattern 12 protrudes from the first surface 31a of the insulating layer 31. A portion of the second conductor pattern 12 that protrudes from the first surface 31a of the insulating layer 31 overlaps with the first conductor pattern 11 in a side view. In this embodiment, the thickness of the second conductor pattern 12 is greater than the thickness of the first conductor pattern 11.

In this embodiment, as described above, the second conductor pattern 12 belonging to the conductor layer 1 is thicker than the first conductor pattern 11 also belonging to the conductor layer 1. That is, a plurality of conductor patterns having different thicknesses are mixed in the conductor layer 1, which is a single conductor layer. Therefore, a conductive path that is desired to be formed with a relatively thick conductor pattern can be mixed with conductors other than such a conductive path in the conductor layer 1. In particular, wiring patterns that require both narrow wiring width and low conductor resistance can be mixed with conductor patterns other than such wiring patterns.

For example, the second conductor pattern 12 is formed as a wiring pattern that is desired to be composed of thick conductive paths in order to obtain low conductor resistance. In the wiring board of the embodiment, the second conductor pattern 12 may be a signal line. Signal lines may propagate electrical signals that change potential over time. The conductor resistance is small, so a signal line with a small voltage drop may be obtained. Further, by having a small conductor resistance, a desired characteristic impedance can be obtained, and as a result, a signal line with low reflection and attenuation and excellent in transmission of high-frequency signals can be obtained.

On the other hand, in the case of a conductor pattern having a large planar area, for example, a so-called solid pattern, which is a plate-shaped conductor pattern extending in an arbitrary direction so as to occupy a predetermined area, a large thickness may not necessarily be desirable. For example, in the case of a conductor pattern having a large planar area, it may be difficult to obtain uniformity in thickness as the conductor pattern becomes thicker. If uniformity in thickness is not achieved in a conductor pattern with a large planar area that can occupy a large area of the wiring board in plan view, the flatness of the surface of the wiring board may be impaired. Conversely, with a conductor pattern having a large planar area, relatively low conductor resistance is likely to be obtained even if the thickness is not large. Therefore, for example, a conductor pattern having such a relatively large planar area is realized by the first conductor pattern 11. The first conductor pattern 11 may be a power supply pattern or a ground pattern. When the wiring board is used, the power supply pattern and the ground pattern are considered to have a power supply potential or a ground potential when the power supply potential or ground potential of an electrical device in which the wiring board is used is applied. It is considered that such a power supply pattern or ground pattern is preferably realized by a so-called solid pattern with a large planar area in order to obtain a stable potential.

In this way, in this embodiment, since conductor patterns having different thicknesses are mixed in one conductor layer, each conductor pattern has desired electrical characteristics and/or physical (shape) characteristics. There are things you can get. For example, since there is a high degree of freedom in the thickness of the conductor pattern, a wiring pattern having the same width and thickness as the wiring pattern arranged in the buildup layer 51 may be arranged in the conductor layer 1 in some cases. That is, wiring patterns having the same characteristic impedance may be arranged on both the buildup layer 51 and the core substrate layer 50. Being able to arrange such a wiring pattern is particularly beneficial when a small portion of the wiring pattern that functions as a signal line cannot be placed on a conductor layer within a buildup layer such as the buildup layer 51. Sometimes. That is, according to the present embodiment, it is possible to avoid providing individual conductor layers for each conductor pattern having different thicknesses, and therefore, an increase in thickness and cost due to an increase in the number of layers of the wiring board can be avoided. This may contribute to making the wiring board thinner and lower in cost.

In the example of FIG. 1, the second conductor pattern 12 protruding from the first surface 31a of the insulating layer 31 penetrates the insulating layer 32. One surface 12a of the second conductor pattern 12 facing in the same direction as the one surface 10a of the core substrate 10 is exposed on the surface 10a. The side surface of the portion of the second conductor pattern 12 protruding from the first surface 31 a of the insulating layer 31 is covered with an insulating layer 32 . Further, in the example of FIG. 1, the second conductor pattern 12 penetrates through the insulating layer 31 and further penetrates into the core layer 30. That is, the end of the second conductor pattern 12 on the second surface 31b side of the insulating layer 31 protrudes from the second surface 31b of the insulating layer 31 and is embedded in the core layer 30. That is, a portion of the second conductor pattern 12 fills a recess 30c provided on one surface 30a of the core layer 30.

The insulating layers 31 to 34 and the insulating layer 5b are each mainly formed of any resin having appropriate insulating properties. The insulating layers 31 to 34 and the insulating layer 5b may each contain, for example, a thermosetting resin such as an epoxy resin, a bismaleimide triazine resin (BT resin), and a phenol resin. Each of these insulating layers may contain a thermoplastic resin such as a fluororesin, a liquid crystal polymer (LCP), a fluorinated ethylene (PTFE) resin, a polyester (PE) resin, and a modified polyimide (MPI) resin. Each of these insulating layers may further contain a filler (not shown) made of particles of silicon dioxide, alumina, or the like. Although not shown, each of these insulating layers may further include a reinforcing material made of, for example, glass fiber. However, in terms of ease of forming the second conductor pattern 12, the insulating layer 31 and the insulating layer 32 that do not contain reinforcing material may be preferable.

On the other hand, in the example of FIG. 1, the core layer 30 is made of a glass substrate mainly made of glass. Therefore, the core substrate layer 50 includes a glass substrate, and the insulating layer 31 and the insulating layer 33 are laminated on the glass substrate constituting the core layer 30. Since the core substrate layer 50 includes a glass substrate generally made of glass having high rigidity, it is considered that the wiring board 100 is unlikely to warp. Examples of the glass forming the core layer 30 include soda lime glass, alkali-free glass, quartz glass, and borosilicate glass. Note that the core layer 30 is not necessarily made of a glass substrate, and may be made of an insulating resin as described later.

The solder resist layers 61 and 62 are made of any insulating resin such as photosensitive epoxy resin or polyimide resin. Openings 63 are formed in each of the solder resist layers 61 and 62 to expose a portion of the conductor layer 5a.

As described above, the conductor layer 1 includes any conductor pattern including at least the first conductor pattern 11 and the second conductor pattern 12, and the conductor layer 2 and each conductor layer 5a also include any conductor pattern. . Each of these conductor layers, through-hole conductor 4, and via conductor 5c are formed of any metal having appropriate conductivity, such as copper or nickel. In the example of FIG. 1, the first conductor pattern 11 of the conductor layer 1 has a single layer structure, and the second conductor pattern 12 has a multilayer structure consisting of two layers. In the example of FIG. 1, the conductor layer 2 has a single-layer structure like the first conductor pattern 11, and the through-hole conductor 4 has a multilayer structure consisting of two layers like the second conductor pattern 12. .

In the example of FIG. 1, the first conductor pattern 11 of the conductor layer 1 and the conductor layer 2 are made of metal foil. On the other hand, the second conductor pattern 12 having a multilayer structure includes a first metal film 121 and a second metal film 122. The first metal film 121 is interposed between the second metal film 122 and the insulating layer 31, and the side and bottom surfaces of the second metal film 122 (the second surface 31b of the insulating layer 31 in the second metal film 122) surfaces facing in the same direction). That is, the side surfaces of each second conductor pattern 12 and the bottom surface of each second conductor pattern 12 facing in the same direction as the second surface 31b of the insulating layer 31 are constituted by the first metal film 121.

The first metal film 121 may be, for example, an electroless plating film or a sputtering film. The second metal film 122 is, for example, an electroplated film. The second metal film 122 may be formed, for example, by electroplating using the first metal film 121 as a power supply layer. In this way, in the wiring board of the embodiment, the first conductor pattern 11 may include metal foil. On the other hand, the second conductor pattern 12 may include a plating film without including the metal foil. Furthermore, the second conductor pattern 12 may include an electrolytic plated film (second metal film 122) and a metal film (first metal film 121) interposed between the electrolytic plated film and the insulating layer 31. If the first conductor pattern 11 has less uneven thickness and the second conductor pattern 12 is thicker than the first conductor pattern 11, it may be easier to form the second conductor pattern 12.

In the example of FIG. 1, the through-hole conductor 4 is also composed of a first metal film 121 and a second metal film 122. The first metal film 121 forming the through-hole conductor 4 covers the side surface of the second metal film 122 forming the through-hole conductor 4. The first metal film 121 constitutes the side surface of the through-hole conductor 4 . In the example of FIG. 1, the through-hole conductor 4 is formed in a through-hole 10c penetrating the core substrate 10. The through hole 10c is filled with first and second metal films 121 and 122 that constitute the through hole conductor 4.

Further, in the example of FIG. 1, each conductor layer 5a and each via conductor 5c also have a multilayer structure consisting of two layers. Each conductor layer 5a and each via conductor 5c include a metal film 5aa and a metal film 5ab, respectively. I'm here. A metal film 5ab is formed on the metal film 5aa. The metal film 5aa may be, for example, an electroless plating film or a sputtering film like the first metal film 121, and the metal film 5ab may be an electrolytic plating film formed using the metal film 5aa as a power supply layer, for example. .

The through-hole conductor 4 shown in FIG. 1, which penetrates the entire core substrate 10, protrudes from the first surface 31a of the insulating layer 31 and penetrates the insulating layer 32 at the end on the end surface 4a side. Further, the through-hole conductor 4a protrudes from the surface (upper surface) of the insulating layer 33 on the side opposite to the core layer 30 side at the end portion on the end surface 4b side and penetrates the insulating layer 34. The side surfaces of the through-hole conductor 4 that protrude from the first surface 31a of the insulating layer 31 are covered with an insulating layer 32, and the side surfaces of the through-hole conductor 4 that protrude from the top surface of the insulating layer 33 are covered with an insulating layer 32. It is covered by 34.

In the example of FIG. 1, the through-hole conductor 4 protrudes from the first surface 31a of the insulating layer 31, but penetrates the insulating layer 32 without contacting the conductor layer 1. That is, the through-hole conductor 4 does not have a so-called through-hole land, which is provided in a general through-hole conductor, on the end surface 4a side. The through-hole conductor 4 in the example of FIG. 1 is a so-called landless through-hole at the end on the insulating layer 31 and conductor layer 1 side. Therefore, a conductor pattern that should be placed electrically apart from the through-hole conductor 4 in the conductor layer 1 may be formed close to the through-hole conductor 4 . Higher wiring density in the conductor layer 1 and miniaturization of the wiring board 100 may be promoted.

On the other hand, in the example of FIG. 1, the end of the through-hole conductor 4 on the side opposite to the insulating layer 31 and the conductor layer 1 is in contact with the conductor layer 2. It is considered that the conductor layer 2 and the conductor such as the conductor layer 5a in the buildup layer 51 are electrically connected via the through-hole conductor 4 through a short path.

The through-hole conductor 4 in the example of FIG. 1 has a shape that tapers from each of the end surfaces 4a and 4b toward the center of the through-hole conductor 4 in the Z direction, and has a constriction at the center in the Z direction. are doing. Note that the through-hole conductor 4 may have a columnar shape having a substantially constant width from the end surface 4a to the end surface 4b, for example, instead of having a shape whose width changes in the Z direction as in the example of FIG.

In the example of FIG. 1, the surface 11a of the first conductor pattern 11 and the surface 12a of the second conductor pattern 12 are located on the same plane. Note that the surface 11a is a surface of the first conductor pattern 11 facing in the opposite direction to the first surface 31a of the insulating layer 31. The surface 12a is a surface of the second conductor pattern 12 that faces in the same direction as the surface 11a of the first conductor pattern 11, the end surface 4a of the through-hole conductor 4, and the surface 32a of the insulating layer 32. Surface 11a and surface 12a, each of which is the upper surface of conductor layer 1, constitute a part of one surface 10a of core substrate 10. Since the surface 11a and the surface 12a are located on the same plane, one surface 10a of the core substrate 10 tends to be flat, and the surface of the wiring board 100 also tends to be flat.

In the example of FIG. 1, the end surface 4a of the two end surfaces 4a and 4b of the through-hole conductor 4 on the first surface 31a side of the insulating layer 31, the surface 11a of the first conductor pattern 11, and the second conductor pattern 12 are located on the same plane. As described above, the end surface 4a of the through-hole conductor 4 also constitutes a part of the one surface 10a of the core substrate 10. Since the end surface 4a and the surfaces 11a and 12a are located on the same plane, one surface 10a of the core substrate 10 tends to become even more flat, and the surface of the wiring board 100 also tends to become even more flat.

Furthermore, in the example of FIG. 1, the surface 32a of the insulating layer 32 is located on the same plane as the end surface 4a of the through-hole conductor 4, the surface 11a of the first conductor pattern 11, and the surface 12a of the second conductor pattern 12. There is. As described above, the surface 32a of the insulating layer 32 also constitutes a part of the surface 10a of the core substrate 10. Since the surface 32a of the insulating layer 32, the end surface 4a, and the surfaces 11a and 12a are located on the same plane, one surface 10a of the core substrate 10 tends to become even more flat, and the surface of the wiring board 100 also becomes even more flat. easy to become

As shown in FIG. 2A, the first conductor pattern 11 and the second conductor pattern 12 of the conductor layer 1, the through-hole conductor 4, and the insulating layer 32 are exposed on one surface 10a of the core substrate 10. Regarding the second conductor pattern 12, the first metal film 121 and the second metal film 122 constituting the second conductor pattern 12 are exposed, and regarding the through-hole conductor 4, the first metal film constituting the through-hole conductor 4 is exposed. The film 121 and the second metal film 122 are exposed. The first conductor pattern 11 in the example of FIG. 2A is spaced apart from the second conductor pattern 12 and the through-hole conductor 4.

In the example of FIG. 2A, the three second conductor patterns 12 extend along a predetermined direction (Y direction indicated by the symbol Y in the example of FIG. 2A) parallel to one surface 10a of the core substrate 10. The rightmost second conductor pattern 12 among the three second conductor patterns 12 includes a conductor pad 123 . The conductor pad 123 is connected to an interlayer connection conductor such as the via conductor 5c illustrated in FIG. 1, for example. The conductor pad 12 and a conductor such as the conductor layer 5a in the buildup layer 51 are electrically connected via the interlayer connection conductor. In this way, the second conductor pattern 12 may include a conductor pad (a so-called via conductor receiving pad) that is in contact with a connection conductor that connects the conductor layer 1 and a conductor layer other than the conductor layer 1.

As described above, a signal line for propagating an electric signal may be formed as the second conductor pattern 12, and a conductor pattern with a large planar area, such as a so-called solid pattern, may be formed as the first conductor pattern 11. Therefore, the first conductor pattern 11 as a whole may have an area that is five times or more the area of the entire second conductor pattern 12 in plan view. In other words, the entire area of the second conductor pattern 12 in plan view may be 20% or less of the entire area of the first conductor pattern 11 in plan view. Further, the entire area of the second conductor pattern 12 in plan view may be 10% or less of the entire area of the first conductor pattern 11 in plan view. By mixing the required minimum second conductor pattern 12 with the first conductor pattern 11, the conductor layer 1 may be formed efficiently.

As shown in FIG. 2B, the conductor pattern 21 of the conductor layer 2, the through-hole conductor 4, and the insulating layer 34 are exposed on the other surface 10b of the core substrate 10. Also on the other surface 10b, the first metal film 121 and the second metal film 122 constituting the through-hole conductor 4 are exposed. In the example of FIG. 2B, the left conductor pattern 21 of the two conductor patterns 21 is spaced apart from the through-hole conductor 4, and an insulating layer 34 is interposed between this conductor pattern 21 and the through-hole conductor 4. ing. On the other hand, the right conductor pattern 21 is in contact with the through-hole conductor 4, and the conductor pattern 21 and the through-hole conductor 4 are electrically connected.

3A and 3B respectively show a wiring board 101 and a wiring board 102, which are modified examples of the wiring board 100 of this embodiment. Further, FIGS. 4 and 5 respectively show a core substrate 10α and a core substrate 10β, which are modified examples of the core substrate 10 in the wiring board 100 of this embodiment. Note that FIG. 4 only partially shows the vicinity of one surface 10a of the core substrate 10β. Modifications shown in each of these drawings will be explained below. Note that in FIGS. 3A, 3B, 4, and 5, the same components as those included in the wiring board 100 and core board 10 in FIG. The same reference numerals will be given or the reference numerals will be omitted as appropriate, and repeated explanations of these similar components will be omitted.

In the modified wiring board 101 shown in FIG. 3A, the first conductor pattern 11 of the conductor layer 1 and the conductor layer 2 have a multilayer structure consisting of two layers. The first conductor pattern 11 and the conductor layer 2 of the wiring board 101 include a first metal film 111 and a second metal film 112 formed on the first metal film 111. The first metal film 111 may be, for example, an electroless plating film or a sputtering film. Further, the second metal film 112 is, for example, an electroplated film. The second metal film 112 may be formed, for example, by electrolytic plating using the first metal film 111 as a power supply layer. As described above, in the wiring board of the embodiment, the first conductor pattern 11 and the conductor layer 2 may have a multilayer structure, and the first conductor pattern 11 and the conductor layer 2 may have a multilayer structure, and the first metal film 11 ) and an electroplated film (second metal film 112).

In the wiring board 101 shown in FIG. 3A, each conductor layer 5a in each of the buildup layer 51 and the buildup layer 52 is formed in a recess 5ba formed on the upper surface of each insulating layer 5b. Each conductor layer 5a is embedded in an insulating layer 5b below each conductor layer 5a. Each conductor layer 5a of the wiring board 101 includes a metal film 5aa and a metal film 5ab, similar to the conductor layer 5a in the example of FIG. However, in each conductor pattern 5ac included in the conductor layer 5a of the wiring board 101, the metal film 5aa is interposed between the metal film 5ab and the insulating layer 5b, and the side and bottom surfaces of the metal film 5ab (metal film 5ab (the surface facing the core substrate 10 side). The side surfaces of the conductor pattern 5ac and the bottom surface of the conductor pattern 5ac facing the core substrate 10 are formed of a metal film 5aa. In this way, in the wiring board of the embodiment, each conductor layer constituting the buildup layer, such as the conductor layer 5a, may be embedded in the insulating layer below each conductor layer. In a buildup layer such as buildup layer 51, a conductor pattern such as conductor pattern 5ac may be arranged more finely.

In the wiring board 102 of the modified example shown in FIG. 3B, the buildup layer 51 and the buildup layer 52 each include a conductor layer 5d including conductor patterns having different thicknesses, similar to the conductor layer 1 in the core board 10. I'm here. An insulating layer 5ea is laminated on each of the one surface 10a and the other surface 10b of the core substrate 10, and an insulating layer 5eb is further laminated on the upper surface of the insulating layer 5ea. The insulating layer 5ea and the insulating layer 5eb may be formed using the same material as the insulating layer 31 and the insulating layer 32 in the core substrate 10, respectively.

The conductor layer 5d includes a conductor pattern 5da and a conductor pattern 5db thicker than the conductor pattern 5da. The conductive pattern 5da is formed entirely on the upper surface of the insulating layer 5ea, and its side surfaces are covered with the insulating layer 5eb. The upper surface of the conductor pattern 5da is exposed on the upper surface of the insulating layer 5eb and is located on the same plane as the upper surface of the insulating layer 5eb. Conductive pattern 5db has a portion formed inside a recess formed on the upper surface of insulating layer 5ea and a portion penetrating through insulating layer 5eb. That is, the conductor pattern 5db partially fills the recess of the insulating layer 5ea and protrudes from the upper surface of the insulating layer 5ea. The upper surface of conductor pattern 5db is exposed on the upper surface of insulating layer 5eb and is located on the same plane as the upper surface of insulating layer 5eb.

The conductor pattern 5da has a single layer structure made of, for example, metal foil, and the conductor pattern 5db includes a metal film 5dc that may be an electroless plating film or a sputtering film, and a metal film 5dd that may be an electrolytic plating film. I'm here. The side surfaces of the metal film 5dd and the bottom surface facing the core substrate 10 side are covered with the metal film 5dc, and the side surfaces of the conductor pattern 5db and the bottom surface facing the core substrate 10 side are constituted by the metal film 5dc.

A via conductor 5f is formed in the insulating layer 5ea and the insulating layer 5eb, penetrating these two insulating layers. The via conductor 5f is formed of a metal film 5dc and a metal film 5dd similarly to the conductor pattern 5db. Via conductor 5f can connect conductors (for example, through-hole conductor 4 and upper via conductor 5f) sandwiching insulating layer 5ea and insulating layer 5eb. In the buildup layer 51 and the buildup layer 52 in the example of FIG. 3B, two sets of laminates each of the insulating layer 5ea and the insulating layer 5eb including the via conductor 5f and the conductor layer 5d are stacked.

The conductive layer 5d, the insulating layer 5ea, and the insulating layer 5eb included in the wiring board 102 are the same as the conductive layer 1, the insulating layer 31, and the insulating layer in the core board 10, except that the conductive pattern 5db does not penetrate the insulating layer 5ea. It has a structure similar to No. 32. As in the example of FIG. 3B, the build-up layer included in the wiring board of the embodiment is formed across two insulating layers, similar to the conductor layer in the core board, and has conductor patterns of different thicknesses. The conductor layer may also include a conductive layer.

In the wiring board 102, the second conductor pattern 12 of the conductor layer 1 penetrates the insulating layer 31, but does not protrude from the second surface 31b of the insulating layer 31. The end surface (lower surface) of the second conductor pattern 12 on the second surface 31b side of the insulating layer 31 and the second surface 31b of the insulating layer 31 are substantially flush with each other. Therefore, the length of the second conductor pattern 12 along the Z direction is approximately equal to the sum of the thicknesses of the insulating layer 31 and the insulating layer 32. In this manner, in the wiring board of the embodiment, the lower surface of the second conductor pattern 12 and the second surface 31b of the insulating layer 31 may be substantially flush with each other.

In the wiring board 102, the conductor layer 2 also has the same structure as the conductor layer 1, and includes conductor patterns having mutually different thicknesses. In the wiring board of the embodiment, a core board such as the core board 10 may be provided with conductor layers including conductor patterns having different thicknesses on each of its both surfaces.

Further, in the wiring board 102, the through-hole conductor 4 is in contact with the conductor layer 1. The through-hole conductor 4 on the right side in FIG. 3B is in contact with the first conductor pattern 11. In FIG. Furthermore, the through-hole conductor 4 on the left side in FIG. 3B includes a through-hole land made of a first conductor pattern 11 that is in contact with the through-hole conductor 4. In this way, the through-hole conductors included in the wiring board of the embodiment may be in contact with a conductor layer, such as the conductor layer 1, that includes conductor patterns having mutually different thicknesses.

In the core substrate 10α of the modified example shown in FIG. Not yet. Therefore, the surface 11a of the first conductor pattern 11 and the surface 12a of the second conductor pattern 12 are not located on the same plane. For example, if the first conductor pattern 11 does not need to be connected to another conductor, the first conductor pattern 11 does not need to be exposed from the insulating layer 32. Rather, the number of steps required to expose the first conductor pattern 11 in manufacturing the wiring board of the embodiment may be reduced.

Furthermore, in the core substrate 10α in the example of FIG. 4, the second conductor pattern 12 does not penetrate the insulating layer 31. That is, in the example of FIG. 4, the void 311 of the insulating layer 31 is a recess provided in the first surface 31a of the insulating layer 31, and the second conductor pattern 12 is a part of the recess provided in the first surface 31a. A certain void 311 is filled. However, also in the example of FIG. 4, the thickness of the second conductor pattern 12 is greater than the thickness of the first conductor pattern 11. As in the example of FIG. 4, the second conductor pattern 12 does not need to penetrate the insulating layer 31, and therefore the lower surface of the second conductor pattern 12 does not need to reach the second surface 31b of the insulating layer 31.

In the modified core substrate 10β shown in FIG. 5, the core layer 30 is formed of an insulating layer resin instead of a glass substrate. Therefore, the core layer 30 in the example of FIG. 5 is also an insulating layer like the core layer 30 in the example of FIG. The core layer 30 of the core substrate 10β is made of thermosetting resin such as epoxy resin, BT resin, and phenol resin, or fluororesin, LCP, PTFE resin, PE resin, and the like, as well as the insulating layer 31 described above. It may be made of thermoplastic resin such as MPI resin. As shown in FIG. 5, the core layer 30 may include a reinforcing material 30d made of, for example, glass fiber. The rigidity of the core board 10β may be improved, and warping of the wiring board of the embodiment may be suppressed. The core layer 30 may include a filler (not shown) made of particles such as silicon dioxide or alumina.

The core layer 30 in the example of FIG. 5 has one surface 30a (first surface) and the other surface 30b (second surface) opposite to the one surface 30a, like the core layer 30 in the example of FIG. It has a gap 311 that opens to 30a. The void 311 in the example of FIG. 5 is a recess provided on one surface 30a. An insulating layer 32 is laminated on one surface 30a of the core layer 30, and a conductor layer 1 is formed on the one surface 30a of the core layer 30 and inside the core layer 30. The first conductor pattern 11 of the conductor layer 1 is formed entirely on one surface 30a of the core layer 30. The second conductor pattern 12 of the conductor layer 1 includes a portion formed inside the void 311. That is, in the core substrate 10β, the core layer 30 functions as the insulating layer 31 (first insulating layer) in the example of FIG. 1 with respect to the conductor layer 1. As described above, in this embodiment, the conductor layer 1 may be formed so as to extend over the surface (first surface) of the insulating layer constituting the core layer 30 and inside the insulating layer.

Next, the method for manufacturing the wiring board of this embodiment will be described with reference to FIGS. 6A to 6H, taking as an example the case where the wiring board 100 of FIG. 1 is manufactured. In the following description, the "method for manufacturing a wiring board according to the present embodiment" is also simply referred to as the "method according to the embodiment." Note that each component formed in the manufacturing method described below may be formed using the material specified or exemplified in the description of the wiring board 100 in FIG. 1 for the corresponding component, unless otherwise specified. .

When the wiring board 100 of FIG. 1 is manufactured, as shown in FIG. 6A, a glass substrate 300 mainly made of, for example, soda lime glass, alkali-free glass, quartz glass, or borosilicate glass is prepared. Ru. The glass substrate 300 can be prepared, for example, by a common plate glass manufacturing method such as a float glass method.

A resin 310 is laminated on both sides of the glass substrate 300, and a metal foil 110 made of a metal having appropriate conductivity such as copper or nickel is further laminated thereon. The resin 310 may be a thermosetting resin such as an epoxy resin, which is exemplified as a material for the insulating layer 31 (see FIG. 1) in the description of the wiring board 100 in FIG. 1, or a thermoplastic resin such as LCP. In the example of FIG. 6A, the resin 310 is formed into a film in the B-stage state, and then laminated on both surfaces of the glass substrate 300. Although not shown, the resin 310 may include a filler made of particles of silicon dioxide, alumina, or the like. Further, the resin 310 may be formed into a sheet shape and may include a reinforcing material (not shown) such as glass fiber.

The resin 310 and metal foil 110 laminated on both sides of the glass substrate 300 are pressurized and heated at appropriate pressure and temperature. Due to the pressure and heating, the resin 310 is once softened, and the resin 310, the glass substrate 300, and the metal foil 110 are bonded together.

As a result, as shown in FIG. 6B, an insulating layer 31 (first insulating layer) made of the resin 310 in FIG. 6A that has been softened and then hardened is formed on one surface 30a of the core layer 30 made of the glass substrate 300 in FIG. 6A. It is formed. Similarly, an insulating layer 33 is formed on the other surface 30b of the core layer 30. The insulating layer 31 has a first surface 31a, which is a surface opposite to the core layer 30 side, and a second surface 31b, which is a surface opposite to the first surface 31a. Thus, the method of the embodiment includes preparing the insulating layer 31 (first insulating layer).

Note that instead of preparing the insulating layer 31 with the core layer 30 shown in the example of FIG. It may be prepared as an insulating layer (first insulating layer) that functions as an insulating layer. Then, the steps described below may be performed using the insulating layer functioning as the core layer 30 as a starting substrate. In that case, the core substrate 10β shown in FIG. 5 referred to above may be formed.

On the first surface 31a of the insulating layer 31, a metal layer 1a made of the metal foil 110 shown in FIG. 6A is formed. Similarly, on the surface of the insulating layer 33, a metal layer 2a made of the metal foil 110 shown in FIG. 6A is formed. As will be described later, the first conductor pattern 11 of the wiring board 100 of FIG. 1 is formed by patterning the metal layer 1a, and the conductor layer 2 of the wiring board 100 is formed by patterning the metal layer 2a. Note that the metal layer 1a and the metal layer 2a are formed not by the method of laminating the metal foils 110 shown in FIG. 6A, but by, for example, forming a metal film by electroless plating or sputtering, and electrolytic plating using the metal film as a power supply layer. It may also be formed by panel plating. In that case, the first conductor pattern 11 and conductor layer 2 shown in FIG. 3A referred to above may be formed.

After that, a portion of each of the metal layer 1a and the metal layer 2a is removed. For example, a portion of each metal layer is removed by etching using an etch mask with appropriate openings and an etchant containing, for example, ferric chloride or cupric chloride. Each metal layer is patterned to have a desired pattern. As described above, the first conductor pattern 11 and the conductor layer 2 of the wiring board 100 in FIG. 1 are formed by patterning the metal layer 1a and the metal layer 2a, respectively. Therefore, the metal layer 1a is patterned so that a portion corresponding to the first conductor pattern 11 remains, and the metal layer 2a is patterned so that a portion corresponding to the conductor pattern included in the conductor layer 2 remains.

As a result of patterning the metal layer 1a and the metal layer 2a in FIG. 6B, the first conductor pattern 11 is formed on the first surface 31a of the insulating layer 31, as shown in FIG. A conductor layer 2 including a desired conductor pattern is formed.

As shown in FIG. 6C, an insulating layer 32 (second insulating layer) is laminated on the first surface 31a of the insulating layer 31 and on the first conductor pattern 11. The first conductor pattern 11 is covered with an insulating layer 32. For example, the same material as the insulating layer 31 is used for the insulating layer 32. For example, the insulating layer 32 is prepared by laminating an appropriate resin such as an epoxy resin formed into a film on the first surface 31a of the insulating layer 31 and the first conductor pattern 11 in the same way as the insulating layer 31 described above. , formed by heating and pressurizing.

An insulating layer 34 is formed on the surface of the insulating layer 33 and on the conductor layer 2. The insulating layer 34 may be formed using the same material and the same method as the insulating layer 32, for example. The resin forming the insulating layer 32 and the insulating layer 34 may include a reinforcing material made of glass fiber or the like, such as the reinforcing material 30d shown in FIG. 5 referred to above. However, insulating layers 32 and 34 that do not include such reinforcing materials may be preferable in terms of ease of polishing that can be performed in a subsequent process.

In the example of FIG. 6C, a metal foil F made of copper, for example, is laminated on the surfaces of the insulating layer 33 and the insulating layer 34. The metal foil F is laminated in the same manner as the metal foil 110 described with reference to FIG. 6A. Although the metal foils F are not necessarily laminated, the undulations of the surfaces of the insulating layers 32 and 34 may be reduced by the metal foils F.

As shown in FIG. 6D, a void 311 is formed in the insulating layer 31 and opens to the first surface 31a of the insulating layer 31. In the example shown in FIG. 6D, a void 311 penetrating the insulating layer 31 is formed. Furthermore, a recess 30c communicating with the void 311 is formed on one surface 30a of the core layer 30. Furthermore, a through hole 321 is formed in the insulating layer 32 and is open to the upper surface of the metal foil F and communicates with the void 311. That is, the core layer 30, the insulating layer 31, the insulating layer 32, and the metal foil F include the recess 30c of the core layer 30, the void 311 of the insulating layer 31, and the through hole 321 of the insulating layer 32, and the upper surface of the metal foil F An open recess R is formed. The recess 30a, the void 311, and the through hole 321 are formed at the position where the second conductor pattern 12 of the wiring board 100 in FIG. 1 is formed.

In addition, in the example of FIG. 6D, the insulating layer 32, the insulating layer 31, the core layer 30, the insulating layer 33, and the insulating layer 34 are connected all at once from the metal foil F on the insulating layer 32 to the metal foil F on the insulating layer 34. A through hole 40 is formed therethrough. The through hole 40 is formed in the wiring board 100 of FIG. 1 at the position where the through hole conductor 4 is formed.

The recess R is formed, for example, by laser processing using an excimer laser. The recessed portion R may be formed by irradiation with a laser beam other than an excimer laser. The through-hole 40 may be formed in the same laser beam irradiation process as the recess R, but it may also be formed in a laser beam irradiation process different from that for forming the recess R, before or after the recess R formation process. For example, the through hole 40 may be formed by irradiation with carbon dioxide laser light or YAG laser light from the insulating layer 32 side and the insulating layer 34 side, respectively. Further, the through hole 40 may be formed by machining such as drilling.

In FIG. 6D, a recess 30c is formed in the core layer 30 in forming the recess R, but the laser light irradiation conditions such as laser power are set so that the core layer 30 made of a glass substrate can function as a laser light stopper. may be adjusted and the core layer 30 may be used as a stopper. In that case, a recess R having a bottom surface substantially flush with the second surface 31b of the insulating layer 31 is formed. By forming such a recess R, the second conductor pattern 12 shown in FIG. 3B referred to above can be formed. Further, a recess R that does not penetrate the insulating layer 31 may be formed. In that case, the second conductor pattern 12 shown in FIG. 4 referred to above may be formed. In this way, a recess R that does not reach the inside of the core layer 30 may be formed, and a recess R that does not penetrate the insulating layer 31 may be formed. That is, a void 311 penetrating the insulating layer 31 may be formed, or a concave-shaped void 311 with a bottom that does not penetrate the insulating layer 31 may be formed within the insulating layer 31.

As shown in FIG. 6E, the exposed surfaces of the insulating layer 31, the insulating layer 32, and the core layer 30 exposed in the recess R, and the exposed surfaces of the insulating layers 31 to 34 and the conductive layer 2 exposed in the through hole 40 A first metal film 121 is formed thereon. The first metal film 121 is also formed on the upper surface of the metal foil F. A metal film made of copper, nickel, or the like is formed as the first metal film 121 by, for example, electroless plating or sputtering.

Further, on the first metal film 121, a second metal film 122 made of a plating film of a metal having appropriate conductivity such as copper or nickel is formed by electrolytic plating using the first metal film 121 as a power supply layer. . The inside of the recess R, that is, the inside of each of the void 311 of the insulating layer 31, the recess 30c of the core layer 30, and the through hole 321 of the insulating layer 32 is covered by a conductive film made of the first metal film 121 and the second metal film 122. Filled. As a result, the second conductor pattern 12 consisting of the first metal film 121 and the second metal film 122 is formed in the recess R.

Similarly, the inside of the through hole 40 is filled with the first metal film 121 and the second metal film 122. As a result, a through-hole conductor 4 made of the first metal film 121 and the second metal film 122 is formed in the through-hole 40 .

In the example shown in FIG. 6E, the second metal film 122 is also formed on the first metal film 121 formed on the metal foil F. That is, a conductive film consisting of the first metal film 121 and the second metal film 122 is also formed on the surface 32a of the insulating layer 32 and the surface 34a of the insulating layer 34, and the surface 32a and the surface 34a are made of metal foil. It is covered with this conductive film via F. Since the second metal film 122 is thus formed on the entire surface of the first metal film 121, formation of a plating resist on the first metal film 121 can be omitted.

After that, the first metal film 121 and the second metal film 122 on the surface 32a of the insulating layer 32 and the surface 34a of the insulating layer 34 are removed. For example, by exposing the first metal film 121 and the second metal film 122 to an etching solution containing ferric chloride or cupric chloride, the first metal film 121 and the second metal film 122 are Metal film 121 and second metal film 122 are removed.

As a result, as shown in FIG. 6F, the second conductor patterns 12 are electrically and physically isolated from each other, and the through-hole conductors 4 are also electrically and physically isolated from each other. Furthermore, the through-hole conductor 4 and the second conductor pattern 12 are also electrically and physically separated. Individual second conductor patterns 12 and through-hole conductors 4 are obtained which are insulated from conductors that are not to be electrically connected. The second conductor pattern 12 having a portion formed inside the gap 311 of the insulating layer 31 has a thickness larger than the thickness of the first conductor pattern 11, which also depends on the length of the gap 311 in the Z direction. is formed. On the other hand, since the second conductor pattern 12 and the first conductor pattern 11 have portions that overlap each other in side view, they can belong to the same conductor layer. That is, a conductor layer 1 (first conductor layer) including the first conductor pattern 11 and the second conductor pattern 12 is obtained. The first conductor pattern 11 is entirely located on the first surface 31a of the insulating layer 31. The first conductor pattern 11 and the second conductor pattern 12 are formed at positions that do not overlap each other in plan view.

As described above, the method of the embodiment includes, in addition to preparing the insulating layer 31, a portion located on the surface (first surface 31a) of the insulating layer 31 and the first conductor pattern 11 and the second conductor pattern. It further comprises forming a conductor layer 1 comprising 12. As described above, forming the conductor layer 1 involves providing the metal layer 1a (see FIG. 6B) covering the first surface 31a of the insulating layer 31 and partially removing the metal layer 1a. 1 conductor pattern 11 on the first surface 31a of the insulating layer 31. Forming the conductive layer 1 further includes, as described above, forming the void 311 in the insulating layer 31 that opens to the first surface 31a of the insulating layer 31, and forming a conductive film including a plating film (first metal forming the second conductor pattern 12 by filling the void 311 with a film 121 and a second metal film 122). The second conductor pattern 12 includes a portion made of a conductive film that fills the void 311. In the method of the embodiment, the second conductor pattern 12 is formed to have a greater thickness than the first conductor pattern 11.

The method of the embodiment may further include laminating the insulating layer 32 (second insulating layer) covering the first conductor pattern 11 on the first surface 31a of the insulating layer 31 as described above. Forming the void 311 in the insulating layer 31 may include forming a through hole 321 in the insulating layer 32 that communicates with the void 311 . In that case, forming the second conductive pattern 12 in the method of the embodiment may include filling the through hole 321 with a conductive film (first metal film 121 and second metal film 122) that fills the void 311. . In that case, filling the through hole 321 means forming a conductive film filling the void 311 up to the surface 32a of the insulating layer 32 opposite to the insulating layer 31, and filling the surface 32a of the insulating layer 32 with the void 311. It may include covering with a conductive film (see FIG. 6E). In that case, forming the second conductive pattern 12 in the method of the embodiment further involves removing the conductive film (the first metal film 121 and the second metal film 122) on the surface 32a of the insulating layer 32. may include.

In the example of FIG. 6F, the end of the second conductor pattern 12 on the insulating layer 32 side is also removed by etching so that the surface 12a on this end side is recessed toward the insulating layer 31 side from the surface 32a of the insulating layer 32. There is. Also. Both ends of the through-hole conductor 4 are also removed by etching so that the end surfaces 4a and 4b are recessed toward the core layer 30 side relative to the surface 32a of the insulating layer 32 or the surface 34a of the insulating layer 34, respectively. It is considered that the second conductor patterns 12, the through-hole conductors 4, and the second conductor patterns 12 and the through-hole extensions 4 are reliably separated electrically and mechanically.

As shown in FIG. 6G, a portion of the insulating layer 32 and the insulating layer 34 in the thickness direction is removed. Along with the removal of a portion of the insulating layer 32, the end of the second conductor pattern 12 on the surface 32a side of the insulating layer 32 and the end of the through-hole conductor 4 on the end surface 4a side are also removed. Furthermore, along with the removal of a portion of the insulating layer 34, the end portion of the through-hole conductor 4 on the end surface 4b side is also removed. A portion of the insulating layer 32, the end of the second conductor pattern 12, and the end of the through-hole conductor 4 on the end surface 4a side preferably include a surface 32a of the insulating layer 32, a surface 12a of the second conductor pattern 12, and the end surfaces 4a of the through-hole conductors 4 are removed so that they are located on the same plane. Similarly, a portion of the insulating layer 34 and the end portion of the through-hole conductor 4 on the end surface 4b side are preferably arranged such that the surface 34a of the insulating layer 34 and the end surface 4b of the through-hole conductor 4 are located on the same plane. removed. A core substrate 10 having one flat surface 10a and the other flat surface 10b is obtained.

Portions of the insulating layer 32 and the insulating layer 34, as well as the ends of the second conductive pattern 12 and the through-hole conductor, may be removed by any method, such as polishing. For example, the insulating layer 32 and the insulating layer 32 can be removed by mechanical polishing such as sanding with a belt sander or buffing, chemical polishing using soluble plasma gas, or chemical mechanical polishing (CMP) that is a combination of these. A portion of layer 34 and the ends of second conductor pattern 12 and through-hole conductor 4 are removed.

In the example of FIG. 6G, parts of the insulating layer 32 and the insulating layer 34 are exposed until the surface 11a of the first conductor pattern 11 and the upper surface of the conductor layer 2 (the surface of the conductor layer 2 opposite to the conductor layer 1) are exposed. is removed by a suitable method, such as the various polishing methods exemplified above. In this manner, the method of the embodiment may further include removing a portion of the insulating layer 32 to expose the first conductor pattern 11. Preferably, polishing is performed to remove a portion of the insulating layer 32 so that the surface 11a of the first conductor pattern 11 and the surface 32a of the insulating layer 32 are located on the same plane. Similarly, polishing is performed to remove a portion of the insulating layer 34 so that the upper surface of the conductor layer 2 and the surface 34a of the insulating layer 34 are located on the same plane. A core substrate 10 having one flat surface 10a and the other flat surface 10b is obtained. Through the above steps, the core substrate 10 of the wiring board 100 in FIG. 1 is completed.

When the wiring board 100 of FIG. 1 is manufactured, as shown in FIG. 6H, the build-up layers 51 and 52 are formed by alternately forming the insulating layers 5b and the conductor layers 5a on both sides of the core board 10, respectively. be done. For example, the insulating layer 5b can be formed by laminating a film-like epoxy resin on the core substrate 10 or on the already formed insulating layer 5b, and heating and pressurizing the epoxy resin. Further, the conductor layer 5a in FIG. 6H is formed by forming a metal film 5aa and a gold storage film 5ab by, for example, a semi-additive method after forming a through hole in the insulating layer 5b. Inside the insulating layer 5b, a via conductor 5c is formed and removed at the same time as the conductor layer 5a is formed.

Then, a solder resist layer 61 is formed on the buildup layer 51, and a solder resist layer 62 is formed on the buildup layer 52. The solder resists 61 and 62 are formed, for example, by supplying photosensitive epoxy resin or polyimide resin by spraying, laminating, printing, or the like. An opening 63 is formed at a predetermined position by exposure using an exposure mask (not shown) having an appropriate opening, development, or laser processing. Through the above steps, the wiring board 100 shown in FIG. 1 is completed.

Note that the conductor layer 5a in the example of FIG. 3A referred to above is formed by a method similar to the method of forming the second conductor pattern 12 described with reference to FIGS. 6D to 6F. That is, the conductor layer 5a in FIG. 3A is formed by forming a recess 5ba in the insulating layer 5b by laser processing or the like, and filling the recess 5ba with a metal film 5aa and a metal film 5ab produced by, for example, electroless plating and electrolytic plating. can be formed. Further, the conductive layer 5d, the insulating layer 5ea, and the insulating layer 5eb in the example of FIG. 3B referred to above are the first conductive pattern 11, the second conductive pattern 12, The insulating layer 31 and the insulating layer 32 may be formed by a method similar to that of the insulating layer 31 and the insulating layer 32. Furthermore, the first conductor pattern 11 shown in FIG. 3B is an etching mask suitable for forming the first conductor pattern 11 in the example of FIG. 3B in the patterning of the metal layer 1a described with reference to FIGS. 6B and 6C. can be formed by using

Further, the first conductor pattern 11 that is not exposed from the insulating layer 32 illustrated in FIG. The insulating layer 32 may be formed by completing a removal process of a portion of the insulating layer 32, such as various types of polishing, before the insulating layer 32 is exposed. Note that if particular flatness is not required for the surface of the core substrate 10, the step of removing part of the insulating layer 32 and the insulating layer 34 may be omitted. Alternatively, as a result of removing the first and second metal films 121 and 122 (see FIG. 6E) on the surface 32a of the insulating layer 32, the surface 12a of the second conductor pattern 12 and the end surface 4a of the through-hole conductor 4 become the surface. 32a, the step of removing part of the insulating layer 32 may be omitted. Similarly, when the end surface 4b of the through-ball conductor 4 is located on the same plane as the surface of the insulating layer 34 as a result of removing the first and second metal films 121 and 122 on the surface of the insulating layer 34 , the step of removing part of the insulating layer 34 may be omitted.

According to the method of the embodiment, since the first conductor pattern and the second conductor pattern having different thicknesses are formed in one conductor layer, conductor patterns requiring different characteristics can be mixed in the same conductor layer. There is. In addition, since the second conductor pattern is formed at least partially within the gap provided in the insulating layer, it has a high aspect ratio, that is, the thickness is large relative to the wiring width, and therefore it can achieve low conductor resistance even though it is a fine wiring. In some cases, it may be possible to realize a wiring pattern that has the following characteristics. On the other hand, in order to form a thick conductor pattern with a large planar area inside an insulating layer, a lot of time is required to form cavities such as extensive recesses and through holes in the insulating layer. , the thickness of the conductor pattern may become non-uniform. However, in the method of the embodiment, the first conductor pattern is formed separately from the second conductor pattern on the surface of the insulating layer in which the second conductor pattern 12 is partially formed. It is thought that it can be easily formed with a certain thickness.

The wiring board of the embodiment is not limited to the structure illustrated in each drawing and the structure, shape, and material illustrated in this specification. For example, in the wiring board of the embodiment, a through-hole conductor penetrating the core board may not be provided. Further, the wiring board of the embodiment does not need to include a buildup layer, and does not need to include a core board or a layered component that can be interpreted as a core board layer. That is, in the wiring board of the embodiment, the conductor layer including conductor patterns having mutually different thicknesses and the insulating layer covering the side surface of the conductor layer do not need to be part of the core board.

The method of manufacturing the wiring board of the embodiment is not limited to the method described with reference to each drawing. For example, a wiring board having an arbitrary laminated structure having an arbitrary number of layers can be manufactured by the wiring board manufacturing method of the embodiment. Furthermore, as described above, the metal foils F in FIG. 6C are not necessarily laminated. In addition, along with the removal of a portion of the insulating layer 32 and the insulating layer 34 described with reference to FIG. 6G, a portion of each of the first conductor pattern 11 and the conductor layer 2 is also removed to reduce their thickness. You can. In the method for manufacturing a wiring board according to the embodiment, any steps other than the steps described above may be added, or some of the steps described above may be omitted.

100, 101, 102 Wiring board 10, 10α, 10β Core substrate 1 Conductor layer 1a Metal layer 11 First conductor pattern 110 Metal foil 11a Surface 12 Second conductor pattern 12a Surface 300 Glass substrate 31 Insulating layer (first insulating layer)
31a First surface 31b Second surface 311 Gap 32 Insulating layer (second insulating layer)
32a Surface 4 Through-hole conductors 4a, 4b End surface 50 Core substrate layers 51, 52 Buildup layer 5a Conductor layer 5b Insulating layer

Claims (19)

a first insulating layer having a first surface and a second surface opposite to the first surface;
a conductor layer having a portion formed on the first surface of the first insulating layer;
A wiring board comprising:
The first insulating layer has a void opening on the first surface,
The conductor layer has a first conductor pattern formed entirely on the first surface and a portion formed inside the gap, and overlaps with the first conductor pattern in plan view. a second conductor pattern that does not
The thickness of the second conductive pattern is greater than the thickness of the first conductive pattern. The wiring board according to claim 1,
The first conductor pattern is a power supply pattern or a ground pattern,
The second conductor pattern is a signal line. 2. The wiring board according to claim 1, wherein the surface of the first conductor pattern facing in a direction opposite to the first insulating layer is the same direction as the surface of the first conductor pattern facing in the second conductor pattern. The surfaces facing the surface are located on the same plane. 2. The wiring board according to claim 1, wherein the entire area of the second conductor pattern in plan view is 20% or less of the entire area of the first conductor pattern in plan view. 2. The wiring board according to claim 1, wherein the second conductor pattern does not include metal foil, and the first conductor pattern includes metal foil. 6. The wiring board according to claim 5, wherein the second conductor pattern includes an electrolytically plated film and a metal film interposed between the electrolytically plated film and the first insulating layer. The wiring board according to claim 1, further comprising a through-hole conductor penetrating the first insulating layer,
An end surface of the first insulating layer of the through-hole conductor on the first surface side and a surface of the second conductor pattern facing in the same direction as the end surface of the through-hole conductor are located on the same plane. are doing. 8. The wiring board according to claim 7, wherein the end surface of the through-hole conductor is located on the same plane as a surface of the first conductor pattern facing in a direction opposite to the first insulating layer. 8. The wiring board according to claim 7, wherein the through-hole conductor protrudes from the first surface of the first insulating layer without contacting the conductor layer. The wiring board according to claim 1,
The wiring board includes a core board layer and a buildup layer constituted by insulating layers and conductor layers that are alternately laminated on the surface of the core board layer,
The first insulating layer and the conductor layer constitute a part of the core substrate layer. 11. The wiring board according to claim 10, wherein the first insulating layer contains a thermosetting resin. The wiring board according to claim 11,
The core substrate layer includes a glass substrate, and the first insulating layer is laminated on the glass substrate. The wiring board according to claim 1, further comprising:
a second insulating layer stacked on the first surface of the first insulating layer;
a through-hole conductor penetrating the first insulating layer and protruding from the first surface,
the second conductor pattern protrudes from the first surface of the first insulating layer;
A side surface of the first conductor pattern and a side surface of each of the second conductor pattern and the through-hole conductor protruding from the first surface are covered with the second insulating layer. The wiring board according to claim 13,
The surface of the second insulating layer facing in the opposite direction to the first insulating layer is the same as the end surface of the through-hole conductor on the second insulating layer side and the surface of the second insulating layer of the second conductor pattern. lies on the same plane as the surface toward which it faces. 15. The wiring board according to claim 14, wherein the surface of the second insulating layer is located on the same plane as a surface of the first conductor pattern facing in a direction opposite to the first insulating layer. providing a first insulating layer;
forming a conductor layer having a portion located on the surface of the first insulating layer and including a first conductor pattern and a second conductor pattern;
A method for manufacturing a wiring board, the method comprising:
Forming the conductor layer includes:
providing a metal layer covering the surface of the first insulating layer;
forming the first conductor pattern on the surface by partially removing the metal layer;
forming a void in the first insulating layer that opens to the surface of the first insulating layer;
By filling the void with a conductive film including a plating film, the second conductive pattern including the portion made of the conductive film within the void is formed to have a thickness greater than that of the first conductive pattern. And,
Contains. 17. The method of manufacturing a wiring board according to claim 16, further comprising laminating a second insulating layer covering the first conductor pattern on the surface of the first insulating layer.
Forming the void includes forming a through hole communicating with the void in the second insulating layer,
Forming the second conductor pattern includes filling the through hole with the conductive film. 18. The method for manufacturing a wiring board according to claim 17,
Filling the through hole with the conductive film includes forming the conductive film up to the surface of the second insulating layer opposite to the first insulating layer, and filling the surface of the second insulating layer with the conductive film. including covering;
Forming the second conductive pattern further includes removing the conductive film on the surface of the second insulating layer. 18. The method of manufacturing a wiring board according to claim 17, further comprising removing a portion of the second insulating layer to expose the first conductor pattern.

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