JP2024001682A - Control device of display device, and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress deviation of light emission start timing during each sub-frame period in a display device.

SOLUTION: In a control method of a display device 1 having a pixel circuit 30, the pixel circuit 30 includes a drive transistor 33 and a light emitting element 32 connected to the source of the drive transistor 33, a frame period includes a first sub-frame period and at least one second sub-frame period, the control method of the display device 1 includes a first extinction step for maintaining the light emitting element 32 in an extinction state during the first sub-frame period and a second extinction step for maintaining the light emitting element 32 in an extinction state during the second sub-frame period, the first extinction step includes a first initialization step and a second initialization step, the second extinction step includes a third initialization step, and the length of a period from start of the first sub-frame period to the end of the second initialization step is equal to the length of a period from start of the second sub-frame period to the end of the third initialization step.

SELECTED DRAWING: Figure 8

COPYRIGHT: (C)2024,JPO&INPIT

Description

The present disclosure relates to a method of controlling a display device and a display device.

In display devices using organic EL (Electro Luminescence), etc., the organic EL element is extinguished (lights are turned off) in order to initialize the potential of the source of the drive transistor included in the pixel circuit and to write a signal corresponding to an image. period and a light emission period in which the organic EL element can emit light are repeated. When the frequency of such repetition is 60 Hz or less, flicker (flickering of the screen) caused by the repetition of light emission and extinction is visible.

As a countermeasure against flicker, a subframe driving method is known in which a frame period is divided into a plurality of subframe periods by inserting a extinction period in the middle of a light emission period (see, for example, Patent Document 1). The invention described in Patent Document 1 attempts to suppress flicker using such a drive method.

Japanese Patent Application Publication No. 2012-13741

According to the above driving method, a luminance difference may occur in each subframe period due to a light emission delay due to a bootstrap operation after a signal is written to a pixel circuit. In order to suppress this brightness difference, a method can be considered in which a bootstrap operation is performed after initializing the potential of the source of the drive transistor of the pixel circuit to a constant potential before the start of light emission in each subframe period.

However, even with such a method, the light emission start timing in each subframe period may be shifted.

The present disclosure has been made in view of the above-mentioned circumstances, and an object of the present disclosure is to provide a control method for a display device, etc. that can suppress deviations in light emission start timing in each subframe period.

In order to achieve the above object, in a method for controlling a display device according to one embodiment of the present disclosure, the display device includes a plurality of pixel circuits, each of the plurality of pixel circuits including a light emitting element and a drive transistor. , a pixel capacitor, the drive transistor has a gate, a source, and a drain, the light emitting element is connected to the source, and one end and the other end of the pixel capacitor are respectively connected to the gate, and a frame period connected to the source and in which the same image is displayed on the display device has a first subframe period and one or more second subframe periods following the first subframe period, The length of each of the one or more second subframe periods is equal to the length of the first subframe period, and the control method for the display device includes controlling the light emission for a predetermined extinction period in the first subframe period. a first quenching step of maintaining the element in a quenched state, and a first light emitting step of causing the light emitting element to emit light after the first quenching step, and in each of the one or more second subframe periods, the quenching a second quenching step of maintaining the light emitting device in a quenched state for a period of time; and a second light emitting step of causing the light emitting device to emit light after the second quenching step, and the first quenching step includes causing the source to emit light in a predetermined manner. a first initialization step of applying an initialization potential of; after the first initialization step, a write step of applying a signal corresponding to the image to the pixel capacitance; and after the write step, a predetermined initialization potential of a second initialization step of applying the initialization potential to the source for an initialization period; the second quenching step includes a third initialization step of applying the initialization potential to the source; The length of the period from the start of one subframe period to the end of the second initialization step is from the start of each of the one or more second subframe periods to the end of the third initialization step. equal to the length of the period.

In order to achieve the above object, a display device according to one embodiment of the present disclosure includes a plurality of pixel circuits and a control device that controls the plurality of pixel circuits, and each of the plurality of pixel circuits includes a light emitting element. , a drive transistor, and a pixel capacitor, the drive transistor has a gate, a source, and a drain, the light emitting element is connected to the source, one end of the pixel capacitor, and the other end of the pixel capacitor. Frame periods connected to the gate and the source and in which the same image is displayed on the display device include a first subframe period and one or more second subframe periods following the first subframe period. and the length of each of the one or more second subframe periods is equal to the length of the first subframe period, and the control device is configured to control the length of each of the one or more second subframe periods for a predetermined extinction period in the first subframe period. a first light-emitting section that stops and maintains the light-emitting element in an extinguished state; a first light-emitting section that causes the light-emitting element to emit light by supplying current to the light-emitting element in the first subframe period; In each of the above second subframe periods, a second extinction section maintains the light emitting element in the extinction state over the extinction period, and in each of the one or more second subframe periods, current is supplied to the light emitting element. a second light emitting section that causes the light emitting element to emit light by performing the following steps; , a writing section that applies a signal corresponding to the image to the pixel capacitor, and a second initialization section that applies the initialization potential to the source, and the second extinction section is configured to perform a predetermined initialization period. a third initialization section that applies the initialization potential to the source over a period from the start of the first subframe period to the time when the second initialization section finishes applying the initialization potential; The length is equal to the length of a period from the start time of each of the one or more second subframe periods to the time point when the third initialization section finishes applying the initialization potential.

In order to achieve the above object, a display device according to another aspect of the present disclosure includes a plurality of pixel circuits, one or more dummy pixel circuits, and a control device that controls the plurality of pixel circuits, Each of the plurality of pixel circuits has a light emitting element, a driving transistor, and a pixel capacitor, the driving transistor has a gate, a source, and a drain, the light emitting element is connected to the source, and the driving transistor has a gate, a source, and a drain. One end and the other end of the pixel capacitor are connected to the gate and the source, respectively, each of the one or more dummy pixel circuits has a capacitive element, and the control device controls the control of the plurality of pixel circuits. The dummy pixel circuit includes an initialization section that applies a predetermined initialization potential to the source of the drive transistor included in at least one of the pixel circuits and to the capacitor of each of the one or more dummy pixel circuits.

According to the present disclosure, it is possible to provide a display device control method that can suppress a shift in light emission start timing in each subframe period.

Schematic diagram showing a configuration example of a display device according to Embodiment 1 A circuit diagram showing a configuration of a pixel circuit according to Embodiment 1 Block diagram showing the functional configuration of a control device according to Embodiment 1 A diagram schematically showing a light emission waveform of a light emitting element included in a display device of a comparative example. A diagram schematically showing a light emission waveform of a light emitting element when a extinction period is inserted in a display device of a comparative example. A diagram illustrating the detailed operation of a pixel circuit included in a display device of a comparative example when a video signal has a high gradation level. A diagram illustrating detailed operation of a pixel circuit included in the display device according to Embodiment 1. Timing chart showing the states of the control signal ENB and the control signal INI in the first subframe period and the second subframe period according to Embodiment 1 A first schematic diagram showing the position of a row to be initialized in the display unit of the display device according to Embodiment 1. A second schematic diagram showing the position of a row to be initialized in the display unit of the display device according to Embodiment 1. A diagram schematically showing a time waveform of a potential of a power supply line to which an initialization potential of the display device according to Embodiment 1 is applied. Schematic diagram showing a configuration example of a display device according to Embodiment 2 A circuit diagram showing a configuration example of a dummy pixel circuit according to Embodiment 2 Circuit diagram showing the configuration of a pixel circuit according to modification 1 A circuit diagram showing the configuration of a pixel circuit according to modification 2

Embodiments of the present disclosure will be described below with reference to the drawings. The embodiments described below are all preferred specific examples of the present disclosure. Therefore, the numerical values, shapes, materials, components, arrangement positions and connection forms of the components shown in the following embodiments are merely examples and do not limit the present disclosure. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims representing the most important concept of the present disclosure will be described as arbitrary constituent elements.

Note that each figure is a schematic diagram and is not necessarily strictly illustrated. Further, in each figure, substantially the same configurations are denoted by the same reference numerals, and overlapping explanations will be omitted or simplified.

(Embodiment 1)
A display device and a method of controlling the display device according to Embodiment 1 will be described. In this embodiment, a case where an organic EL element is used in a display device will be described as an example.

[1-1. Display device configuration]
The configuration of the display device according to this embodiment will be explained using FIG. 1. FIG. 1 is a schematic diagram showing a configuration example of a display device 1 according to the present embodiment. The display device 1 includes a display panel 10 and a control device 20, as shown in FIG.

[1-2. Display panel configuration]
The display panel 10 includes a display section 12 having a plurality of pixel circuits 30, as shown in FIG. The display panel 10 also includes a gate drive circuit 14, a source drive circuit 16, and a power supply circuit 18 as peripheral circuits of the display section 12. The display section 12, gate drive circuit 14, source drive circuit 16, scanning line 40, signal line 42, and power supply line 44 are mounted on a panel substrate (not shown) made of, for example, glass or resin such as acrylic. ing. Note that the gate drive circuit 14 and the source drive circuit 16 do not need to be mounted on the panel substrate. The gate drive circuit 14 and the source drive circuit 16 may be mounted, for example, on a flexible substrate connected to a panel substrate using COF (Chip On Film or Chip On Flexible).

The display unit 12 displays images based on a video signal input to the display panel 10 from the outside. As shown in FIG. 1, the display unit 12 includes a plurality of pixel circuits 30 arranged in rows and columns, and includes scanning lines 40 in rows (that is, extending in the left-right direction in FIG. 1) and scanning lines 40 in columns ( That is, signal lines 42 and power lines 44 (extending in the vertical direction in FIG. 1) are wired. In the display section 12, an initialization operation, a write operation, and a light emitting operation are performed sequentially in rows of the plurality of pixel circuits 30.

A plurality of pixel circuits 30 are included in the display panel 10 and arranged in a matrix. More specifically, each of the plurality of pixel circuits 30 is arranged at a position where the scanning line 40 and the signal line 42 intersect. The detailed configuration of each pixel circuit 30 will be described later.

The scanning line 40 is arranged for each row of the plurality of pixel circuits 30. One end of the scanning line 40 is connected to the pixel circuit 30, and the other end of the scanning line 40 is connected to the gate drive circuit 14.

The signal line 42 is arranged for each column of the plurality of pixel circuits 30. One end of the signal line 42 is connected to the pixel circuit 30, and the other end of the signal line 42 is connected to the source drive circuit 16.

The power supply line 44 is arranged for each column of the plurality of pixel circuits 30. One end of the power line 44 is connected to the pixel circuit 30, and the other end of the power line 44 is connected to the power supply circuit 18. A plurality of power supply lines 44 to which different potentials are applied are connected to each of the plurality of pixel circuits 30. Note that although FIG. 1 shows a column-shaped power line 44, the wiring configuration of the power line 44 is not limited to this. The power supply line 44 may have any wiring configuration that can apply a potential from the power supply circuit 18 to each of the plurality of pixel circuits 30. For example, column-shaped power lines 44 and row-shaped power lines 44 may be wired. Further, when the column-shaped power supply lines 44 and the row-shaped power supply lines 44 are wired, the number of the column-shaped power supply lines 44 may be less than the number of columns of the plurality of pixel circuits 30 arranged in the matrix. good.

The gate drive circuit 14 is also called a scanning line drive circuit, and is composed of, for example, a shift register. The gate drive circuit 14 is connected to the scanning line 40 and controls turning on and off of each transistor included in the pixel circuit 30 by outputting a gate control signal to the scanning line 40. In the present embodiment, the gate drive circuit 14 uses, for example, a control signal WS, a control signal REF, a control signal INI, and a control signal ENB as gate control signals that control on and off of each transistor included in the pixel circuit 30. It is output to the gate of each transistor included in the pixel circuit 30.

The source drive circuit 16 is also called a signal line drive circuit. The source drive circuit 16 is connected to the signal line 42 and outputs a signal corresponding to the video signal supplied from the control device 20 in units of frames to the signal line 42, thereby transmitting the video signal to each pixel circuit 30. supply to. The source drive circuit 16 writes luminance information based on the video signal in the form of a current value or a voltage value to each of the pixel circuits 30 through the signal line 42 . Note that the video signal input to the source drive circuit 16 is, for example, digital serial data (video signals R, G, B) for each of the three primary colors of RGB. The video signals R, G, and B input to the source drive circuit 16 are converted into parallel data on a row-by-row basis inside the source drive circuit 16. Furthermore, the parallel data in units of rows is converted into analog data in units of rows inside the source drive circuit 16, and outputted to the signal line 42 as a video signal. Note that although an example in which the plurality of pixel circuits 30 includes pixel circuits 30 corresponding to the three primary colors of RGB has been described above, the configuration of the plurality of pixel circuits 30 is not limited to this. For example, the plurality of pixel circuits 30 may include pixel circuits 30 corresponding to RGBW.

The power supply circuit 18 is a circuit that applies a potential to each of the plurality of pixel circuits 30. The power supply circuit 18 generates a plurality of different potentials and applies them to each of the plurality of pixel circuits 30 via the plurality of power supply lines 44 .

[1-3. Pixel circuit configuration]
The configuration of the pixel circuit 30 will be explained using FIG. 2. FIG. 2 is a circuit diagram showing the configuration of the pixel circuit 30 according to this embodiment.

The plurality of pixel circuits 30 are arranged, for example, in N rows and M columns. N and M vary depending on the size and resolution of the display screen. For example, when the pixel circuits 30 corresponding to the three primary colors of RGB are adjacent in a row at a resolution called HD (High Definition), N is at least 1080 rows and M is at least 1920×3 columns. In this embodiment, each pixel circuit 30 has an organic EL element as the light emitting element 32.

As shown in FIG. 2, the pixel circuit 30 includes a light emitting element 32, a drive transistor 33, a selection transistor 35, switch transistors 34, 36, and 37, and a pixel capacitor 38. Note that in FIG. 2, the pixel capacitance 38 is also written as Cs.

The light emitting element 32 has a cathode and an anode, the cathode is connected to a power supply line 44 to which a cathode potential Vcat is applied, and the anode is connected to the source of the drive transistor 33. The light-emitting element 32 emits light with a brightness corresponding to the signal voltage of the video signal as a current flows through the light-emitting element 32 and is supplied from the drive transistor 33 and corresponds to the signal voltage of the video signal. The light emitting element 32 is, for example, an organic EL element. Note that the light emitting element 32 is not limited to an organic EL element, but may be a self-emitting element such as an inorganic EL element or a QLED, and may not be a self-emitting element as long as it is an element controlled by current drive.

Drive transistor 33 has a gate, a source, and a drain. The gate of the drive transistor 33 is connected to one electrode of the pixel capacitor 38, the drain is connected to the source of the switch transistor 34, and the source is connected to the anode of the light emitting element 32. The source is also connected to the other electrode of the pixel capacitor 38, etc. The drive transistor 33 converts a signal voltage applied between its gate and source into a current (referred to as a drain-source current) corresponding to the signal voltage. Then, the drive transistor 33 is turned on and supplies a drain-source current to the light emitting element 32, thereby causing the light emitting element 32 to emit light. The drive transistor 33 is composed of, for example, an n-type thin film transistor (n-type TFT).

The switch transistor 34 has a gate connected to the scanning line 40 , one of the source and drain connected to a power supply line 44 that supplies the drive potential Vcc, and the other of the source and drain connected to the drain of the drive transistor 33 . The switch transistor 34 is turned on or off depending on the control signal ENB supplied from the scanning line 40. When turned on, the switch transistor 34 connects the drive transistor 33 to the power supply line 44 to which the drive potential Vcc is applied, and supplies current between the drain and source of the drive transistor 33 to the light emitting element 32. The switch transistor 34 is composed of, for example, a p-type thin film transistor (p-type TFT).

The selection transistor 35 has its gate connected to the scanning line 40 , one of its source and drain connected to the signal line 42 , and the other of its source and drain connected to one electrode of the pixel capacitor 38 . The selection transistor 35 is turned on or off depending on the control signal WS supplied from the scanning line 40. When the selection transistor 35 is turned on, it applies the signal voltage of the video signal supplied from the signal line 42 to the electrode of the pixel capacitor 38, and causes the pixel capacitor 38 to accumulate a charge corresponding to the signal voltage. The selection transistor 35 is composed of, for example, an n-type thin film transistor (n-type TFT).

Furthermore, as will be described later, in the control method for the display device 1 according to the present embodiment, the potential of the gate of the drive transistor 33 connected to the source or drain of the switch transistor 35 changes from a potential higher than the signal voltage to a lower potential. It varies over a wide range. Therefore, in the control method for the display device 1 according to the present embodiment, it is necessary to maintain the switch transistor 35 in an off state in a wider gate-source voltage range than in the conventional control method. In order to reduce the leakage current of the switch transistor 35 in a wide gate-source voltage range and maintain the off state of the switch transistor 35, a TFT using an oxide semiconductor may be used as the switch transistor 35. , a multi-channel TFT in which the gate electrode is divided into a plurality of parts may be used.

The switch transistor 36 has a gate connected to the scanning line 40 , one of the source and drain connected to the power supply line 44 that supplies the reference potential Vref, and the other of the source and drain connected to one electrode of the pixel capacitor 38 and the drive transistor 33 connected to gates, etc. The switch transistor 36 is turned on or off depending on the control signal REF supplied from the scanning line 40. When the switch transistor 36 is turned on, it sets the electrode of the pixel capacitor 38 to the reference potential Vref. The switch transistor 36 is composed of, for example, an n-type thin film transistor (n-type TFT).

Further, similarly to the switch transistor 35, in the control method of the display device 1 according to the present embodiment, it is necessary to maintain the switch transistor 36 in the off state in a wider gate-source voltage range than in the conventional control method. . In order to reduce the leakage current of the switch transistor 36 in a wide gate-source voltage range and maintain the switch transistor 36 in an off state, a TFT using an oxide semiconductor may be used as the switch transistor 36. , a multi-channel TFT in which the gate electrode is divided into a plurality of parts may be used. Further, when the switch transistor 35 is a multi-channel TFT, a multi-channel TFT having the same number of channels as the switch transistor 35 or one more channel than the number of channels may be adopted as the switch transistor 36. .

The switch transistor 37 has a gate connected to the scanning line 40, one of the source and drain connected to the source of the drive transistor 33 and the other electrode of the pixel capacitor 38, and the other of the source and drain connected to the initialization potential Vini. It is connected to a power supply line 44 that supplies power. The switch transistor 37 is turned on or off depending on the control signal INI supplied from the scanning line 40. The switch transistor 37 sets the potential of the anode of the light emitting element 32 to the initialization potential Vini by being turned on. The switch transistor 37 is composed of, for example, an n-type thin film transistor (n-type TFT).

The pixel capacitor 38 is a capacitor to which a video signal is applied. One end and the other end of the pixel capacitor 38 are connected to the gate and source of the drive transistor 33, respectively. One end of the pixel capacitor 38 is also connected to the source of the selection transistor 35 and the source of the switch transistor 36. The pixel capacitor 38 accumulates charges corresponding to the video signal supplied from the signal line 42. For example, the pixel capacitor 38 stably maintains the voltage between the gate and source of the drive transistor 33 after the selection transistor 35 and the switch transistor 36 are turned off. In this manner, the pixel capacitor 38 applies a voltage between the gate and source of the drive transistor 33 in accordance with the voltage corresponding to the accumulated charge when the selection transistor 35 and the switch transistor 36 are in the off state.

The EL capacitor 39 is a parasitic capacitance inherent in the light emitting element 32, which is an EL element, and after this capacitance is charged and the voltage between the electrodes increases, a current starts flowing to the light emitting element 32, and the light emitting element 32 emits light. Start. The EL capacitor 39 is also written as Cel.

Note that the conductivity types of each of the drive transistor 33, selection transistor 35, switch transistor 36, and switch transistor 37 are not limited to those described above. For example, the switch transistor 34 may be an n-type TFT. Further, in each of the transistors described above, n-type and p-type TFTs may be appropriately mixed. Further, each transistor is not limited to a polysilicon TFT, and may be formed of an amorphous silicon TFT, an oxide semiconductor TFT, or the like.

[1-4. Configuration of control device]
The functional configuration of the control device 20 of the display device 1 according to the present embodiment will be described using FIG. 3. FIG. 3 is a block diagram showing the functional configuration of control device 20 according to this embodiment. As shown in FIG. 3, the control device 20 according to the present embodiment functionally includes a first light extinction section 21, a first light emission section 27, a second light extinction section 25, and a second light emission section 28. and has.

In the display device 1 according to the present embodiment, a frame period in which the same image is displayed includes a first subframe period and one or more second subframe periods following the first subframe period. The length of each of the one or more second subframe periods is equal to the length of the first subframe period.

The first extinction section 21 is a processing section that maintains the light emitting element 32 in the extinction state for a predetermined extinction period in the first subframe period. The first extinction section 21 controls the state of the light emitting element 32 by controlling the control signal sent from the gate drive circuit 14 to each transistor of the plurality of pixel circuits 30. The first extinction section 21 includes a first initialization section 22, a writing section 23, and a second initialization section 24. The first initialization section 22 is a processing section that applies a predetermined initialization potential Vini to the source of the drive transistor 33 over a predetermined initialization period. The writing unit 23 is a processing unit that applies a signal corresponding to an image displayed in a frame period to the pixel capacitor 38. The second initialization section 24 is a processing section that applies an initialization potential Vini to the source of the drive transistor 33.

The first light emitting unit 27 causes the light emitting element 32 to emit light by supplying current to the light emitting element 32 during the first subframe period. The first light emitting section 27 controls the state of the light emitting element 32 by controlling the control signal sent from the gate drive circuit 14 to each transistor of the plurality of pixel circuits 30.

The second extinction section 25 is a processing section that maintains the light emitting element 32 in the extinction state for a predetermined extinction period in each of one or more second subframe periods. The second extinction section 25 controls the state of the light emitting element 32 by controlling the control signal sent from the gate drive circuit 14 to each transistor of the plurality of pixel circuits 30. The second extinction section 25 has a third initialization section 26.

The third initialization section 26 is a processing section that applies an initialization potential Vini to the source of the drive transistor 33 over a predetermined initialization period.

The second light emitting unit 28 is a processing unit that causes the light emitting element 32 to emit light by supplying current to the light emitting element 32 in each of one or more second subframe periods. The second light emitting section 28 controls the state of the light emitting element 32 by controlling the control signal sent from the gate drive circuit 14 to each transistor of the plurality of pixel circuits 30.

[1-5. Control method]
A method of controlling the display device 1 according to this embodiment and its effects will be explained. Below, a method of controlling the display device 1 according to the present embodiment will be described while comparing it with a method of controlling a display device of a comparative example.

[1-5-1. Control method of display device of comparative example]
First, a method of controlling a display device of a comparative example will be described. The display device of the comparative example differs from the control method of the display device 1 according to the present embodiment in the control method, but is the same in other respects. In other words, the display device of the comparative example differs from the display device 1 according to the present embodiment in the configuration of the control device, but is the same in other respects.

The light emission waveform of the display device of the comparative example will be explained using FIGS. 4 and 5. FIG. 4 is a diagram schematically showing a light emission waveform of a light emitting element included in a display device of a comparative example. FIG. 5 is a diagram schematically showing a light emission waveform of a light emitting element when a extinction period is inserted, that is, when subframe driving is performed in a display device of a comparative example. 4 and 5 also show a signal writing period (broken line) and a extinction period (dotted line).

As shown in FIG. 4, in the light emitting element, a frame period (Tf) including a extinction period and a light emission period is repeated. Therefore, flicker is visible when the frame period is long, that is, when the frame frequency is low. For example, flicker is visible when the frame frequency is 60 Hz or less. Therefore, when the frame frequency is low, a measure is taken to insert a extinction period in the middle of the light emission period, as shown in FIG. As shown in FIG. 5, the period from the end of the signal writing period to the start of light emission is longer than the period from the end of the inserted extinction period to the start of light emission. As described above, in the display device of the comparative example, flicker cannot be sufficiently suppressed because the period from the end of the signal writing period to the start of light emission occurs every frame period Tf. The detailed operation of the display device of such a comparative example will be explained using FIG. 6. FIG. 6 is a diagram illustrating detailed operation of a pixel circuit included in a display device of a comparative example.

First, as shown in FIG. 6, an initialization operation is performed from time t01. Specifically, at time t01, the control device 20 controls the gate drive circuit 14 to set the control signal ENB to High level, the control signal REF to High level, and the control signal INI to High level. WS is set to Low level. As a result, the switch transistor 34 is turned off, the switch transistor 36 is turned on, the switch transistor 37 is turned on, and the selection transistor 35 is turned off. Note that in the following, the control device 20 will simply refer to the control device 20 controlling each control signal by controlling the gate drive circuit 14 or the source drive circuit 16 to control each control signal, etc. Also called.

Accordingly, the gate potential Vg of the drive transistor 33 changes to the reference potential Vref, and the source potential Vs changes to the initialization potential Vini. The source potential Vs corresponds to the anode potential of the light emitting element 32, and the anode potential is less than the sum of the light emission threshold voltage Vtel and the cathode potential Vcat (Vtel+Vcat). Therefore, the light emitting element 32 is maintained in a light-extinguished state.

Subsequently, at time t02, the control device 20 switches the control signal ENB to Low level and switches the control signal INI to Low level. As a result, the switch transistor 34 is turned on and the switch transistor 37 is turned off. Along with this, the drive potential Vcc is applied to the drain of the drive transistor 33. In this state, the gate potential Vg of the drive transistor 33 is maintained at the reference potential Vref, and the gate-source voltage converges to the threshold voltage Vth of the drive transistor 33 (threshold correction operation). This state is maintained until the following time t03. The period from time t01 to time t03 is an initialization period.

Subsequently, at time t03, the control signal REF is switched to Low level, and the control signal WS is switched to High level. As a result, the switch transistor 36 is turned off and the selection transistor 35 is turned on, so that the voltage corresponding to the video signal is applied to the pixel capacitor 38 (that is, the gate of the drive transistor 33) via the signal line 42. ) is applied to In this way, the video signal is written into the pixel capacitor 38 of the pixel circuit 30.

By applying a voltage corresponding to the video signal to the pixel capacitor 38, the gate potential Vg increases in accordance with the voltage. Along with this, the source potential Vs also rises, and the voltage across the pixel capacitor 38 becomes a voltage corresponding to the video signal. This state is maintained until the following time t04. The period from time t03 to time t04 is a signal writing period.

Subsequently, at time t04, the control signal WS is switched to Low level. As a result, the selection transistor 35 is turned off. Accordingly, a current corresponding to the gate-source voltage flows through the drive transistor 33. Here, first, the EL capacitor 39 of the light emitting element 32 is charged by the drive transistor 33. Along with this, a bootstrap operation is performed in which the anode potential of the light emitting element 32, that is, the source potential Vs of the drive transistor 33 increases. Then, at time t05, the source potential Vs of the drive transistor becomes equal to or higher than the light emission threshold voltage Vtel of the light emitting element 32, so that the light emitting element 32 starts emitting light.

In this bootstrap operation, the speed at which the source potential Vs rises (that is, the slope of the curve showing the source potential Vs in FIG. 6) changes as the gate-source voltage decreases, that is, the video signal As it grows, it becomes smaller.

Therefore, when the video signal has a low gradation, as shown in FIG. 6, the time required for the source potential Vs to rise to the emission threshold voltage Vtel is longer than when the video signal has a high gradation. . In other words, the time from the end of the signal writing period (time t04) to the start of light emission (time t05) becomes longer.

Subsequently, at time t06, as shown in FIG. 6, the control signal ENB is switched to High level. As a result, the switch transistor 34 is turned off, so that the supply of current from the drive transistor 33 to the light emitting element 32 is stopped. Accordingly, the light emitting element 32 is maintained in a light-extinguished state. This state is maintained until the following time t07. The period from time t06 to time t07 is the extinction period.

Subsequently, at time t07, the control signal ENB is returned to the Low level again. As a result, the supply of current to the light emitting element 32 is restarted, and the light emitting element 32 resumes light emission. Here, the period from time t07 until the light emitting element 32 starts emitting light does not depend on the gradation of the video signal, and the light emitting element 32 starts emitting light immediately after time t07.

Subsequently, at time t08, initialization is started similarly to time t01.

As described above, in the control method for the display device of the comparative example, especially when the video signal has a low gradation, the extinction period from time t01 to time t05 is longer than the extinction period from time t06 to time t07. significantly longer. Therefore, in the display device of the comparative example, a long extinction period from time t01 to time t05 occurs in each frame period, and flicker cannot be suppressed.

[1-5-2. Control method of display device according to the present embodiment]
A method of controlling the display device 1 according to this embodiment will be explained using FIG. 7. FIG. 7 is a diagram illustrating detailed operation of the pixel circuit 30 included in the display device 1 according to the present embodiment.

As shown in FIG. 7, in the control method for the display device 1 according to the present embodiment, the frame period in which the same image continues to be displayed is a first sub-frame period and one or more frame periods following the first sub-frame period. and a second subframe period. In the example shown in FIG. 7, the frame period has a single second subframe period. The first subframe period is a period from time t11 to time t24, and the second subframe period is a period from time t24 to time t29.

In the example shown in FIG. 7, at time t11, the control device 20 sets the control signal ENB to High level, the control signal REF to Low level, the control signal INI to Low level, and the control signal WS to Low level. are set to Low level. Thereby, by turning off the switch transistor 34, the current supply to the drive transistor 33 and the light emitting element 32 is stopped (first extinction step). Current supply to the light emitting element 32 is stopped for a predetermined extinction period. In this embodiment, the extinction period is a period from time t11 to time t22. Accordingly, the light emitting element 32 that was in the light emitting state is switched to the extinction state.

Subsequently, at time t12, the control device 20 switches the control signal REF to High level. Thereby, the reference potential Vref is applied to the gate of the drive transistor 33 by maintaining the switch transistor 36 in the on state.

Subsequently, at time t13, the control device 20 switches the control signal INI to High level. Thereby, by maintaining the switch transistor 37 in the on state, the initialization potential Vini is applied to the source of the drive transistor 33 (first initialization step).

Subsequently, at time t14, the control device 20 switches the control signal INI to Low level. As a result, the switch transistor 37 is maintained in an off state, thereby stopping the application of the initialization potential Vini to the source of the drive transistor 33.

Subsequently, at time t15, the control device 20 switches the control signal ENB to Low level. As a result, the switch transistor 34 is turned on, and current supply to the drive transistor 33 and the light emitting element 32 is started. Along with this, the gate-source voltage of the drive transistor 33 converges to a voltage equal to the threshold voltage Vth of the drive transistor 33, similar to the control method of the display device of the comparative example.

Subsequently, at time t16, the control device 20 switches the control signal REF to Low level. Thereby, by turning off the switch transistor 36, application of the reference potential Vref to the gate of the drive transistor 33 is stopped.

Subsequently, at time t17, the control device 20 switches the control signal WS to High level. As a result, the selection transistor 35 is switched on, so that the signal corresponding to the image displayed in the main frame period (that is, the signal corresponding to the video signal) is transferred to the pixel capacitor 38 (that is, the driving (write step). Along with this, the potential of the gate of the drive transistor 33 rises in accordance with the video signal.

Subsequently, at time t18, the control device 20 switches the control signal WS to Low level. As a result, the selection transistor 35 is turned off. Along with this, application of the signal corresponding to the image to the pixel capacitor 38 is stopped.

Subsequently, at time 19, the control device 20 switches the control signal ENB to High level. This turns off the switch transistor 34, thereby stopping the current supply to the drive transistor 33 and the light emitting element 32.

Subsequently, at time t20, the control device 20 switches the control signal INI to High level. Thereby, by maintaining the switch transistor 37 in the on state, the initialization potential Vini is applied to the source of the drive transistor 33 (second initialization step). Accordingly, the source potential Vs becomes the initialization potential Vini, and the gate potential Vg changes in accordance with the source potential Vs while maintaining the gate-source voltage constant.

Subsequently, at time t21, the control device 20 switches the control signal INI to Low level. As a result, the switch transistor 37 is turned off. Accordingly, application of the initialization potential Vini to the source of the drive transistor 33 is stopped.

Subsequently, at time t22, the control device 20 switches the control signal ENB to Low level. As a result, the switch transistor 34 is turned on. Accordingly, a current corresponding to the gate-source voltage of the drive transistor 33 flows. As a result, the source potential Vs increases due to the bootstrap operation, similar to the comparative example. Then, at time t23, the source potential Vs becomes equal to or higher than the light emission threshold voltage Vtel of the light emitting element 32, so that the light emitting element 32 emits light (first light emitting step). This light emission continues until time t24 when the first subframe period ends.

Subsequently, at time t24 when the second subframe period starts, the control signal ENB is switched to High level. As a result, the switch transistor 34 is turned off, so that the supply of current from the drive transistor 33 to the light emitting element 32 is stopped. Along with this, the light emitting element 32 is maintained in the extinction state (second extinction step). The current supply to the light emitting element 32 is stopped for the same extinction period as the first extinction step. In this embodiment, the extinction period is a period from time t24 to time t27.

Subsequently, at time t25, similar to the operation at time t20, the control device 20 switches the control signal INI to High level. As a result, the initialization potential Vini is applied to the source of the drive transistor 33 (third initialization step). Accordingly, the source potential Vs becomes the initialization potential Vini, and the gate potential Vg changes in accordance with the source potential Vs while maintaining the gate-source voltage.

Subsequently, at time t26, similar to the operation at time t21, the control device 20 switches the control signal INI to Low level. As a result, the switch transistor 37 is turned off.

Subsequently, at time t27, similar to the operation at time t22, the control device 20 switches the control signal ENB to Low level. As a result, a current corresponding to the gate-source voltage flows through the drive transistor 33. Along with this, the source potential Vs increases due to the bootstrap operation. Then, at time t28, the source potential Vs becomes equal to or higher than the sum (Vtel+Vcat) of the light emission threshold voltage Vtel and the cathode potential Vcat of the light emitting element 32, so that the light emitting element 32 emits light (second light emitting step). This light emission continues until time t29 when the second subframe period ends.

Here, the timing of each extinction period and each initialization period of the first subframe period and the second subframe period will be explained using FIG. 8. FIG. 8 is a timing chart showing the states of the control signal ENB and the control signal INI in the first subframe period and the second subframe period according to the present embodiment. In FIG. 8, a timing chart for the first subframe period and a timing chart for the second subframe period are shown side by side.

As shown in FIG. 8, the length of the second subframe period is equal to the length of the first subframe period. Further, the length of the extinction period in the first subframe period (that is, in the first extinction step) is equal to the length of the extinction period in the second subframe period (that is, in the second extinction step).

Further, the length of the period from the start point of the first subframe period (time t11 shown in FIG. 7) to the end point of the second initialization step (time t21 shown in FIG. 7) is the same as that of the second subframe period. is equal to the length of the period from the start point (time t24 shown in FIG. 7) to the end point (time t26 shown in FIG. 7) of the third initialization step.

Furthermore, in this embodiment, the length of the period from the start time of the first subframe period (time t11 shown in FIG. 7) to the start time of the first initialization step (time t13 shown in FIG. 7) is , is equal to the length of the period from the start time of the second subframe period (time t24 shown in FIG. 7) to the start time of the third initialization step (time t25 shown in FIG. 7).

As described above, the method for controlling the display device 1 according to the present embodiment includes the first extinction step of maintaining the light emitting element 32 in the extinction state for a predetermined extinction period in the first subframe period, and the first extinction step. After that, a first light emitting step of causing the light emitting element 32 to emit light is included. In addition, the method for controlling the display device 1 according to the present embodiment includes, in each of the one or more second subframe periods, a second extinction step of maintaining the light emitting element 32 in the extinction state over the extinction period, and a second extinction step. After that, a second light emitting step of causing the light emitting element 32 to emit light is included. The first extinction step includes a first initialization step of applying a predetermined initialization potential Vini to the source of the drive transistor 33, and, after the first initialization step, a signal corresponding to the image displayed in the frame period. The process includes a write step of applying the voltage to the capacitance, and a second initialization step of applying the initialization potential Vini to the source of the drive transistor 33 for an initialization period after the write step. The second extinction step includes a third initialization step of applying an initialization potential Vini to the source of the drive transistor 33.

In this way, by initializing the source potential Vs of the drive transistor 33 after the write step in the first subframe period and in the second subframe period, the second initial stage in the first subframe period can be initialized. The source potential Vs of the drive transistor 33 immediately after the initialization step and immediately after the third initialization step in the second subframe period can be equalized to the initialization potential Vini. Therefore, by the bootstrap operation, the time required for the source potential Vs to rise to the sum of the light emission threshold voltage Vtel and the cathode potential Vcat can be made equal between the first subframe period and the second subframe period. In other words, it is possible to suppress the difference in light emission start timing between the first subframe period and the second subframe period. Therefore, according to the display device 1 according to the present embodiment, the occurrence of flicker can be suppressed compared to the display device of the comparative example.

Furthermore, in this embodiment, the length of the first subframe period is equal to the length of the second subframe period, and the period from the start of the first subframe period to the end of the second initialization step The length of is equal to the length of the period from the start of the second subframe period to the end of the third initialization step. Thereby, it is possible to further suppress the deviation in the light emission start timing between the first subframe period and the second subframe period. Also, the length of the period from the end of the second initialization step to the end of the first subframe period, and the length of the period from the end of the third initialization step to the end of the second subframe period. It is possible to match the height. Therefore, the length of the light emission period in the first subframe period and the length of the light emission period in the second subframe period can be made equal. Therefore, according to the display device 1 according to the present embodiment, the occurrence of flicker can be further suppressed.

As described above, the method for controlling the display device 1 according to the present embodiment includes the second initialization step and the third initialization step, thereby changing the source potential Vs of the drive transistor 33 to the initialization potential Vini. However, in reality, the potential of the power supply line 44 to which the initialization potential Vini is applied fluctuates. Specifically, the potential of the power line 44 fluctuates due to the voltage drop in the power line 44 . The voltage drop in the power supply line 44 increases as the length of the wiring from the power supply circuit 18 to the pixel circuit 30 increases.

When initializing the source potential Vs of the drive transistor 33 to the initialization potential Vini, by keeping the switch transistor 37 in the on state, the EL capacitor 39 is Discharge the charge that was accumulated in the This operation is performed almost simultaneously in a plurality of pixel circuits 30 connected to the same scanning line 40. The total charge of the EL capacitor 39 is approximately 0.1 μF or more and several tens of μF or less, although it depends on the size of the screen. Even if it is assumed that the change in the source potential Vs of the drive transistor 33 before and after initialization is 10 V or less, the discharge current immediately after the start of initialization can reach nearly 100 mA. The effect of temporarily storing the discharge current from the pixel circuit 30 in the power supply line 44 is achieved by utilizing the parasitic capacitance of the power supply line 44 itself (capacitance that is 0.5 times or more and less than 2 times the capacity of the EL capacitor 39). Even if it is used, a voltage drop of several hundred mV occurs due to the resistance of the power supply line 44 through which the discharge current flows.

In particular, when the switch transistor 37 that controls the application of the initialization potential Vini is directly connected to the source of the drive transistor 33 as in this embodiment, the switch transistor 37 is connected to the drain of the drive transistor 33. Since the amount of charge discharged to the power supply line 44 in the initialization step is larger than that in the case where the power supply line 44 is connected, the potential fluctuation becomes even larger.

Furthermore, during the frame period, the potential of the power supply line 44 is changed depending on the number of pixel circuits 30 to be initialized (in other words, the number of rows to be initialized among the plurality of pixel circuits 30 arranged in a matrix). The amount of change fluctuates. The potential fluctuation of the power supply line 44 to which the initialization potential Vini is applied will be explained using FIGS. 9 to 11. 9 and 10 are a first schematic diagram and a second schematic diagram, respectively, showing the positions of rows to be initialized on the display unit 12 of the display device 1 according to the present embodiment. FIG. 11 is a diagram schematically showing a time waveform of the potential of the power supply line 44 to which the initialization potential Vini of the display device 1 according to the present embodiment is applied.

9 and 10, the number of lines included in one frame (that is, the number of horizontal synchronization signals included in one frame) is 120, and the rows of a plurality of pixel circuits 30 arranged in a matrix on the display section 12 are shown. An example is shown in which the number (the number of display lines on the display panel 10) is 100, the light emission duty is 75%, and each subframe period corresponds to 40 horizontal scanning periods. That is, of the 40 rows of pixel circuits 30, 10 rows of pixel circuits 30 are maintained in the extinguished state. In FIGS. 9 and 10, rows that are maintained in the extinction state are hatched. Further, FIG. 10 shows the state of the display section 12 after 20 horizontal scanning periods at the timing shown in FIG.

As shown in FIGS. 9 and 10, the number of rows maintained in the extinction state differs depending on the timing in the frame period. At the timing shown in FIG. 9, the pixel circuits 30 for 30 rows are maintained in the extinguished state, but at the timing shown in FIG. 10, the pixel circuits 30 for 20 rows are maintained in the extinguished state. In other words, the number of rows to be initialized differs depending on the timing in the frame period. Therefore, the amount of charge discharged from the source of the drive transistor 33 to the power supply line 44 to which the initialization potential Vini is applied varies depending on the timing of the frame period. Accordingly, as shown in FIG. 11, the potential of the power supply line 44 to which the initialization potential Vini is applied changes in accordance with the timing of each subframe period.

When the potential of the power supply line 44 fluctuates as shown in FIG. 11, the source potential Vs of the drive transistor 33 to be initialized differs depending on the timing of initialization. Along with this, the deviation in the source potential Vs before the bootstrap operation increases, and therefore the deviation in the light emission timing of the light emitting element 32 in each subframe period increases. Therefore, the brightness of the light emitting element 32 changes in accordance with fluctuations in the potential of the power supply line 44. In other words, uneven brightness occurs in the image displayed by the display unit 12.

In this embodiment, as described above, the length of the period from the start of the first subframe period to the end of the second initialization step is the same as the length of the period from the start of the second subframe period to the end of the third initialization step. equal to the length of the period up to the end of . That is, in each subframe period, the end timings of each initialization step are aligned. Here, as shown in FIG. 11, since the potential fluctuation of the power supply line 44 fluctuates at the same period as the subframe period, by aligning the end timing of each initialization step in each subframe period, each initialization step can be completed at the same time. The source potentials Vs of the drive transistors 33 at the end of the conversion step can be made equal. Thereby, it is possible to suppress the deviation in the light emission start timing between the first subframe period and the second subframe period. Therefore, brightness unevenness in the image displayed by the display unit 12 can be suppressed.

Further, in this embodiment, as shown in FIG. 7, the first initialization step starts after the first extinction step starts, and the third initialization step starts after the second extinction step starts. In other words, the first initialization section 22 of the control device 20 starts applying the initialization potential Vini after the first extinction section 21 stops supplying current to the light emitting element 32, and the third initialization section 26 starts applying the initialization potential Vini. After the second quenching section 25 stops supplying current to the light emitting element 32, application of the initialization potential Vini is started.

In this way, by performing each initialization step after starting the first extinction step and the second extinction step, the source potential Vs of the drive transistor 33 at the start of each initialization step can be lowered. Therefore, in the initialization step, the amount of discharge to the power supply line 44 can be reduced by the amount of charge corresponding to the reduction in potential. Thereby, potential fluctuations of the power supply line 44 can be reduced.

Furthermore, the length of the period from the start time of the first subframe period (time t11 shown in FIG. 7) to the start time of the first initialization step (time t13 shown in FIG. 7) is equal to one or more second subframe periods. It is equal to the length of the period from the start time of each subframe period (time t24 shown in FIG. 7) to the start time of the third initialization step (time t25 shown in FIG. 7). In other words, the length of the period from the start of the first subframe period to the start of application of the initialization potential Vini of the first initialization unit 22 is the same as the length of the period from the start of each of the one or more second subframe periods to the start of application of the initialization potential Vini of the first initialization unit 22. It is equal to the length of the period up to the point in time when the initialization potential Vini of the third initialization section 26 starts being applied. This makes it possible to equalize the amount of decrease in the source potential Vs of the drive transistor 33 in each extinction step, so that the source potential Vs of the drive transistor 33 at the start of the initialization step can be made equal. Therefore, it is possible to equalize the amount of potential fluctuation in each subframe period of the power supply line 44 to which the initialization potential Vini is applied.

The length of the period from the start of the first subframe period to the start of the first initialization step, and the length of the period from the start of each of the one or more second subframe periods to the start of the third initialization step. The length of the period may be, for example, one horizontal scanning period or more, five horizontal scanning periods or more, or nine horizontal scanning periods or more. By increasing the length of the period, the source potential Vs of the drive transistor 33 in each extinction step can be sufficiently lowered.

Furthermore, in the present embodiment, in the third initialization step, the initialization potential Vini is continuously applied to the source of the drive transistor 33 from the start to the end of the third initialization step. In other words, the third initialization section 26 continuously applies the initialization potential Vini during the extinction period from when it starts applying the initialization potential Vini until it finishes applying the initialization potential Vini.

Thereby, the difference in potential between the source potential Vs of the drive transistor 33 at the end of the third initialization step and the power supply line 44 to which the initialization potential Vini is applied can be reduced. In other words, the source potential Vs of the drive transistor 33 can be reliably initialized.

In this embodiment, the operation of initializing the source potential Vs of the drive transistor 33 to Vini includes a first initialization step to a third initialization step. In the first initialization step of these initialization steps, in order to apply the potential necessary to start the subsequent threshold correction operation of the drive transistor 33 to the source of the drive transistor 33, the variation range of the source potential Vs is is not as large as other initialization steps. It is sufficient that the source potential Vs of the drive transistor 33 after the threshold value correction operation is Vref-Vth. Further, the second initialization step is executed immediately after writing the video signal. Therefore, in the second initialization step, the source potential Vs is initialized from a potential that is increased from Vref-Vth by the voltage α corresponding to the video signal, so the potential difference before and after the initialization is relatively small. Therefore, initialization can be performed relatively easily in the second initialization step. Note that the voltage α corresponding to the video signal depends on the capacitance size of each of the pixel capacitor 38 and the EL capacitor 39, but is determined by the difference between the voltage corresponding to the video signal corresponding to the peak luminance and the reference potential Vref. The value is approximately 10% or more and 60% or less.

On the other hand, in the third initialization step, the source potential Vs of the drive transistor 33 before initialization is the sum of the voltage applied to the light emitting element 32 corresponding to the peak luminance and the cathode potential Vcat in the case where the source potential Vs of the drive transistor 33 before initialization becomes the highest. The potential is lower than the corresponding potential by the potential drop before the initialization of the second quenching step. Immediately before the third initialization step, the source potential Vs of the drive transistor 33 is Vtel+Vcat even after waiting for the discharge of the EL capacitor 39 to be completed after the start of the second extinction period. Therefore, in the third initialization step, it is necessary to lower the source potential Vs from a potential equal to or higher than Vtel+Vcat to the initialization potential Vini.

On the other hand, regarding the source potential Vs (=Vref−Vth+α) immediately before the second initialization step, the following inequality holds between the light emission threshold voltage Vtel and the cathode potential Vcat.

Vref-Vth+α<Vtel+Vcat

Therefore, the source potential Vs (=Vtel+Vcat) immediately before the third initialization step is higher than the source potential Vs (<Vtel+Vcat) immediately before the second initialization step.

As described above, in the third initialization step, the fluctuation range of the source potential Vs is larger than in the second initialization step.

In the second initialization step and the third initialization step, as described above, a reference potential is applied to the source of the drive transistor 33 before the light emitting element 32 transitions from the non-emitting state to the emitting state; When the potential changes, the length of the light emission period changes, which can cause flicker. Since the fluctuation range of the source potential Vs is larger in the third initialization step than in the second initialization step, in the third initialization step, the initialization potential Vini is continued to be applied to the source of the drive transistor 33 for as long as possible. It is effective to apply this to improve flicker.

In this embodiment, initialization is performed in a plurality of consecutive rows, as shown in FIGS. 9 and 10. That is, the sources of the drive transistors 33 included in the pixel circuits 30 in multiple rows are simultaneously connected to the power supply line 44 to which the initialization potential Vini is applied.

Therefore, when initialization of the source of the driving transistor 33 of one pixel circuit 30 is started, the source of the driving transistor 33 of the pixel circuit 30 located below the pixel circuit 30 (lower in FIGS. 9 and 10) has already started initialization and is maintained at the initialization potential Vini or a potential close to it. Therefore, the voltage is discharged from the source of the pixel circuit 30 where initialization is started not only to the power supply circuit 18 via the power supply line 44 but also to the source of the drive transistor 33 of the pixel circuit 30 below. In this way, it is possible to discharge from the source of the drive transistor 33 not only to the power supply circuit 18 but also to the source of the drive transistor 33 of the pixel circuit 30 below, so that potential fluctuations in the power supply line 44 can be reduced.

In addition, although the case where the scanning direction in the display panel 10 is from the top to the bottom in FIGS. 9 and 10 has been described above, the scanning direction in the display panel 10 is not limited to this, and is It may be directed upwards. In this case, when initialization of the source of the drive transistor 33 of one pixel circuit 30 is started, the drive transistor 33 of the pixel circuit 30 located above the pixel circuit 30 (upper in FIGS. 9 and 10) is The source has already started initialization.

As described above, in this embodiment, when the initialization of the source of the drive transistor 33 of one pixel circuit 30 is started, the source of the drive transistor 33 of the other pixel circuit 30 whose initialization has already started is By utilizing the discharge to, potential fluctuations in the power supply line 44 can be reduced.

The length of the initialization period in the third initialization step may be 50% or more of the length of the extinction period. As a result, discharging can be performed via the power supply line 44 for a long time, and the EL connected to the source of the drive transistor 33 of the pixel circuit 30 that started the third initialization step earlier than the pixel circuit 30 concerned Since charge transfer from the capacitor 39 can also be used, the source of the drive transistor 33 can be reliably initialized. Further, the length of the initialization period in the third initialization step may be 75% or more of the length of the extinction period. Thereby, the source of the drive transistor 33 can be initialized more reliably.

(Embodiment 2)
A display device and a method of controlling the display device according to Embodiment 2 will be described. The display device according to the present embodiment differs from the display device 1 according to the first embodiment in that it includes a dummy pixel circuit. The display device and the method of controlling the display device according to the present embodiment will be described below, focusing on the differences from the display device and the method of controlling the display device according to the first embodiment.

The configuration of the display device according to this embodiment will be described using FIG. 12. FIG. 12 is a schematic diagram showing a configuration example of display device 101 according to this embodiment. The display device 101 includes a display panel 110 and a control device 20, as shown in FIG. The display panel 110 includes a display section 12, a gate drive circuit 14, a source drive circuit 16, and a power supply circuit 18. In this embodiment, display panel 110 further includes one or more dummy pixel circuits 130. Here, an example of the circuit configuration of the dummy pixel circuit 130 will be described using FIG. 13. FIG. 13 is a circuit diagram showing a configuration example of the dummy pixel circuit 130 according to this embodiment.

As shown in FIG. 13, the dummy pixel circuit 130 includes a light emitting element 32. It has the same configuration as the light emitting element 32 included in the pixel circuit 30. Thereby, the dummy pixel circuit 130 can be formed at the same time as the pixel circuit 30 is formed, so that the manufacturing process of the display device 101 can be simplified. As described above, the light emitting element 32 has the EL capacitor 39. The light emitting element 32 included in the dummy pixel circuit 130 is an example of a capacitive element included in the dummy pixel circuit 130. An initialization potential Vini is applied to the anode of the light emitting element 32 via a power supply line 44.

The control device 20 according to the present embodiment connects the source of the drive transistor 33 of at least one pixel circuit 30 among the plurality of pixel circuits 30 and the capacitive element (in the present embodiment) of each of the one or more dummy pixel circuits. A third initialization section 26 is provided as an initialization section that applies an initialization potential Vini to the light emitting element 32). In other words, in the third initialization step, the source of the drive transistor 33 of at least one pixel circuit 30 among the plurality of pixel circuits 30 and the capacitor of each of the one or more dummy pixel circuits 130 are set at the initialization potential. Apply Vini. In this manner, in this embodiment, not only the source of the drive transistor 33 of the pixel circuit 30 but also the light emitting element 32 of the dummy pixel circuit 130 is initialized. Note that in this embodiment, the initialization potential Vini is always applied to the light emitting element 32 of the dummy pixel circuit 130. In this way, when initialization of the source of the drive transistor 33 of one pixel circuit 30 is started, the light emitting element 32 of the dummy pixel circuit 130 can already be initialized. Therefore, the source of the pixel circuit 30 where initialization is started can be discharged not only to the power supply circuit 18 via the power supply line 44 but also to the light emitting element 32 of the dummy pixel circuit 130. In this way, it is possible to discharge from the source of the drive transistor 33 not only to the power supply circuit 18 but also to the light emitting element 32 of the dummy pixel circuit 130, so that fluctuations in the potential of the power supply line 44 can be reduced.

Note that the light emitting element 32 included in the dummy pixel circuit 130 may be, for example, a blue light emitting element 32. Generally, in an organic EL element, the film thickness between the anode and cathode of the light emitting element 32 for blue color is smaller than the film thickness between the anode and cathode of the light emitting element 32 for red or green color. Therefore, by using the blue light emitting element 32 in the dummy pixel circuit 130, the capacity (EL capacity) of the light emitting element 32 can be made larger than when using the red or green light emitting element 32. .

Further, the configuration of the dummy pixel circuit 130 is not limited to the example shown in FIG. 13. The dummy pixel circuit 130 only needs to have a capacitive element. For example, as the capacitive element, a capacitive element having an anode and a cathode similar to those of the light emitting element 32, and having only the thinnest film among the films that the light emitting element 32 has between the anode and the cathode may be used. Thereby, the capacitance of the capacitive element of the dummy pixel circuit 130 can be increased while suppressing the complexity of the manufacturing process.

Further, the dummy pixel circuit 130 may be a capacitive element. In other words, the dummy pixel circuit 130 does not need to have any components other than the capacitive element.

Furthermore, the dummy pixel circuit 130 may have the same configuration as the pixel circuit 30. In this case, the switch transistor 37 that controls the application of the initialization potential Vini may be kept in an on state at all times.

Further, the dummy pixel circuit 130 may be placed outside the display section 12 in the vertical direction (vertical direction in FIG. 12) or outside the display section 12 in the horizontal direction (horizontal direction in FIG. 12). Good too. Further, the dummy pixel circuit 130 may be arranged near the inner edge of the display section 12.

(Other embodiments)
The display device and the control method thereof according to the present disclosure have been described above based on each embodiment, but the display device and the control method thereof according to the present disclosure are limited to the above-mentioned embodiments. isn't it. The present disclosure also includes modifications obtained by making various modifications to the embodiments that can be thought of by those skilled in the art without departing from the gist of the present disclosure.

For example, in each of the above embodiments, the initialization potential Vini is continuously applied in the third initialization step, but the application of the initialization potential Vini is temporarily stopped in the middle of the third initialization step. Good too. In other words, the third initialization section 26 temporarily performs initialization during the extinction period from when it first starts applying the initialization potential Vini until it finally ends the application of the initialization potential Vini. Application of the potential Vini may be stopped.

Moreover, the first initialization step may start simultaneously with the start of the first extinction step. Moreover, the third initialization step may start simultaneously with the start of the second extinction step. In other words, the first initialization section 22 may start applying the initialization potential Vini at the same time as the first extinction section 21 stops supplying current to the light emitting element 32. The third initialization section 26 may start applying the initialization potential Vini at the same time as the second extinction section 25 stops supplying current to the light emitting element 32.

Furthermore, the length of the period from the start of the first subframe period to the start of the first initialization step is the length of the period from the start of each of the one or more second subframe periods to the start of the third initialization step. does not have to be equal to the length of the period. In other words, the length of the period from the start of the first subframe period to the start of application of the initialization potential Vini of the first initialization unit 22 is the same as the length of the period from the start of each of the one or more second subframe periods to the start of application of the initialization potential Vini of the first initialization unit 22. It does not have to be equal to the length of the period up to the point in time when the application of the initialization potential Vini of the initialization section 26 starts.

Further, the configuration of the plurality of pixel circuits 30 is not limited to the configuration example shown in FIG. 2. Other configuration examples of the plurality of pixel circuits 30 will be described below with reference to FIGS. 14 and 15. 14 and 15 are circuit diagrams showing the configurations of a pixel circuit 30a according to a first modification and a pixel circuit 30b according to a second modification, respectively.

Like the pixel circuit 30a according to Modification 1 shown in FIG. 14, the pixel circuit according to the present disclosure may not include the switch transistor 34, and the drive potential Vcc may be directly applied to the drain of the drive transistor 33. Furthermore, like the pixel circuit 30b according to Modification Example 2 shown in FIG. 15, the pixel circuit according to the present disclosure does not need to include the switch transistor 36. The pixel circuit according to the present disclosure may have any configuration as long as it can apply the initialization potential Vini to the source of the drive transistor 33.

Additionally, the embodiments described below may also be included within the scope of one or more aspects of the present disclosure.

(1) Some of the components included in each of the above display devices (for example, the control device 20, etc.) are computer systems consisting of a microprocessor, ROM, RAM, hard disk unit, display unit, keyboard, mouse, etc. There may be. A computer program is stored in the RAM or hard disk unit. The microprocessor achieves its functions by operating according to the computer program. Here, a computer program is configured by combining a plurality of instruction codes indicating instructions to a computer in order to achieve a predetermined function.

(2) Some of the components included in each of the above display devices may be configured from one system LSI (Large Scale Integration). A system LSI is a super-multifunctional LSI manufactured by integrating multiple components onto a single chip, and specifically, it is a computer system that includes a microprocessor, ROM, RAM, etc. . A computer program is stored in the RAM. The system LSI achieves its functions by the microprocessor operating according to the computer program.

(3) Some of the components included in each of the display devices described above may be composed of an IC card or a single module that is removably attached to each device. The IC card or the module is a computer system composed of a microprocessor, ROM, RAM, etc. The IC card or the module may include the above-mentioned super multifunctional LSI. The IC card or the module achieves its functions by the microprocessor operating according to a computer program. This IC card or this module may be tamper resistant.

(4) Some of the components included in each of the display devices described above may store the computer program or the digital signal on a computer-readable recording medium, such as a flexible disk, hard disk, CD-ROM, MO, or DVD. , DVD-ROM, DVD-RAM, BD (Blu-ray (registered trademark) Disc), semiconductor memory, or the like. Alternatively, the signal may be the digital signal recorded on these recording media.

Further, some of the components included in each of the above display devices transmit the computer program or the digital signal via a telecommunications line, a wireless or wired communication line, a network typified by the Internet, data broadcasting, etc. It may also be transmitted.

(5) The present disclosure may be a method of controlling the display device described above. Further, it may be a computer program that implements the control method described above by a computer, or it may be a digital signal formed from the computer program. Further, the present disclosure may be realized as a non-transitory computer-readable recording medium such as a CD-ROM on which the computer program is recorded.

(6) The present disclosure also provides a computer system including a microprocessor and a memory, wherein the memory stores the computer program, and the microprocessor may operate according to the computer program. .

(7) Also, by recording the program or the digital signal on the recording medium and transferring it, or by transferring the program or the digital signal via the network etc. It may be implemented by a system.

The present disclosure is particularly useful in technical fields such as television systems, game consoles, and personal computer displays that can be driven at low refresh rates.

1, 101 display device 10, 110 display panel 12 display section 14 gate drive circuit 16 source drive circuit 18 power supply circuit 20 control device 21 first extinction section 22 first initialization section 23 writing section 24 second initialization section 25 Second quenching section 26 Third initialization section 27 First light emitting section 28 Second light emitting section 30, 30a, 30b Pixel circuit 32 Light emitting element 33 Drive transistor 34, 36, 37 Switch transistor 35 Selection transistor 38 Pixel capacitor 39 EL capacitor 40 Scanning Line 42 Signal line 44 Power line 130 Dummy pixel circuit

Claims (17)

A method for controlling a display device, the method comprising:
The display device includes a plurality of pixel circuits,
Each of the plurality of pixel circuits includes a light emitting element, a drive transistor, and a pixel capacitor,
The drive transistor has a gate, a source, and a drain,
the light emitting element is connected to the source,
One end and the other end of the pixel capacitor are connected to the gate and the source, respectively,
A frame period in which the same image is displayed on the display device includes a first subframe period and one or more second subframe periods following the first subframe period,
The length of each of the one or more second subframe periods is equal to the length of the first subframe period,
The method for controlling the display device includes:
In the first subframe period,
a first quenching step of maintaining the light emitting element in a quenched state for a predetermined quenching period;
After the first quenching step, a first light emitting step of causing the light emitting element to emit light,
In each of the one or more second subframe periods,
a second quenching step of maintaining the light emitting element in a quenched state over the quenching period;
a second light emitting step of causing the light emitting element to emit light after the second extinction step,
The first quenching step includes:
a first initialization step of applying a predetermined initialization potential to the source;
After the first initialization step, a writing step of applying a signal corresponding to the image to the pixel capacitance;
a second initialization step of applying the initialization potential to the source for a predetermined initialization period after the write step;
The second extinction step includes a third initialization step of applying the initialization potential to the source,
The length of the period from the start of the first subframe period to the end of the second initialization step is the length of the period from the start of each of the one or more second subframe periods to the end of the third initialization step. equal to the length of the period up to the point in time How the display device is controlled. The method for controlling a display device according to claim 1, wherein the third initialization step starts after the second extinction step starts. The length of the period from the start of the first subframe period to the start of the first initialization step is the length of the period from the start of each of the one or more second subframe periods to the start of the third initialization step. The method for controlling a display device according to claim 2, wherein the length is equal to the length of the period up to the point in time. The display according to any one of claims 1 to 3, wherein in the third initialization step, the initialization potential is continuously applied to the source from the start to the end of the third initialization step. How to control the device. The method for controlling a display device according to claim 1, wherein the length of the initialization period is 50% or more of the length of the extinction period. The display device further includes one or more dummy pixel circuits,
Each of the one or more dummy pixel circuits has a capacitive element,
In the third initialization step, the initialization potential is applied to the source of the drive transistor of at least one pixel circuit among the plurality of pixel circuits and to the capacitor of each of the one or more dummy pixel circuits. The method for controlling a display device according to any one of claims 1 to 3, further comprising applying: A display device,
multiple pixel circuits,
and a control device that controls the plurality of pixel circuits,
Each of the plurality of pixel circuits includes a light emitting element, a drive transistor, and a pixel capacitor,
The drive transistor has a gate, a source, and a drain,
the light emitting element is connected to the source,
One end and the other end of the pixel capacitor are connected to the gate and the source, respectively,
A frame period in which the same image is displayed on the display device includes a first subframe period and one or more second subframe periods following the first subframe period,
The length of each of the one or more second subframe periods is equal to the length of the first subframe period,
The control device includes:
a first light-extinguishing section that stops to maintain the light-emitting element in a light-off state for a predetermined light-off period in the first subframe period;
a first light emitting unit that causes the light emitting element to emit light by supplying current to the light emitting element in the first subframe period;
a second light-extinguishing section that maintains the light emitting element in a light-off state over the light-off period in each of the one or more second subframe periods;
a second light emitting section that causes the light emitting element to emit light by supplying current to the light emitting element in each of the one or more second subframe periods;
The first quenching section is
a first initialization section that applies a predetermined initialization potential to the source over a predetermined initialization period;
a writing unit that applies a signal corresponding to the image to the pixel capacitor;
a second initialization unit that applies the initialization potential to the source,
The second extinction section includes a third initialization section that applies the initialization potential to the source for a predetermined initialization period,
The length of the period from the start of the first subframe period to the time when the second initialization unit finishes applying the initialization potential is the length of the period from the start of each of the one or more second subframe periods. The display device is equal to the length of the period up to the point in time when the third initialization section finishes applying the initialization potential. The display device according to claim 7, wherein the third initialization section starts applying the initialization potential after the second extinction section stops supplying current to the light emitting element. The length of the period from the start of the first subframe period to the start of application of the initialization potential of the first initialization section is equal to the length of the period from the start of each of the one or more second subframe periods 9. The display device according to claim 8, wherein the length of the period is equal to the length of the period up to the point in time when application of the initialization potential of the three initialization units starts. The third initialization section continuously applies the initialization potential during the extinction period from when it first starts applying the initialization potential until it finally ends the application of the initialization potential. The display device according to any one of claims 7 to 9. The display device according to claim 7, wherein the length of the initialization period is 50% or more of the length of the extinction period. further comprising one or more dummy pixel circuits,
Each of the one or more dummy pixel circuits has a capacitive element,
The third initialization unit applies the initialization potential to the source of the drive transistor of at least one pixel circuit among the plurality of pixel circuits and to the capacitor of each of the one or more dummy pixel circuits. The display device according to any one of claims 7 to 9, wherein: The display device according to claim 12, wherein the capacitive element has the same configuration as the light emitting element. The display device according to claim 12, wherein each of the one or more dummy pixel circuits is the capacitive element. A display device,
multiple pixel circuits,
one or more dummy pixel circuits,
and a control device that controls the plurality of pixel circuits,
Each of the plurality of pixel circuits includes a light emitting element, a drive transistor, and a pixel capacitor,
The drive transistor has a gate, a source, and a drain,
the light emitting element is connected to the source,
One end and the other end of the pixel capacitor are connected to the gate and the source, respectively,
Each of the one or more dummy pixel circuits has a capacitive element,
The control device applies a predetermined initialization potential to the source of the drive transistor of at least one pixel circuit among the plurality of pixel circuits and to the capacitor of each of the one or more dummy pixel circuits. A display device having an initialization section that performs. The display device according to claim 15, wherein the capacitive element has the same configuration as the light emitting element. The display device according to claim 15 or 16, wherein each of the one or more dummy pixel circuits is the capacitive element.

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