JP2023551309A - How to make flip chip micro light emitting diode - Google Patents

Abstract

A micro-light emitting diode (uLED) device includes a mesa having multiple semiconductor layers including an n-type layer, an active layer, and a p-type layer, and a p-contact layer in contact with the p-type layer, and a first layer of the n-type layer. a cathode in contact with a sidewall; a first region of dielectric material insulating the p-contact layer, the active layer, and a first sidewall of the p-type layer from the cathode; and the top surface of the p-contact layer. and a second region of dielectric material insulating the active layer, a second sidewall of the p-type layer, and the second sidewall of the n-type layer from the anode. The top surface of the p-contact layer has a different planar orientation than the first and second sidewalls of the n-type layer. Also provided are methods of making and using uLED devices.

Description

Embodiments of the present disclosure generally relate to micro light emitting diode (micro LED or uLED or μLED) devices and methods of manufacturing the same. More particularly, the present embodiment relates to an individual micro light emitting diode device having a thin film flip chip (TFFC) design, said design comprising a cathode in contact with the first sidewall of the n-type layer and a top part of the p-contact layer. With the anode in contact with the surface, the first sidewall of the n-type layer and the top surface of the p-contact layer are in two different planar orientations.

A light emitting diode (LED) is a semiconductor light source that emits visible light when an electric current is passed through it. LEDs are composed of a combination of p-type and n-type semiconductors. Typically, LEDs use III-V compound semiconductors. III-V compound semiconductors provide stable operation at high temperatures compared to devices using other semiconductors. III-V compounds are typically formed on substrates made of sapphire aluminum oxide (Al ₂ O ₃ ) or silicon carbide (SiC).

A variety of emerging display applications, including wearable devices, head-mounted displays, and large-area displays, rely on small chips consisting of arrays of dense micro-LEDs (μLEDs or uLEDs) with lateral dimensions less than 100μm x 100μm. It becomes necessary. Micro-LEDs typically have a diameter or width of about 50 μm or less, smaller than those used in the manufacture of color displays, by closely arranging uLEDs containing red, blue, and green wavelengths. The approach for assembling displays made up of individual dies is referred to as "pick and place" of individual LEDs. The pick-and-place (or pick-and-place) approach consists of a pick-up step, an alignment step, followed by mounting the individual blue, green, and red wavelength micro-LEDs onto the backplane, then attaching the backplane to the driver electrically connecting to the integrated circuit. Due to the small size of each micro-LED, this assembly sequence is slow and prone to manufacturing errors. Additionally, to meet increasing resolution requirements for displays, die size decreases and a greater number of dies must be transferred in each pick-and-place operation to form a display of the required dimensions. .

The devices used for standalone uLED pixels or pick-and-place assembly fall into two broad categories: thin film flip chip (TFFC) or vertical thin film (VTF). Each has its own advantages and applications, and limitations regarding their typical design. TFFC designs typically offer lower forward voltage, higher current drive capability, and therefore higher brightness and efficiency performance. VTF designs, on the other hand, offer easier size reduction for smaller, more dense micro-LED designs.

For many standalone micro-LED devices, the goal is to manufacture them reliably and efficiently, and the micro-LED devices themselves need to be efficient. Efficient fabrication of stand-alone micro-LED pixels facilitates the use of micron-sized spacing for effective light transmission. Additionally, there remains a need to maximize the light emitting area while improving the handling and processing of stand-alone micro-LEDs.

Light sources and methods of manufacturing them are provided herein. uLED with thin film flip chip (TFFC) design combines the advantages of both thin film flip chip (TFFC) and vertical thin film (VTF) architectures through a dimensionally reducible design while maximizing the epitaxy light emitting area (LEA). It is significant in that it provides This design also maximizes light output extraction.

In some embodiments, the micro-light emitting diode (uLED) device comprises:
Mesa,
a plurality of semiconductor layers including an n-type layer, an active layer, and a p-type layer;
a p-contact layer in contact with the p-type layer;
and the mesa has a height extending from a top surface of the p-contact layer to a bottom surface of the n-type layer and a width extending from a first sidewall of the n-type layer to a second sidewall of the n-type layer. a mesa, the top surface of the p-contact layer having a different planar orientation than the first and second sidewalls of the n-type layer;
a cathode in contact with the first sidewall of the n-type layer;
a first region of dielectric material insulating the p-contact layer, the active layer, and a first sidewall of the p-type layer from the cathode;
an anode in contact with the upper surface of the p-contact layer;
a second region of dielectric material insulating the active layer, the second sidewall of the p-type layer, and the second sidewall of the n-type layer from the anode;
has.

In another aspect, the display device includes:
backplane and
a plurality of individually positioned uLED devices attached to the backplane, each of the uLED devices having a uLED device as described in any embodiment of the present application;
a housing including a display surface surrounding the plurality of individually disposed uLED devices;
has.

Another aspect has a method of manufacturing a micro-light emitting diode (uLED) device, comprising:
The method is
Depositing a plurality of semiconductor layers including an n-type layer, an active layer, and a p-type layer on the substrate;
forming a p-contact layer on the plurality of semiconductor layers;
depositing a hard mask layer on the p-contact layer;
etching a portion of the semiconductor layer, the p-contact layer, and the hardmask layer to form a trench and a plurality of mesas, each mesa extending from the top surface of the p-contact layer to the n-contact layer; a step having a height extending to a bottom surface of a mold layer and a width extending from a first sidewall of the n-type layer to a second sidewall of the n-type layer;
depositing a dielectric metal across the substrate, in the trench and on the top surface of the substrate;
exposing the p-contact layer and a first portion of the surface of the substrate by a first etch;
exposing the n-type layer and a second portion of the surface of the substrate by a second etch;
forming a first metal film in the region exposed by the first etching and the second etching;
forming a cathode and an anode insulated from each other by etching;
has
Each of the above steps forms a processing structure.

Another aspect is a method of manufacturing a display device,
The method is
attaching a plurality of micro light emitting diodes (uLEDs) to the backplane using a pick and place method;
enclosing the plurality of LEDs in a housing having a display surface;
has
Each of the uLEDs includes a uLED device as described in embodiments of the present application.

In order that the above-described features of the disclosure may be understood in detail, a more specific description of the present disclosure, which has been briefly summarized above, may be obtained by reference to the embodiments. Some of the embodiments are illustrated in the accompanying drawings. It should be understood, however, that the accompanying drawings depict only typical embodiments of the present disclosure and are not intended to limit the scope of the present disclosure, as the present disclosure recognizes other equally effective embodiments. It is necessary to keep this in mind. The embodiments described herein are shown by way of example and are not limited to the illustrations in the accompanying drawings. Like reference numbers represent like elements. The drawings are not shown to scale.

3 illustrates a cross-section of a stack of a semiconductor layer, a metal layer (e.g., a p-contact layer or a p-metal reflective layer), and a dielectric layer (e.g., a hardmask layer) deposited on a substrate, according to one or more embodiments; FIG. It is a diagram. FIG. 3 illustrates a cross-section of a stack after a step in manufacturing an LED device in accordance with one or more embodiments. FIG. 3 illustrates a cross-section of a stack after a step in manufacturing an LED device in accordance with one or more embodiments. FIG. 3 illustrates a cross-section of a stack after a step in manufacturing an LED device in accordance with one or more embodiments. FIG. 3 illustrates a cross-section of a stack after a step in manufacturing an LED device in accordance with one or more embodiments. FIG. 3 illustrates a cross-section of a stack after a step in manufacturing an LED device in accordance with one or more embodiments. FIG. 3 illustrates a cross-section of a stack after a step in manufacturing an LED device in accordance with one or more embodiments. FIG. 3 illustrates a cross-section of a stack after a step in manufacturing an LED device in accordance with one or more embodiments. FIG. 3 illustrates a cross-section of a stack after a step in manufacturing an LED device in accordance with one or more embodiments. FIG. 3 illustrates a cross-section of a stack after a step in manufacturing an LED device in accordance with one or more embodiments. FIG. 3 illustrates a cross-section of a stack after a step in manufacturing an LED device in accordance with one or more embodiments. FIG. 3 is a cross-sectional diagram of an individualized uLED device on a substrate in accordance with one or more embodiments. FIG. 2B illustrates a cross-section of an individualized uLED device on a substrate in accordance with one or more embodiments after a passivation layer has been deposited on the uLED device of FIG. 2A. 2C depicts a cross-section of an individualized uLED device on a substrate, according to one or more embodiments, after the uLED device of FIG. 2C has been further processed. FIG. FIG. 3 is a cross-sectional diagram of a personalized uLED device in accordance with one or more embodiments showing lift-off of the substrate after the anode and cathode are bonded to the support. FIG. 3 illustrates a cross-section of an individualized uLED device in accordance with one or more embodiments in which an anode and a cathode are bonded to a support and a passivation layer is deposited. FIG. 3 illustrates a cross-section of a personalized uLED device in accordance with one or more embodiments. FIG. 2 illustrates an exemplary process flow for manufacturing a uLED device. 1 schematically depicts an exemplary display device; FIG. 1 schematically depicts an exemplary camera flash system having uLEDs according to embodiments of the present application; FIG. 1 schematically illustrates an example augmented reality/virtual reality (AR/VR) system having uLEDs according to embodiments of the present application; FIG.

Before describing some exemplary embodiments of the present disclosure, it is understood that the present disclosure is not limited to the details of construction or process steps set forth in the description that follows. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

The term "substrate" as used in one or more embodiments refers to a structure, intermediate, or end product that has a surface or part of a surface on which a process operates. Also, the term substrate in some embodiments refers to only a portion of a substrate, unless the context clearly indicates otherwise. Further, references to depositing on a substrate according to some embodiments include depositing on a bare substrate or a substrate on which one or more thin films, features or materials have been deposited or formed.

In one or more embodiments, "substrate" refers to any substrate or material surface formed on which thin film processes are performed during the manufacturing process. In exemplary embodiments, the substrate surface to be processed may include silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, etc., depending on the application. , gallium arsenide, glass, sapphire, and any suitable materials, such as metals, metal nitrides, Group III nitrides (e.g., GaN, AlN, InN and alloys), metal alloys, and other conductive materials, including. The substrate includes light emitting diode (LED) devices including, but not limited to, uLED devices. In some embodiments, the substrate is subjected to a pretreatment process in which the substrate surface is polished, etched, reduced, oxidized, hydroxylated, heat treated, UV cured, e-beam cured, and/or Fired. In addition to direct thin film processing on the surface of the substrate itself, in some embodiments any disclosed thin film processing steps are performed on an underlying layer formed on the substrate, and the term "substrate surface" , it is intended to include such underlying layers where the context indicates. Thus, for example, when a thin film/layer or partial thin film/layer is deposited on a substrate surface, the exposed surface of the newly deposited thin film/layer becomes the substrate surface.

The terms "wafer" and "substrate" are used interchangeably in this disclosure. Thus, the wafer used in this application serves as a substrate for the formation of the LED devices described in this application.

The term microLED (uLED or μLED) refers to a light emitting diode that has one or more characteristic dimensions (e.g., height, width, depth, thickness, etc.) less than 100 microns. In one or more embodiments, one or more of the dimensions height, width, depth, thickness has a value ranging from 2 to 25 microns.

Methods for depositing thin films include, but are not limited to, sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic These include layer deposition (PEALD), plasma enhanced chemical vapor deposition (PECVD), and combinations thereof.

Advantages of uLEDs with thin film flip chip (TFFC) include, but are not limited to: increased semiconductor (epilayer) active area with increased p-contact reflective area; increased reflective sidewalls; and increased light emitting surface area. Includes light extraction. uLED has a small footprint and can extract light efficiently, making it an excellent use of space and materials for work below the micro level. The uLEDs of the present application are generally suitable for extremely high brightness requirements found in advanced automatic ADB or high resolution high brightness displays. uLED is also suitable for a wide range of other flash, display and lighting applications that currently use LEDs.

Referring to the drawings, FIGS. 1A-1J provide cross-sectional views of the stack of layers that are constructed and processed during the manufacture of a uLED device. In FIG. 5, an exemplary process flow diagram for manufacturing a uLED device is provided.

FIG. 1A illustrates a semiconductor layer, a metal layer (e.g., p-contact layer or p-metal reflective layer), and a dielectric layer (e.g., , hardmask layer). Referring to FIG. 1A and the flow diagram 500 of FIG. 5, in operations 502, 504, and 506, a semiconductor layer 104 is grown on the substrate 102. In one or more embodiments, semiconductor layer 104 includes an epitaxial layer, a III-nitride layer, or an epitaxial III-nitride layer.

The substrate may be any substrate known to those skilled in the art. In one or more embodiments, the substrate includes one or more of sapphire, silicon carbide, silicon (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, and the like. In one or more embodiments, the substrate is unpatterned prior to growth of the epitaxial layer. Thus, in some embodiments, the substrate is unpatterned and can be considered flat or substantially flat. In other embodiments, the substrate is patterned, such as a patterned sapphire substrate (PSS).

In one or more embodiments, semiconductor layer 104 comprises a III-nitride material, and in certain embodiments comprises an epitaxial III-nitride material. In some embodiments, the III-nitride material includes one or more of gallium (Ga), aluminum (Al), and indium (In). Accordingly, in some implementations, semiconductor layer 104 includes gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InGaN), indium aluminum nitride ( InAlN), aluminum indium gallium nitride (AlInGaN), etc. In one or more particular embodiments, semiconductor layer 104 includes a p-type layer, an active region, and an n-type layer.

In one or more embodiments, substrate 102 is placed in a metal organic vapor phase epitaxy (MOVPE) reactor for epitaxy of LED device layers and semiconductor layer 104 is grown.

In one or more embodiments, semiconductor layer 104 comprises a stack of undoped III-nitride material and doped III-nitride material. Group III-nitride materials include silicon (Si), oxygen (O), boron (B), and phosphorus (P), depending on whether p-type or n-type Group III-nitride material is required. , germanium (Ge), manganese (Mn), or magnesium (Mg). In some embodiments, the semiconductor layer 104 includes an n-type layer 104n, an active layer 106, and a p-type layer 104p.

In one or more embodiments, the semiconductor layer 104 has a thickness in the range of about 2 μm to about 10 μm, including about 2 μm to about 9 μm, 2 μm to about 8 μm, 2 μm to about 7 μm, 2 μm to about 2 μm. 6μm, 2μm to about 5μm, 2μm to about 4μm, 2μm to about 3μm, 3μm to about 10μm, 3μm to about 9μm, 3μm to about 8μm, 3μm to about 7μm, 3μm to about 6μm, 3μm to about 5μm, 3μm to about 4μm, 4μm to about 10μm, 4μm to about 9μm, 4μm to about 8μm, 4μm to about 7μm, 4μm to about 6μm, 4μm to about 5μm, 5μm to about 10μm, 5μm to about 9μm, 5μm to about 8μm, 5μm to about 7 μm to about 6 μm, 6 μm to about 10 μm, 6 μm to about 9 μm, 6 μm to about 8 μm, 6 μm to about 7 μm, 7 μm to about 10 μm, 7 μm to about 9 μm, or 7 μm to about 8 μm.

In one or more embodiments, active layer 106 is formed between n-type layer 104n and p-type layer 104p. Active layer 106 may include any suitable material known to those skilled in the art. In one or more embodiments, active layer 106 is comprised of a multiple quantum well (MQW) of III-nitride material and an electron blocking layer of III-nitride.

In one or more embodiments, p-contact layer 105 and hardmask layer 108 are deposited on p-type layer 104p. As shown, p-contact layer 105 is deposited on p-type layer 104p, and hard mask layer 108 is on p-contact layer 105. In some embodiments, p-contact layer 105 is deposited directly on p-type layer 104p. In other embodiments not shown, one or more additional layers may be present between p-type layer 104p and p-contact layer 105. In some embodiments, hardmask layer 108 is deposited directly on p-contact layer 105. In other embodiments not shown, one or more additional layers may be present between hardmask layer 108 and p-contact layer 105. Hardmask layer 108 and p-contact layer 105 may be deposited by any suitable technique known to those skilled in the art. In one or more embodiments, hardmask layer 108 and p-contact layer 105 are formed by sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced deposition, etc. The film is deposited by one or more of atomic layer deposition (PEALD) and plasma enhanced chemical vapor deposition (PECVD).

"Sputter deposition" as used in this application refers to a physical vapor deposition (PVD) method of depositing a thin film by sputtering. In sputter deposition methods, material, such as metal, is ejected from a source target onto a substrate. This technique is based on ion bombardment of the target source material. In ion bombardment, a gas phase is generated by a purely physical process, ie by sputtering of the target material.

As used in some embodiments of this application, "atomic layer deposition" (ALD) or "cyclic deposition" refers to a vapor phase technique used to deposit thin films onto a substrate surface. . The process of ALD involves exposing the surface of a substrate, or a portion of a substrate, to alternating precursors, ie, two or more reactive compounds, to deposit a layer of material onto the substrate surface. The precursors are introduced sequentially or simultaneously when the substrate is exposed to alternating precursors. A precursor is introduced into a reaction zone of a processing chamber, and the substrate or a portion of the substrate is separately exposed to the precursor.

"Chemical vapor deposition (CVD)," as used in some embodiments, refers to a process in which thin films of materials are deposited from the vapor phase by the decomposition of chemicals on the surface of a substrate. In CVD, a substrate surface is exposed to precursors and/or auxiliary reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either co-flow or when the exposure of the precursors is largely overlapped.

"Plasma enhanced atomic layer deposition" (PEALD), as used in some embodiments, refers to a technique for depositing thin films on a substrate. As opposed to thermal ALD processes, some examples of PEALD processes form materials from the same chemical precursors, but at higher deposition rates and lower temperatures. Generally, in a PEALD process, a reactive gas and a reactive plasma are sequentially introduced into a process chamber having a substrate therein. A first reactant gas is pulsed within the process chamber and adsorbed onto the substrate surface. A reactive plasma is then pulsed within the process chamber to react with the first reactive gas to form a deposition material, eg, a thin film, on the substrate. Similar to thermal ALD processes, a purge step may be performed between each reactant feed.

"Plasma enhanced chemical vapor deposition" (PECVD), as used in one or more embodiments, refers to a technique for depositing thin films on a substrate. In the PECVD process, a source material in the gas or liquid phase is introduced into the PECVD chamber, such as a vapor phase III-nitride material co-carried with a carrier gas, or a vapor of a liquid phase III-nitride material. Ru. A plasma starting gas is also introduced into the chamber. Formation of a plasma within the chamber generates excited radicals that are chemically bonded to the surface of a substrate placed within the chamber, upon which the desired film is formed.

In one or more embodiments, hardmask layer 108 may be formed using materials and patterning techniques known in the art. In some embodiments, hardmask layer 108 includes a metallic or dielectric material or a photoresist material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlO _x ), aluminum nitride (AlN), and the like. Includes a combination of Those skilled in the art will recognize that the use of a formula such as SiO to represent silicon oxide does not imply any particular stoichiometric relationship between the elements. This formula merely specifies the main elements of the thin film.

In one or more embodiments, p-contact layer 105 may include any suitable metal known to those skilled in the art. In one or more embodiments, p-contact layer 105 is aluminum (Al), titanium (Ti), platinum (Pt), silver (Ag), gold (Au), palladium (Pd), titanium-tungsten (TiW). , or various combinations thereof. In one embodiment, p-contact layer 105 includes silver (Ag). In one or more embodiments, p-contact layer 105 is reflective.

The p contact layer has the property of forming an ohmic contact with the p layer 104p (eg, p-GaN). One embodiment includes a p-metal, which has appropriate reflective properties for the particular application of the device and provides an etch stop during etching of the p-contact. In one or more embodiments, the p-contact layer is deposited by a vapor deposition or sputtering process, or a combination of both. In one or more embodiments, the p-contact layer has a thickness range of 1.5 μm or less.

As a non-limiting example, fabrication of uLED devices in operations 502, 504, and 506 begins with the deposition of p-metal on a gallium nitride (GaN) semiconductor (p-side up) grown on a sapphire wafer substrate. . Thereafter, a dielectric hard mask having a semiconductor layer (epi layer) approximately 0.5 times thicker is formed.

FIG. 1B is a cross-sectional view of a stack after a step in the manufacture of LED device 100 in accordance with one or more embodiments. Referring to FIGS. 1B and 5, in operation 508 the hard mask layer 108 and the p-contact layer 105 are patterned to form at least one opening 110 in the hard mask layer 108 and the p-contact layer 105 over the top of the semiconductor layer 104. The surface 104t and the sidewalls 108s and 105s of the hard mask layer 108 and the p-contact layer 105 are exposed.

In one or more embodiments, hardmask layer 108 and p-contact layer 105 are patterned according to any suitable patterning technique known to those skilled in the art. In one or more embodiments, hardmask layer 108 and p-contact layer 105 are patterned by etching. In one or more embodiments, hard mask layer 108 and p-contact layer 105 can be patterned using conventional masking, wet etching, and/or dry etching processes.

In other embodiments, the pattern is transferred to hardmask layer 108 and p-contact layer 105 using nanoimprint lithography. In one or more embodiments, the substrate 102 is etched in a reactive ion etch (RIE) tool such that the hard mask layer 108 and the p-contact layer 105 etch efficiently, but the p-type layer 104p etches very slowly. Alternatively, it is etched using conditions that do not cause etching at all. In other words, the etching is selective to hard mask layer 108 and p-contact layer 105 across p-type layer 104p. It is understood that the patterning step may use masking techniques to obtain the desired pattern.

As a non-limiting example, in operation 508, manufacturing a uLED device includes applying a mask, eg, a photomask, to pattern the hard mask. This is followed by an anisotropic etch of hardmask and photoresist removal, followed by an anisotropic etch of the p-metal.

FIG. 1C is a cross-sectional view of a stack after a step in the manufacture of LED device 100 in accordance with one or more embodiments. Referring to FIGS. 1C and 5, in operation 510 the semiconductor layer 104 is etched to form at least one mesa, eg, a first mesa 150a and a second mesa 150b. In one or more embodiments, the mesa is processed to include other features or configurations. In the embodiment shown in FIG. 1C, first mesa 150a and second mesa 150b are separated by trench 111x. On the opposite side of mesa 150a is trench 111y, and on the opposite side of mesa 150b is trench 111z. Each trench is typically referred to as a trench 111. Each trench 111 has sidewalls 113.

Regarding etching, in one or more embodiments, a highly anisotropic etching method is used, with angles ranging from vertical (90°) to 80°, and even smaller values, and all values in between. is achieved. Mesa/junction etch depth typically does not exceed 5 microns. In one or more embodiments, the trenches are formed using anisotropic etching of the mesa.

FIG. ID is a cross-sectional view of a stack after a step in the manufacture of LED device 100 in accordance with one or more embodiments. Referring to FIGS. 1D and 5, a conformal layer of material is deposited in operation 512 to form bond spacers 114 on the top of the mesa and on the sidewalls and bottom of trench 111. Bonding spacer 114 may include any suitable material known to those skilled in the art. In one or more embodiments, bond spacer 114 includes a dielectric material.

The term "dielectric" as used herein refers to an electrically insulating material that can be polarized by an applied electric field. In one or more embodiments, bond spacer 114 is made of oxides, such as silicon _oxide ( _SiO2 ), aluminum oxide ( _Al2O3 ), nitrides, such as silicon nitride ( _Si3N4 ), and combinations _. , for example, silicon oxynitride (SiON). In one or more embodiments, bond spacer 114 includes silicon nitride (Si ₃ N ₄ ). In other embodiments, bond spacer 114 includes silicon oxide ( _SiO2 ). In some embodiments, the composition of junction spacer 114 is non-stoichiometric compared to the ideal molecular formula. In one or more embodiments, bond spacer 114 includes _SiO2 , SiN, _SiON , _Al2O3 , or various combinations thereof. The bonding spacer may provide properties of low light absorption and favorable refractive index contrast at the thin film interface of the combined thin films.

In some embodiments, junction spacer 114 may be a distributed Bragg reflector (DBR). As used herein, a "distributed Bragg reflector" refers to a structure formed from a multilayer stack of alternating layers of thin film materials of varying refractive index, e.g. a multilayer stack of high and low refractive index films (e.g. mirrors). ) represents.

In one or more embodiments, the bonding spacer 114 is formed using sputter deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition ( PEALD), and plasma enhanced chemical vapor deposition (PECVD). The remaining thickness of the sidewalls typically does not exceed 1.5 microns.

In one or more embodiments, the bonding spacer is a bilayer or multilayer structure. In one or more embodiments, the first layer has a higher refractive index (RI) (e.g., _Al2O3 has an RI of 1.4) than the second layer (e.g., _SiO2 has an RI of _1.4 ). with an RI of 1.8), which provides excellent reflection properties for photons impinging on the mesa sidewalls.

In one or more embodiments, the junction spacer 114 is in the range of about 200 nm to about 1 μm, such as about 300 nm to about 1 μm, about 400 nm to about 1 μm, about 500 nm to about 1 μm, about 600 nm to about 1 μm, about 700 nm to about Approximately 1μm, approximately 800nm to approximately 1μm, approximately 500nm to approximately 1μm, approximately 200nm to approximately 900nm, 300nm to approximately 900nm, approximately 400nm to approximately 900nm, approximately 500nm to approximately 900nm, approximately 600nm to approximately 900nm, approximately 700nm to approximately 900nm, From about 800nm to about 900nm, from about 200nm to about 800nm, from about 300nm to about 800nm, from about 400nm to about 800nm, from about 500nm to about 500nm, from about 600nm to about 800nm, from about 700nm to about 800nm, from about 200nm to about 700nm, from about 300nm Approximately 700nm, approximately 400nm to approximately 700nm, approximately 500nm to approximately 700nm, approximately 600nm to approximately 700nm, approximately 200nm to approximately 600nm, approximately 300nm to approximately 600nm, approximately 400nm to approximately 600nm, approximately 500nm to approximately 600nm, approximately 200nm to approximately 500nm , about 300 nm to about 500 nm, about 300 nm to about 400 nm, about 200 nm to about 400 nm, or about 300 nm to about 400 nm.

FIG. 1E is a cross-sectional view of a stack after a step in the manufacture of LED device 100 in accordance with one or more embodiments. Referring to FIG. 1E and FIG. 5, in operation 514, further etching is performed. Horizontal portions of the junction spacer are etched from the bottom of the trench and the top of the hard mask. A portion of hard mask 108 is also etched. Also, semiconductor layer 104 is etched, trench 111 is expanded (ie, the depth of the trench is increased), and upper surface 102t of substrate 102 is exposed. In one or more embodiments, the etch is selective and bond spacers 114 remain on the sidewalls of trenches 111. In one or more embodiments, trench 111 has a bottom 111b and sidewalls 113. In one or more embodiments, the trench 111 has a depth from the top surface 104t of the semiconductor layer, forming a mesa ranging from about 0.5 μm to about 2 μm. In one or more embodiments, highly anisotropic etching methods are used to achieve angles ranging from vertical (90°) to 80°, and all values in between. In one or more embodiments, anisotropic etching is used to deepen the trench and/or further shape the device.

Referring to FIGS. 1C-1E, the method includes a self-aligning step in which the edges of dielectric layer 114 are aligned with the edges of n-layer 104n. This achieves internal quantum efficiency for the semiconductor layers within the p-layer 104p, the active layer 106, and the n-layer 104n, causing them to remain aligned and resulting in no internal quantum efficiency within the semiconductor, which would lead to efficiency loss in the final device. There is no need to spread the current laterally.

FIGS. 1F.1 and 1F.2 are cross-sectional views of a stack after certain steps in the manufacture of LED device 100 in accordance with one or more embodiments. Referring to FIG. 5, in operation 516, the dielectric material is deposited again. Referring to FIG. 1F.1, a conformal layer of material is deposited to form trench spacers 115 on the top of the mesa and on the sidewalls and bottom of trench 111. Trench spacer 115 may include any suitable material known to those skilled in the art. In one or more embodiments, trench spacer 115 includes a dielectric material as described with respect to junction spacer 114. Referring to FIG. 1F.2, the various dielectric materials of hardmask layer 108, junction spacers 114, and trench spacers 115 of FIG. 1F.1 are combined to show a combined dielectric region 117. In one or more embodiments, combined dielectric region 117 includes a plurality of different dielectric materials. In one or more alternative embodiments, combined dielectric region 117 includes a single dielectric material.

FIG. 1G is a cross-sectional view of a stack after a step in the manufacture of LED device 100 in accordance with one or more embodiments. Referring to FIG. 1G and FIG. 5, an etching procedure referred to as a "p-contact etch" is performed in operation 518 to expose at least a portion of the top surface of the p-contact layer 105t and the top surface 102t of the substrate. In one or more embodiments, a portion of the side of the p-contact layer 105s that is in a different planar orientation than the top surface is exposed.

In one or more embodiments, the substrate is masked prior to the "p-contact etch," and the mask is then removed.

In one or more embodiments, the p-contact etch is an anisotropic etch of the dielectric with high selectivity (>10:1) to the p-metal and sufficient etch for subsequent contact with the electrode metal. The P-metal is partially exposed as the area is shown. During this etch, it is expected that a small portion of the sidewalls will be exposed with slight overetching, but this will not interfere with the deposition of electrode metal in later steps.

FIG. 1H is a cross-sectional view of a stack after a step in the manufacture of LED device 100 in accordance with one or more embodiments. 1H and 5, in operation 520 an etching procedure referred to as an "n-contact etch" is performed to remove at least a first sidewall of the n-layer 104n-s and a portion of the top surface 102t of the substrate. be exposed. In one or more embodiments, a portion of the side of the p-contact layer that is in a different planar orientation than the top surface is exposed.

In one or more embodiments, the substrate is masked prior to the "p-contact etch," and the mask is then removed.

In some embodiments, "n-contact etch" and "p-contact etch" masking is performed in the same step, and subsequent mask removal is performed in the same step.

In one or more embodiments, the n-contact etch is an isotropic etch of the trench spacer dielectric that exposes the n-layer sidewalls (e.g., N-GaN) for formation of the n-contact in a subsequent step. . To ensure a suitable or timely etch stop for this lateral etch into the semiconductor layer (epi), and using the previous example of the Al ₂ O ₃ -SiO ₂ bilayer, the (epi) to junction spacer Lateral etching of _SiO2 trench oxide _overetch to ensure clearance finally stops safely on _Al2O3 .

Photoresist removal chemistries and processes are selected based on compatibility/selectivity to exposed dielectric, metal, and semiconductor layers (epi).

FIG. 1I is a cross-sectional view of a stack after a step in manufacturing an LED device 100 in accordance with one or more embodiments. Referring to FIGS. 1I and 5, in operation 522, electrode metal 118 for the p-contact (anode) and n-contact (cathode) is deposited. In one or more embodiments, the operation 522 of depositing the electrode metal is a blanket co-formed film. Further, the electrode metal is also called a bonding metal. In one or more embodiments, the bonding metal 118 includes aluminum (Al), titanium (Ti), platinum (Pt), silver (Ag), gold (Au), palladium (Pd), or various combinations thereof. .

The bonding metal has the property of forming an ohmic contact with the n-layer (eg N-GaN) and the p-contact layer/p-metal reflective layer with suitable reflective properties for the particular application of the device. In one or more embodiments, the bond metal is deposited by either a vapor deposition, sputtering, or electroplating process, or a combination thereof. The range of bond metal thickness can range from 1 micron or less to several microns.

In one or more embodiments, the electrode metal is provided as a patterned bonding layer. In one embodiment, the patterned bonding layer is prepared by depositing a photoresist, depositing metal for the bonding layer, lifting off any excess metal and photoresist. According to one embodiment, the patterned bonding layer is prepared by depositing a metal for the bonding layer, depositing a photoresist, ion beam etching, and removing the photoresist. In one embodiment, the patterned bonding layer is prepared by seed metal deposition deposition, photoresist application, metal plating, photoresist removal, and seed etching.

FIG. 1J is a cross-sectional view of a stack after a step in the manufacture of LED device 100 in accordance with one or more embodiments. Referring to FIGS. 1J and 5, metal 118 is etched in operation 524 to form n-contact (cathode) 119 and p-contact (anode) 125. The cathode and anode are insulated from each other.

At this point, processing structuring is complete and post-processing is ready.

Thereafter, in operation 526, the resulting structure is post-processed for further use. In one or more embodiments, further processing includes forming a passivation layer around part or all of the uLED. In one or more embodiments, the processed structure is singulated while retaining the substrate and further processed as shown in FIGS. 2A-2C. In one or more embodiments, the processed structure is inverted, secured to a support, such as a tape support, and the substrate is removed, as shown in FIGS. 3A-3B. Removal of the substrate is performed by conventional methods including laser lift-off of the substrate. Upon removal of the substrate, individualized uLEDs are created.

Further processing may include depositing a layer of downconverter material, such as a phosphor material.

FIG. 2A is a cross-sectional view of an individualized uLED device 200 on a substrate 202, according to the embodiment made in FIGS. 1A-1J and FIG. 2B-2C are cross-sectional views of the uLED device on the substrate of FIG. 2A after post-processing according to operation 526 of FIG. 5. FIG. 2A-2C, mesa 250 has multiple semiconductor layers including an n-type layer 204n, an active layer 206, and a p-type layer 204p. P contact layer 205 contacts p-type layer 204p. In this embodiment, there is a direct contact between p-contact layer 205 and p-type layer 204p. Other embodiments may include an intervening layer. As shown in FIG. 2A and also applicable to FIGS. 2B-2C, the mesa has a height (“H”) from the top surface of p-contact layer 205t to the bottom surface of n-type layer 204b; The width (“W”) from the first sidewall of n-type layer 204n-s1 to the second sidewall of n-type layer 204n-s2, and the upper surface of p-contact layer 205t is The first sidewall of s1 and the second sidewall 204n-s1 of n-type layer 204n-s1 have a different planar orientation. In FIGS. 2A-2C, cathode 219 contacts the first sidewall of n-type layer 204n-s1. Also in this embodiment, the cathode 219 contacts the n-layer on another surface 204n-t that is in a different planar orientation than the first sidewall of the n-type layer 204n-s1. A first region of dielectric material 217a insulates p-contact layer 204p, active layer 206, and a first sidewall of p-type layer 204p-s1 from cathode 219. Anode 325 contacts the top surface of p-contact layer 205t. Also in this embodiment, anode 225 contacts a p-contact layer on another surface 205s that is in a different planar orientation than the top surface of p-contact layer 205t. A second region of dielectric material 217b insulates active layer 206, a second sidewall of p-type layer 204ps-2, and a second sidewall of n-type layer 204n-s2 from anode 225.

As shown in FIGS. 2A-2C, the planar orientation of the first sidewall of n-type layer 204n-s1 is different from the planar orientation of the top surface of p-contact layer 205t.

In FIG. 2B, a passivation layer 231 is deposited over the structure of FIG. 2A, which is planarized in accordance with one or more embodiments. In other embodiments, the passivation layer may be deposited conformally to the topography of the following features: In this way, the uLED of FIG. 2B can be further handled, transported, processed, incorporated into a final display or device, etc. while the anode and cathode and other features remain protected.

In FIG. 2C, during the additional lithography and etching of FIG. 2B, a portion of passivation layer 231 is removed and pads 239 and 245 are deposited to provide access to cathode 219 and anode 225. In this way, the uLED of FIG. 2C (and a plurality or array thereof) can be incorporated into a final display or device, etc.

In one or more embodiments, the width of the mesa is less than 100 microns. In one or more embodiments, the height of the mesa is less than or equal to the width of the mesa.

As shown in Figure 2A and applicable to Figures 2B to 2C, both the cathode and anode extend the uLED device longitudinally and lie along the uLED axis "A" excluding the substrate, anode, and cathode. In contrast, the entire axial distance is extended.

Significantly, the cathode surrounds a portion of the n-type layer 204n-s1 and a first portion of the first region of dielectric material 217a. Similarly, the anode surrounds p-contact layer 205 and a portion of the second region of dielectric material 217b. In this way, the presence of reflective sidewalls is enhanced.

More significantly, embodiments of the present application have a semiconductor (epi) active region that includes an increased p-contact reflective region. To facilitate efficient light extraction and increase light extraction from the emissive surface, in one or more embodiments, the p-contact layer in contact with the p-type layer substantially spans the width of the p-type layer. For example, a p-type contact layer that substantially contacts a p-type layer may extend between 75% and 100% of the width of the p-type layer, including between 80% and 90% of the width. , 95% or more, 99% or more, 99.5% or more, 99.9% or more, and 100% or less.

To facilitate efficient light extraction and increase light extraction from the emissive surface, in one or more embodiments, the p-type layer substantially spans the width of the active layer. For example, a p-type layer in substantial contact with the active layer may extend between 75% and 100% of the width of the active layer, including at least 80%, 90%, and 95% of the width. Includes 99% or more, 99.5% or more, 99.9% or more, and 100% or less.

To facilitate efficient light extraction and increase light extraction from the emissive surface, in one or more embodiments, the widths of the p-contact layer, the p-layer, and the active layer are ±10% of each other; This includes ±5% of each other and ±1% of each other.

In one or more embodiments, the cathode contacts two planar orientations of the n-type layer.

In one or more embodiments, the anode contacts two planar orientations of the p-contact layer.

In one or more embodiments, the semiconductor layer has a total thickness in the range of 2 μm to 10 μm.

In one or more embodiments, the n-type layer includes N-GaN and the p-type layer includes P-GaN.

In one or more embodiments, the dielectric material of the first region and the second region each independently comprises a material selected from the group consisting of SiO ₂ , AlO _x , and SiN; It has a thickness ranging from 200nm to 1μm.

FIG. 3A is a cross-sectional view of a personalized uLED device 300 in accordance with one or more embodiments, showing lift-off of the substrate after the anode and cathode are bonded to the support. In FIG. 3A, the mesa has multiple semiconductor layers including an n-type layer 304n, an active layer 306, and a p-type layer 304p. P contact layer 305 contacts p-type layer 304p. In this embodiment, p-contact layer 305 and p-type layer 304p are in direct contact. Cathode 319 contacts the first sidewall of n-type layer 304n-s1. Also in this embodiment, the cathode 319 contacts the n-layer on another surface 304n-t that is in a different planar orientation than the first sidewall of the n-type layer 304n-s1. A first region of dielectric material 317a insulates p-contact layer 304p, active layer 306, and a first sidewall of p-type layer 304p-s1 from cathode 319. Anode 325 contacts the top surface of p-contact layer 305t. Also in this embodiment, anode 325 contacts a p-contact layer on another surface 305s that is in a different planar orientation than the top surface of p-contact layer 305t. A second region of dielectric material 317b insulates active layer 306, a second sidewall of p-type layer 304ps-2, and a second sidewall of n-type layer 304n-s2 from anode 325.

In this embodiment, a device similar to FIG. 2A is turned upside down. The bonding surfaces of cathode 319 and anode 325 are fixed to support 303. Substrate 302 is then removed by conventional known methods such as substrate laser lift-off.

In FIG. 3A, the first longitudinal surface of cathode 319-s1 defines a first bonding surface of the uLED, the first longitudinal surface of anode 325-s1 defines a second bonding surface of uLED, and The first longitudinal surface of the cathode and the first longitudinal surface of the anode are arranged on the same side of p-contact layer 305.

The second longitudinal surface of the cathode 319-s2 forms a first lift-off end of the uLED, the second longitudinal surface of the anode 325-s2 forms a second lift-off end of the uLED, A second longitudinal surface of the cathode and a second longitudinal surface of the anode are disposed on opposite sides of the n-type layer 304n.

FIG. 3B shows a cross-sectional view of the uLED device of FIG. 3A. In the figure, the anode and cathode are bonded to a support 303 and a passivation layer 331 is deposited. In one or more embodiments, the uLED devices described herein further include a passivation layer 331 disposed on the cathode 319, the anode 225, and the second portion of the first region of dielectric material 317a.

FIG. 4 is a cross-sectional view of an individualized uLED device 400 according to one or more embodiments made according to FIGS. 1A-1J and FIG. The uLED of FIG. 4 is similar to the uLED of FIG. 2, except that the wall is angled relative to the underlying substrate (not shown) on which it is formed. This can be achieved by anisotropic etching selected at the desired angle. In FIG. 4, the mesa has multiple semiconductor layers including an n-type layer 404n, an active layer 406, and a p-type layer 404p. P contact layer 405 contacts p-type layer 404p. Cathode 419 contacts the first sidewall of n-type layer 404n-s1. A first region of dielectric material 417a insulates p-contact layer 404p, active layer 406, and a first sidewall of p-type layer 404p-s1 from cathode 419. Anode 425 contacts the top surface of p-contact layer 405t. A second region of dielectric material 417b insulates active layer 406, a second sidewall of p-type layer 404ps-2, and a second sidewall of n-type layer 404n-s2 from anode 425.

(display device)
FIG. 6 schematically depicts an exemplary display device using the uLED device disclosed herein. In one or more embodiments, the display device is an LED lighting array and lens system. In one or more embodiments, the display device is an LED light emitting array. As shown in FIG. 6, the display device 650 has a plurality or array of uLEDs 601 of various colors, with 600r of red pixels, 600b of blue pixels, and 600g of green pixels. In one or more embodiments, each of the uLEDs is individually addressable and illuminable. It is understood that the number of each color and the arrangement of colors is application specific. A plurality of pixels are attached to a backplane 652. In one or more embodiments, automated pick-and-place equipment picks each uLED from the support (e.g., 303 in FIGS. 3A-3B), mounts the uLED to a backplane, and applies thermal and/or ultrasound and/or Alternatively, the bonding surfaces of the uLED (eg, cathode first bonding surface 319-s1 and anode second bonding surface 325-s1) may be welded to the backplane by any combination of methods of compression. In one or more embodiments, a bond metal pattern is present on the backplane that corresponds to the bond surface of the uLED. A housing 358 having a display surface (or lens or other optical feature) 660 surrounds the plurality of pixels. Electrodes 654 and 656 electrically connect backplane 652 to a driver integrated circuit (not shown).

In one or more embodiments, an array of micro LEDs (μLEDs or uLEDs) is used. Micro-LEDs can support high density pixels with lateral dimensions less than 100 μm x 100 μm. In some embodiments, micro-LEDs with a diameter or width of about 50 μm or less can be used. Such micro-LEDs can be used in the production of color displays by placing micro-LEDs containing red, blue, and green wavelengths in close proximity.

In some embodiments, the light emitting array has a small number of micro-LEDs arranged on a substrate in a centimeter-scale or larger area. In some embodiments, the light emitting array comprises a micro LED pixel array containing hundreds, thousands, or millions of light emitting LEDs arranged together on a substrate in a centimeter-scale area or on a smaller substrate. have In some embodiments, micro LEDs can have light emitting diodes between 30 microns and 500 microns in size. The light emitting array can be monochromatic, RGB, or other desired chromaticity. In some embodiments, pixels can have a square, rectangular, hexagonal, or curved perimeter. The pixels may be the same size, different sizes, or similarly sized and grouped to provide a larger effective pixel size.

In some embodiments, the circuitry supporting the light emitting pixels and light emitting arrays is packaged and optionally has a submount or printed circuit board to power and control light production by the semiconductor LEDs. connected to. In some embodiments, the printed circuit board supporting the light emitting array includes electrical vias, heat sinks, ground planes, electrical traces, and flip-chip or other mounting systems. The submount or printed circuit board may be formed of any suitable material, such as ceramic, silicon, aluminum, etc. If the submount material is conductive, an insulating layer is formed over the substrate material, and a metal electrode pattern is formed over the insulating layer. The submount can act as a mechanical support, provide an electrical interface and power source between electrodes on the light emitting array, and also provide heat sink functionality.

In some embodiments, the LED light emitting array includes optical elements such as lenses, metalenses, and/or precollimators. Additionally or alternatively, the optical element may include an aperture, a filter, a Fresnel lens, a convex lens, a concave lens, or any other suitable optical element that affects the light projected from the light emitting array. can. Additionally, one or more optical elements can have one or more coatings, including UV-blocking coatings or anti-reflection coatings. In some embodiments, the optical system is used to correct optical errors including pincushion aberration, barrel aberration, longitudinal chromatic aberration, spherical aberration, chromatic aberration, curvature of field, astigmatism, or any other type of optical error. Dimensional or three-dimensional optical errors may be corrected or minimized. In some embodiments, optical elements may be used to magnify and/or correct images. In some embodiments, display image magnification can make the light emitting array physically smaller, weigh less, and require less power than larger displays. Magnification can also increase the field of view of the displayed content, making the display view equal to the user's normal field of view.

(Application)
FIG. 7 schematically depicts an exemplary camera flash system 700 using the uLEDs disclosed herein. Camera flash system 700 includes an LED lighting array and a lens system 702 in electrical communication with an LED driver 704. Camera flash system 700 also includes a controller 706, such as a microprocessor. Controller 706 is coupled to LED driver 704. Controller 706 may also be coupled to camera 708 and sensor 710 and may be operated according to instructions and profiles stored in memory 712. Camera 708, LED lighting array, and lens system 702 may be controlled by controller 706 to match their field of view.

Sensors 710 may include, for example, position sensors (eg, gyroscopes and/or accelerometers) and/or other sensors that may be used to determine the position, velocity, and orientation of system 700. Signals from sensor 710 are provided to controller 706 to determine the preferred path of operation of controller 706 (e.g., which LED is currently illuminating the target and which LED will illuminate the target after a predetermined period of time). may be used for

In operation, the illumination from some or all of the pixels of the LED array at 702 may be modulated, deactivated, operated at full intensity, or operated at intermediate intensity. As mentioned above, at 702, beam focusing or steering of the light emitted by the LED array can be accomplished electronically by activating one or more subsets of pixels, and by activating one or more subsets of pixels in the illumination device. Dynamic adjustment of the beam shape is possible without changing the focus or moving the optical elements.

The LED lighting arrays and lens systems described herein may support various other beam steering or other applications. In this case, benefits are obtained from fine intensity, spatial and temporal control of the light distribution. These applications include, but are not limited to, precise spatial patterning of light emitted from blocks of pixels or individual pixels. Depending on the application, the emitted light may be spectrally discrete, temporally adaptive, and/or environmentally responsive. The light emitting pixel array may provide preprogrammed light distributions in various intensity, spatial, or temporal patterns. The associated optics may be separate at the pixel, pixel block, or device level. An exemplary emissive pixel array may have an arrangement that includes a commonly controlled central block of high intensity pixels with associated common optics, and edge pixels may have individual optics. good. In addition to flashlights, common applications supported by light emitting pixel arrays include video lighting, automotive headlights, architectural and area lighting, and street lighting.

FIG. 8 schematically depicts an exemplary augmented reality/virtual reality (AR/VR) system 800 using uLEDs disclosed herein. The one or more AR/VR systems include an augmented (AR) or virtual (VR) headset, glasses, and a projector. AR/VR system 800 includes an LED light emitting array 802, an LED driver (or light emitting array controller) 804, a system controller 806, an AR or VR display 808, and a sensor system 810. Control inputs are provided to sensor system 810, while power 812 and user data inputs are provided to system controller 806. As will be appreciated, in some embodiments, the modules included in the AR/VR system 800 can be compactly arranged in a single structure, or one or more elements can be separately mounted, wireless or Can be connected via wired communication. For example, the light emitting array 802, AR or VR display 808, and sensor system 810 can be attached to a headset or glasses, with the LED driver 804 and/or system controller 806 separately attached.

In one embodiment, light emitting array 802 can be used to project light into a graphical or object pattern that can support an AR/VR system. In some embodiments, a separate light emitting array can be used to provide display images. The AR features are provided by separate and isolated micro-LED arrays. In some embodiments, selected groups of pixels can be used to display content to a user, and the tracking pixels provide tracking light used for eye tracking. The content display pixels are designed to emit visible light having at least a portion of the visible band (approximately 400 nm to 750 nm). Tracking pixels, on the other hand, can emit light in the visible band, in the infrared band (approximately 750 nm to 2,200 nm), or some combination thereof. In another example, tracking pixels can operate in the 800 to 1000 nanometer range. In some embodiments, the tracking pixel may emit tracking light during times when the content pixel is turned off and no content is displayed to the user.

The AR/VR system 800 can incorporate a wide range of optics into the LED light emitting array 802 and/or the AR/VR display 808, for example, as described above, to It can be coupled to a VR display 808. For AR/VR applications, these optics may have nanofins and be configured to polarize the light they transmit.

In one embodiment, a light emitting array controller 804 may be used to provide power and real-time control to the light emitting array 802. For example, the light emitting array controller 804 can implement pixel or group pixel level amplitude and duty cycle control. In some embodiments, the light emitting array controller 804 further includes a frame buffer to hold formed or processed images that may be provided to the light emitting array 802. Other supported modules can be configured to transmit the Inter-Integrated Circuit (I2C) Serial Bus, Serial Peripheral Interface (SPI), USB-C, HDMI, Display Port, or any required image data, control data or instructions. A digital control interface may be included, such as a digital camera or other suitable image or control module.

In operation, the pixels in the image can be used to define the response of the corresponding light emitting array 802, and the intensity and spatial modulation of the LED pixels is based on the image. To reduce data rate issues, in some embodiments, groups of pixels (eg, 5x5 blocks) can be controlled as a single block. In some embodiments, high speed and high data rate operation is supported, and pixel values from successive images can be loaded as a series of frames in an image sequence at a rate between 30Hz and 100Hz. 60Hz is typical. Using pulse width modulation, each pixel is controlled to emit light in a pattern with an intensity that is at least partially image dependent.

In some embodiments, the sensor system 810 includes external sensors such as a camera, depth sensor, or audio sensor to monitor the environment, and an accelerometer or two- or three-axis to monitor the AR/VR headset position. and an internal sensor such as a gyroscope. Other sensors may include, but are not limited to, air pressure sensors, stress sensors, temperature sensors, or any other suitable sensors necessary for local or remote environmental monitoring. In some embodiments, the control input may include a detected touch or tap, gesture input, or control based on headset or display position, as another example, measuring translational or rotational movement. Based on one or more measurement signals from one or more gyroscopes or position sensors, an estimated position relative to the initial position of AR/VR system 800 can be determined.

In some embodiments, the system controller 806 uses data from the sensor system 810 to integrate measurement signals received from the accelerometer over time, estimate a velocity vector, and calculate the velocity vector over time. is integrated to determine the estimated position of the reference point of the AR/VR system 800. In other embodiments, the reference points used to represent the position of the AR/VR system 800 may be based on depth sensors, camera placement views, or optical field flows.

Based on changes in position, orientation, or movement of AR/VR system 800, system controller 806 can send images or instructions to light emitting array controller 804. Also, changes or modifications to the images or instructions can be made by user data entry or by automatic data entry, if desired. User data input includes, but is not limited to, voice commands, tactile feedback, eye or pupil placement, or those provided by an attached keyboard, mouse, or game controller.

(Embodiment)
Various embodiments are listed below. It is understood that the embodiments presented below may be combined with all aspects and other embodiments according to the scope of the invention.

Embodiment (a)
A micro light emitting diode (uLED) device,
Mesa,
a plurality of semiconductor layers including an n-type layer, an active layer, and a p-type layer;
a p-contact layer in contact with the p-type layer;
and the mesa has a height extending from a top surface of the p-contact layer to a bottom surface of the n-type layer and a width extending from a first sidewall of the n-type layer to a second sidewall of the n-type layer. a mesa, the top surface of the p-contact layer having a different planar orientation than the first and second sidewalls of the n-type layer;
a cathode in contact with the first sidewall of the n-type layer;
a first region of dielectric material insulating the p-contact layer, the active layer, and a first sidewall of the p-type layer from the cathode;
an anode in contact with the upper surface of the p-contact layer;
a second region of dielectric material insulating the active layer, the second sidewall of the p-type layer, and the second sidewall of the n-type layer from the anode;
A uLED device with

Embodiment (b)
The uLED device of embodiment (a), wherein the mesa width is less than 100 microns.

Embodiment (c)
The uLED device according to any one of embodiments (a) to (b), wherein the height of the mesa is less than or equal to the width of the mesa.

Embodiment (d)
The uLED device according to any one of embodiments (a) to (c), wherein both the cathode and the anode extend the uLED device longitudinally.

Embodiment (e)
The uLED device according to any one of embodiments (a) to (d), wherein the p-contact layer in contact with the p-type layer substantially spans the width of the p-type layer.

Embodiment (f)
The uLED according to any one of embodiments (a) to (e), wherein the cathode surrounds a portion of the n-type layer and a first portion of the first region of the dielectric material. Device.

Embodiment (g)
The uLED device according to any one of embodiments (a) to (f), wherein the anode surrounds a portion of the p-contact layer and a portion of the second region of dielectric material.

Embodiment (h)
a first longitudinal surface of the cathode defines a first bonding surface of the uLED;
a first longitudinal surface of the anode defines a second bonding surface of the uLED;
In any one of embodiments (a) to (g), the first longitudinal surface of the cathode and the first longitudinal surface of the anode are arranged on the same side of the p-contact layer. uLED device as described.

Embodiment (i)
The uLED device of embodiment (h), wherein the first longitudinal surface of the cathode and the first longitudinal surface of the anode are planar.

Embodiment (j)
a second longitudinal surface of the cathode defines a first lift-off end of the uLED;
a second longitudinal surface of the anode defines a second lift-off end of the uLED;
Any one of embodiments (a) to (i), wherein the second longitudinal surface of the cathode and the second longitudinal surface of the anode are disposed on opposite sides of the n-type layer. uLED device described in.

Embodiment (k)
The uLED device according to any one of embodiments (a) to (j), having a passivation layer disposed on the cathode, the anode, and a second portion of the first region of dielectric material. .

Embodiment (l)
The uLED device according to any one of embodiments (a) to (k), wherein the cathode contacts two planar orientations of the n-type layer.

Embodiment (m)
The uLED device according to any one of embodiments (a) to (l), wherein the anode contacts two planar orientations of the p-contact layer.

Embodiment (n)
The uLED device according to any one of embodiments (a) to (m), wherein the semiconductor layer has a total thickness in the range of 2 μm to 10 μm.

Embodiment (o)
The uLED device according to any one of embodiments (a) to (n), wherein the n-type layer includes N-GaN and the p-type layer includes P-GaN.

Embodiment (p)
The dielectric material of the first region and the second region each independently includes a material selected from the group consisting of SiO ₂ , AlO _x , and SiN, and each independently has a diameter in the range of 200 nm to 1 μm. The uLED device according to any one of embodiments (a) to (o), having a thickness of .

Embodiment (q)
A display device,
backplane and
a plurality of individually disposed uLED devices attached to the backplane, each of the uLED devices comprising a uLED device according to any one of embodiments (a) to (p); a device;
a housing including a display surface surrounding the plurality of individually disposed uLED devices;
A display device having:

Embodiment (r)
The display device according to embodiment (q), wherein each of the uLEDs is a uLED device according to any one of embodiments (a) to (p).

Embodiment(s)
A display system comprising a display device according to any one of embodiments (q) to (r) and one or more controllers in communication with the plurality of uLED devices.

Embodiment (t)
The display system of embodiment (s), wherein the plurality of uLED devices are independently controllable.

Embodiment (u)
A method of manufacturing a micro light emitting diode (uLED) device, the method comprising:
Depositing a plurality of semiconductor layers including an n-type layer, an active layer, and a p-type layer on the substrate;
forming a p-contact layer on the plurality of semiconductor layers;
depositing a hard mask layer on the p-contact layer;
etching a portion of the semiconductor layer, the p-contact layer, and the hardmask layer to form a trench and a plurality of mesas, each mesa extending from the top surface of the p-contact layer to the n-contact layer; a step having a height extending to a bottom surface of a mold layer and a width extending from a first sidewall of the n-type layer to a second sidewall of the n-type layer;
depositing a dielectric metal across the substrate, in the trench and on the top surface of the substrate;
exposing the p-contact layer and a first portion of the surface of the substrate by a first etch;
exposing the n-type layer and a second portion of the surface of the substrate by a second etch;
forming a first metal film in the region exposed by the first etching and the second etching;
forming a cathode and an anode insulated from each other by etching;
has
A method, wherein each of the steps forms a processing structure.

Embodiment (v)
The method of embodiment (u), wherein the mesa width is less than 100 microns.

Embodiment (w)
Embodiment (u), wherein the height of the mesa is equal to or less than the width of the mesa.
or as described in (v).

Embodiment (x)
The method according to any one of embodiments (u) to (w), wherein the first etching and/or the second etching, independently of each other, comprise anisotropic etching.

Embodiment (y)
The method according to any one of embodiments (u) to (x), further comprising the step of performing masking before exposing the p-contact layer by etching.

Embodiment (z)
The method of any one of embodiments (u)-(y), wherein two planar orientations of the p-contact layer are exposed during the step of exposing the p-contact layer by etching.

Embodiment (aa)
The method of any one of embodiments (u) to (z), wherein two planar orientations of the n-layer are exposed during the step of exposing the n-layer by the etching.

Embodiment (bb)
The method according to any one of embodiments (u) to (aa), further comprising the step of performing masking before exposing the n-type layer by etching.

Embodiment (cc)
The method as in any one of embodiments (u) to (bb), comprising forming a passivation layer on the treated structure.

Embodiment (dd)
adhering the bonding surfaces of the cathode and the anode to a support;
removing the substrate;
individualizing the mesas to form individual uLED devices;
The method according to any one of embodiments (u) to (cc), comprising:

Embodiment (ee)
The method according to any one of embodiments (u) to (dd), wherein the n-type layer includes N-GaN and the p-type layer includes P-GaN.

Embodiment (ff)
The dielectric material of the first region and the second region each independently has a material selected from the group consisting of SiO ₂ , AlO _x , and SiN, and each independently has a material of 200 nm to 1 μm. The method of any one of embodiments (u) to (ee), having a thickness in a range of thicknesses.

Embodiment (gg)
The method of any one of embodiments (u) to (ff), wherein the p-contact layer in contact with the p-type layer substantially spans the width of the p-type layer.

Embodiment (hh)
The method of any one of embodiments (u) to (gg), wherein the p-type layer substantially spans the width of the active layer.

Embodiment (ii)
A method of manufacturing a display device, the method comprising:
attaching a plurality of micro light emitting diodes (uLEDs) to the backplane using a pick and place method;
enclosing the plurality of LEDs in a housing having a display surface;
has
A method, wherein each of the uLEDs comprises a uLED according to any one of embodiments (a) to (p).

Embodiment (jj)
The method of embodiment (ii), wherein the mesa width is less than 100 microns.

Embodiment (kk)
The method according to any one of embodiments (ii) to (jj), wherein the height of the mesa is less than or equal to the width of the mesa.

Embodiment (ll)
A method according to any of embodiments (ii) to (kk), wherein the p-contact layer in contact with the p-type layer extends substantially the width of the p-type layer.

Embodiment (mm)
A method according to any of embodiments (ii) to (ll), wherein the p-type layer extends substantially the width of the active layer.

Throughout this application, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "embodiments" refer to the specific features, structures, materials, features, structures, materials, etc. described in connection with an embodiment. or characteristic is included in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places in this application does not necessarily refer to the present disclosure. are not representative of the same embodiment. Additionally, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

Many modifications and other embodiments of the invention will be apparent to those skilled in the art having the benefit of the suggestions presented in the foregoing description and associated drawings. It is therefore understood that this invention is not limited to the particular embodiments disclosed, but that modifications and embodiments are intended to come within the scope of the appended claims. It is also understood that other embodiments of the invention may be practiced in the absence of elements/steps not specifically disclosed herein.

Claims (19)

A method of manufacturing a micro light emitting diode (uLED) device, the method comprising:
Depositing a plurality of semiconductor layers including an n-type layer, an active layer, and a p-type layer on the substrate;
forming a p-contact layer on the plurality of semiconductor layers;
depositing a hard mask layer on the p-contact layer;
etching a portion of the semiconductor layer, the p-contact layer, and the hardmask layer to form a trench and a plurality of mesas, each mesa extending from the top surface of the p-contact layer to the n-contact layer; a step having a height extending to a bottom surface of a mold layer and a width extending from a first sidewall of the n-type layer to a second sidewall of the n-type layer;
depositing a dielectric metal across the substrate, in the trench and on the top surface of the substrate;
exposing the p-contact layer and a first portion of the surface of the substrate by a first etch;
exposing the n-type layer and a second portion of the surface of the substrate by a second etch;
forming a first metal film in the region exposed by the first etching and the second etching;
forming a cathode and an anode insulated from each other by etching;
has
A method, wherein each of the steps forms a processing structure. 2. The method of claim 1, wherein the mesa width is less than 100 microns. 2. The method of claim 1, wherein the mesa height is equal to or less than the mesa width. 2. The method according to claim 1, wherein the first etching and/or the second etching independently of each other comprise anisotropic etching. 2. The method of claim 1, further comprising the step of performing masking before exposing the p-contact layer by etching. 2. The method of claim 1, wherein two planar orientations of the p-contact layer are exposed during the step of exposing the p-contact layer by the etching. 2. The method of claim 1, wherein two planar orientations of the n-layer are exposed during the step of exposing the n-layer by the etching. 2. The method of claim 1, further comprising the step of performing masking before exposing the n-type layer by etching. 2. The method of claim 1, comprising forming a passivation layer over the treated structure. adhering the bonding surfaces of the cathode and the anode to a support;
removing the substrate;
individualizing the mesas to form individual uLED devices;
The method according to claim 1, comprising: 2. The method of claim 1, wherein the n-type layer comprises N-GaN and the p-type layer comprises P-GaN. The dielectric material of the first region and the second region each independently has a material selected from the group consisting of SiO ₂ , AlO _x , and SiN, and each independently has a material of 200 nm to 1 μm. 2. The method of claim 1, having a range of thicknesses. 2. The method of claim 1, wherein the p-contact layer in contact with the p-type layer substantially spans the width of the p-type layer. 2. The method of claim 1, wherein the p-type layer substantially spans the width of the active layer. A method of manufacturing a display device, the method comprising:
attaching a plurality of micro light emitting diodes (uLEDs) to the backplane using a pick and place method;
enclosing the plurality of LEDs in a housing having a display surface;
has
Each of the uLEDs is
Mesa,
a plurality of semiconductor layers including an n-type layer, an active layer, and a p-type layer;
a p-type contact layer in contact with the p-type layer;
and the mesa has a height extending from a top surface of the p-contact layer to a bottom surface of the n-type layer and a width extending from a first sidewall of the n-type layer to a second sidewall of the n-type layer. and a mesa, wherein the top surface of the p-contact layer has a different planar orientation than the first and second sidewalls of the n-type layer;
a cathode in contact with the first sidewall of the n-type layer;
a first region of dielectric material insulating the p-contact layer, the active layer, and a first sidewall of the p-type layer from the cathode;
an anode in contact with the upper surface of the p-contact layer;
a second region of dielectric material insulating the active layer, the second sidewall of the p-type layer, and the second sidewall of the n-type layer from the anode;
A method having. 16. The method of claim 15, wherein the mesa width is less than 100 microns. 16. The method of claim 15, wherein the mesa height is less than or equal to the mesa width. 16. The method of claim 15, wherein the p-contact layer in contact with the p-type layer extends substantially the width of the p-type layer. 16. The method of claim 15, wherein the p-type layer extends substantially the width of the active layer.

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