JP2023511338A - Installation method and installation apparatus for integrated semiconductor wafer equipment - Google Patents

Abstract

Installation method for an integrated semiconductor wafer device, in particular an integrated semiconductor component device as an intermediate product in production, comprising: a glass substrate (1 ), - one or more semiconductor wafers, in particular semiconductor components (9), to be placed in the recesses (2), and - the recesses of the one or more semiconductor wafers (9) engaging the recesses (2) A method having at least one spring element (19) formed on the glass substrate (1) for position retention and/or alignment at location (2) comprises the following method steps: ) with a relaxed spring element (19) engaging the contour space (K) of the semiconductor wafer (9) to be positioned; and/or with an operating element (25) adapted to the contour space (K) of the at least one spring element (19), - moving the glass substrate (1) relative to the spring manipulator substrate (22), which prestresses the spring element (19) outside the contour space (K) of the semiconductor wafer (9) by actuating its operating element (25) into the recess (2) so as to deflect the spring element (19). - placing the semiconductor wafer (9) in the recess (2); and - moving the glass substrate (1) back against the spring manipulator substrate (22), whereby the spring element (19 ) outside the contour space (K) of the semiconductor wafer (9) so that the at least one spring element (19) acts on the semiconductor wafer (9). and holding its position and/or aligning it in the recess (2).

Description

The present invention claims priority from German patent application DE 102020200817.5, the content of which is incorporated herein by reference.

The present invention relates to an installation method for an integrated semiconductor wafer device, in particular an integrated semiconductor component device as a manufacturing intermediate, and to an installation device for carrying out this installation method.

The following information is intended to clarify the background of the invention. The semiconductor industry has grown rapidly thanks to continuous improvements in the integration density of various electronic components. To a large extent, this improvement in integration density results from a reduction in the minimum feature size repetition which means that more components can be integrated in a particular area.

As demands for smaller size, higher speed and greater bandwidth and lower power consumption have increased in recent years, the need for smaller and more creative packaging technologies for unpackaged semiconductor wafers, also called dies, has risen. are doing.

In the course of sequential integration, a large number of assemblies previously mounted adjacent to each other on circuit substrates as individual semiconductor wafers are combined to form a "larger" semiconductor wafer. In this case, "larger" means the number of circuits on a die, as the absolute size can be reduced through continuous improvement in manufacturing methods.

In stacked semiconductor devices, active circuits, such as logic circuits, memory, processor circuits, etc., are at least partially fabricated on separate substrates and then physically and electrically coupled together to form functional devices. . Such bonding methods use very sophisticated techniques and improvements are desired.

A combination of two complementary assemblies, for example a CPU and a cache on a semiconductor wafer, can be rewritten using the term "on-die": the CPU has the cache "on-die", i.e. it has the cache directly on the same semiconductor wafer. , which speeds up the exchange of data considerably. Assembly Technology and Packaging Technology (AVT) deals with further processing of semiconductor wafer packaging and integration into circuit environments.

Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual semiconductor wafers on the wafer are singulated by cutting the integrated circuits along cutting lines. Individual semiconductor wafers are typically packaged (encapsulated) separately, eg, in multi-semiconductor wafer modules or in other types of packages.

A wafer level package (WLP) structure is used as a packaging structure for semiconductor components of electronic products. Increased demand for large numbers of electrical input/output (I/O) terminals and high power integrated circuits (ICs) allows for greater center-to-center distances for electrical I/O terminals. led to the development of WLP structures of the type.

In this case, an electrical redistribution structure with one or more electrical redistribution layers (redistribution layers: RDL) is used. Each RDL may be designed as a structured metallization layer and acts as an electrical interconnect. Electrical wiring connects the encapsulated electronic components to external terminals of the semiconductor component package and/or to one or more electrodes of one or more semiconductor wafers located on the bottom surface of the semiconductor component package.

US Pat. No. 5,300,001 discloses a semiconductor package in which a semiconductor wafer is embedded in a casting/potting material. A redistribution layer includes solder balls for surface mounting of semiconductor wafer packages. A via through the semiconductor package (through glass via) has a solder material on the surface of the semiconductor package so that the second semiconductor package can be stacked on top of the first semiconductor package.

US Pat. No. 5,300,009 discloses a semiconductor wafer package for surface mounting. A plurality of terminals are provided on the major surface to which a second semiconductor wafer package can be attached.

US Pat. No. 5,300,008 discloses an electronic module with logic circuit components and power components. Logic circuitry and power components are placed on substrates positioned one above the other and molded together.

US Pat. Nos. 6,301,001 and 6,000,000 further describe TSMC's 3D semiconductor wafer integration. Semiconductor wafers are molded in plastic resin and vias are made in the form of through-silicon vias or embedded in the casting material in the form of metal rods.

US Pat. No. 6,200,000 deals with underfilling of CSPs and discloses a holder having a recess with sidewalls for receiving a semiconductor chip in its carrier as an in-manufacturing-intermediate product therein.

US Pat. No. 6,200,000 discloses a holder for processing chips made of metal or plastic, which has resilient means and recesses for receiving at least partially aligned chips.

In addition, US Pat. No. 6,200,000 relates to complex 3D integration, and US Pat.

Introduction of the casting material results in relative movement between the semiconductor wafers and relative movement to predetermined intended locations for the semiconductor wafers. Curing-induced shrinkage of the casting material creates additional tension forces that can lead to uneven deformations. The dynamic forces of the incoming casting material also cause drift of the semiconductor wafer on the substrate. Moreover, it is already known that machining the backside metallization can cause warping problems.

To avoid the above disadvantages, the closest prior art, US Pat. Prior to introduction of the casting material, a substrate made of glass having at least one recess in which the casting material is introduced is positioned or secured against the semiconductor wafers so that at least the individual semiconductor wafers are aligned with the walls of the glass substrate. surrounded by Therefore, placing one or more semiconductor wafers in respective recesses and placing them separately from the other semiconductor wafers optimally protects them from undesired effects caused by the introduction of the casting material. be done. Tests have already shown that the glass substrate limits the displacement of the semiconductor wafer parallel to the main plane of extension of the substrate or of the plastic substrate carrying the semiconductor wafer to less than 100 μm and in some embodiments to less than 10 μm. ing. For this purpose, the glass substrate forms a mask with recesses adapted to the semiconductor wafer, which can preferably already be provided with through-holes (through glass vias: TGV) to allow through-connections. do.

DE102007022959A1 US6716670B1 DE102006033175A1 US2014/0091473A1 US2015/0069623A1 WO1998/037580A1 US4953283A US2015/0303174A1 US2017/0207204A1 WO2019/091728A1

Furthermore, it is known from this prior art according to DE 10 2005 003 000 A1 to provide the walls of the glass substrate with spring elements for holding and/or orienting the semiconductor wafer in the recess. The introduction of the semiconductor wafer into the corresponding recesses presents a problem here, because for this purpose the delicate spring elements are positioned outside the space occupied by the outline of the semiconductor wafer. This is because there must be a proper handling between the positions--herein referred to as "contour space"--and the positions acting on the semiconductor wafer.

To solve this problem, the present invention provides a corresponding installation method for such an integrated semiconductor wafer device as a manufacturing intermediate according to the characterizing part of claim 1 and a corresponding implementation of the method according to claim 8. provides a corresponding installation device for

Accordingly, the installation method according to the invention has the following steps:
- the glass substrate is provided with a relaxed spring element that engages the contour space of the semiconductor wafer to be positioned;
- the spring manipulator substrate is provided with a manipulation element (manipulation element) adapted to the contour space of the semiconductor wafer to be positioned and/or of the at least one spring element,
- moving the glass substrate relative to the spring manipulator substrate, thereby prestressing the spring element outside the contour space of the semiconductor wafer and allowing its manipulation element to enter the recess so as to deflect the spring element; ,
- placing the semiconductor wafer in the recess, and - moving the glass substrate back against the spring manipulator substrate, thereby releasing the spring element by moving its manipulation element outside the contour space of the semiconductor wafer. movement, so that at least one spring element acts on the semiconductor wafer to hold its position in the recess and/or align it.

The method according to the invention uses a spring manipulator substrate in order to achieve a defined and very gentle manipulation of one or more spring elements on a glass substrate in a technically simple manner.

Glass substrates and spring manipulator substrates are processed by laser irradiation with nonlinear self-focusing and then undergo anisotropic material removal by etching at a suitable etch rate and for a suitable etch duration, so that they are nearly flat. A smooth wall surface is created as the boundary surface of the recess and the side of the existing structure in the substrate, whereby the semiconductor wafer can be placed at a very small distance from the side wall surface and hence from the adjacent semiconductor wafer.

Laser-induced deep etching, known by the name LIDE (Laser Induced Deep Etching), is used in a method for manufacturing recesses forming sidewall surfaces in glass substrates and spring manipulator substrates. In this case, the LIDE method makes it possible to introduce very precise holes (through glass vias = TGV) and structures at very high speeds, thus making it possible for rational production of glass substrates and spring manipulator substrates. requirements are brought.

The dependent claims specify preferred developments of the installation method according to the invention. The operating element therefore penetrates into its recess to a maximum depth of less than half the thickness of the glass substrate. This represents a sensible compromise between the required operating stroke for the spring element(s) and the smallest possible undercut of the available depth of the recess to accommodate the semiconductor wafer.

The operating element preferably enters the recess in the glass substrate from below, so that the semiconductor wafer can conveniently fit into the recess from above.

A convenient shape for the operating element is a trapezoidal projection with a trapezoidal cross-section and with lateral operating flanks for each spring element. This projection may preferably be integrally formed on the plate-like base of the spring manipulator substrate. The obliquely set lateral operating flanks produce a gradual and therefore gentle action on the delicate spring elements. Here, the operating elements themselves are designed to be sufficiently stable for a large number of production cycles.

The semiconductor wafer in the recess is preferably located on the operating element in a raised intermediate position by relative movement between the glass substrate and the spring manipulator substrate, the operating element being displaced outwardly from the recess. It is then lowered to its final position in the recess. By extension of the spring manipulator substrate and associated actuation/activation of the spring element, it is held in the recess by said spring element and aligned therein.

In one method technical development, the semiconductor wafer may be subjected to a vacuum as an additional fixing for the semiconductor wafer temporarily located on the operating element. Similarly, the application of negative pressure between the glass substrate and the spring manipulator substrate can also ensure relative movement between these two components.

In terms of the device, according to one preferred embodiment, a continuous suction channel in the thickness direction is formed in the spring manipulator substrate, in particular in the base body and/or the operating element.

Exemplary embodiments are shown in the drawings and are described below to further explain the invention.

Fig. 2 shows a vertical cross-sectional illustration of a glass substrate (glass substrate) with recesses and through glass vias (TGVs) in an embodiment not according to the invention; Fig. 2 shows a horizontal cross-sectional illustration of a glass substrate with recesses and through-glass vias, also in an embodiment not according to the invention; 1 shows a vertical cross-sectional illustration of an integrated semiconductor wafer package. 1 shows a schematic cross-sectional plan view of one embodiment of an integrated semiconductor wafer device with spring elements for orienting a semiconductor wafer; FIG. (and FIG. 6) shows a schematic cross-sectional plan view of a glass substrate in a further embodiment with spring elements in two different installation positions; (and FIG. 5) shows a schematic cross-sectional plan view of a glass substrate in a further embodiment with spring elements in two different installation positions; 1 shows a schematic vertical section illustration of an installation device with a glass substrate, the glass substrate and the spring manipulator substrate in a relative position away from each other; FIG. 7 shows an illustration similar to FIG. 7, with the spring manipulator substrate penetrating the glass substrate. Figure 9 shows an illustration similar to Figures 7 and 8 with successive installation-intermediate stages for the installation device; Figure 9 shows an illustration similar to Figures 7 and 8 with successive installation-intermediate stages for the installation device; Figure 9 shows an illustration similar to Figures 7 and 8 with successive installation-intermediate stages for the installation device; Figure 9 shows an illustration similar to Figures 7 and 8 with successive installation-intermediate stages for the installation device;

Figure 1 shows the most important features of a glass substrate 1 intended for the installation method described below. A glass substrate 1 of thickness D is provided with a plurality of recesses 2 and spacings b. A through hole 4, known as a "through glass via", TGV for short, is formed in the wall 3 of the glass substrate 1, surrounding the recess 2, and is conventionally provided with a metallization 5. introduced into The glass substrate 1 consists at least essentially of alkali-free glass, in particular of aluminoborosilicate glass or borosilicate glass.

FIG. 2 shows a plan view of a similar glass substrate 1 again with a recess 2 which is rectangular in plan view. In the area of the wall 3, through holes 4 are introduced on both sides of the recess 2 shown on the left in FIG. Further through holes 4 of this type are located in two parallel rows below the recesses 2 shown on the right in FIG.

The recess 2 may be designed as a through hole--as shown in FIG. 1--but it may also be designed as a blind hole.

Further geometrical ratios in the case of the glass substrate 1 according to FIGS. be. The wall thickness b of the wall 3 is less than 500 μm, preferably less than 300 μm, less than 200 μm, less than 100 μm or less than 50 μm, preferably less than the material thickness D of the glass substrate 1 . Correspondingly, the ratio b/D of the maximum remaining wall thickness b between two recesses 2 in the glass substrate 1 to its material thickness D is less than 1:1, preferably less than 2:3, 1 : less than 3 or less than 1:6.

As can be seen from FIG. 3, the size of the recess 2 in the glass substrate 1 is in principle chosen such that the semiconductor component 9 can be accommodated there with the smallest possible distance from the side wall surface 8 . The positions of the recesses 2 are chosen such that they correspond to the desired subsequent positioning of semiconductor components 9 formed as semiconductor wafers in an integrated semiconductor component arrangement known as a so-called "chip package" or "fan-out package". .

FIG. 3 now shows schematically how the glass substrate 1 can be used in the manufacture of chip packages. The distance between the side wall surface 8 of the wall 3 and the side surface of the semiconductor component 9 facing them is in this case for example less than 30 μm, preferably less than 20 μm, less than 10 μm or less than 5 μm.

A casting material 12 is poured into the recesses to fix the semiconductor components 9 in their position within the glass substrate 1 . This results in a small unit of semiconductor component 9 embedded in the glass substrate 1 , the through holes 4 introduced therein by the metallization 5 and the casting material 12 . Further processing of the device according to FIG. 3 by applying solder balls positioned there to contact the redistribution layer and the semiconductor component 9 is not the subject of the present invention and is described in detail in US Pat.

For the corners of the component 9--as shown in FIG. It is possible to form notches 17 in the glass substrate 1 in the corner regions of each recess 2 .

Furthermore, a plurality of stops 18 protruding from the side wall surface 8 are arranged on the glass substrate 1 , so that a so-called “overdeterminism” when fixing the position of the semiconductor component 9 in the recess 2 can be avoided.

Finally, the pre-fixing of the semiconductor component 9 is additionally further optimized by two spring elements 19 on the side wall surface 8 of the glass substrate 1 facing the stop 18 . However, it should be noted that the structural element recesses 17, stoppers 18 and spring elements 19 can also be inserted separately, each alone or otherwise in various combinations, into various recesses 2 of the integrated semiconductor wafer device. .

Installation methods embodying the present invention and installation devices correspondingly used therein are described in more detail below. In this case, FIGS. 5 and 6, like FIG. 4, again show a glass substrate 1 with a recess 2 for receiving a semiconductor wafer, not depicted here. It is indicated only by its contour space K marked in dashed form in FIGS. Contour space K represents the outer profile occupied by the semiconductor wafer with respect to its plan view. In this embodiment, the two spring elements 19 are each formed by a spring arm 20, which at their ends connects to the glass substrate and at their other ends points towards each other. , projecting slightly obliquely into the recess 2 in their relaxed position shown in FIG. The spring arm 20 thereby engages the contour space K. FIG. 6 shows the biased tensioned position of the spring arms 20, in which they have moved outside the contour space K and no longer intersect it.

7 and 8, the installation device 21 according to the invention will now be described, the core component of which is the spring manipulator substrate 22 . It is likewise produced in a glass substrate 1 using a corresponding filigree method, comprising a plate-shaped base body 23 and trapezoidal projections with a trapezoidal cross-section and with lateral operating flanks 26. and an operating element 25 formed on its upper side 24 in a form. The profile and height of these operating elements 25 are chosen so that they can adequately intersect the spring arms 20 of the spring elements 19 . In particular, in order to move the glass substrate 1 with respect to the spring manipulator substrate 22 , the spring manipulator substrate 22 is moved from below relative to the glass substrate 1 so that the operating element 25 projects into the recess 2 . , gradually grasp the spring arms 20 by their operating flanks 26 and bring them from the relaxed position shown in FIGS. This step is also illustrated in Figures 9a and 9b.

In this position, the contour space K is opened so that the spring arm 20 is pushed outwards to such an extent that the semiconductor component 9 can be placed from above in the recess 2 on the operating element 25 located there without any hindrance. - see Figure 9c.

The spring manipulator substrate 22 is then lowered again so that first the respective semiconductor component 9 is lowered further into the recess 2 and then the spring arm 20 is released. These spring arms thus act on the semiconductor components 9 and align them in the recesses 2 precisely in position. Based on this intermediate manufacturing step, it is again possible - analogously to the prior art, as described above - to cast the semiconductor component 9 into the recess 2 and apply a redistribution layer and solder balls.

From the point of view of the device, the spring manipulator substrate 22 still has to be supplemented by providing continuous suction channels 27, 28 in the thickness direction DR in the region of the operating element 25 and between them. The suction channel 27, centrally drawn in FIGS. 9a-9d, is level with the wall 3 between the recesses 2 and is drawn between the glass substrate 1 and the spring manipulator substrate 22 by application of a negative pressure p. It functions to drive motion during relative movement. The semiconductor components 9 are likewise fixed in their position on the operating element 25 via another suction channel 28 by application of a negative pressure p.

The bending/deflection of the spring arm 20 is about 5 to 100 μm. The height h of the operating element 25 and thus its maximum penetration depth t into the recess is rather small, preferably less than half the thickness D of the glass substrate 1 .

1 glass substrate 2 recess 3 wall 9 semiconductor wafer 19 spring element 22 spring manipulator substrate 25 operating element K contour space

Claims (11)

An installation method for an integrated semiconductor wafer device, in particular an integrated semiconductor component device as an intermediate product in manufacturing, comprising:
- a glass substrate (1) having at least one recess (2) formed by a wall (3),
- one or more semiconductor wafers, in particular semiconductor components (9), to be placed in said recess (2); at least one spring element (19) formed in the glass substrate (1) for position retention and/or alignment in the recess (2),
The following method steps:
- said glass substrate (1) is provided with a relaxed spring element (19) engaging the contour space (K) of said semiconductor wafer (9) to be positioned,
- a spring manipulator substrate (22) with an operating element (25) adapted to said contour space (K) of said semiconductor wafer (9) to be positioned and/or of said at least one spring element (19),
- moving said glass substrate (1) relative to said spring manipulator substrate (22), thereby prestressing said spring elements (19) outside said contour space (K) of said semiconductor wafer (9); and causing its operating element (25) to enter said recess (2) so as to deflect said spring element (19),
- placing said semiconductor wafer (9) in said recess (2); and - moving said glass substrate (1) back with respect to said spring manipulator substrate (22), thereby said spring element. (19) to move its operating element (25) outside said contour space (K) of said semiconductor wafer (9), so that said at least one spring element (19) acting on the wafer (9) to hold its position and/or align it in said recess (2);
A method characterized by 4. Characterized in that said operating element (21) penetrates said recess (2) to a maximum penetration depth (t) which is less than half the thickness (D) of said glass substrate (1). 1. The installation method described in 1. 3. Installation method according to claim 1 or 2, characterized in that the operating element (25) enters the recess (2) of the glass substrate (1) from below. 4. Any one of claims 1 to 3, characterized in that a projection with a trapezoidal cross-section and with lateral operating flanks (26) for the spring element (19) is used as the operating element (25). Installation method described in item 1. The semiconductor wafer (9) in the recess (2) rests on the operating element (25) in a raised intermediate position, the operating element (25) being moved outwards from the recess (2). Installation method according to any one of the preceding claims, characterized in that it is lowered to its final position in said recess (2) when it is pressed. 6. The method according to claim 5, characterized in that the semiconductor wafer (9) located on the operating element (25) is fixed on the operating element (25) in the intermediate position by application of a vacuum. Installation method. Claims 1 to 6, characterized in that the relative movement between the glass substrate (1) and the spring manipulator substrate (22) is realized by application of a vacuum (p) between these two components. The installation method according to any one of . An installation device for carrying out the installation method according to any one of claims 1 to 7,
a spring manipulator substrate (22) movable relative to said glass substrate (1) in its thickness direction (DR);
Said spring manipulator substrate (22) has at least one operating element (25) adapted to said contour space (K) of said semiconductor wafer (9) to be positioned and/or of said at least one spring element (19). A setting device comprising: 9. Installation according to claim 8, characterized in that the spring manipulator substrate (22) is formed from a plate-like base body (23) with the at least one operating element (25) arranged thereon. Device. 10. According to claim 8 or 9, characterized in that the operating element (25) is designed as a projection with a trapezoidal cross-section and with lateral operating flanks (26) for the spring element (19). Installation equipment as described. A suction channel (27, 28) continuous in the thickness direction (DR) is formed in the spring manipulator substrate (22), in particular in the plate-like substrate (23) and/or the operating element (25). 11. The installation device according to any one of claims 8 to 10, characterized in that:

Images