JP2023173902A - Imaging element - Google Patents

Abstract

To control two elements of spatial resolution and time resolution more in detail while decreasing the number of transistors added to one common pixel structure to one.SOLUTION: An imaging element is based upon a 4-transistor type, and each common pixel structure 10 is provided with one transfer gate control transistor (hereinafter, TGC), and the TGC has its gate connected to one of a transfer timing signal line and a transfer gate control signal line, and one of its source and drain connected to the other of the transfer timing signal line and transfer gate control signal line and the other connected to the gate of each gate transistor (hereinafter TG), where the number of common pixel structure included in each control unit is N and the number of TGs that each common pixel structure has is N, a TGC provided for each common pixel structure being connected to the gate terminal of one TG made to correspond to the TGC among N TGs provided for the common pixel structure to drive the TG.SELECTED DRAWING: Figure 1

Description

The present invention particularly relates to an imaging device for acquiring moving images, in which pixel portions are arranged in an array, and signals from at least some of the pixel portions in the row direction are simultaneously read, for example.

An image sensor (hereinafter simply referred to as an image sensor) converts light imaged by an imaging lens into electricity using photodiodes arranged in a two-dimensional plane, and reads out photo-induced charges accumulated in the photodiodes. This is a semiconductor chip that has the function of acquiring a two-dimensional spatial distribution of light intensity as an image. Further, an image sensor for capturing a moving image captures a moving image by periodically reading charges accumulated in pixels.
When shooting moving images, generally, if the number of pixels in the horizontal direction is H, the number of pixels in the vertical direction is V, and the frame rate that is the image readout cycle is F [fps], the number of pixels read out per second is The "pixel readout rate" is obtained by multiplying H×V×F [pixel/sec], and the value of this rate has a large effect on power consumption, A/D conversion circuit performance, and output data rate. give. In the field of image sensors, in addition to introducing cutting-edge semiconductor manufacturing technologies such as microfabrication processes and three-dimensional stacking technology, efforts are being made to improve circuit technology and on-chip signal processing technology to improve performance. It is not easy to increase the pixel readout rate.

In the general video acquisition method described above, the spatial resolution (number of pixels in horizontal and vertical directions) and temporal resolution (frame rate) of the video image acquired are both constant during shooting due to the structure of the image sensor. However, in view of the nature of moving images, it does not necessarily have to be constant.
That is, when photographing a stationary object, there is no need to maintain a high frame rate, and even when photographing at a low frame rate, it is possible to suppress a decrease in subjective image quality. On the other hand, when photographing a moving object, the spatial frequency is reduced due to motion blur, so there is no need to maintain a high spatial resolution, and even when photographing at a low spatial resolution, the subjective image quality It is possible to suppress the decrease in

Considering the above-mentioned characteristics of video images, when the object to be photographed is stationary, the spatial resolution is high and the frame rate is low, and when the object is moving, the spatial resolution is low and the frame rate is high. Compared to an image sensor that captures images with high spatial resolution and high frame rate, an image sensor that can capture images with high spatial resolution and a high frame rate can suppress deterioration in subjective image quality while keeping the pixel readout rate low.
Additionally, since the photographed screen generally contains various objects that move at different speeds, some areas are photographed with high spatial resolution and low frame rate, while others are photographed with low spatial resolution and high frame rate. It is desirable that a screen is constructed by combining areas photographed at a frame rate with each other.

As a technique for realizing such imaging, an image sensor using a pixel parallel structure described in Patent Document 1 below is known. This image sensor has a structure in which one A/D conversion circuit is formed for each pixel in the same area as the pixel using a three-dimensional laminated structure. With this structure, since a readout operation can be performed independently for each pixel, it is possible to realize control of spatial resolution and frame rate.
In addition, the following non-patent document 1 describes that instead of providing one A/D conversion circuit for one pixel as in the following patent document 1, 16 A/D conversion circuits are provided for 16 × 16 pixels. An image sensor is disclosed in which a circuit is formed and the exposure time is controlled for each block.
Further, Non-Patent Document 2 listed below discloses an image sensor in which a 1-bit memory is provided in each pixel, and pixel readout is skipped based on information recorded in the memory.

International publication number WO2016/009832 A1

T. Hirata et. al., “7.8 A 1-inch 17Mpixel 1000fps Block-Controlled Coded-Exposure Back-Illuminated Stacked CMOS Image Sensor for Computational Imaging and Adaptive Dynamic Range Control,” in 2021 IEEE International Solid- State Circuits Conference (ISSCC ), San Francisco, CA, USA, Feb. 2021, pp. 120-122. doi: 10.1109/ISSCC42613.2021.9365740. J. Zhang, J. P. Newman, X. Wang, C. S. Thakur, and J. Rattray, “A Closed-Loop, All-Electronic Pixel-Wise Adaptive Imaging System for High Dynamic Range Videography,” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, vol. 67, no. 6, p. 12, 2020.

In the technology described in Patent Document 1, it is difficult to make the pixel smaller than the area of the A/D conversion circuit, so there is a limit to the miniaturization of the pixel, and the size of the pixel actually reported is is as large as 6.9 μm, and the goal of miniaturization has not been achieved.
Furthermore, according to the technology described in Non-Patent Document 1, it is known that the pixel size can be reduced to 2.8 μm, but the control unit is coarse, 16 × 16 pixels, and the control Since this method is limited to controlling the exposure time using a shutter, it is not possible to change the two elements of spatial resolution and temporal resolution while maintaining the pixel readout rate constant.
Furthermore, according to the technology described in the above-mentioned Non-Patent Document 2, it is possible to control the spatial resolution by thinning readout and the temporal resolution by adjusting the frame rate by skipping readout. This requires additional transistors, making it difficult to reduce the pixel size. In fact, the pixel size reported in Non-Patent Document 2 is 6.5 μm.

In this way, in the conventional technology, it is theoretically possible to control the spatial resolution and temporal resolution, but the number of added transistors is large and it is not possible to achieve pixel miniaturization, or it is possible to miniaturize the pixel. However, the units of control are either coarse or coarse, and there has been a desire for an image sensor that can control pixels smaller than the 5 μm size generally used in television cameras with high precision.

By the way, with current semiconductor manufacturing technology, transistors can only be formed on the wafer surface, so the number of built-in transistors has a large effect on the pixel size. On the other hand, in recent years, it has become common to manufacture image sensors with a back-illuminated structure in which light enters from the opposite side to the side on which the wiring is formed, and the wiring layers are formed in multiple layers of four or more layers. Therefore, there are few restrictions on pixel size due to wiring formation.
Therefore, in order to reduce the pixel size, it is important to reduce the number of transistors per pixel.

In recent years, it has become possible to reduce the number of transistors per pixel (photodiode) by adopting a shared pixel structure in which multiple pixels (photodiode PD) share one floating diffusion FD, amplification transistor SF, and selection transistor SL. It is common practice to keep the number of transistors per shared pixel constant and as small as possible in order to achieve a desired function while suppressing deterioration and variation in sensitivity. Of course, when adding functionality, it is most desirable to have a structure in which the number of additional transistors per shared pixel structure, which is a repeating unit, can be suppressed to one.
The present invention provides an image sensor that is miniaturized by reducing the number of transistors added per shared pixel structure to one, and has a structure that allows finer control of two elements, spatial resolution and temporal resolution. The purpose is to

The image sensor of the present invention includes:
At least a predetermined number of photodiodes, and a transfer gate transistor provided corresponding to each of the photodiodes, which directly or indirectly reads out the charge accumulated in each of the photodiodes to a floating diffusion; A predetermined number of shared pixel structures are provided for each control unit, including a reset transistor that resets the floating diffusion to a predetermined voltage, and a source follower transistor that reads the charge read out to the floating diffusion as a voltage,
Further, each of the shared pixel structures is provided with one transfer gate control transistor;
The transfer gate control transistor has a gate terminal connected to one of a transfer timing signal line and a transfer gate control signal line, and one of a source terminal and a drain terminal connected to the other of the transfer timing signal line and the transfer gate control signal line. and the other of the source terminal and the drain terminal is connected to the gate terminal of the transfer gate transistor,
When the number of shared pixel structures included in each of the control units is N, the number of transfer gate transistors included in each shared pixel structure is N,
The one transfer gate control transistor provided in each of the shared pixel structures is one of the N transfer gate transistors provided in each of the shared pixel structures corresponding to the one transfer gate control transistor. The device is characterized in that it is connected to each of the gate terminals of the transfer gate transistors and is configured to drive the transfer gate transistors.
Further, the shared pixel structure can be configured to include a selection transistor that outputs the voltage read out by the source follower transistor to an output signal line.

Here, the above-mentioned "predetermined number" means any number selected from "one or more".
In addition, "directly" in "directly or indirectly" means that a transistor for reading out the charge accumulated in each of the photodiodes to a floating diffusion corresponds to each of the photodiodes. ``Indirectly'' in ``directly or indirectly'' means that the transfer gate transistor provided is a transfer gate transistor that reads out the charge stored in each of the photodiodes into a floating diffusion. This means that in addition to the transfer gate transistor provided corresponding to each of the photodiodes, another transistor combined with the transfer gate transistor is provided as a transistor for the photodiode and the floating diffusion. This means that one or more predetermined transistors are provided in addition to the transfer gate transistor and are provided in series with the transfer gate transistor. For example, the predetermined transistor is set to be a global transfer transistor and is driven by a signal line common to the image pickup device.
Furthermore, the terms "one of the transfer timing signal line and the transfer gate control signal line" and "the other of the transfer timing signal line and the transfer gate control signal line" are replaced by "one of the transfer timing signal line and the transfer gate control signal line" If is a transfer timing signal line, "the other of the transfer timing signal line and the transfer gate control signal line" becomes the transfer gate control signal line, and "one of the transfer timing signal line and the transfer gate control signal line" becomes the transfer gate control signal line. If it is a line, it means that "the other of the transfer timing signal line and the transfer gate control signal line" becomes the transfer timing signal line.
In addition, the terms "one of the source terminal and the drain terminal" and "the other of the source terminal and the drain terminal" are used when "one of the source terminal and the drain terminal" is the source terminal, and "the other of the source terminal and the drain terminal" is the source terminal. " is a drain terminal, and if "one of the source terminal and the drain terminal" is the drain terminal, it means that "the other of the source terminal and the drain terminal" is the source terminal.

A plurality of pixels to which transfer timing signals from the transfer timing signal line are simultaneously input are arranged in one of a row direction and a column direction, and a plurality of pixels to which transfer gate control signals from the transfer gate control signal line are simultaneously input. The pixels may be arranged in one of the row direction and the column direction.
Here, the terms "one of the row direction and the column direction" and "the other of the row direction and the column direction" mean that if "one of the row direction and the column direction" is the row direction, "the row direction and the column direction "The other" means the column direction, and if "one of the row direction and the column direction" is the column direction, "the other of the row direction and the column direction" means the row direction.

Further, the transistors included in each of the shared pixel structures include N transfer gate transistors, and one each of the reset transistor, the source follower transistor, the selection transistor, and the transfer gate control transistor. It can be done.

Further, the number of the shared pixel structures included in each of the control units may be set to four, and the number of transfer gate transistors included in each of the shared pixel structures may be set to four.
In this case, each of the control units can be configured by arranging two shared pixel structures in the horizontal direction and two in the vertical direction.
Furthermore, each of the control units can be configured by arranging one shared pixel structure in one of the horizontal and vertical directions and four shared pixel structures in the other of the horizontal and vertical directions.

According to the image sensor of the present invention, the number of shared pixel structures included in each control unit is N, and each control unit includes ^N2 pixels (photodiodes), and each of the shared pixel structures has one The transfer gate control transistor has its gate terminal connected to one of the transfer timing signal line and the transfer gate control signal line, and its source terminal or drain terminal connected to the transfer timing signal line. and the other of the transfer gate control signal lines, and the other of the source terminal and the drain terminal is connected to the gate terminal of the transfer gate transistor. Furthermore, when the number of the shared pixel structures included in each control unit is N, the number of transfer gate transistors included in each shared pixel structure is N, and each of the transfer gate control transistors The one transfer gate control transistor provided in the shared pixel structure is one transfer gate control transistor corresponding to the one transfer gate control transistor among the N transfer gate transistors provided in each of the shared pixel structures. The transfer gate transistor is connected to each of the gate terminals of the gate transistor and configured to drive the transfer gate transistor.
This allows you to arbitrarily select between the first readout method, which reads out pixel signals individually to increase spatial resolution, and the second readout method, which reads out signals from multiple pixels together and increases the frame rate (temporal resolution). It is possible to do so.
In other words, it is possible to provide an image sensor that can more finely control the two elements of spatial resolution and temporal resolution for each control unit while limiting the number of transistors added per shared pixel structure to one. Become.

1 is a schematic diagram showing a circuit configuration of an image sensor according to Embodiment 1. FIG. FIG. 2 is a schematic diagram showing an enlarged configuration of one shared pixel structure (N=2) of the image sensor shown in FIG. 1. FIG. 3 shows a timing chart of each drive signal in the image sensor according to the first embodiment. 2 is a schematic diagram showing a circuit configuration of an image sensor according to a modification of Embodiment 1. FIG. FIG. 2 is a schematic diagram showing a circuit configuration of an image sensor according to a second embodiment. 6 is a schematic diagram showing a simplified configuration of each control unit of the image sensor shown in FIG. 5. FIG. FIG. 7 is a schematic diagram showing a simplified configuration of each control unit of an image sensor according to a modification of the second embodiment. FIG. 7 is a schematic diagram showing a simplified configuration of a control unit of an image sensor according to Embodiment 3. FIG. 1 is a schematic diagram showing a circuit configuration of an image sensor according to a prior art.

Hereinafter, an image sensor according to an embodiment of the present invention will be described with reference to the drawings.
(Embodiment 1)
First, the basic configuration of the image sensor 100 according to the first embodiment (N=2 (N is the number of shared pixel structures in each control unit; the same applies hereinafter)) will be explained with reference to FIG. This will be explained in comparison with FIG. 9, which shows the basic configuration of an image sensor 400 according to the technique (N=2). Note that FIG. 2 shows an enlarged view of one shared pixel structure 10 of the image sensor 100 according to the first embodiment.
In this embodiment, members whose functions are substantially the same as those of the prior art shown in FIG. 9 are denoted by the same reference numerals.
That is, the image sensor 100 according to the present embodiment includes a pixel array area in which a plurality of pixels each having a photodiode (photoelectric conversion unit: PD) are arranged in an array, and By driving the arrayed pixels and the pixels arrayed in the column direction (vertical direction in the figure), the charge accumulated in the pixels is read out as a signal.

First, an image sensor 400 according to the prior art to be compared will be described. As shown in FIG. 9, since the number of shared pixel structures in each control unit is two (N=2), this image sensor 400 has two photodiodes PD (hereinafter simply referred to as PD). , one floating diffusion FD (hereinafter simply referred to as FD), two transfer gate transistors TG (hereinafter simply referred to as TG), one reset transistor RT (hereinafter simply referred to as RT), one The transistor is composed of a total of five transistors, including a source follower transistor SF (hereinafter simply referred to as SF), and one selection transistor SL (hereinafter simply referred to as SL). Here, in FIG. 9, each transistor is represented by one gate, and the structure for controlling the high resistance state and the low resistance state between the diffusion layers at both ends is shown in a simplified manner (Fig. 1 (The same applies to)

In FIG. 9, if the PD located in the top row of the drawing is defined as the first PD (k=1) and the PD located in the row below it as the second PD (k=2), then the first PD is defined as the first TG timing signal ( The gate voltages of the corresponding first TG and second TG are controlled by the second PD and the second TG timing signal (TG(y+1)), and charges are read out from the PD to the FD. The first TGs in the top row of the shared pixel structure 40 are all controlled by the same first TG timing signal (TG(y)), and the second TGs are all controlled by the same second timing signal (TG(y+1)). Therefore, all the shared pixel structures 40 in the same row perform the same operation.

In contrast, in the image sensor 100 of the first embodiment shown in FIGS. 1 and 2, one transfer gate control transistor TGC (hereinafter simply referred to as TGC) is added to each shared pixel structure 10, and N=2 Therefore, each control unit is provided with two shared pixel structures (a first shared pixel structure and a second shared pixel structure) arranged in the horizontal direction, and a pixel array is formed by repeating the control units. ing.

Here, the configuration of the one-shared pixel structure 10 of the image sensor 100 will be explained using FIG. 2, which is a partially enlarged view of FIG. 1.
Similar to the conventional image sensor shown in FIG. 9, signal charges accumulated in the PD are transferred to the FD by setting the gate voltages of the TGs (first TG, second TG) to a high potential. In this embodiment, a TGC that controls the potential of the gate terminal of the TG is provided for each pixel or for each pixel group that performs the same control.

The gate terminal of this TGC is connected to the TG timing signal line (TG(y)) provided for each row, and the drain terminal (or source terminal) is connected to the TG control signal line (TGCn) arranged in the same number as the vertical signal lines. (x)) (n is a natural number), and the source terminals (or drain terminals) of the TGCs are respectively connected to the gate terminals of the TGs as described above. Note that in the following description, a source terminal or a drain terminal may be simply referred to as a source or a drain, or may be referred to as one diffusion layer and the other diffusion layer, but both have the same meaning.

To explain the above-mentioned contents as a configuration in one control unit, as shown in FIG. 1, the shared pixel structure (first shared pixel structure 10A) arranged on the left in the control unit (y, x) One diffusion layer of the first TGC added to the first TGC receives the first TG control signal (TGC1(x)), the gate receives the TG timing signal (TG(y)), and the other diffusion layer receives the control unit (y , x), the gates of the first TGs in the first shared pixel structure 10A and the second shared pixel structure 10B are connected to each other.

On the other hand, one diffusion layer of the second TGC added to the shared pixel structure (second shared pixel structure 10B) drawn on the right in the control unit (y, ), the gate receives the TG timing signal (TG(y)), and the other diffusion layer receives the TG timing signal (TG(y)) in the first shared pixel structure 10A and the second shared pixel structure 10B included in the control unit (y,x). The gates of the 2TGs are connected to each other.
Note that since the same TG timing signal (TG(y)) is connected to the TGC of each shared pixel structure 10 included in the control unit arranged in the horizontal direction (row direction), the shared pixel structure 10 is The number of TG timing signals crossing in the horizontal direction (row direction) has been reduced from two to one.

According to the characteristic structure of the first embodiment configured as described above, it is possible to select the following four different output results, which cannot be obtained with the prior art, according to the input of the TG timing signal.
(1) When the first TG control signal (TGC1(x)) from the TG control signal line connected to the control unit is input to the source or drain of the first TG, the first TG is turned on and within the control unit. It becomes possible to perform charge transfer from the first PD to the FD.
(2) When the second TG control signal (TGC2(x)) from the TG control signal line connected to the control unit is input to the source or drain of the second TG, the second TG is turned on and within the control unit. It becomes possible to perform charge transfer from the second PD to the FD.
(3) Also, when the first TG control signal (TGC1(x)) and the second TG control signal (TGC2(x)) are both input, charge transfer from the first PD and second PD in the control unit to the FD is performed, and it is possible to read out a signal that is the sum of both.
(4) Also, if both the first TG control signal (TGC1(x)) and the second TG control signal (TGC2(x)) are not input, any one from the first PD and second PD in the control unit to the FD It is also possible to continue exposure and signal accumulation without any charge transfer.

As described above, according to the present embodiment, since the first TG control signal and the second TG control signal can be input for each control unit, such control of charge transfer from the first PD and the second PD is possible. It is possible to perform this independently for each control unit. Further, since the vertical direction (column direction) in the drawing is scanned sequentially with a time difference, it is also possible to independently control the vertical control unit using the time difference.

(Control method of Embodiment 1)
A method of controlling the spatial resolution and temporal resolution for each control unit using the pixel structure of the first embodiment shown in FIGS. 1 and 2 will be described using the timing diagram shown in FIG. 3.
For convenience of explanation, the pixel structure of the first embodiment shown in FIG. 1 is a partial region of four pixels vertically and four pixels horizontally in the pixel array. That is, in the first embodiment, N representing the number of shared pixel structures in one control unit is set to 2, and by arranging two shared pixel structures in the horizontal direction (row direction), the number of shared pixel structures in the vertical direction ( One control unit is a block in which two pixels are arranged in the column direction (column direction) and two pixels are arranged in the horizontal direction (row direction).

In Figure 1, four control units are lined up, and these four control units are (y,x), (y,x+1), (y+1,x), and (y+ 1. By defining the lower right as k=4, it is written as (y,x,k) together with the above address of the control unit.
Corresponding to vertical address y, TG timing signals TG(y) and TG(y+1), reset timing signals RT(y) and RT(y+1), and selection signals SL(y) and SL(y+1) are The TG control signals TGC1(x), TGC2(x), TGC1(x+1), and TGC2(x+1) are input from the bottom of the drawing corresponding to the address x in the horizontal direction. has been done.

Pixel charges are transferred to the FD and read out sequentially in accordance with the scanning that moves vertically on the screen, but in any scan f and the next scan (f+1), the charges in the y and y+1 rows are FIG. 3 shows the signal input to each signal when the read timing comes.
To read the y-th row in scan f, SL(y) is turned on to make SL conductive, RT(y) is turned on to reset the FD, and then TG is turned on at the timing when TG is turned on. (y) is input.

When TGC1(x), TGC1(x+1), and TGC2(x+1) are inputted at the timing when this TG(y) turns on, in accordance with the transfer timing of the yth row of a predetermined scan f, the control unit (y ,x), the charge of pixel (y,x,1) is read out and output to output signal line 1(x), and the charge of pixel (y,x,2) is read out and output to output signal line 2. (x) is output.
On the other hand, in control unit (y,x+1), the charges of pixel (y,x+1,1) and pixel (y,x+1,3) are summed, read out, and output signal line 1 ( x+1), the charges of pixel (y, x+1, 2) and pixel (y, x+1, 4) are summed, read out, and output to output signal line 2 (x+1).

In other words, the signals read by scan f are the signals of pixel (y,x,1), pixel (y,x,2), pixel (y,x+1,1), and pixel (y,x+1,3). Sum, pixel (y,x+1,2) and pixel (y,x+1,4), pixel (y+1,x,1), pixel (y+1,x,2), pixel ( y+1,x+1,1), each charge of pixel (y+1,x+1,2) is read out.

In scan f+1, the input of the TG control signal is different from that in scan f, and the input of the TG control signal is different from that of scan f, and it is pixel (y, x, 3), pixel (y, x, 4), pixel (y, x + 1, 1), and pixel ( y,x+1,3), pixel (y,x+1,2) and pixel (y,x+1,4), pixel (y+1,x,3), pixel (y+ 1,x,4), pixel (y+1,x+1,3), and pixel (y+1,x+1,4) are read out.

To summarize the above, in the control units (y,x), (y+1,x), (y+1,x+1), all pixels are individually scanned using two scans, scan f and scan f+1. If the pattern is read out and this pattern is repeated, the exposure time will be two scan cycles.
On the other hand, in the control unit (y, x+1), in both scan f and scan f+1, the two pixels aligned in the vertical direction within the control unit are read out in total, and the exposure time is one scan cycle. .

In other words, in the control units (y,x), (y+1,x), (y+1,x+1), images with high spatial resolution and low temporal resolution are obtained; ), an image with high temporal resolution can be obtained at the cost of lower spatial resolution due to summing.
Furthermore, the two types of imaging methods are controlled by the TG control signal in the X address direction (horizontal direction in the drawing, row direction), and by time sharing by scanning in the Y address direction (vertical direction in the drawing, column direction). From this, it is possible to read signals by specifying any method for any control unit.

(Modification of Embodiment 1)
FIG. 4 shows a modification of the first embodiment. This modified example also has N=2 as in the first embodiment, and one TGC is added for one shared pixel structure compared to the conventional technology. However, the difference from the first embodiment is that the TG timing signal is input to one diffusion layer of the TGC, and the first TG control signal TGC1(x) and the second TG control signal TGC2(x) are input to the first TGC and the second TGC. The difference is that it is input to the gate terminal of 2'TGC.
In this modification, as in the first embodiment, when the TG timing signal and the kth TG control signal are input simultaneously, the kth TG in the control unit is controlled and the charge is transferred from the kth PD to the FD. Since the effect is the same, detailed explanation will be omitted.

(Embodiment 2)
FIG. 5 schematically shows an image sensor according to a second embodiment in which N is set to 4.
Moreover, FIG. 6 shows a simplified version of each configuration in FIG. 5. In FIG. That is, the corresponding number of the TGC added in each shared pixel structure is shown in a circle, and the corresponding number of each photodiode in each shared pixel structure is shown in a square.
In addition, each control unit is shown surrounded by a dotted line, and the photodiode included in this unit (encircled by □) is controlled by the included TGC with the same number (encircled by ○) (4 One shared pixel structure is represented by two □ and one ○).

In the conventional technology (not shown), when N is 4, the shared pixel structure includes 4 PDs, 1 FD, 4 TGs, 1 RT, 1 SF, and 1 pixel structure. It is composed of a total of seven SL transistors. Here, in each shared pixel structure, the PD located at the upper left in the drawing is the first PD (k = 1), the PD located at the upper right in the drawing is the second PD (k = 2), and the PD located at the lower left in the drawing If we define the PD as the third PD (k=3) and the PD located at the lower right in the drawing as the fourth PD (k=4), the gate voltage of the corresponding kth TG is controlled by the kth TG timing signal, Charges are read out from the kth PD to the FD (k is any natural number from 1 to 4).
Since the kth TG included in each shared pixel structure arranged in the horizontal direction (row direction) is all controlled by the same kth timing signal, all the shared pixel structures in the same row perform the same operation.

On the other hand, the pixel structure of the image sensor according to the second embodiment is different from the above-mentioned conventional technology in that one transistor (TGC) is added for one shared pixel structure. Also, since N is 4, one control unit is formed by a total of four shared pixel structures, two in the horizontal direction and two in the vertical direction, and such a two-dimensional control unit (y, x) A pixel array is formed by repeating the steps.

In each control unit, a first TG control signal line (TGC1(x)) is connected to the gate of the TGC (first TGC) arranged in the shared pixel structure (first shared pixel structure 20A) drawn at the upper left in the drawing. , a TG timing signal line (TG(y)) was arranged in one diffusion layer (source or drain), and one for each shared pixel structure of this control unit in the other diffusion layer (source or drain). The gates of the four first TGs are connected to each other.

Furthermore, in each control unit, in the TGC (second TGC) arranged in the shared pixel structure (second shared pixel structure 20B) drawn in the upper right corner of the drawing, the gate is connected to the second TG control signal line (TGC2(x)). ), one diffusion layer (source or drain) is provided with a TG timing signal line (TG(y)), and the other diffusion layer (source or drain) is provided with one TG timing signal line (TG(y)) for each shared pixel structure of this control unit. The gates of the four second TGs are connected to each other.

Furthermore, in each control unit, in the TGC (third TGC) arranged in the shared pixel structure (third shared pixel structure 20C) drawn at the lower left in the drawing, the gate is connected to the third TG control signal line (TGC3(x)). ), one diffusion layer (source or drain) is provided with a TG timing signal line (TG(y)), and the other diffusion layer (source or drain) is provided with one TG timing signal line (TG(y)) for each shared pixel structure of this control unit. The gates of the four third TGs are connected to each other.

Furthermore, in each control unit, in the TGC (fourth TGC) arranged in the shared pixel structure (fourth shared pixel structure 20D) drawn at the lower right in the drawing, the gate is connected to the fourth TG control signal line (TGC4(x )), one diffusion layer (source or drain) has a TG timing signal line (TG(y)), and the other diffusion layer (source or drain) has one for each shared pixel structure of this control unit. The gates of the four fourth TGs arranged are connected to each other.

In this way, since the same TG timing signal is connected to the TGC arranged in each shared pixel structure arranged in the horizontal direction (row direction), the TG timing signal that crosses the shared pixel structure in the horizontal direction The number of pixels per shared pixel structure has been significantly reduced from 4 in the prior art to 0.5.
According to the characteristic structure of the second embodiment configured in this way, the following characteristic output results (1) to (3), which cannot be obtained with the prior art, are obtained according to the input of the TG timing signal. ) can be obtained.

(1) When the kth TG control signal is input to the control unit in accordance with the input of the TG timing signal, charge transfer from the kth PD to the FD within the control unit can be performed.
(2) Also, if multiple TG control signals among the four TG control signals from the first to the fourth are input at the same time, both from the corresponding PD among the four PDs from the first to the fourth in the control unit. Charge transfer is performed, and it is possible to read a signal that is the sum of these charges.
(3) Also, if none of the four TG control signals from the first to fourth TG control signals is input, any one of the four PDs from the first to the fourth in the control unit It is also possible to continue exposure and signal accumulation without charge transfer from the PD.

In this way, according to the present embodiment, any signal input can be selected from among the four TG control signals from the first TG control signal to the fourth TG control signal for each control unit. , control of charge transfer from the first PD to the fourth PD can be performed independently for each control unit. Further, since the vertical direction (column direction) in the drawing is scanned sequentially with a time difference, it is also possible to independently control the vertical control unit using the time difference.
Also, in this embodiment in which N=4, similarly to the modification of the first embodiment, a modification in which the terminals of the input TG control transistor (TGC) are set oppositely for the TG timing signal and the TG control signal. It is also possible to do so.

(Modification of Embodiment 2)
A modification of the second embodiment is shown in FIG. 7 using the same display style as in FIG. 6 . Similarly to the second embodiment, this modification also has N=4, and one TGC is added for one shared pixel structure compared to the conventional technique. However, each control unit in the second embodiment is configured by arranging two shared pixel structures in the horizontal direction (row direction) and two in the vertical direction (column direction), but in this modification, , four shared pixel structures are arranged in the horizontal direction (row direction) and one shared pixel structure is arranged in the vertical direction (column direction).

(Embodiment 3)
Embodiment 3 is an image sensor in which N is 8. A conceptual diagram of the third embodiment is shown in FIG. 8 using the same display style as FIGS. 6 and 7.
That is, the corresponding number of the TGC added in each shared pixel structure is shown in a circle, and the corresponding number of each photodiode in each shared pixel structure is shown in a square.
As shown in FIG. 8, a total of eight shared pixel structures, two in the horizontal direction (row direction) and four in the vertical direction (column direction), are arranged in this control unit (x, y). It is shown that the TGC arranged in each shared pixel structure controls the PD (and TG) with the same number in each shared pixel structure, which corresponds to the number enclosed in the circle. There is.

As described above, according to the present embodiment, the charge transfer from the first PD to the eighth PD is controlled independently for each control unit in the horizontal direction (row direction) due to the same effect as in the first and second embodiments. It is possible to do so. Further, since the vertical direction (column direction) in the drawing is scanned sequentially with a time difference, it is also possible to independently control the vertical control unit using the time difference.

(Change mode)
The image pickup device of the present invention is not limited to that of the above-described embodiments, but can be modified to various other types. For example, in the above embodiment, one pixel is a four-transistor type in which four transistors are configured (instead of providing a selection transistor, the function of a selection transistor is provided by controlling the potential of VDD of a source follower transistor. It is also possible to use a five-transistor type in which one pixel is composed of five transistors.
The 5-transistor type includes a global transfer transistor in addition to the four types of transistors of the 4-transistor type. This global transfer transistor is a transistor (provided in the same number as the number of photodiodes) that reads the charge accumulated in each photodiode to charge storage nodes provided in the same number as the number of photodiodes. Note that the charges in these plurality of charge storage nodes are read out to the floating diffusion by the transfer gate transistor.
Furthermore, all global transfer transistors are driven at the same timing from the end of one scan of the transfer timing signal to the start of the next scan.

Further, it is also possible to construct an image sensor including control units having a larger number of shared pixel structures according to the same rules as the image sensor of the present embodiment described above. In this case, the ratio between the number of shared pixel structures in the horizontal direction and the number in the vertical direction can be set as appropriate. On the other hand, the image sensor of the present invention can also be constructed with a control unit having one shared pixel structure.
Further, the pixels of the image sensor according to each of the embodiments described above are assumed to be electron storage type pixels, and each transistor constituting the pixel is described as an NMOS type, but each transistor is a PMOS type. It is also possible to form an image sensor by forming a mold and replacing the high potential and low potential of each signal with each other.

10, 10', 10A, 10B, 20A, 20B, 20C, 20D, 40 Shared pixel structure 100, 100', 200, 200', 300, 400 Image sensor PD Photodiode FD Floating diffusion TG TG transistor (transfer transistor)
TGC TG control transistor (transfer control transistor)
RT Reset transistor SF Source follower transistor SL Selection transistor

Claims (7)

At least a predetermined number of photodiodes, and a transfer gate transistor provided corresponding to each of the photodiodes, which directly or indirectly reads out the charge accumulated in each of the photodiodes to a floating diffusion; A predetermined number of shared pixel structures are provided for each control unit, including a reset transistor that resets the floating diffusion to a predetermined voltage, and a source follower transistor that reads the charge read out to the floating diffusion as a voltage,
Further, each of the shared pixel structures is provided with one transfer gate control transistor;
The transfer gate control transistor has a gate terminal connected to one of a transfer timing signal line and a transfer gate control signal line, and one of a source terminal and a drain terminal connected to the other of the transfer timing signal line and the transfer gate control signal line. and the other of the source terminal and the drain terminal is connected to the gate terminal of the transfer gate transistor,
When the number of shared pixel structures included in each of the control units is N, the number of transfer gate transistors included in each shared pixel structure is N,
The one transfer gate control transistor provided in each of the shared pixel structures is one of the N transfer gate transistors provided in each of the shared pixel structures corresponding to the one transfer gate control transistor. 1. An image pickup device configured to be connected to each of the gate terminals of the two transfer gate transistors and to drive the transfer gate transistor. The image sensor according to claim 1, wherein the shared pixel structure is configured to include a selection transistor that outputs the voltage read by the source follower transistor to an output signal line. A plurality of pixels to which transfer timing signals from the transfer timing signal line are simultaneously input are arranged in one of a row direction and a column direction, and a plurality of pixels to which transfer gate control signals from the transfer gate control signal line are simultaneously input. The image sensor according to claim 1, wherein the pixels are arranged in one of the row direction and the column direction. The transistors included in each of the shared pixel structures include N transfer gate transistors, and one each of the reset transistor, the source follower transistor, the selection transistor, and the transfer gate control transistor. The image sensor according to claim 2, characterized in that: Claim characterized in that the number of the shared pixel structures included in each of the control units is set to four, and the number of transfer gate transistors included in each of the shared pixel structures is set to four. 1. The image sensor according to 1. 6. The image sensor according to claim 5, wherein each of the control units is configured by arranging two of the shared pixel structures in the horizontal direction and two in the vertical direction. 6. Each of the control units is configured by arranging one shared pixel structure in one of the horizontal and vertical directions and four shared pixel structures in the other of the horizontal and vertical directions. The image sensor described.

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