JP2023143620A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of reducing the loss at turn-on.SOLUTION: A semiconductor device includes a first electrode, a semiconductor part, a second electrode, a structure body, and an insulating part. The semiconductor part includes a p-type first semiconductor region located on the first electrode, an n-type second semiconductor region located on the first semiconductor region, a p-type third semiconductor region located on the second semiconductor region, and an n-type fourth semiconductor region and a p-type fifth semiconductor region that are located on the third semiconductor region. The structure body includes a gate part and a dummy part, the gate part including at least one gate electrode, and the dummy part including at least two dummy electrodes. The gate part and the dummy part are alternately arranged. A first potential is applied to the second electrode. A second potential greater than the first potential is applied to the gate electrode. A third potential greater than the first potential is applied to the dummy electrode located at a position next to the gate part.SELECTED DRAWING: Figure 2

Description

Embodiments relate to semiconductor devices.

Semiconductor devices such as insulated gate bipolar transistors (IGBTs) are used for applications such as power conversion. In such semiconductor devices, there is a need to reduce loss during turn-on.

Japanese Patent Application Publication No. 2013-080796

An object of the embodiments is to provide a semiconductor device that can reduce loss during turn-on.

A semiconductor device according to an embodiment includes a first electrode, a semiconductor section, a second electrode, a structure, and an insulating section. The semiconductor section includes a p-type first semiconductor region provided on the first electrode, an n-type second semiconductor region provided on the first semiconductor region, and a second semiconductor region of the second semiconductor region. a p-type third semiconductor region provided above, an n-type fourth semiconductor region provided above the third semiconductor region, and a p-type fifth semiconductor region provided above the third semiconductor region. A semiconductor region. The second electrode is provided on the semiconductor section. The structure includes a gate portion and a dummy portion. The gate portion includes at least one gate electrode. The dummy section includes at least two dummy electrodes. The gate portions and the dummy portions are alternately arranged in a second direction perpendicular to the first direction from the first semiconductor region to the second semiconductor region. The insulating section is provided between the gate electrode and the semiconductor section. The gate portion is provided within the fourth semiconductor region. A first potential is applied to the second electrode. A second potential higher than the first potential is applied to the gate electrode. A third potential higher than the first potential is applied to the dummy electrode provided at a position adjacent to the gate portion.

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIGS. 3A and 3B are graphs showing simulation results of the characteristics of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing a semiconductor device according to a first modification of the first embodiment. FIG. 7 is a plan view showing a semiconductor device according to a second modification of the first embodiment. FIG. 7 is a cross-sectional view showing a semiconductor device according to a second modification of the first embodiment. FIG. 3 is a plan view showing a semiconductor device according to a second embodiment. FIG. 3 is a cross-sectional view showing a semiconductor device according to a second embodiment.

Each embodiment will be described below with reference to the drawings. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be shown differently depending on the drawing. Further, in this specification and each figure, the same elements as those described in the previous figures are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

Further, in order to make the explanation easier to understand, the arrangement and configuration of each part will be explained using an XYZ orthogonal coordinate system. The X-axis, Y-axis, and Z-axis are orthogonal to each other. Further, the direction in which the X axis extends is referred to as the "X direction," the direction in which the Y axis extends in the "Y direction," and the direction in which the Z axis extends in the "Z direction." Furthermore, in order to make the explanation easier to understand, the direction of the arrow in the Z direction is assumed to be upward, and the opposite direction is assumed to be downward, but these directions are unrelated to the direction of gravity.

Furthermore, in the following, the notation + and - represent relative levels of impurity concentration in each conductivity type. Specifically, a notation with a "+" attached indicates that the impurity concentration is higher than a notation with neither a "+" nor a "-" attached. A notation with a "-" indicates that the impurity concentration is lower than a notation with neither a "+" nor a "-". Here, the "impurity concentration" refers to the net impurity concentration after these impurities cancel each other out, when each region contains both an impurity that serves as a donor and an impurity that serves as an acceptor.

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment.
FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment.
FIG. 2 is a sectional view taken along line A1-A2 shown in FIG.
As shown in FIGS. 1 and 2, the semiconductor device 100 according to the first embodiment includes a first electrode 10, a semiconductor section 20, a second electrode 30, a structure 40, and a first insulating section 51. , a second insulating section 52. The semiconductor device 100 is an IGBT.

The first electrode 10 is provided at the bottom of the semiconductor device 100. The first electrode 10 is a lower electrode. The first electrode 10 functions, for example, as a collector electrode. The upper and lower surfaces of the first electrode 10 are generally parallel to the XY plane. The first electrode 10 is made of a conductive material such as a metal material.

The semiconductor section 20 includes a first semiconductor region 21 , a second semiconductor region 22 , a third semiconductor region 23 , a fourth semiconductor region 24 , and a fifth semiconductor region 25 .

The first semiconductor region 21 is provided on the first electrode 10. The first semiconductor region 21 is a p-type semiconductor region. The first semiconductor region 21 is a p ⁺ semiconductor region. The impurity concentration of the first semiconductor region 21 is higher than the impurity concentration of the third semiconductor region 23, for example.

The second semiconductor region 22 is provided on the first semiconductor region 21 . The second semiconductor region 22 is an n-type semiconductor region. The second semiconductor region 22 includes a first layer 22a and a second layer 22b. The first layer 22a is provided on the first semiconductor region 21. The second layer 22b is provided on the first layer 22a. The first layer 22a is an n ⁻ semiconductor region. The impurity concentration of the first layer 22a is lower than that of the second layer 22b, for example.

The third semiconductor region 23 is provided on the second semiconductor region 22. The third semiconductor region 23 is provided on the second layer 22b. The third semiconductor region 23 is a p-type semiconductor region.

The fourth semiconductor region 24 is provided on the third semiconductor region 23. The fourth semiconductor region 24 is an n-type semiconductor region. The fourth semiconductor region 24 is an n ⁺ semiconductor region. The impurity concentration of the fourth semiconductor region 24 is higher than the impurity concentration of the second layer 22b of the second semiconductor region 22, for example.

The fifth semiconductor region 25 is provided on the third semiconductor region 23. The fifth semiconductor region 25 is a p-type semiconductor region. The fifth semiconductor region 25 is a p ⁺ semiconductor region. The impurity concentration of the fifth semiconductor region 25 is higher than the impurity concentration of the third semiconductor region 23, for example.

A first direction from the first semiconductor region 21 to the second semiconductor region 22 is along the Z direction. The second direction perpendicular to the first direction is along the X direction. In this example, the fourth semiconductor regions 24 and the fifth semiconductor regions 25 are arranged alternately in the X direction. In this example, the fourth semiconductor regions 24 and the fifth semiconductor regions 25 are arranged alternately in the Y direction.

The first semiconductor region 21, the second semiconductor region 22, the third semiconductor region 23, the fourth semiconductor region 24, and the fifth semiconductor region 25 are made of a semiconductor material such as silicon and impurities corresponding to each region. include.

A structure 40 is provided inside the semiconductor section 20 . The structure 40 has a structure in which gate portions 41 and dummy portions 43 are alternately arranged in the X direction. That is, the structure 40 includes a plurality of gate parts 41 and a plurality of dummy parts 43. The gate portions 41 and the dummy portions 43 are arranged alternately in the X direction. The gate portion 41 and the dummy portion 43 each extend in the Y direction.

Gate portion 41 is provided within fourth semiconductor region 24 . Gate section 41 includes at least one gate electrode 42 . In this example, the gate section 41 includes three gate electrodes 42. In this example, the gate section 41 consists of three gate electrodes 42.

The gate electrode 42 extends in the Z direction from the upper end of the fourth semiconductor region 24 through the third semiconductor region 23 and the second layer 22b of the second semiconductor region 22 to the first layer 22a of the second semiconductor region. . That is, the gate electrode 42 is aligned with the fourth semiconductor region 24, the third semiconductor region 23, the second layer 22b of the second semiconductor region 22, and the first layer 22a of the second semiconductor region in the X direction. The gate electrode 42 is made of a conductive material such as a metal material or polysilicon, for example.

A first insulating section 51 is provided between the gate electrode 42 and the semiconductor section 20. A part of the first insulating section 51 is located between the gate electrode 42 and the fourth semiconductor region 24, between the gate electrode 42 and the third semiconductor region 23, and between the gate electrode 42 and the second semiconductor region 22 in the X direction. It is located between the second layer 22b and between the gate electrode 42 and the first layer 22a of the second semiconductor region 22. Another part of the first insulating section 51 is located between the gate electrode 42 and the first layer 22a of the second semiconductor region 22 in the Z direction. A portion of the first insulating section 51 functions, for example, as a gate insulating film. The first insulating portion 51 is made of an insulating material such as silicon oxide or silicon nitride, for example.

In this example, the dummy portion 43 is provided within the fifth semiconductor region 25. Dummy section 43 includes at least two dummy electrodes 44 . In this example, dummy section 43 includes three dummy electrodes 44 . In this example, the dummy section 43 consists of three dummy electrodes 44.

The dummy electrode 44 extends in the Z direction from the upper end of the fifth semiconductor region 25 through the second layer 22b of the third semiconductor region 23 and the second semiconductor region 22 to the first layer 22a of the second semiconductor region. . That is, the dummy electrode 44 is lined up with the fifth semiconductor region 25, the third semiconductor region 23, the second layer 22b of the second semiconductor region 22, and the first layer 22a of the second semiconductor region in the X direction. The lower end of the dummy electrode 44 is aligned with the lower end of the gate electrode 42, for example, in the X direction. The dummy electrode 44 is made of a conductive material such as a metal material or polysilicon, for example.

A second insulating section 52 is provided between the dummy electrode 44 and the semiconductor section 20. A part of the second insulating section 52 is located between the dummy electrode 44 and the fifth semiconductor region 25, between the dummy electrode 44 and the third semiconductor region 23, and between the dummy electrode 44 and the second semiconductor region 22 in the X direction. It is located between the second layer 22b and between the dummy electrode 44 and the first layer 22a of the second semiconductor region 22. Another part of the second insulating section 52 is located between the dummy electrode 44 and the first layer 22a of the second semiconductor region 22 in the Z direction. The second insulating portion 52 is made of an insulating material such as silicon oxide or silicon nitride, for example.

In this example, the structure 40 includes gate parts 41a, 41b, and 41c, and dummy parts 43a and 43b. The parts are arranged in the order of gate part 41b, dummy part 43a, gate part 41a, dummy part 43b, and gate part 41c in the X direction.

The gate portion 41a has gate electrodes 42a, 42b, and 42c. The gate portion 41b includes a gate electrode 42d and two gate electrodes 42 (not shown). The gate portion 41c includes a gate electrode 42e and two gate electrodes 42 (not shown). The dummy portion 43a has dummy electrodes 44a, 44b, and 44c. The dummy portion 43b has dummy electrodes 44d, 44e, and 44f.

The second electrode 30 is provided on the semiconductor section 20. The second electrode 30 is provided on the fourth semiconductor region 24 and the fifth semiconductor region 25. The second electrode 30 is the upper electrode. The second electrode 30 functions, for example, as an emitter electrode. The second electrode 30 is made of a conductive material such as a metal material. In FIG. 1, the second electrode 30 is omitted. An insulating section is provided between the second electrode 30 and the gate electrode 42.

A first potential is applied to the second electrode 30. The first potential is, for example, an emitter potential E. The first potential is, for example, 0V.

A second potential is applied to the gate electrode 42. The second potential is, for example, the gate potential G. The second potential is higher than the first potential. The second potential is, for example, 15V.

A third potential is applied to the dummy electrode 44 provided at a position adjacent to the gate portion 41 among the dummy electrodes 44 . The third potential is higher than the first potential. In this example, a dummy electrode 44a provided at a position adjacent to the gate portion 41b, dummy electrodes 44c and 44d provided at a position adjacent to the gate portion 41a, and a dummy electrode provided at a position adjacent to the gate portion 41c. A third potential is applied to 44f.

The third potential is, for example, higher than the first potential and lower than or equal to the second potential. The third potential is, for example, equal to the second potential. The third potential is, for example, higher than 0V and lower than or equal to 15V. The third potential is, for example, 15V. That is, for example, a gate potential G is applied to the dummy electrode 44 provided at a position adjacent to the gate portion 41 among the dummy electrodes 44 . In other words, among the dummy electrodes 44, the dummy electrode 44 provided at a position adjacent to the gate portion 41 is connected to the gate electrode 42, for example. Among the dummy electrodes 44, the dummy electrode 44 provided at a position adjacent to the gate portion 41 is connected to the gate electrode 42 at the end of the semiconductor device 100 in the Y direction, for example.

On the other hand, among the dummy electrodes 44, a first potential is applied to the dummy electrodes 44 provided at positions not adjacent to the gate portion 41, for example. In this example, the first potential is applied to the dummy electrodes 44b and 44e provided at positions not adjacent to the gate portion 41. That is, for example, the emitter potential E is applied to the dummy electrode 44 provided at a position not adjacent to the gate portion 41 among the dummy electrodes 44 . In other words, among the dummy electrodes 44, the dummy electrodes 44 provided at positions not adjacent to the gate portion 41 are connected to the second electrode 30, for example.

Next, the operation and effects of the semiconductor device 100 will be explained.
When a voltage equal to or higher than a threshold is applied to the gate electrode 42 while a positive voltage is applied to the first electrode 10 (collector electrode) with respect to the second electrode 30 (emitter electrode), the semiconductor device is turned on. becomes. At this time, a channel (inversion layer) is formed in a region of the third semiconductor region 23 near the first insulating portion 51 (gate insulating film). Electrons are injected from the fourth semiconductor region 24 into the second semiconductor region 22 through this channel, and holes are injected from the first semiconductor region 21 into the second semiconductor region 2. Thereafter, when the voltage applied to the gate electrode 42 becomes lower than the threshold value, the channel in the third semiconductor region 23 disappears, and the semiconductor device turns off.

A structure 40 in which a gate part 41 including a gate electrode 42 and a dummy part 43 including a dummy electrode 44 are arranged alternately is provided inside the semiconductor part 20, and a first potential (emitter potential E) is applied to the dummy electrode 44. By applying the voltage, the capacitance of the gate electrode 42 can be reduced. Thereby, response speed can be improved.

On the other hand, when the first potential is applied to the dummy electrode 44 provided at a position adjacent to the gate part 41, the hole current is discharged by the hole inversion layer at the time of turn-on, and the hole accumulation rate decreases. tends to decline.

On the other hand, in the semiconductor device 100 according to the first embodiment, by applying a third potential higher than the first potential to the dummy electrode 44 provided at a position adjacent to the gate section 41, the hole accumulation rate is increased. This makes it possible to improve the fall characteristics of the collector-emitter voltage Vce at turn-on. Thereby, loss at turn-on can be reduced.

Furthermore, by making the third potential applied to the dummy electrode 44 provided at a position adjacent to the gate part 41 equal to the second potential (gate potential G) applied to the gate electrode 42, loss at turn-on can be reduced. It can be further reduced. For example, by connecting a dummy electrode 44 provided at a position adjacent to the gate portion 41 to the gate electrode 42, the third potential can be made equal to the second potential.

Further, by applying the first potential to the dummy electrode 44 provided at a position not adjacent to the gate portion 41, the response speed can be improved. For example, by connecting the dummy electrode 44 provided at a position not adjacent to the gate part 41 to the second electrode 30, the first potential is applied to the dummy electrode 44 provided at a position not adjacent to the gate part 41. be able to.

Furthermore, since the gate section 41 includes three gate electrodes 42 and the dummy section 43 includes three dummy electrodes 44, an improvement in response speed and an improvement in on-voltage and on-resistance can be achieved in a better balance. I can do it.

FIGS. 3A and 3B are graphs showing simulation results of the characteristics of the semiconductor device according to the first embodiment.
In FIGS. 3(a) and 3(b), the horizontal axis represents time [a. u. ]. In FIG. 3(a), the vertical axis represents the collector-emitter current Ic [a. u. ] and collector-emitter voltage Vce[a. u. ]. In FIG. 3(b), the vertical axis represents the loss [a. u. ]. "au" indicates an arbitrary unit.

In FIGS. 3A and 3B, in a structure in which a gate part 41 including three gate electrodes 42 and a dummy part 43 including three dummy electrodes 44 are arranged alternately, the gate part 41 is Simulation of characteristics of Experimental Example 1 in which gate potential was applied to dummy electrodes 44 provided at adjacent positions and Experimental Example 2 in which emitter potential was applied to dummy electrodes 44 provided in adjacent positions to gate portion 41 Showing results.
Note that in Experimental Examples 1 and 2, a gate potential is applied to the gate electrode 42. Further, in Experimental Examples 1 and 2, the gate potential is set to 15V, and the emitter potential is set to 0V.

In FIG. 3(a), the time-dependent changes in the collector-emitter current Ic and the collector-emitter voltage Vce at turn-on in Experimental Example 1 are shown by broken lines, and the collector-emitter current Ic and collector-emitter voltage Vce at turn-on in Experimental Example 2 are shown by broken lines. The change in the voltage Vce over time is shown by a solid line.
Further, in FIG. 3(b), a broken line shows the change in loss over time in turn-on of Experimental Example 1, and a solid line shows a change in loss over time in turn-on in Experimental Example 2.

As shown in FIGS. 3(a) and 3(b), in Experimental Example 1, the fall characteristics of the collector-emitter voltage Vce at turn-on are better than in Experimental Example 2, and the loss at turn-on is has been reduced.

Therefore, according to the first embodiment, by applying a third potential (for example, gate potential) higher than the first potential to the dummy electrode 44 provided at a position adjacent to the gate part 41, the gate part It has been suggested that the loss during turn-on can be reduced compared to the case where a first potential (eg, emitter potential) is applied to the dummy electrode 44 provided at a position adjacent to the dummy electrode 41.

FIG. 4 is a cross-sectional view showing a semiconductor device according to a first modification of the first embodiment.
As shown in FIG. 4, in the semiconductor device 100A according to the first modification of the first embodiment, the gate potential G is A resistance section 60 is provided between them. Other than that, the semiconductor device 100 is substantially the same as the semiconductor device 100 described above.

More specifically, a resistance section 60 is provided between the dummy electrodes 44a, 44c, 44d, and 44f and the gate potential G. As a result, the third potential applied to the dummy electrodes 44a, 44c, 44d, and 44f becomes lower than the second potential (gate potential G). In this way, the third potential may be adjusted by providing the resistor section 60 or the like.

Also in the semiconductor device 100A according to the first modification of the first embodiment, hole accumulation is achieved by applying a third potential higher than the first potential to the dummy electrode 44 provided at a position adjacent to the gate portion 41. It is possible to secure the speed and improve the falling characteristics of the collector-emitter voltage Vce at turn-on. Thereby, loss at turn-on can be reduced.

FIG. 5 is a plan view showing a semiconductor device according to a second modification of the first embodiment.
FIG. 6 is a cross-sectional view showing a semiconductor device according to a second modification of the first embodiment.
FIG. 6 is a sectional view taken along the line B1-B2 shown in FIG.
As shown in FIGS. 5 and 6, in the semiconductor device 100B according to the second modification of the first embodiment, the second electrode 30 includes a first conductive part 31 and a second conductive part 32. In FIG. 5, the first conductive part 31 is omitted.

The first conductive part 31 is provided on the semiconductor part 20. The second conductive part 32 is provided below the first conductive part 31. The second conductive section 32 is provided within the semiconductor section 20 . At least a portion of the second conductive portion 32 is located between two gate electrodes 42 adjacent to each other in the X direction. In this example, the second conductive portion 32 is provided between two adjacent gate electrodes 42, between two adjacent dummy electrodes 44, and between adjacent gate electrodes 42 and dummy electrodes 44. ing.

In this example, the third semiconductor region 23 includes a first portion 23a and a second portion 23b. The second portion 23b is provided on the first portion 23a. The fourth semiconductor region 24 is provided on the first portion 23a. In this example, along the B1-B2 line, the fourth semiconductor region 24 and the second portion 23b of the third semiconductor region 23 are alternately arranged in the X direction. In this example, on the side surface of the gate electrode 42, the fourth semiconductor region 24 and the second portion 23b of the third semiconductor region 23 are alternately arranged in the Y direction. Further, in this example, the dummy portion 43 is provided in the second portion 23b of the third semiconductor region 23.

Further, in this example, the fifth semiconductor region 25 is provided under the second conductive portion 32. The fifth semiconductor region 25 is provided between the first portion 23a of the third semiconductor region 23 and the second conductive portion 32 in the Z direction. The fifth semiconductor region 25 is aligned with the first portion 23a of the third semiconductor region 23 in the X direction. Other than that, the semiconductor device 100 is substantially the same as the semiconductor device 100 described above.

The second conductive portion 32 provided between two adjacent gate electrodes 42 is provided within the fourth semiconductor region 24 . The second conductive part 32 provided between two gate electrodes 42 adjacent to each other passes from the lower end of the first conductive part 31 through the fourth semiconductor region 24 in the Z direction to the first part of the third semiconductor region 23. It extends to part 23a. That is, the second conductive portion 32 provided between two mutually adjacent gate electrodes 42 is aligned with the fourth semiconductor region 24 and the first portion 23a of the third semiconductor region 23 in the X direction.

The second conductive portion 32 provided between two adjacent dummy electrodes 44 is provided in the second portion 23b of the third semiconductor region 23. The second conductive part 32 provided between two dummy electrodes 44 adjacent to each other passes from the lower end of the first conductive part 31 through the second portion 23b of the third semiconductor region 23 in the Z direction to the third semiconductor It extends to the first portion 23a of the region 23. That is, the second conductive portion 32 provided between two dummy electrodes 44 adjacent to each other is aligned with the first portion 23a and second portion 23b of the third semiconductor region 23 in the X direction.

The second conductive portion 32 provided between the gate electrode 42 and the dummy electrode 44 that are adjacent to each other is provided at the boundary between the fourth semiconductor region 24 and the second portion 23b of the third semiconductor region 23. The second conductive part 32 provided between the gate electrode 42 and the dummy electrode 44 that are adjacent to each other extends from the lower end of the first conductive part 31 to the second portion 23b of the third semiconductor region 23 and the fourth semiconductor It extends through the region 24 to the first portion 23a of the third semiconductor region 23. That is, the second conductive portion 32 provided between the gate electrode 42 and the dummy electrode 44 that are adjacent to each other is connected to the first portion 23a and the second portion of the fourth semiconductor region 24 and the third semiconductor region 23 in the X direction. It is lined up with 23b.

Also in the semiconductor device 100B according to the second modification of the first embodiment, hole accumulation is achieved by applying a third potential higher than the first potential to the dummy electrode 44 provided at a position adjacent to the gate portion 41. It is possible to secure the speed and improve the falling characteristics of the collector-emitter voltage Vce at turn-on. Thereby, loss at turn-on can be reduced.

FIG. 7 is a plan view showing a semiconductor device according to a second embodiment.
FIG. 8 is a cross-sectional view showing a semiconductor device according to the second embodiment.
FIG. 8 is a cross-sectional view taken along line C1-C2 shown in FIG.
As shown in FIGS. 7 and 8, in the semiconductor device 200 according to the second embodiment, the gate section 41 includes at least two gate electrodes 42. Furthermore, in the semiconductor device 200, the dummy section 43 includes at least one dummy electrode 44. Other than that, the semiconductor device 100B is substantially the same as the semiconductor device 100B described above. In FIG. 7, the first conductive part 31 is omitted.

More specifically, the gate section 41 includes at least a first gate electrode 42x and a second gate electrode 42y. The first gate electrode 42x is provided at one end of the fourth semiconductor region 24 in the X direction. The second gate electrode 42y is provided at the other end of the fourth semiconductor region 24 in the X direction. The first gate electrode 42x is located between the fourth semiconductor region 24 and the second portion 23b of the third semiconductor region 23 in the X direction. The second gate electrode 42y is located between the fourth semiconductor region 24 and the second portion 23b of the third semiconductor region 23 in the X direction. The fourth semiconductor region 24 is provided between the first gate electrode 42x and the second gate electrode 42y in the X direction.

In the X direction, a third semiconductor region 23 is provided between one gate section 41 (for example, gate section 41a) and another gate section 41 adjacent thereto (for example, gate section 41b or gate section 41c). A second portion 23b is provided. One side surface of the first gate electrode 42x in the X direction faces the second portion 23b of the third semiconductor region 23. The other side surface of the first gate electrode 42x in the X direction faces the fourth semiconductor region 24. One side surface of the second gate electrode 42y in the X direction faces the fourth semiconductor region 24. The other side surface of the second gate electrode 42y in the X direction faces the second portion 23b of the third semiconductor region 23.

The gate section 41 may further include a third gate electrode 42z provided between the first gate electrode 42x and the second gate electrode 42y. The third gate electrode 42z is provided in the fourth semiconductor region 24. In this example, the gate section 41 includes one third gate electrode 42z. That is, in this example, the gate section 41 consists of three gate electrodes 42. The number of third gate electrodes 42z included in the gate portion 41 may be zero, one, or two or more.

In this example, the dummy section 43 includes one dummy electrode 44. In this example, the dummy section 43 consists of one dummy electrode 44. That is, in this example, the number of dummy electrodes 44 included in the dummy portion 43 is one. The number of dummy electrodes 44 included in the dummy portion 43 may be one, or two or more.

In this example, the structure 40 includes gate parts 41a, 41b, and 41c, and dummy parts 43a and 43b. The parts are arranged in the order of gate part 41b, dummy part 43a, gate part 41a, dummy part 43b, and gate part 41c in the X direction.

The gate parts 41a, 41b, and 41c each have a first gate electrode 42x, a second gate electrode 42y, and a third gate electrode 42z. The dummy portion 43a has a dummy electrode 44a. The dummy portion 43b has a dummy electrode 44b.

In this example, the first potential is applied to the second electrode 30 and the dummy electrode 44. The first potential is, for example, an emitter potential E. The first potential is, for example, 0V. On the other hand, a second potential is applied to the gate electrode 42. The second potential is, for example, the gate potential G. The second potential is higher than the first potential. The second potential is, for example, 15V.

Next, the operation and effects of the semiconductor device 200 will be explained.
When a voltage equal to or higher than a threshold is applied to the gate electrode 42 while a positive voltage is applied to the first electrode 10 (collector electrode) with respect to the second electrode 30 (emitter electrode), the semiconductor device is turned on. becomes. At this time, a channel (inversion layer) is formed in a region of the third semiconductor region 23 near the first insulating portion 51 (gate insulating film). Electrons are injected from the fourth semiconductor region 24 into the second semiconductor region 22 through this channel, and holes are injected from the first semiconductor region 21 into the second semiconductor region 22. Thereafter, when the voltage applied to the gate electrode 42 becomes lower than the threshold value, the channel in the third semiconductor region 23 disappears, and the semiconductor device turns off.

A structure 40 in which a gate part 41 including a gate electrode 42 and a dummy part 43 including a dummy electrode 44 are arranged alternately is provided inside the semiconductor part 20, and the gate part 41 is provided at one end of the fourth semiconductor region 24. By including the first gate electrode 42x provided at the other end of the fourth semiconductor region 24 and the second gate electrode 42y provided at the other end of the fourth semiconductor region 24, the capacitance of the gate electrode 42 can be reduced. Thereby, response speed can be improved. Furthermore, it is possible to ensure the hole accumulation rate and improve the falling characteristics of the collector-emitter voltage Vce at turn-on. Thereby, loss at turn-on can be reduced. Note that the simulation results of the characteristics of the semiconductor device according to the second embodiment are also similar to the simulation results of the characteristics of the semiconductor device according to the first embodiment shown in FIGS. 3(a) and 3(b) above. .

Further, if the number of dummy electrodes 44 included in the dummy portion 43 is one, the gate capacitance can be reduced and the drive loss can be reduced, for example, compared to the second modification of the first embodiment. If the dummy electrode 44 to which the emitter potential E is applied is not provided and the gate potential G is applied to all dummy electrodes 44, negative capacitance (gate charge becomes smaller when the gate potential G is increased) is generated when a load is short-circuited. phenomenon) occurs, making gate vibration more likely to occur. On the other hand, by providing a dummy electrode 44 to which the emitter potential E is applied, gate vibration can be suppressed. In this example, when compared with the second modification of the first embodiment shown in FIGS. 5 and 6, the area ratio of the fourth semiconductor region 24 that supplies an electron current when turned on is the same. However, since the number of electrodes to which the gate potential G is applied is small, the gate capacitance is small and the drive loss is small. Furthermore, the gate driver for driving this IGBT can be made small. The number of electrodes to which adjacent gate potentials G are continuously applied is three in the example of FIG. 8, compared to five in the example of FIG. 6, which has the advantage that negative capacitance is less likely to occur. However, apart from the load on the gate driver, a smaller gate capacitance is not necessarily better depending on the application, so it is preferable to use the structure of the first embodiment and the structure of the second embodiment.

Embodiments may include the following configurations.

(Configuration 1)
a first electrode;
a p-type first semiconductor region provided on the first electrode, an n-type second semiconductor region provided on the first semiconductor region, and a p-type second semiconductor region provided on the second semiconductor region. a p-type third semiconductor region, an n-type fourth semiconductor region provided on the third semiconductor region, and a p-type fifth semiconductor region provided on the third semiconductor region; a semiconductor section, including;
a second electrode provided on the semiconductor portion;
Gate portions including at least one gate electrode and dummy portions including at least two dummy electrodes are alternately arranged in a second direction perpendicular to the first direction from the first semiconductor region to the second semiconductor region. struct and
an insulating section provided between the gate electrode and the semiconductor section;
Equipped with
The gate portion is provided in the fourth semiconductor region,
A first potential is applied to the second electrode,
A second potential higher than the first potential is applied to the gate electrode,
A semiconductor device, wherein a third potential higher than the first potential is applied to the dummy electrode provided at a position adjacent to the gate portion.

(Configuration 2)
The fourth semiconductor region and the fifth semiconductor region are alternately arranged in the second direction,
The semiconductor device according to Configuration 1, wherein the dummy portion is provided in the fifth semiconductor region.

(Configuration 3)
The second electrode is located between a first conductive part provided on the semiconductor part and two gate electrodes provided below the first conductive part and adjacent to each other in the second direction. 2 conductive parts;
The third semiconductor region includes a first portion and a second portion provided on the first portion,
the fourth semiconductor region is provided on the first portion,
The fourth semiconductor region and the second portion are alternately arranged in the second direction,
the fifth semiconductor region is provided under the second conductive section,
The semiconductor device according to Configuration 1, wherein the dummy portion is provided within the second portion.

(Configuration 4)
4. The semiconductor device according to any one of configurations 1 to 3, wherein the third potential is equal to the second potential.

(Configuration 5)
5. The semiconductor device according to any one of configurations 1 to 4, wherein the second potential is 15V.

(Configuration 6)
The dummy part includes at least three of the dummy electrodes,
6. The semiconductor device according to any one of configurations 1 to 5, wherein the first potential is applied to the dummy electrode provided at a position not adjacent to the gate portion.

(Configuration 7)
a first electrode;
a p-type first semiconductor region provided on the first electrode, an n-type second semiconductor region provided on the first semiconductor region, and a p-type second semiconductor region provided on the second semiconductor region. a p-type third semiconductor region, an n-type fourth semiconductor region provided on the third semiconductor region, and a p-type fifth semiconductor region provided on the third semiconductor region; a semiconductor section, including;
a second electrode provided on the semiconductor portion;
Gate portions including at least one gate electrode and dummy portions including at least two dummy electrodes are alternately arranged in a second direction perpendicular to the first direction from the first semiconductor region to the second semiconductor region. struct and
an insulating section provided between the gate electrode and the semiconductor section;
Equipped with
The gate portion is provided in the fourth semiconductor region,
A semiconductor device, wherein the dummy electrode provided at a position adjacent to the gate portion is connected to the gate electrode.

(Configuration 8)
The fourth semiconductor region and the fifth semiconductor region are alternately arranged in the second direction,
8. The semiconductor device according to configuration 7, wherein the dummy portion is provided in the fifth semiconductor region.

(Configuration 9)
The second electrode is located between a first conductive part provided on the semiconductor part and two gate electrodes provided below the first conductive part and adjacent to each other in the second direction. 2 conductive parts;
The third semiconductor region includes a first portion and a second portion provided on the first portion,
the fourth semiconductor region is provided on the first portion,
The fourth semiconductor region and the second portion are alternately arranged in the second direction,
the fifth semiconductor region is provided under the second conductive section,
8. The semiconductor device according to configuration 7, wherein the dummy portion is provided within the second portion.

(Configuration 10)
The dummy part includes at least three of the dummy electrodes,
10. The semiconductor device according to any one of configurations 7 to 9, wherein the dummy electrode provided at a position not adjacent to the gate portion is connected to the second electrode.

(Configuration 11)
The gate portion includes the three gate electrodes,
The semiconductor device according to any one of Configurations 1 to 10, wherein the dummy portion includes three of the dummy electrodes.

(Configuration 12)
a first electrode;
a p-type first semiconductor region provided on the first electrode, an n-type second semiconductor region provided on the first semiconductor region, and a p-type second semiconductor region provided on the second semiconductor region. a p-type third semiconductor region, an n-type fourth semiconductor region provided on the third semiconductor region, and a p-type fifth semiconductor region provided on the third semiconductor region; a semiconductor section, including;
a second electrode provided on the semiconductor portion;
Gate portions including at least two gate electrodes and dummy portions including at least one dummy electrode are alternately arranged in a second direction perpendicular to the first direction from the first semiconductor region to the second semiconductor region. struct and
an insulating section provided between the gate electrode and the semiconductor section;
Equipped with
The second electrode is located between a first conductive part provided on the semiconductor part and two gate electrodes provided below the first conductive part and adjacent to each other in the second direction. 2 conductive parts;
The third semiconductor region includes a first portion and a second portion provided on the first portion,
the fourth semiconductor region is provided on the first portion,
The fourth semiconductor region and the second portion are alternately arranged in the second direction,
the fifth semiconductor region is provided under the second conductive section,
the dummy part is provided in the second part,
The gate portion includes a first gate electrode provided at one end of the fourth semiconductor region in the second direction, and a second gate electrode provided at the other end of the fourth semiconductor region in the second direction. semiconductor devices, including

(Configuration 13)
13. The semiconductor device according to configuration 12, wherein the number of the dummy electrodes included in the dummy portion is one.

As described above, according to the embodiments, it is possible to provide a semiconductor device that can reduce loss during turn-on.

Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included within the scope and gist of the invention, as well as within the scope of the claimed invention and its equivalents.

100, 100A, 100B, 200 semiconductor device 10 first electrode 20 semiconductor section 21 first semiconductor region 22 second semiconductor region 22a first layer 22b second layer 23 third semiconductor region 23a, 23b first, second portion 24 th 4 semiconductor region 25 5th semiconductor region 30 2nd electrode 31, 32 1st, 2nd conductive part 40 Structure 41, 41a to 41c Gate part 42, 42a to 42e Gate electrode 42x to 42z 1st to 3rd gate electrode 43 , 43a, 43b dummy part 44, 44a to 44f dummy electrode 51 first insulating part 52 second insulating part 60 resistor part

Claims (13)

a first electrode;
a p-type first semiconductor region provided on the first electrode, an n-type second semiconductor region provided on the first semiconductor region, and a p-type second semiconductor region provided on the second semiconductor region. a p-type third semiconductor region, an n-type fourth semiconductor region provided on the third semiconductor region, and a p-type fifth semiconductor region provided on the third semiconductor region; a semiconductor section, including;
a second electrode provided on the semiconductor portion;
Gate portions including at least one gate electrode and dummy portions including at least two dummy electrodes are alternately arranged in a second direction perpendicular to the first direction from the first semiconductor region to the second semiconductor region. struct and
an insulating section provided between the gate electrode and the semiconductor section;
Equipped with
The gate portion is provided in the fourth semiconductor region,
A first potential is applied to the second electrode,
A second potential higher than the first potential is applied to the gate electrode,
A semiconductor device, wherein a third potential higher than the first potential is applied to the dummy electrode provided at a position adjacent to the gate portion. The fourth semiconductor region and the fifth semiconductor region are alternately arranged in the second direction,
2. The semiconductor device according to claim 1, wherein the dummy portion is provided within the fifth semiconductor region. The second electrode is located between a first conductive part provided on the semiconductor part and two gate electrodes provided below the first conductive part and adjacent to each other in the second direction. 2 conductive parts;
The third semiconductor region includes a first portion and a second portion provided on the first portion,
the fourth semiconductor region is provided on the first portion,
The fourth semiconductor region and the second portion are alternately arranged in the second direction,
the fifth semiconductor region is provided under the second conductive section,
2. The semiconductor device according to claim 1, wherein the dummy portion is provided within the second portion. 2. The semiconductor device according to claim 1, wherein the third potential is equal to the second potential. The semiconductor device according to claim 1, wherein the second potential is 15V. The dummy part includes at least three of the dummy electrodes,
2. The semiconductor device according to claim 1, wherein the first potential is applied to the dummy electrode provided at a position not adjacent to the gate portion. a first electrode;
a p-type first semiconductor region provided on the first electrode, an n-type second semiconductor region provided on the first semiconductor region, and a p-type second semiconductor region provided on the second semiconductor region. a p-type third semiconductor region, an n-type fourth semiconductor region provided on the third semiconductor region, and a p-type fifth semiconductor region provided on the third semiconductor region; a semiconductor section, including;
a second electrode provided on the semiconductor portion;
Gate portions including at least one gate electrode and dummy portions including at least two dummy electrodes are alternately arranged in a second direction perpendicular to the first direction from the first semiconductor region to the second semiconductor region. struct and
an insulating section provided between the gate electrode and the semiconductor section;
Equipped with
The gate portion is provided in the fourth semiconductor region,
A semiconductor device, wherein the dummy electrode provided at a position adjacent to the gate portion is connected to the gate electrode. The fourth semiconductor region and the fifth semiconductor region are alternately arranged in the second direction,
8. The semiconductor device according to claim 7, wherein the dummy portion is provided within the fifth semiconductor region. The second electrode is located between a first conductive part provided on the semiconductor part and two gate electrodes provided below the first conductive part and adjacent to each other in the second direction. 2 conductive parts;
The third semiconductor region includes a first portion and a second portion provided on the first portion,
the fourth semiconductor region is provided on the first portion,
The fourth semiconductor region and the second portion are alternately arranged in the second direction,
the fifth semiconductor region is provided under the second conductive section,
8. The semiconductor device according to claim 7, wherein the dummy portion is provided within the second portion. The dummy part includes at least three of the dummy electrodes,
8. The semiconductor device according to claim 7, wherein the dummy electrode provided at a position not adjacent to the gate portion is connected to the second electrode. The gate portion includes the three gate electrodes,
The semiconductor device according to any one of claims 1 to 10, wherein the dummy section includes three of the dummy electrodes. a first electrode;
a p-type first semiconductor region provided on the first electrode, an n-type second semiconductor region provided on the first semiconductor region, and a p-type second semiconductor region provided on the second semiconductor region. a p-type third semiconductor region, an n-type fourth semiconductor region provided on the third semiconductor region, and a p-type fifth semiconductor region provided on the third semiconductor region; a semiconductor section, including;
a second electrode provided on the semiconductor portion;
Gate portions including at least two gate electrodes and dummy portions including at least one dummy electrode are alternately arranged in a second direction perpendicular to the first direction from the first semiconductor region to the second semiconductor region. struct and
an insulating section provided between the gate electrode and the semiconductor section;
Equipped with
The second electrode is located between a first conductive part provided on the semiconductor part and two gate electrodes provided below the first conductive part and adjacent to each other in the second direction. 2 conductive parts;
The third semiconductor region includes a first portion and a second portion provided on the first portion,
the fourth semiconductor region is provided on the first portion,
The fourth semiconductor region and the second portion are alternately arranged in the second direction,
the fifth semiconductor region is provided under the second conductive section,
the dummy part is provided in the second part,
The gate portion includes a first gate electrode provided at one end of the fourth semiconductor region in the second direction, and a second gate electrode provided at the other end of the fourth semiconductor region in the second direction. semiconductor devices, including 13. The semiconductor device according to claim 12, wherein the number of said dummy electrodes included in said dummy portion is one.

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