CN116805651A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Abstract

The embodiment provides a semiconductor device capable of reducing loss during turn-on. The semiconductor device of the embodiment includes a first electrode, a semiconductor portion, a second electrode, a structure, and an insulating portion. The semiconductor portion includes a p-type first semiconductor region provided over the first electrode, an n-type second semiconductor region provided over the first semiconductor region, a p-type third semiconductor region provided over the second semiconductor region, and an n-type fourth semiconductor region and a p-type fifth semiconductor region provided over the third semiconductor region. The structure includes a gate portion including at least one gate electrode and a dummy portion including at least two dummy electrodes. The gate portions and the dummy portions are alternately arranged. For the second electrode, a first potential is applied. A second potential higher than the first potential is applied to the gate electrode. A third potential higher than the first potential is applied to the dummy electrode provided at a position adjacent to the gate portion.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Related application

The present application enjoys priority of Japanese patent application No. 2022-47254 (application date: 2022, 3/23/day) and Japanese patent application No. 2022-140947 (application date: 2022, 9/5/day). The present application encompasses the entire contents of the basic applications by reference to these basic applications.

Technical Field

Embodiments relate to a semiconductor device.

Background

Semiconductor devices such as Insulated Gate Bipolar Transistors (IGBTs) are used for power conversion and other purposes. In such a semiconductor device, it is required to reduce the loss at the time of turn-on.

Disclosure of Invention

An object of the present application is to provide a semiconductor device capable of reducing a loss at the time of turn-on.

The semiconductor device of the embodiment includes a first electrode, a semiconductor portion, a second electrode, a structure, and an insulating portion. The semiconductor portion includes a first semiconductor region of a p-type provided over the first electrode, a second semiconductor region of an n-type provided over the first semiconductor region, a third semiconductor region of a p-type provided over the second semiconductor region, a fourth semiconductor region of an n-type provided over the third semiconductor region, and a fifth semiconductor region of a p-type provided over the third semiconductor region. The second electrode is arranged on the semiconductor part. The structure includes a gate portion and a dummy portion. The gate portion includes at least one gate electrode. The dummy portion includes at least two dummy electrodes. The gate portions and the dummy portions are alternately arranged in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region. The insulating portion is provided between the gate electrode and the semiconductor portion. The gate portion is disposed in the fourth semiconductor region. A first potential is applied to the second electrode. A second potential higher than the first potential is applied to the gate electrode. A third potential higher than the first potential is applied to the dummy electrode provided at a position adjacent to the gate portion.

Drawings

Fig. 1 is a plan view showing a semiconductor device according to a first embodiment.

Fig. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment.

Fig. 3 (a) and 3 (b) are graphs showing simulation results of the characteristics of the semiconductor device according to the first embodiment.

Fig. 4 is a cross-sectional view showing a semiconductor device according to a first modification of the first embodiment.

Fig. 5 is a plan view showing a semiconductor device according to a second modification of the first embodiment.

Fig. 6 is a cross-sectional view showing a semiconductor device according to a second modification of the first embodiment.

Fig. 7 is a plan view showing a semiconductor device according to a second embodiment.

Fig. 8 is a cross-sectional view showing a semiconductor device according to a second embodiment.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each portion, the ratio of the sizes between the portions, and the like are not necessarily the same as reality. Even when the same portions are shown, the dimensions and ratios of the portions may be different from each other according to the drawings. In the present specification and the drawings, the same elements as those described with respect to the drawings already appearing are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

In the following, for ease of explanation, the arrangement and structure of each part will be explained using an XYZ orthogonal coordinate system. The X axis, the Y axis and the Z axis are mutually orthogonal. The direction in which the X axis extends is referred to as the "X direction", the direction in which the Y axis extends is referred to as the "Y direction", and the direction in which the Z axis extends is referred to as the "Z direction". For easy understanding, the direction of the arrow in the Z direction is set to be upward and the opposite direction is set to be downward, but these directions are not related to the direction of gravity.

In the following, the marks "+", "-" indicate the relative heights of the impurity concentrations of the respective conductivity types. Specifically, the sign with "+" indicates that the impurity concentration is higher than the sign without either of "+" and "-" added. The symbol to which "-" is added indicates that the impurity concentration is lower than that of the symbol to which either "+" or "-" is not added. Here, the "impurity concentration" refers to a net impurity concentration after these impurities cancel each other out when both the impurity serving as a donor and the impurity serving as an acceptor are contained in each region.

Fig. 1 is a plan view showing a semiconductor device according to a first embodiment.

Fig. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment.

Fig. 2 is a sectional view based on the line A1-A2 shown in fig. 1.

As shown in fig. 1 and 2, the semiconductor device 100 according to the first embodiment includes a first electrode 10, a semiconductor portion 20, a second electrode 30, a structure 40, a first insulating portion 51, and a second insulating portion 52. The semiconductor device 100 is an IGBT.

The first electrode 10 is provided in a lower portion of the semiconductor device 100. The first electrode 10 is a lower electrode. The first electrode 10 functions as a collector electrode, for example. The upper and lower surfaces of the first electrode 10 are substantially parallel to the XY plane. The first electrode 10 is made of a conductive material such as a metal material.

The semiconductor portion 20 includes a first semiconductor region 21, a second semiconductor region 22, a third semiconductor region 23, a fourth semiconductor region 24, and a fifth semiconductor region 25.

The first semiconductor region 21 is provided above the first electrode 10. The first semiconductor region 21 is a p-type semiconductor region. The first semiconductor region 21 is p ⁺ Is formed on the semiconductor substrate. The impurity concentration of the first semiconductor region 21 is, for example, higher than that of the third semiconductor region23 is high in impurity concentration.

The second semiconductor region 22 is provided above the first semiconductor region 21. The second semiconductor region 22 is an n-type semiconductor region. The second semiconductor region 22 includes a first layer 22a and a second layer 22b. The first layer 22a is provided over the first semiconductor region 21. The second layer 22b is disposed over the first layer 22a. The first layer 22a is n ^- Is formed on the semiconductor substrate. The impurity concentration of the first layer 22a is lower than that of the second layer 22b, for example.

The third semiconductor region 23 is provided above the second semiconductor region 22. The third semiconductor region 23 is provided over the second layer 22b. The third semiconductor region 23 is a p-type semiconductor region.

The fourth semiconductor region 24 is provided above the third semiconductor region 23. The fourth semiconductor region 24 is an n-type semiconductor region. The fourth semiconductor region 24 is n ⁺ Is formed on the semiconductor substrate. The impurity concentration of the fourth semiconductor region 24 is, for example, higher than that of the second layer 22b of the second semiconductor region 22.

The fifth semiconductor region 25 is provided above the third semiconductor region 23. The fifth semiconductor region 25 is a p-type semiconductor region. The fifth semiconductor region 25 is p ⁺ Is formed on the semiconductor substrate. The impurity concentration of the fifth semiconductor region 25 is higher than that of the third semiconductor region 23, for example.

The first direction from the first semiconductor region 21 toward the second semiconductor region 22 is along the Z direction. A second direction perpendicular to the first direction is along the X direction. In this example, the fourth semiconductor regions 24 and the fifth semiconductor regions 25 are alternately arranged in the X direction. In this example, in the Y direction, the fourth semiconductor regions 24 and the fifth semiconductor regions 25 are alternately arranged.

The first semiconductor region 21, the second semiconductor region 22, the third semiconductor region 23, the fourth semiconductor region 24, and the fifth semiconductor region 25 include a semiconductor material such as silicon and impurities corresponding to the respective regions.

A structure 40 is provided inside the semiconductor portion 20. The structure 40 has a structure in which gate portions 41 and dummy portions 43 are alternately arranged in the X direction. That is, the structure 40 has a plurality of gate portions 41 and a plurality of dummy portions 43. The gate portions 41 and the dummy portions 43 are alternately arranged in the X direction. The gate portion 41 and the dummy portion 43 extend in the Y direction, respectively.

The gate portion 41 is provided in the fourth semiconductor region 24. The gate portion 41 includes at least one gate electrode 42. In this example, the gate portion 41 includes three gate electrodes 42. In this example, the gate portion 41 is constituted by three gate electrodes 42.

The gate electrode 42 extends from the upper end of the fourth semiconductor region 24 to the first layer 22a of the second semiconductor region through the third semiconductor region 23 and the second layer 22b of the second semiconductor region 22 in the Z direction. That is, the gate electrode 42 is aligned with the fourth semiconductor region 24, the third semiconductor region 23, the second layer 22b of the second semiconductor region 22, and the first layer 22a of the second semiconductor region in the X direction. The gate electrode 42 is made of a conductive material such as a metal material or polysilicon.

A first insulating portion 51 is provided between the gate electrode 42 and the semiconductor portion 20. A part of the first insulating portion 51 is located between the gate electrode 42 and the fourth semiconductor region 24, between the gate electrode 42 and the third semiconductor region 23, between the gate electrode 42 and the second layer 22b of the second semiconductor region 22, and between the gate electrode 42 and the first layer 22a of the second semiconductor region 22 in the X direction. Another portion of the first insulating portion 51 is located between the gate electrode 42 and the first layer 22a of the second semiconductor region 22 in the Z direction. A part of the first insulating portion 51 functions as a gate insulating film, for example. The first insulating portion 51 is made of an insulating material such as silicon oxide or silicon nitride, for example.

In this example, the dummy portion 43 is provided in the fifth semiconductor region 25. The dummy portion 43 includes at least two dummy electrodes 44. In this example, the dummy portion 43 includes three dummy electrodes 44. In this example, the dummy portion 43 is constituted by three dummy electrodes 44.

The dummy electrode 44 extends from the upper end of the fifth semiconductor region 25 to the first layer 22a of the second semiconductor region through the third semiconductor region 23 and the second layer 22b of the second semiconductor region 22 in the Z direction. That is, the dummy electrode 44 is aligned with the fifth semiconductor region 25, the third semiconductor region 23, the second layer 22b of the second semiconductor region 22, and the first layer 22a of the second semiconductor region in the X direction. The lower end of the dummy electrode 44 is arranged with the lower end of the gate electrode 42 in, for example, the X direction. The dummy electrode 44 is made of a conductive material such as a metal material or polysilicon.

A second insulating portion 52 is provided between the dummy electrode 44 and the semiconductor portion 20. A part of the second insulating portion 52 is located between the dummy electrode 44 and the fifth semiconductor region 25, between the dummy electrode 44 and the third semiconductor region 23, between the dummy electrode 44 and the second layer 22b of the second semiconductor region 22, and between the dummy electrode 44 and the first layer 22a of the second semiconductor region 22 in the X direction. Another portion of the second insulating portion 52 is located between the dummy electrode 44 and the first layer 22a of the second semiconductor region 22 in the Z direction. The second insulating portion 52 is made of an insulating material such as silicon oxide or silicon nitride.

In this example, the structure 40 includes gate portions 41a, 41b, 41c and dummy portions 43a, 43b. The respective portions are arranged in the order of the gate portion 41b, the dummy portion 43a, the gate portion 41a, the dummy portion 43b, and the gate portion 41c in the X direction.

The gate portion 41a has gate electrodes 42a, 42b, 42c. The gate portion 41b has a gate electrode 42d and two gate electrodes 42 not shown. The gate portion 41c has a gate electrode 42e and two gate electrodes 42 not shown. The dummy portion 43a has dummy electrodes 44a, 44b, 44c. The dummy portion 43b has dummy electrodes 44d, 44e, 44f.

The second electrode 30 is provided on the semiconductor portion 20. The second electrode 30 is disposed over the fourth semiconductor region 24 and over the fifth semiconductor region 25. The second electrode 30 is an upper electrode. The second electrode 30 functions as an emitter electrode, for example. The second electrode 30 is made of a conductive material such as a metal material. In fig. 1, the second electrode 30 is omitted. An insulating portion is provided between the second electrode 30 and the gate electrode 42.

For the second electrode 30, a first potential is applied. The first potential is, for example, the emitter potential E. The first potential is, for example, 0V.

A second potential is applied to the gate electrode 42. The second potential is, for example, the gate potential G. The second potential is higher than the first potential. The second potential is, for example, 15V.

A third potential is applied to the dummy electrode 44 provided at a position adjacent to the gate portion 41 among the dummy electrodes 44. The third potential is higher than the first potential. In this example, the third potential is applied to the dummy electrode 44a provided at a position adjacent to the gate portion 41b, the dummy electrodes 44c and 44d provided at a position adjacent to the gate portion 41a, and the dummy electrode 44f provided at a position adjacent to the gate portion 41 c.

The third potential is, for example, higher than the first potential and lower than the second potential. The third potential is, for example, equal to the second potential. The third potential is, for example, higher than 0V and lower than 15V. The third potential is, for example, 15V. That is, the gate potential G is applied to the dummy electrode 44 provided adjacent to the gate portion 41, for example, among the dummy electrodes 44. In other words, the dummy electrode 44 provided at a position adjacent to the gate portion 41 among the dummy electrodes 44 is connected to the gate electrode 42, for example. The dummy electrode 44 provided at a position adjacent to the gate portion 41 among the dummy electrodes 44 is connected to the gate electrode 42 at an end portion of the semiconductor device 100 in the Y direction, for example.

On the other hand, a first potential is applied to, for example, the dummy electrode 44 provided at a position not adjacent to the gate portion 41 among the dummy electrodes 44. In this example, a first potential is applied to the dummy electrodes 44b and 44e provided at positions not adjacent to the gate portion 41. That is, for example, the emitter potential E is applied to the dummy electrode 44 provided at a position not adjacent to the gate portion 41 among the dummy electrodes 44. In other words, the dummy electrode 44 provided at a position not adjacent to the gate portion 41 among the dummy electrodes 44 is connected to the second electrode 30, for example.

Next, the operation and effects of the semiconductor device 100 will be described.

When a voltage equal to or higher than a threshold value is applied to the gate electrode 42 in a state where a positive voltage is applied to the first electrode 10 (collector) with respect to the second electrode 30 (emitter electrode), the semiconductor device is turned on. At this time, a channel (inversion layer) is formed in a region near the first insulating portion 51 (gate insulating film) of the third semiconductor region 23. Electrons are injected from the fourth semiconductor region 24 into the second semiconductor region 22 through the channel, and holes are injected from the first semiconductor region 21 into the second semiconductor region 22. Then, when the voltage applied to the gate electrode 42 becomes lower than the threshold value, the channel in the third semiconductor region 23 disappears, and the semiconductor device is turned off.

In the semiconductor portion 20, a structure 40 in which gate portions 41 including gate electrodes 42 and dummy portions 43 including dummy electrodes 44 are alternately arranged is provided, and the capacitance of the gate electrodes 42 can be reduced by applying a first potential (emitter potential E) to the dummy electrodes 44. This can improve the response speed.

On the other hand, when the first potential is applied to the dummy electrode 44 provided at a position adjacent to the gate portion 41, the hole current is discharged through the hole inversion layer at the time of turning on, and the hole accumulation rate is liable to decrease.

In contrast, in the semiconductor device 100 according to the first embodiment, by applying the third potential higher than the first potential to the dummy electrode 44 provided at the position adjacent to the gate portion 41, the hole accumulation rate can be ensured, and the drop characteristic of the collector-emitter voltage Vce at the time of on can be improved. This can reduce the loss at the time of switching on.

Further, by equalizing the third potential applied to the dummy electrode 44 provided at a position adjacent to the gate portion 41 with the second potential (gate potential G) applied to the gate electrode 42, the loss at the time of turning on can be further reduced. For example, by connecting the dummy electrode 44 provided at a position adjacent to the gate portion 41 to the gate electrode 42, the third potential and the second potential can be equalized.

Further, by applying the first potential to the dummy electrode 44 provided at a position not adjacent to the gate portion 41, the response speed can be improved. For example, by connecting the dummy electrode 44 provided at a position not adjacent to the gate portion 41 to the second electrode 30, the first potential can be applied to the dummy electrode 44 provided at a position not adjacent to the gate portion 41.

Further, by including three gate electrodes 42 in the gate portion 41 and three dummy electrodes 44 in the dummy portion 43, an improvement in response speed, an improvement in on-voltage and on-resistance can be achieved more in balance.

Fig. 3 (a) and 3 (b) are graphs showing simulation results of characteristics of the semiconductor device according to the first embodiment.

In fig. 3 (a) and 3 (b), the horizontal axis represents time [ a.u ]. In fig. 3 (a), the vertical axes are collector-emitter current Ic [ a.u ] and collector-emitter voltage Vce [ a.u ]. In fig. 3 (b), the vertical axis is loss [ a.u ]. "a.u." means an arbitrary unit (arbitrary unit).

Fig. 3 (a) and 3 (b) show simulation results of characteristics of example 1 in which a gate potential is applied to the dummy electrode 44 provided at a position adjacent to the gate portion 41 and example 2 in which an emitter potential is applied to the dummy electrode 44 provided at a position adjacent to the gate portion 41 in a structure in which the gate portion 41 including three gate electrodes 42 and the dummy portion 43 including three dummy electrodes 44 are alternately arranged.

In addition, in experimental examples 1 and 2, a gate potential was applied to the gate electrode 42. In experimental examples 1 and 2, the gate potential was set to 15V and the emitter potential was set to 0V.

In fig. 3 (a), the time-dependent changes in the collector-emitter current Ic and the collector-emitter voltage Vce at the time of turning on in experimental example 1 are shown by a broken line, and the time-dependent changes in the collector-emitter current Ic and the collector-emitter voltage Vce at the time of turning on in experimental example 2 are shown by a solid line.

In fig. 3 (b), the time-dependent change in the loss at the time of the on state of experimental example 1 is shown by a broken line, and the time-dependent change in the loss at the time of the on state of experimental example 2 is shown by a solid line.

As shown in fig. 3 (a) and 3 (b), in experimental example 1, the collector-emitter voltage Vce at the time of on was excellent in the drop characteristic, and the loss at the time of on was reduced, as compared with experimental example 2.

This implies that according to the first embodiment, by applying the third potential (for example, the gate potential) higher than the first potential to the dummy electrode 44 provided at the position adjacent to the gate portion 41, the loss at the time of turning on can be reduced as compared with the case where the first potential (for example, the emitter potential) is applied to the dummy electrode 44 provided at the position adjacent to the gate portion 41.

Fig. 4 is a cross-sectional view showing a semiconductor device according to a first modification of the first embodiment.

As shown in fig. 4, in the semiconductor device 100A according to the first modification of the first embodiment, the resistor 60 is provided between the gate potential G and the dummy electrode 44 provided at a position adjacent to the gate 41 among the dummy electrodes 44. Otherwise, the method is substantially the same as the semiconductor device 100 described above.

More specifically, the resistor 60 is provided between the dummy electrodes 44a, 44c, 44d, 44f and the gate potential G. Thus, the third potential applied to the dummy electrodes 44a, 44c, 44d, 44f is lower than the second potential (gate potential G). In this way, the third potential can also be adjusted by providing the resistor portion 60 or the like.

In the semiconductor device 100A according to the first modification of the first embodiment, by applying the third potential higher than the first potential to the dummy electrode 44 provided at the position adjacent to the gate portion 41, the hole accumulation rate can be ensured, and the drop characteristic of the collector-emitter voltage Vce at the time of on can be improved. This can reduce the loss at the time of switching on.

Fig. 5 is a plan view showing a semiconductor device according to a second modification of the first embodiment.

Fig. 6 is a cross-sectional view showing a semiconductor device according to a second modification of the first embodiment.

Fig. 6 is a sectional view based on the line B1-B2 shown in fig. 5.

As shown in fig. 5 and 6, in the semiconductor device 100B according to the second modification of the first embodiment, the second electrode 30 includes the first conductive portion 31 and the second conductive portion 32. In fig. 5, the first conductive portion 31 is omitted.

The first conductive portion 31 is provided on the semiconductor portion 20. The second conductive portion 32 is disposed under the first conductive portion 31. The second conductive portion 32 is disposed in the semiconductor portion 20. At least a portion of the second conductive portion 32 is located between two gate electrodes 42 adjacent to each other in the X direction. In this example, the second conductive portion 32 is provided between two gate electrodes 42 adjacent to each other, between two dummy electrodes 44 adjacent to each other, and between the gate electrodes 42 and the dummy electrodes 44 adjacent to each other.

In this example, the third semiconductor region 23 includes a first portion 23a and a second portion 23b. The second portion 23b is disposed over the first portion 23a. The fourth semiconductor region 24 is provided over the first portion 23a. In this example, on the B1-B2 line, the fourth semiconductor region 24 and the second portion 23B of the third semiconductor region 23 are alternately arranged in the X direction. In this example, the fourth semiconductor regions 24 and the second portions 23b of the third semiconductor regions 23 are alternately arranged in the Y direction on the side surfaces of the gate electrode 42. In this example, the dummy portion 43 is provided in the second portion 23b of the third semiconductor region 23.

In addition, in this example, the fifth semiconductor region 25 is provided under the second conductive portion 32. The fifth semiconductor region 25 is provided between the first portion 23a of the third semiconductor region 23 and the second conductive portion 32 in the Z direction. The fifth semiconductor region 25 is aligned with the first portion 23a of the third semiconductor region 23 in the X direction. Otherwise, the method is substantially the same as the semiconductor device 100 described above.

The second conductive portion 32 provided between two gate electrodes 42 adjacent to each other is provided in the fourth semiconductor region 24. The second conductive portion 32 provided between two gate electrodes 42 adjacent to each other extends from the lower end of the first conductive portion 31 to the first portion 23a of the third semiconductor region 23 through the fourth semiconductor region 24 in the Z direction. That is, the second conductive portion 32 provided between two gate electrodes 42 adjacent to each other is aligned with the fourth semiconductor region 24 and the first portion 23a of the third semiconductor region 23 in the X direction.

The second conductive portion 32 provided between two dummy electrodes 44 adjacent to each other is provided in the second portion 23b of the third semiconductor region 23. The second conductive portion 32 provided between two dummy electrodes 44 adjacent to each other extends from the lower end of the first conductive portion 31 to the first portion 23a of the third semiconductor region 23 through the second portion 23b of the third semiconductor region 23 in the Z direction. That is, the second conductive portion 32 provided between two adjacent dummy electrodes 44 is aligned with the first portion 23a and the second portion 23b of the third semiconductor region 23 in the X direction.

The second conductive portion 32 provided between the gate electrode 42 and the dummy electrode 44 adjacent to each other is provided at the boundary between the fourth semiconductor region 24 and the second portion 23b of the third semiconductor region 23. The second conductive portion 32 provided between the gate electrode 42 and the dummy electrode 44 adjacent to each other extends from the lower end of the first conductive portion 31 to the first portion 23a of the third semiconductor region 23 through the second portion 23b and the fourth semiconductor region 24 of the third semiconductor region 23 in the Z direction. That is, the second conductive portion 32 provided between the gate electrode 42 and the dummy electrode 44 adjacent to each other is aligned with the first portion 23a and the second portion 23b of the fourth semiconductor region 24 and the third semiconductor region 23 in the X direction.

In the semiconductor device 100B according to the second modification of the first embodiment, by applying the third potential higher than the first potential to the dummy electrode 44 provided at a position adjacent to the gate portion 41, the hole accumulation rate can be ensured, and the drop characteristic of the collector-emitter voltage Vce at the time of on can be improved. This can reduce the loss at the time of switching on.

Fig. 7 is a plan view showing a semiconductor device according to a second embodiment.

Fig. 8 is a cross-sectional view showing a semiconductor device according to a second embodiment.

Fig. 8 is a cross-sectional view taken along line C1-C2 of fig. 7.

As shown in fig. 7 and 8, in the semiconductor device 200 according to the second embodiment, the gate portion 41 includes at least two gate electrodes 42. In the semiconductor device 200, the dummy portion 43 includes at least one dummy electrode 44. Otherwise, the method is substantially the same as the semiconductor device 100B. In fig. 7, the first conductive portion 31 is omitted.

More specifically, the gate portion 41 includes at least a first gate electrode 42x and a second gate electrode 42y. The first gate electrode 42X is provided at one end of the fourth semiconductor region 24 in the X direction. The second gate electrode 42y is provided at the other end of the fourth semiconductor region 24 in the X direction. The first gate electrode 42X is located between the fourth semiconductor region 24 and the second portion 23b of the third semiconductor region 23 in the X direction. The second gate electrode 42y is located between the fourth semiconductor region 24 and the second portion 23b of the third semiconductor region 23 in the X direction. The fourth semiconductor region 24 is provided between the first gate electrode 42X and the second gate electrode 42y in the X direction.

In the X direction, the second portion 23b of the third semiconductor region 23 is provided between one gate portion 41 (for example, the gate portion 41 a) and the other gate portion 41 (for example, the gate portion 41b or the gate portion 41 c) adjacent thereto. One side surface of the first gate electrode 42X in the X direction faces the second portion 23b of the third semiconductor region 23. The other side surface in the X direction of the first gate electrode 42X faces the fourth semiconductor region 24. One side surface of the second gate electrode 42y in the X direction faces the fourth semiconductor region 24. The other side surface in the X direction of the second gate electrode 42y faces the second portion 23b of the third semiconductor region 23.

The gate portion 41 may further include a third gate electrode 42z provided between the first gate electrode 42x and the second gate electrode 42y. The third gate electrode 42z is disposed in the fourth semiconductor region 24. In this example, the gate portion 41 includes one third gate electrode 42z. That is, in this example, the gate portion 41 is constituted by three gate electrodes 42. The number of the third gate electrodes 42z included in the gate portion 41 may be 0, one, or two or more.

In this example, the dummy portion 43 includes one dummy electrode 44. In this example, the dummy portion 43 is constituted by one dummy electrode 44. That is, in this example, the number of the dummy electrodes 44 included in the dummy portion 43 is one. The number of the dummy electrodes 44 included in the dummy portion 43 may be one or two or more.

In this example, the structure 40 includes gate portions 41a, 41b, 41c and dummy portions 43a, 43b. The respective portions are arranged in the order of the gate portion 41b, the dummy portion 43a, the gate portion 41a, the dummy portion 43b, and the gate portion 41c in the X direction.

The gate portions 41a, 41b, 41c have a first gate electrode 42x, a second gate electrode 42y, and a third gate electrode 42z, respectively. The dummy portion 43a has a dummy electrode 44a. The dummy portion 43b has a dummy electrode 44b.

In this example, a first potential is applied to the second electrode 30 and the dummy electrode 44. The first potential is, for example, the emitter potential E. The first potential is, for example, 0V. On the other hand, a second potential is applied to the gate electrode 42. The second potential is, for example, the gate potential G. The second potential is higher than the first potential. The second potential is, for example, 15V.

Next, the operation and effects of the semiconductor device 200 will be described.

When a voltage equal to or higher than a threshold value is applied to the gate electrode 42 in a state where a positive voltage is applied to the first electrode 10 (collector) with respect to the second electrode 30 (emitter electrode), the semiconductor device is turned on. At this time, a channel (inversion layer) is formed in a region near the first insulating portion 51 (gate insulating film) of the third semiconductor region 23. Electrons are injected from the fourth semiconductor region 24 into the second semiconductor region 22 through the channel, and holes are injected from the first semiconductor region 21 into the second semiconductor region 22. Then, when the voltage applied to the gate electrode 42 becomes lower than the threshold value, the channel in the third semiconductor region 23 disappears, and the semiconductor device is turned off.

By providing the structure 40 in which the gate portions 41 including the gate electrode 42 and the dummy portions 43 including the dummy electrode 44 are alternately arranged in the semiconductor portion 20, and by providing the gate portion 41 with the first gate electrode 42x provided at one end of the fourth semiconductor region 24 and the second gate electrode 42y provided at the other end of the fourth semiconductor region 24, the capacitance of the gate electrode 42 can be reduced. This can improve the response speed. In addition, the hole accumulation rate can be ensured, and the drop characteristic of the collector-emitter voltage Vce at the time of on can be improved. This can reduce the loss at the time of switching on. The simulation results of the characteristics of the semiconductor device according to the second embodiment are also similar to those of the semiconductor device according to the first embodiment shown in fig. 3 (a) and 3 (b).

In addition, if the number of the dummy electrodes 44 included in the dummy portion 43 is one, the gate capacitance can be reduced and the driving loss can be reduced as compared with, for example, the second modification of the first embodiment. If the gate potential G is applied to all the dummy electrodes 44 without providing the dummy electrodes 44 to which the emitter potential E is applied, negative capacitance (a phenomenon in which the gate charge becomes small when the gate potential G is increased) is generated at the time of load short circuit or the like, and gate vibration is likely to occur. In contrast, by providing the dummy electrode 44 to which the emitter potential E is applied, gate vibration can be suppressed. In this example, compared with the second modification of the first embodiment shown in fig. 5 and 6, the area ratio of the fourth semiconductor region 24 to which the electron current is supplied at the time of conduction is the same. However, since the number of electrodes to which the gate potential G is applied is small, the gate capacitance becomes small and the driving loss becomes small. In addition, the gate driver that drives the IGBT can be made smaller. The number of electrodes to which the gate potential G is applied, which are continuous and adjacent, is three less in the example of fig. 8 than five in the example of fig. 6, and accordingly there is an advantage in that it is more difficult to generate negative capacitance. However, if the loads of the gate drivers are made different, the gate capacitance is not necessarily smaller as well as is preferable depending on the application, and therefore it is preferable to use this configuration of the first embodiment separately from the configuration of the second embodiment.

The embodiment includes the following configuration.

(constitution 1)

A semiconductor device is provided with:

a first electrode;

a semiconductor portion including a p-type first semiconductor region provided over the first electrode, an n-type second semiconductor region provided over the first semiconductor region, a p-type third semiconductor region provided over the second semiconductor region, an n-type fourth semiconductor region provided over the third semiconductor region, and a p-type fifth semiconductor region provided over the third semiconductor region;

a second electrode provided over the semiconductor portion; ,

a structure in which gate portions including at least one gate electrode and dummy portions including at least two dummy electrodes are alternately arranged in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region; and

an insulating portion provided between the gate electrode and the semiconductor portion;

the gate portion is disposed in the fourth semiconductor region,

for the second electrode, a first potential is applied,

applying a second potential higher than the first potential to the gate electrode,

a third potential higher than the first potential is applied to the dummy electrode provided at a position adjacent to the gate portion.

(constitution 2)

The semiconductor device according to the constitution 1, wherein,

the fourth semiconductor regions and the fifth semiconductor regions are alternately arranged in the second direction,

the dummy portion is disposed in the fifth semiconductor region.

(constitution 3)

The semiconductor device according to the constitution 1, wherein,

the second electrode includes a first conductive portion provided above the semiconductor portion and a second conductive portion provided below the first conductive portion and located between two gate electrodes adjacent to each other in the second direction,

the third semiconductor region includes a first portion and a second portion disposed over the first portion,

the fourth semiconductor region is disposed over the first portion,

the fourth semiconductor regions and the second portions are alternately arranged in the second direction,

the fifth semiconductor region is disposed under the second conductive portion,

the dummy portion is disposed in the second portion.

(constitution 4)

The semiconductor device according to any one of the above 1 to 3, wherein,

the third potential is equal to the second potential.

(constitution 5)

The semiconductor device according to any one of the above 1 to 4, wherein,

the second potential is 15V.

(constitution 6)

The semiconductor device according to any one of the above 1 to 5, wherein,

the dummy portion includes at least three of the dummy electrodes,

the first potential is applied to the dummy electrode provided at a position not adjacent to the gate portion.

(constitution 7)

A semiconductor device is provided with:

a first electrode;

a semiconductor portion including a p-type first semiconductor region provided over the first electrode, an n-type second semiconductor region provided over the first semiconductor region, a p-type third semiconductor region provided over the second semiconductor region, an n-type fourth semiconductor region provided over the third semiconductor region, and a p-type fifth semiconductor region provided over the third semiconductor region;

a second electrode provided over the semiconductor portion;

a structure in which gate portions including at least one gate electrode and dummy portions including at least two dummy electrodes are alternately arranged in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region; and

an insulating portion provided between the gate electrode and the semiconductor portion;

the gate portion is disposed in the fourth semiconductor region,

the dummy electrode provided at a position adjacent to the gate portion is connected to the gate electrode.

(constitution 8)

The semiconductor device according to the constitution 7, wherein,

the fourth semiconductor regions and the fifth semiconductor regions are alternately arranged in the second direction,

the dummy portion is disposed in the fifth semiconductor region.

(constitution 9)

The semiconductor device according to the constitution 7, wherein,

the second electrode includes a first conductive portion provided above the semiconductor portion and a second conductive portion provided below the first conductive portion and located between two gate electrodes adjacent to each other in the second direction,

the third semiconductor region includes a first portion and a second portion disposed over the first portion,

the fourth semiconductor region is disposed over the first portion,

the fourth semiconductor regions and the second portions are alternately arranged in the second direction,

the fifth semiconductor region is disposed under the second conductive portion,

the dummy portion is disposed in the second portion.

(constitution 10)

The semiconductor device according to any one of the above-mentioned configurations 7 to 9, wherein,

the dummy portion includes at least three of the dummy electrodes,

the dummy electrode provided at a position not adjacent to the gate portion is connected to the second electrode.

(constitution 11)

The semiconductor device according to any one of the above 1 to 10, wherein,

the gate portion comprises three of the gate electrodes,

the dummy portion includes three of the dummy electrodes.

(constitution 12)

A semiconductor device is provided with:

a first electrode;

a semiconductor portion including a p-type first semiconductor region provided over the first electrode, an n-type second semiconductor region provided over the first semiconductor region, a p-type third semiconductor region provided over the second semiconductor region, an n-type fourth semiconductor region provided over the third semiconductor region, and a p-type fifth semiconductor region provided over the third semiconductor region;

a second electrode provided over the semiconductor portion;

a structure in which gate portions including at least two gate electrodes and dummy portions including at least one dummy electrode are alternately arranged in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region; and

an insulating portion provided between the gate electrode and the semiconductor portion;

the second electrode includes a first conductive portion provided above the semiconductor portion and a second conductive portion provided below the first conductive portion and located between two gate electrodes adjacent to each other in the second direction,

the third semiconductor region includes a first portion and a second portion disposed over the first portion,

the fourth semiconductor region is disposed over the first portion,

the fourth semiconductor regions and the second portions are alternately arranged in the second direction,

the fifth semiconductor region is disposed under the second conductive portion,

the dummy portion is disposed in the second portion,

the gate portion includes a first gate electrode provided at one end of the fourth semiconductor region in the second direction and a second gate electrode provided at the other end of the fourth semiconductor region in the second direction.

(constitution 13)

The semiconductor device according to the constitution 12, wherein,

the number of the dummy electrodes included in the dummy portion is one.

As described above, according to the embodiments, a semiconductor device in which the loss at the time of turn-on is reduced can be provided.

While the embodiments of the present application have been described above, these embodiments are presented as examples and are not intended to limit the scope of the application. These novel embodiments can be implemented in other various modes, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. These embodiments and modifications thereof are included in the scope and gist of the application, and are included in the application described in the claims and their equivalents.

Claims (13)

1. A semiconductor device is characterized by comprising:

a first electrode;

a semiconductor portion including a p-type first semiconductor region provided over the first electrode, an n-type second semiconductor region provided over the first semiconductor region, a p-type third semiconductor region provided over the second semiconductor region, an n-type fourth semiconductor region provided over the third semiconductor region, and a p-type fifth semiconductor region provided over the third semiconductor region;

a second electrode provided over the semiconductor portion; ,

a structure in which gate portions including at least one gate electrode and dummy portions including at least two dummy electrodes are alternately arranged in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region; and

an insulating portion provided between the gate electrode and the semiconductor portion,

the gate portion is disposed in the fourth semiconductor region,

the second electrode is applied with a first potential,

the gate electrode is applied with a second potential higher than the first potential,

the dummy electrode provided at a position adjacent to the gate portion is applied with a third potential higher than the first potential.

2. The semiconductor device according to claim 1, wherein,

the fourth semiconductor regions and the fifth semiconductor regions are alternately arranged in the second direction,

the dummy portion is disposed in the fifth semiconductor region.

3. The semiconductor device according to claim 1, wherein,

the second electrode includes a first conductive portion provided above the semiconductor portion and a second conductive portion provided below the first conductive portion and located between two gate electrodes adjacent to each other in the second direction,

the third semiconductor region includes a first portion and a second portion disposed over the first portion,

the fourth semiconductor region is disposed over the first portion,

the fourth semiconductor regions and the second portions are alternately arranged in the second direction,

the fifth semiconductor region is disposed under the second conductive portion,

the dummy portion is disposed in the second portion.

4. The semiconductor device according to claim 1, wherein,

the third potential is equal to the second potential.

5. The semiconductor device according to claim 1, wherein,

the second potential is 15V.

6. The semiconductor device according to claim 1, wherein,

the dummy portion includes at least three of the dummy electrodes,

the dummy electrode provided at a position not adjacent to the gate portion is applied with the first potential.

7. A semiconductor device is characterized by comprising:

a first electrode;

a semiconductor portion including a p-type first semiconductor region provided over the first electrode, an n-type second semiconductor region provided over the first semiconductor region, a p-type third semiconductor region provided over the second semiconductor region, an n-type fourth semiconductor region provided over the third semiconductor region, and a p-type fifth semiconductor region provided over the third semiconductor region;

a second electrode provided over the semiconductor portion;

a structure in which gate portions including at least one gate electrode and dummy portions including at least two dummy electrodes are alternately arranged in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region; and

an insulating portion provided between the gate electrode and the semiconductor portion,

the gate portion is disposed in the fourth semiconductor region,

the dummy electrode provided at a position adjacent to the gate portion is connected to the gate electrode.

8. The semiconductor device according to claim 7, wherein,

the fourth semiconductor regions and the fifth semiconductor regions are alternately arranged in the second direction,

the dummy portion is disposed in the fifth semiconductor region.

9. The semiconductor device according to claim 7, wherein,

the second electrode includes a first conductive portion provided above the semiconductor portion and a second conductive portion provided below the first conductive portion and located between two gate electrodes adjacent to each other in the second direction,

the third semiconductor region includes a first portion and a second portion disposed over the first portion,

the fourth semiconductor region is disposed over the first portion,

the fourth semiconductor regions and the second portions are alternately arranged in the second direction,

the fifth semiconductor region is disposed under the second conductive portion,

the dummy portion is disposed in the second portion.

10. The semiconductor device according to claim 7, wherein,

the dummy portion includes at least three of the dummy electrodes,

the dummy electrode provided at a position not adjacent to the gate portion is connected to the second electrode.

11. The semiconductor device according to any one of claims 1 to 10, wherein,

the gate portion comprises three of the gate electrodes,

the dummy portion includes three of the dummy electrodes.

12. A semiconductor device is characterized by comprising:

a first electrode;

a semiconductor portion including a p-type first semiconductor region provided over the first electrode, an n-type second semiconductor region provided over the first semiconductor region, a p-type third semiconductor region provided over the second semiconductor region, an n-type fourth semiconductor region provided over the third semiconductor region, and a p-type fifth semiconductor region provided over the third semiconductor region;

a second electrode provided over the semiconductor portion;

a structure in which gate portions including at least two gate electrodes and dummy portions including at least one dummy electrode are alternately arranged in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region; and

an insulating portion provided between the gate electrode and the semiconductor portion,

the second electrode includes a first conductive portion provided above the semiconductor portion and a second conductive portion provided below the first conductive portion and located between two gate electrodes adjacent to each other in the second direction,

the third semiconductor region includes a first portion and a second portion disposed over the first portion,

the fourth semiconductor region is disposed over the first portion,

the fourth semiconductor regions and the second portions are alternately arranged in the second direction,

the fifth semiconductor region is disposed under the second conductive portion,

the dummy portion is disposed in the second portion,

the gate portion includes a first gate electrode provided at one end of the fourth semiconductor region in the second direction and a second gate electrode provided at the other end of the fourth semiconductor region in the second direction.

13. The semiconductor device according to claim 12, wherein,

the number of the dummy electrodes included in the dummy portion is one.