JP2023137759A - Semiconductor device, method of manufacturing semiconductor device and electronic device - Google Patents

Abstract

To provide a high-performance semiconductor device that comprises a channel layer having superior electron mobility.SOLUTION: A semiconductor device 1 has a substrate 10, a buffer layer 20 and a channel layer 30. The substrate 10 includes AIN. The buffer layer 20 is provided on the side of a surface 10a of the substrate 10, and includes AlxGa1-xN (0.15<x≤0.30) having compressive stress. The channel layer 30 is provided on the side of an opposite surface 20a of the buffer layer 20 from the substrate 10, and includes GaN. The buffer layer 20 including AlxGa1-xN having the compressive stress is so provided that polarization charges on the surface 20a on the side of the channel layer 30 are zero or plus. Consequently, the channel layer 30 has conduction band energy on the side of the buffer layer 20 suppressed from being elevated, and a distribution and wave function of electrons spreads, so that electron mobility of the channel layer 30 is improved. The electron mobility is thus improved to suppress a performance decrease of the semiconductor device 1 such as an output current decrease.SELECTED DRAWING: Figure 3

Description

The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device.

Semiconductor devices using nitride semiconductors are known. For example, GaN (gallium nitride) is used for the channel layer (also called "electron transit layer"), and AlN (aluminum nitride) or AlGaN (aluminum gallium nitride) is used for the barrier layer (also called "electron supply layer"). A high electron mobility transistor (HEMT) used in the present invention is known.

Regarding such a HEMT, a technique is known in which, for example, a channel layer containing GaN is provided on a buffer layer containing Al _x Ga _1-x N. Regarding this technology, it is known that when the thickness of the channel layer is 5 nm, the Al composition of Al _x Ga _1-x N of the buffer layer is set in the range of 8% to 32%.

Further, a buffer layer having a first buffer layer containing Al _α Ga _1-α N (0<α≦1) and a second buffer layer containing Al _β Ga _1-β N (0<β<α≦1) A technique is known in which an electron transit layer of GaN or the like is provided on a back barrier layer containing Al _x Ga _(1-X) N (0<X≦1) provided above. Regarding this technology, the Al composition ratio X of the back barrier layer is not uniquely defined, and may be 0.01 or more and 0.1 or less, 0.1 or more and 0.2 or less, and 0.2 or more and 0.2 or less. It is known that the number may be 3 or less.

US Patent Application Publication No. 2004/0238842 JP2019-121785A

A HEMT in which a channel layer containing GaN is provided on a buffer layer (or back barrier layer) containing AlN or AlGaN has a band structure in which conduction band energy on the buffer layer side of the channel layer is lifted by the buffer layer. When a band structure is formed in which the conduction band energy on the buffer layer side of the channel layer is greatly lifted, the distribution of electrons serving as carriers becomes narrower, the concentration thereof decreases, and the electron mobility of the channel layer may decrease. A decrease in the electron mobility of the channel layer can lead to a decrease in the performance of semiconductor devices including HEMTs, such as a decrease in output current and deterioration of high frequency characteristics.

In one aspect, the present invention aims to realize a high-performance semiconductor device including a channel layer exhibiting excellent electron mobility.

In one embodiment, a substrate containing AlN, and a first Al _x Ga _1-x N (0.15<x≦0.30 ); and a channel layer provided on a second surface side of the buffer layer opposite to the substrate side and containing GaN.

In another aspect, a method of manufacturing the semiconductor device as described above and an electronic device including the semiconductor device as described above are provided.

In one aspect, it becomes possible to realize a high-performance semiconductor device including a channel layer exhibiting excellent electron mobility.

FIG. 2 is a diagram illustrating an example of a semiconductor device. FIG. 2 is a diagram showing a first example of an energy band structure of a semiconductor device. 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment; FIG. FIG. 3 is a diagram showing a second example of an energy band structure of a semiconductor device. FIG. 3 is a diagram showing an example of the relationship between Al composition, polarization charge, spontaneous polarization, and piezo polarization. FIG. 3 is a diagram showing an example of the results of reciprocal lattice mapping performed on a nitride semiconductor stacked structure using X-ray diffraction. FIG. 3 is a diagram showing an example of the relationship between the Al composition of a buffer layer and the electron mobility of a channel layer. FIG. 3 is a diagram showing an example of the relationship between the thickness of a channel layer and electron mobility. FIG. 7 is a diagram illustrating an example of a semiconductor device according to a second embodiment. FIG. 7 is a diagram (part 1) illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment; FIG. 7 is a diagram (part 2) illustrating an example of the method for manufacturing a semiconductor device according to the second embodiment; FIG. 3 is a diagram (part 3) illustrating an example of the method for manufacturing a semiconductor device according to the second embodiment; FIG. 4 is a diagram (part 4) illustrating an example of the method for manufacturing a semiconductor device according to the second embodiment; FIG. 7 is a diagram illustrating an example of a semiconductor device according to a third embodiment. FIG. 7 is a diagram illustrating an example of a semiconductor device according to a fourth embodiment. FIG. 7 is a diagram illustrating an example of a semiconductor package according to a fifth embodiment. It is a figure explaining an example of the power factor improvement circuit concerning a 6th embodiment. It is a figure explaining an example of the power supply device concerning a 7th embodiment. It is a figure explaining an example of the amplifier concerning an 8th embodiment.

Semiconductor devices using nitride semiconductors are being developed as high-voltage, high-output devices by taking advantage of characteristics such as high saturated electron velocity and wide band gap. For example, GaN, which is a nitride semiconductor, has a band gap of 3.4 eV, which is larger than the band gap of Si (silicon), 1.1 eV, and the band gap of GaAs (gallium arsenide), 1.4 eV. It has a high dielectric breakdown electric field. Therefore, nitride semiconductors such as GaN are promising as materials for semiconductor devices that operate at high voltage and have high output, such as those applied to power supply devices, communication devices, radar devices, and the like.

As semiconductor devices using nitride semiconductors, there have been many reports on field effect transistors (FETs), such as HEMTs. As one type of HEMT, a HEMT using GaN as a channel layer and AlGaN as a barrier layer is known. In such a HEMT, two-dimensional electron gas (2DEG) is generated in GaN due to the spontaneous polarization of AlGaN and the piezo polarization that occurs in AlGaN due to the strain caused by the difference in lattice constant with GaN. Output is realized. In addition, in order to further increase the withstand voltage, a quantum well structure (also called a "quantum confinement structure"), in which GaN is sandwiched between AlN or AlGaN, and carrier confinement is strengthened by a relatively large band offset between GaN and AlN or AlGaN. ) has also been proposed.

FIG. 1 is a diagram illustrating an example of a semiconductor device. FIG. 1A schematically shows a cross-sectional view of a main part of a first example of a semiconductor device. FIG. 1B schematically shows a cross-sectional view of a main part of a second example of a semiconductor device.

A semiconductor device 100A shown in FIG. 1A is an example of a HEMT. The semiconductor device 100A includes a substrate 110A, a channel layer 130A, a barrier layer 140A, a gate electrode 150, a source electrode 160, and a drain electrode 170.

Various substrates such as AlN, Si, sapphire, SiC (silicon carbide), and GaN are used for the substrate 110A. A buffer layer made of a nitride semiconductor such as AlN may be provided on the surface layer of the substrate 110A on the side where the channel layer 130A is provided. A relatively thick channel layer 130A is provided on the substrate 110A. A nitride semiconductor such as GaN is used for the channel layer 130A. Barrier layer 140A is provided on channel layer 130A. A nitride semiconductor having a larger band gap than the nitride semiconductor of the channel layer 130A is used for the barrier layer 140A. When GaN is used for the channel layer 130A, a nitride semiconductor such as AlN or AlGaN is used for the barrier layer 140A. A channel layer 130A and a barrier layer 140A are sequentially stacked and grown on the substrate 110A using, for example, Metal Organic Chemical Vapor Deposition (MOCVD) or Metal Organic Vapor Phase Epitaxy (MOVPE), A nitride semiconductor stacked structure as shown in FIG. 1(A) is obtained.

In the semiconductor device 100A, the surface of the substrate 110A on which the channel layer 130A is stacked is the (0001) plane. The channel layer 130A is a layer laminated on the substrate 110A so that its thickness direction is in the [0001] direction, and the surface on which the barrier layer 140A is laminated is the (0001) plane, that is, group III polarity. This is the layer that forms the surface. The barrier layer 140A is a layer stacked on the channel layer 130A so that its thickness direction is in the [0001] direction, and the surface opposite to the channel layer 130A side is the (0001) plane, that is, the group III layer. This layer is a polar surface.

Predetermined metals are used for the gate electrode 150, source electrode 160, and drain electrode 170, respectively. Gate electrode 150 is provided to function as a Schottky electrode. The source electrode 160 and the drain electrode 170 are provided to function as ohmic electrodes.

The semiconductor device 100A has a heterojunction structure including a relatively thick channel layer 130A and a barrier layer 140A. Here, for convenience, such a semiconductor device 100A is also referred to as a "normal semiconductor device 100A." In the semiconductor device 100A, piezoelectric polarization occurs in the barrier layer 140A due to the spontaneous polarization of the barrier layer 140A and the strain caused by the difference in lattice constant with the channel layer 130A. , 2DEG101A are generated. When the semiconductor device 100A operates, a predetermined voltage is supplied between the source electrode 160 and the drain electrode 170, and a predetermined gate voltage is supplied to the gate electrode 150. An electron transport path is formed in the channel layer 130A between the source electrode 160 and the drain electrode 170, and the transistor function of the semiconductor device 100A is realized.

Further, a semiconductor device 100B shown in FIG. 1(B) is another example of a HEMT. The semiconductor device 100B includes a substrate 110B, a buffer layer 120B, a channel layer 130B, a barrier layer 140B, a gate electrode 150, a source electrode 160, and a drain electrode 170.

Various substrates such as AlN, Si, sapphire, SiC, and GaN are used for the substrate 110B. A relatively thin channel layer 130B is provided on the substrate 110B with a buffer layer 120B interposed therebetween. A barrier layer 140B is provided on the channel layer 130B. A nitride semiconductor such as GaN is used for the channel layer 130B. A nitride semiconductor having a larger band gap than the nitride semiconductor of the channel layer 130B is used for the buffer layer 120B and the barrier layer 140B that sandwich the channel layer 130B. When GaN is used for the channel layer 130B, a nitride semiconductor such as AlN or AlGaN is used for the buffer layer 120B and the barrier layer 140B. The buffer layer 120B provided under the channel layer 130B is also called a back barrier layer. A buffer layer 120B, a channel layer 130B, and a barrier layer 140B are sequentially stacked and grown on the substrate 110B using, for example, the MOVPE method to obtain a nitride semiconductor stacked structure as shown in FIG. 1(B).

In the semiconductor device 100B, the surface of the substrate 110B on which the buffer layer 120B is stacked is the (0001) plane. The buffer layer 120B is a layer laminated on the substrate 110B so that its thickness direction is in the [0001] direction, and the surface on which the channel layer 130B is laminated is the (0001) plane, that is, group III polarity. This is the layer that forms the surface. The channel layer 130B is a layer laminated on the buffer layer 120B so that its thickness direction is in the [0001] direction, and the surface on which the barrier layer 140B is laminated is the (0001) plane, that is, the group III layer. This layer is a polar surface. The barrier layer 140B is a layer stacked on the channel layer 130B so that its thickness direction is in the [0001] direction, and the surface opposite to the channel layer 130B side is the (0001) plane, that is, the group III This layer is a polar surface.

Predetermined metals are used for the gate electrode 150, source electrode 160, and drain electrode 170, respectively. Gate electrode 150 is provided to function as a Schottky electrode. The source electrode 160 and the drain electrode 170 are provided to function as ohmic electrodes.

The semiconductor device 100B has a quantum well structure in which a relatively thin channel layer 130B is sandwiched between a buffer layer 120B and a barrier layer 140B. In the semiconductor device 100B, piezoelectric polarization occurs in the barrier layer 140B due to the spontaneous polarization of the barrier layer 140B and the strain caused by the difference in lattice constant between the channel layer 130B and the channel layer 130B. , 2DEG101B are generated. During operation of the semiconductor device 100B, a predetermined voltage is supplied between the source electrode 160 and the drain electrode 170, and a predetermined gate voltage is supplied to the gate electrode 150. An electron transport path is formed in the channel layer 130B between the source electrode 160 and the drain electrode 170, and the transistor function of the semiconductor device 100B is realized.

In the semiconductor device 100B, the relatively large band offset between the channel layer 130B, the buffer layer 120B, and the barrier layer 140B strengthens the confinement of electrons, restricts electron diffusion to the deep part of the device, and prevents electrons from passing through the deep part of the device. The occurrence of leakage current can be suppressed. In the semiconductor device 100B, high breakdown voltage is achieved due to the strong confinement of electrons by the quantum well structure.

Here, FIG. 2 shows the energy band structure of a normal semiconductor device 100A (FIG. 1(A)) in which a quantum well structure is not adopted and a semiconductor device 100B (FIG. 1(B)) in which a quantum well structure is adopted. Explain with reference to.

FIG. 2 is a diagram showing a first example of an energy band structure of a semiconductor device.
FIG. 2 shows an example of the energy band structure (“HEMT _A ” in FIG. 2) of the normal semiconductor device 100A shown in FIG. 1(A) above, and a quantum well structure shown in FIG. 1(B) above. An example of the energy band structure (“HEMT _B ” in FIG. 2) of the semiconductor device 100B is shown.

Regarding the semiconductor device 100A (HEMT _A ), an example is taken in which GaN is used for the channel layer 130A and Al _m Ga _1-m N (0.00<m≦1.00) is used for the barrier layer 140A. Regarding the semiconductor device 100B (HEMT _B ), Al _n Ga _1-n N (0.00<n≦1.00) is used for the buffer layer 120B, GaN is used for the channel layer 130B, and Al _m Ga is used for the barrier layer 140B. The case where _1-m N (0.00<m≦1.00) is used is taken as an example.

In FIG. 2, the horizontal axis represents the depth z from the barrier layer 140A and barrier layer 140B side, and the vertical axis represents the conduction band energy _E.sub.C. In FIG. 2, E _F represents the Fermi level.

In a normal semiconductor device 100A (HEMT _A ), a barrier layer of Al _m Ga _1-m N (0.00<m≦1.00), which has a larger band gap than GaN, is formed on a relatively thick GaN channel layer 130A. 140A are stacked. On the other hand, in the semiconductor device 100B (HEMT _B ) having a quantum well structure, the relatively thin GaN channel layer 130B has Al _n Ga _1-n N (0.00<n≦1), which has a larger band gap than GaN. .00) and a barrier layer 140B of Al _m Ga _1-m N (0.00<m≦1.00).

In the semiconductor device 100B (HEMT _B ) having a quantum well structure, compared to the normal semiconductor device 100A (HEMT _A ), as shown in _{FIG .} 1.00), the conduction band energy E _C of GaN in the relatively thin channel layer 130B is raised. As a result, in the semiconductor device 100B (HEMT _B ) having a quantum well structure, the 2DEG 101B, which is generated when the conduction band energy E _C is lower than the Fermi level E _F , is not generated in the normal semiconductor device 100A (HEMT _A ). Compared to 2DEG101A, it is generated in a narrower area and its concentration is reduced.

In the normal semiconductor device 100A (HEMT _A ) and the semiconductor device 100B (HEMT _B ) having a quantum well structure, the electron mobility μ of the channel layer 130A and the channel layer 130B is mainly limited by phonon scattering at room temperature or higher. Phonon scattering is expressed by the following equation (1) with respect to the electron wave function F _i,m (z).

This indicates that the narrower the electron wave function F _i,m (z) is, the lower the electron mobility μ is.
In the semiconductor device 100B (HEMT _B ) having a quantum well structure, electrons are confined in a narrow region compared to the normal semiconductor device 100A (HEMT _A ), so the wave function thereof is also narrower. That is, as shown in FIG. 2, the wave function of the semiconductor device 100B (HEMT _B ) having a quantum well structure is narrower than the wave function of the normal semiconductor device 100A (HEMT _A ). The electron mobility of the semiconductor device 100B (HEMT _B ) having a quantum well structure is lower than that of the normal semiconductor device 100A (HEMT _A ), which is about 2000 cm ² /V·s, and is about 1000 cm ² /V.・There are cases where it becomes less than s. As a result, in the semiconductor device 100B (HEMT _B ) having a quantum well structure, the sheet resistance of GaN in the channel layer 130B increases compared to the channel layer 130A of the normal semiconductor device 100A (HEMT _A ), resulting in a large current. becomes difficult.

In this way, the semiconductor device 100B having the quantum well structure can have a higher breakdown voltage than the normal semiconductor device 100A, but the electron mobility of the channel layer 130B is lowered and its sheet resistance is increased. A decrease in electron mobility and an increase in sheet resistance of the channel layer 130B may lead to a decrease in performance of the semiconductor device 100B, such as a decrease in output current and deterioration of high frequency characteristics.

In view of the above points, a configuration as described below as an embodiment is adopted here to realize a high-performance semiconductor device including a channel layer exhibiting excellent electron mobility.
[First embodiment]
FIG. 3 is a diagram illustrating an example of the semiconductor device according to the first embodiment. FIG. 3 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.

The semiconductor device 1 shown in FIG. 3 is an example of a HEMT. The semiconductor device 1 includes a substrate 10, a buffer layer 20, a channel layer 30, a barrier layer 40, a gate electrode 50, a source electrode 60, and a drain electrode 70.

As the substrate 10, a substrate containing AlN is used. For example, the substrate 10 is an AlN substrate. Alternatively, the substrate 10 may be one in which a nucleation layer or a buffer layer of AlN is provided on the surface layer portion of the surface 10a side where the buffer layer 20 is provided, of various substrates such as AlN, Si, sapphire, SiC, and GaN. may be used. Here, the surface 10a of the substrate 10 is also referred to as a "first surface."

The buffer layer 20 is provided on the surface 10a side of the substrate 10. For the buffer layer 20, a layer containing a nitride semiconductor having a larger band gap than the nitride semiconductor used for the channel layer 30 is used. For the buffer layer 20, a layer containing AlGaN is used. The buffer layer 20 includes Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress. Here, Al _x Ga _1-x N (0.15<x≦0.30) having such an Al composition x is referred to as "first Al _x Ga _1-x N (0.15<x≦0. 30), and the compressive stress that Al _x Ga _1-x N (0.15<x≦0.30) has is also called the "first compressive stress."

The buffer layer 20 has, for example, a structure in which multiple layers of AlGaN are stacked. As an example, FIG. 3 shows a structure in which a first layer 21 and a second layer 22 of AlGaN are stacked. In the example of FIG. 3, the second layer 22 is provided on the surface 10a of the substrate 10, and the first layer 21 is provided on the second layer 22 (on the surface opposite to the substrate 10 side).

The first layer 21 of the buffer layer 20 is a layer containing Al _x Ga _1-x N (0.15<x≦0.30) having the above-mentioned compressive stress. The second layer 22 of the buffer layer 20 includes Al _y Ga _1-y N (x<y<1.00) having a higher Al composition y than the Al composition x of the first layer 21 and having compressive stress. It is a layer. Here, Al _y Ga _1-y N (x<y<1.00) having such an Al composition y is also referred to as "second Al _y Ga _1-y N (x<y<1.00)". The compressive stress that Al _y Ga _1-y N (x<y<1.00) has is also referred to as "second compressive stress." The second layer 22 is not limited to a single layer, and may have a structure in which multiple layers of AlGaN are stacked. Buffer layer 20 is also called a back barrier layer.

Note that details of the buffer layer 20 will be described later.
The channel layer 30 is provided on the surface 20a side of the buffer layer 20 opposite to the substrate 10 side. Here, the surface 20a of the buffer layer 20 is also referred to as a "second surface." The channel layer 30 is provided so as to be in contact with the surface 20a of the buffer layer 20, that is, the first layer 21. For the channel layer 30, a layer containing a nitride semiconductor having a smaller band gap than the nitride semiconductor used for the buffer layer 20 and the barrier layer 40 is used. For the channel layer 30, a layer containing GaN is used. The channel layer 30 is also called an electron transit layer.

The barrier layer 40 is provided on the side of the surface 30a of the channel layer 30 that is opposite to the side of the buffer layer 20. Here, the surface 30a of the channel layer 30 is also referred to as a "third surface." For the barrier layer 40, a layer containing a nitride semiconductor having a larger band gap than the nitride semiconductor used for the channel layer 30 is used. For the barrier layer 40, a layer containing Al _m Ga _1-m N (0.00<m≦1.00), that is, a layer containing AlN or AlGaN is used. Barrier layer 40 is also called an electron supply layer.

A buffer layer 20, a channel layer 30, and a barrier layer 40 are sequentially stacked and grown on the substrate 10 using, for example, the MOVPE method to obtain a nitride semiconductor stacked structure as shown in FIG. In the semiconductor device 1 , piezoelectric polarization occurs in the barrier layer 40 due to spontaneous polarization of the barrier layer 40 and strain caused by a difference in lattice constant between the channel layer 30 and the channel layer 30 . , 2DEG1a are generated.

In the semiconductor device 1, the surface 10a of the substrate 10 on which the buffer layer 20 is stacked is a (0001) plane, that is, a group III polar plane. The buffer layer 20 is a layer laminated on the substrate 10 so that its thickness direction is in the [0001] direction, and the surface 20a on which the channel layer 30 is laminated is the (0001) plane, that is, the group III This layer is a polar surface. The channel layer 30 is a layer laminated on the buffer layer 20 so that its thickness direction is in the [0001] direction, and the surface 30a on which the barrier layer 40 is laminated is the (0001) plane, that is, the III This is the layer that becomes the group polar plane. The barrier layer 40 is a layer stacked on the channel layer 30 so that its thickness direction is in the [0001] direction, and the surface 40a on the opposite side from the channel layer 30 side is the (0001) plane, that is, the III This is the layer that becomes the group polar plane.

Predetermined metals are used for the gate electrode 50, source electrode 60, and drain electrode 70, respectively. Gate electrode 50 is provided to function as a Schottky electrode. The source electrode 60 and the drain electrode 70 are provided to function as ohmic electrodes.

During operation of the semiconductor device 1, a predetermined voltage is supplied between the source electrode 60 and the drain electrode 70, and a predetermined gate voltage is supplied to the gate electrode 50. An electron transport path is formed in the channel layer 30 between the source electrode 60 and the drain electrode 70, and the transistor function of the semiconductor device 1 is realized. The semiconductor device 1 has a quantum well structure in which a channel layer 30 is sandwiched between a buffer layer 20 and a barrier layer 40. In the semiconductor device 1, the relatively large band offset between the channel layer 30, the buffer layer 20, and the barrier layer 40 strengthens the confinement of electrons, restricts electron diffusion to the deep part of the device, and prevents electrons from passing through the deep part of the device. The occurrence of leakage current can be suppressed. The semiconductor device 1 achieves high breakdown voltage due to the strong confinement of electrons by its quantum well structure.

Here, the energy band structure of the semiconductor device 1 having the quantum well structure as described above will be explained with reference to FIG. 4.
FIG. 4 is a diagram showing a second example of the energy band structure of a semiconductor device.

FIG. 4 shows an example of the energy band structure ("HEMT _C " in FIG. 4) of the semiconductor device 1 having the quantum well structure shown in FIG. 3 above. FIG. 4 further shows an example of the energy band structure (“HEMT _A ” in FIG. 4) of the normal semiconductor device 100A shown in FIG. 1(A) above, and the quantum well structure shown in FIG. 1(B) above. An example of the energy band structure of the semiconductor device 100B (“HEMT _B ” in FIG. 4) is also shown.

Regarding the semiconductor device 1 (HEMT _C ), the buffer layer 20 is made of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress, the channel layer 30 is made of GaN, and the barrier layer 40 is made of Al x Ga 1-x N (0.15<x≦0.30). The case where Al _m Ga _1-m N (0.00<m≦1.00) is used is taken as an example. Regarding the semiconductor device 100A (HEMT _A ), an example is taken in which GaN is used for the channel layer 130A and Al _m Ga _1-m N (0.00<m≦1.00) is used for the barrier layer 140A. Regarding the semiconductor device 100B (HEMT _B ), Al _n Ga _1-n N (0.00<n≦1.00) is used for the buffer layer 120B, GaN is used for the channel layer 130B, and Al _m Ga is used for the barrier layer 140B. The case where _1-m N (0.00<m≦1.00) is used is taken as an example.

In FIG. 4, the horizontal axis represents the depth z from the side of the barrier layer 40 and the barrier layers 140A and 140B, and the vertical axis represents the conduction band energy _E.sub.C. In FIG. 4, E _F represents the Fermi level.

In the semiconductor device 100B (HEMT _B ) having a quantum well structure, compared to the normal semiconductor device _100A (HEMT _A ), the _channel is The conduction band energy E _C of GaN in layer 130B is raised. As a result, in the semiconductor device 100B (HEMT _B ) having a quantum well structure, electrons are confined in a narrower region than in the normal semiconductor device 100A (HEMT _A ). Therefore, the wave function of the semiconductor device 100B (HEMT _B ) having a quantum well structure is narrower than the wave function of the normal semiconductor device 100A (HEMT _A ). The semiconductor device 100B (HEMT _B ) having a quantum well structure is advantageous in increasing the breakdown voltage, but has lower electron mobility than the normal semiconductor device 100A (HEMT _A ).

In the semiconductor device 100B (HEMT _B ) having a quantum well structure, when AlN (n=1.00) is used as the buffer layer 120B, the Group III polarity plane (Al plane) has negative polarization due to strong spontaneous polarization. A polarized charge is generated. In addition, when AlGaN (0.00<n<1.00), which has a larger lattice constant (theoretical value) than AlN, is used as the buffer layer 120B, the lattice constant of AlGaN Due to this difference, dislocations can grow while being introduced and the lattice can be relaxed. AlGaN can grow while introducing dislocations and undergo lattice relaxation if the amount of change in free energy that introduces crystal defects has a higher gain than the force that tries to grow with the same lattice constant as the underlying AlN. . Negative polarization charges are generated by relatively strong spontaneous polarization on the Group III polar plane of AlGaN which has been lattice relaxed and grown with a lattice constant of the theoretical value or a lattice constant equivalent thereto. Due to the negative polarization charge generated on the Group III polar plane of AlN or AlGaN of the buffer layer 120B, the conduction band energy E _C of GaN of the channel layer 130B grown thereon is raised. As a result, in the semiconductor device 100B (HEMT _B ), the electron distribution becomes narrower, the wave function becomes narrower, and the electron mobility decreases.

That is, in the semiconductor device 100B (HEMT _B ), if the polarization charge on the group III polarity plane of the buffer layer 120B can be made zero or positive instead of negative, the conduction band energy of the channel layer 130B grown thereon will be reduced. It is possible to suppress the rise of _EC . If the polarization charge on the Group III polar plane of the buffer layer 120B can be set to 0 or positive, the channel layer 130B has a conduction band energy E _C on the buffer layer 120B side that is lower than or close to the Fermi level E _F. , the distribution of electrons widens and the wave function widens. This makes it possible to increase electron mobility even with a quantum well structure.

In view of these points, in the semiconductor device 1 having a quantum well structure (HEMT _C ), it is considered to generate zero or positive polarization charges on the group III polarity plane of the buffer layer 20 on which the channel layer 30 is grown. In the semiconductor device 1 having a quantum well structure (HEMT _C ), in order to generate 0 or positive polarization charges on the Group III polarity plane of the buffer layer 20, compressive stress is applied to the buffer layer 20 so that the buffer layer 20 What is necessary is just to make it have compressive stress. Therefore, in the semiconductor device 1 (HEMT _C ) having a quantum well structure, Al _x Ga _1-x N(0 .15<x≦0.30) is used.

Note that the Al composition, polarization charge, and compressive stress of AlGaN used for the buffer layer 20 will be described later.
In the semiconductor device 1 (HEMT _C ), the first layer 21 of the buffer layer 20 is made of Al _x Ga _1-x N (0.0. 15<x≦0.30), and the polarization charge of the group III polar plane is 0 or positive. As a result, as shown in FIG. 4, the lift of the conduction band energy E _C of GaN in the channel layer 30 on the Al _x Ga _1-x N (0.15<x≦0.30) side of the buffer layer 20 is suppressed. It will be done. In FIG. 4, the rise in the conduction band energy E C of GaN in the channel layer 30 _in the semiconductor device 1 (HEMT _C ) is shown as the rise in the conduction band energy E _C in GaN in the channel layer 130B in the semiconductor device 100B (HEMT _B ). The thick arrow indicates that it is suppressed rather than lifted. By suppressing the rise in the conduction band energy E _C of GaN of the channel layer 30 in the semiconductor device 1 (HEMT _C ), the conduction band energy E _C of the GaN of the channel layer 30 on the AlGaN side of the buffer layer 20 reaches the Fermi level. level _EF is below or close to it. As a result, the distribution of electrons in GaN of the channel layer 30 is widened, so that the wave function is widened. The wave function of the semiconductor device 1 (HEMT _C ) is wider than the wave function of the semiconductor device 100B (HEMT _B ) having a quantum well structure, and can also be wider than the wave function of the normal semiconductor device 100A (HEMT _A ).

Semiconductor device _{1 (} According to HEMT _C ), the quantum well structure improves the breakdown voltage and improves the electron mobility of the channel layer 30. As a result, a high-performance semiconductor device 1 is realized.

Here, the Al composition, polarization charge, and compressive stress of AlGaN used for the buffer layer 20 will be explained.
The change in polarization charge (piezo polarization) _P of AlGaN due to stress is expressed by the following equation (2) using the Al composition x, stress s, and stress tensor E.

Using this equation (2), the polarization charge of the group III polar plane when AlGaN is subjected to the strongest compressive stress, that is, when it has the same lattice constant as AlN, is calculated and shown in Figure 5. show.

FIG. 5 is a diagram showing an example of the relationship between Al composition, polarization charge, spontaneous polarization, and piezo polarization.
In FIG. 5, the horizontal axis represents the Al composition x[-]. In FIG. 5, the left vertical axis represents polarization charge [cm ⁻² ], and the right vertical axis represents spontaneous polarization [C/m ² ] and piezo polarization [C/m ² ].

As shown in Figure 5, when AlGaN has the same lattice constant as AlN, its spontaneous polarization and piezo polarization change as the Al composition x changes, and as the Al composition x decreases, the polarization charge (total polarization electric charge) shows a tendency to increase. From FIG. 5, it can be seen that the polarization charge of AlGaN becomes 0 or positive when the lattice constant is the same as that of AlN when its Al composition x is 0.30 or less (region AR in FIG. 5). .

On the other hand, when AlGaN with an Al composition x of 0.30 or less is grown on AlN, if the Al composition x of AlGaN is 0.15 or less, the difference in composition and lattice constant (theoretical value) from AlN is large; Due to the large lattice mismatch, lattice relaxation occurs. That is, in the case of AlGaN with an Al composition x of 0.15 or less, the amount of change in free energy that introduces crystal defects has a higher gain than the force that tries to grow with the same lattice constant as the underlying AlN. It grows while introducing dislocations, resulting in lattice relaxation. When AlGaN with an Al composition x of 0.15 or less is grown on a layer grown on AlN with the same lattice constant as the base layer, lattice relaxation similarly occurs due to the large lattice mismatch between them. can occur. As a result, in AlGaN with an Al composition x of 0.15 or less, it becomes difficult to adjust the lattice constant and polarization charge on AlN.

Therefore, when grown on AlN or on a layer grown with a lattice constant equivalent to that of AlN, in order to suppress lattice relaxation and apply compressive stress to make the polarization charge 0 or positive, it is necessary to It is desirable to set the Al composition x in a range of more than 0.15 and less than 0.30. In addition, when the lattice constant of AlGaN exceeds that of AlN (when it has compressive stress but its value decreases), the piezo polarization and polarization charge of AlGaN are lower than when the lattice constant is the same as AlN, and the The Al composition x at which the polarization charge becomes 0 or positive is in the range of 0.30 or less.

Based on such knowledge, the buffer layer 20 provided between the substrate 10 containing AlN and the channel layer 30 containing GaN of the semiconductor device 1 (HEMT _C ) has a compressive stress as the first layer 21. Al _x Ga _1-x N (0.15<x≦0.30) is used. GaN of the channel layer 30 is provided on the first layer 21 of the buffer layer 20 of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress. The lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is greater than or equal to the lattice constant of AlN contained in the substrate 10. Furthermore, the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress corresponds to the Al _x Ga _1-x N (0.15<x≦0.30). The lattice constant is smaller than the theoretical value of Al _x Ga _1-x N having the Al composition x. Here, the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress may match the lattice constant of AlN included in the substrate 10.

In the semiconductor device 1 (HEMT _C ), the first layer 21 of the buffer layer 20 provided on AlN of the substrate 10 is Al _x Ga _1-x N(0 .15<x≦0.30) is used. As a result, the polarization charge of the buffer layer 20 on the Group III polar surface (surface 20a) of the first layer 21, that is, the polarization charge at the junction interface with GaN of the channel layer 30, is adjusted to be 0 or positive. be done. When the polarization charge on the Group III polarity plane of the first layer 21 of the buffer layer 20 is set to 0 or positive, the conduction band energy E _C of the channel layer 30 provided on the first layer 21 increases. (Figure 4). In the channel layer 30, the conduction band energy E _C on the side of the buffer layer 20 is lower than or close to the Fermi level E _F , and the electron distribution is widened and the wave function is widened. As a result, the electron mobility of the channel layer 30 is improved. In the semiconductor device 1 (HEMT _C ), by improving the electron mobility of the channel layer 30, a decrease in output current, deterioration of high frequency characteristics, etc. can be suppressed. A high-performance semiconductor device 1 (HEMT _C ) including a channel layer 30 exhibiting excellent electron mobility is realized.

When Al _x Ga _1-x N with an Al composition x of 0.15<x≦0.30 is grown directly on AlN of the substrate 10, the difference in composition and lattice constant (theoretical value) from AlN is relatively small. Because of the large size, lattice relaxation may occur and compressive stress may not be applied and no compressive stress may be developed. Therefore, in _the semiconductor device ₁ , as shown in FIG. A buffer layer 20 is provided having a second layer 22 comprising Al _y Ga _1-y N (x<y<1.00). The second layer 22 may have a structure in which multiple layers of AlGaN are stacked.

In manufacturing the semiconductor device 1, first, a second layer 22 containing Al _y Ga _1-y N (x<y<1.00) with a relatively high Al composition y is grown on AlN of the substrate 10; A first layer 21 comprising Al _x Ga _1-x N (0.15<x≦0.30) with a relatively low Al composition x is grown thereon. In the growth of the second layer 22 and the subsequent growth of the first layer 21, if the theoretical values of the lattice constants are relatively close and the thickness is thin, the crystal tends to grow with the same lattice constant as the underlying material. properties are used. In the growth of the second layer 22 and the subsequent growth of the first layer 21, the respective thicknesses as well as the respective Al compositions y and Al compositions x are adjusted as appropriate.

Between the AlN of the substrate 10 and the first layer 21, which has a relatively low Al composition x and a relatively large difference in theoretical values in composition and lattice constant from AlN, A second layer 22 is provided in which the difference in theoretical values of constants is relatively small. Since the theoretical values of composition and lattice constant of AlN on the substrate 10 and the second layer 22 grown thereon are relatively close to each other, the second layer 22 grown on the AlN of the substrate 10 has , the occurrence of lattice relaxation can be suppressed. The second layer 22 and the first layer 21 grown on it have relatively similar compositions and theoretical values of lattice constants, so the first layer 21 grown on the second layer 22 This suppresses the occurrence of lattice relaxation.

The second layer 22 containing Al _y Ga _1-y N (x<y<1.00) with a relatively high Al composition y is grown in an attempt to lattice match with AlN of the substrate 10 while suppressing lattice relaxation. It is grown while compressive stress is applied. As a result, Al _y Ga _1-y N (x<y<1.00) having compressive stress is formed as the second layer 22 . The lattice constant of Al _y Ga _1-y N (x<y<1.00) having compressive stress in the second layer 22 is greater than or equal to the lattice constant of AlN in the substrate 10 . Furthermore, the lattice constant of _{Al y} Ga _{1 -y} N (x<y<1.00) having compressive stress of the second layer 22 is is smaller than the theoretical value of the lattice constant of Al _y Ga _1-y N having an Al composition y corresponding to . Here, the lattice constant of the compressive stressed Al _y Ga _1-y N (x<y<1.00) of the second layer 22 may match the lattice constant of AlN of the substrate 10 .

On the second layer 22 containing Al _y Ga _1-y N (x<y<1.00) having such a lattice constant and compressive stress, Al _x Ga ₁ with a relatively low Al composition x is deposited. A first layer 21 containing _-x N (0.15<x≦0.30) is grown. The first layer 21 is grown while trying to lattice match the Al _y Ga _1-y N (x<y<1.00) of the second layer 22 while suppressing lattice relaxation, and is grown while applying compressive stress. be done. As a result, Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is formed as the first layer 21 . The lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) with compressive stress in the first layer 21 is the same as that of Al _y Ga _1-y N with compressive stress in the second layer 22 The lattice constant is greater than or equal to (x<y<1.00). Furthermore, the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress of the first layer 21 is the same as that of Al _x Ga _1-x N (0.15<x≦ 0.30), which is smaller than the theoretical value of the lattice constant of Al _x Ga _1-x N having an Al composition x corresponding to 0.30). Here, the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress of the first layer 21 may match the lattice constant of AlN of the substrate 10 . The lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) with compressive stress in the first layer 21 is the same as that of Al _y Ga _1-y N with compressive stress in the second layer 22 It can match the lattice constant of (x<y<1.00).

Note that the following can be said about Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress in the first layer 21. That is, the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress of the first layer 21 is greater than the lattice constant of AlN of the substrate 10 . Furthermore, the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress of the first layer 21 is the same as that of Al _x Ga _1-x N (0.15<x≦ 0.30), which is smaller than the theoretical value of the lattice constant of Al _x Ga _1-x N having an Al composition x corresponding to 0.30).

Further, regarding the Al _y Ga _1-y N (x<y<1.00) having compressive stress of the second layer 22, the following can be said. That is, the lattice constant of Al _y Ga _1-y N (x<y<1.00) having compressive stress in the second layer 22 is greater than or equal to the lattice constant of AlN in the substrate 10 and The lattice constant is equal to or less than the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) which has compressive stress. Furthermore, the lattice constant of _{Al y} Ga _{1 -y} N (x<y<1.00) having compressive stress of the second layer 22 is is smaller than the theoretical value of the lattice constant of Al _y Ga _1-y N having an Al composition y corresponding to .

As described above, in the semiconductor device 1, Al _y Ga _1-y N(x <y<1.00) is grown. In addition, the first layer contains Al _x Ga _1-x N (0.15<x≦0.30), which has a relatively low Al composition x and a relatively large theoretical difference in composition and lattice constant from AlN. A layer 21 of is grown. This suppresses the occurrence of lattice relaxation in Al _y Ga _1-y N (x<y<1.00) of the second layer 22 grown on the AlN of the substrate 10, and This suppresses the occurrence of lattice relaxation in the Al _x Ga _1-x N (0.15<x≦0.30) of the first layer 21 that is grown. As a result, Al _x Ga ₁ with compressive stress is formed on _the AlN of the substrate 10 via the second layer 22 containing Al y Ga _1-y N (x<y<1.00) with compressive stress. A first layer 21 containing _-x N (0.15<x≦0.30) is grown. The first layer 21 is formed so that the first layer 21 has compressive stress and the polarization charge on the side 20a on which the channel layer 30 is grown is 0 or positive, and the buffer layer 20 including the first layer 21 is formed.

A channel layer 30 is provided on the first layer 21 of such a buffer layer 20. The zero or positive polarization charge of the first layer 21 suppresses the rise of the conduction band energy E _C of the channel layer 30, broadens the electron distribution, broadens the wave function, and improves the electron mobility of the channel layer 30. be done.

FIG. 6 is a diagram showing an example of the results of reciprocal lattice mapping performed using X-ray diffraction on a nitride semiconductor stacked structure.
In FIG. 6, the _horizontal axis represents the reciprocal lattice space coordinates _q represents.

In FIG. 6, Al 0.2 with an Al composition x of 0.20 is deposited on AlN of the substrate 10 via a second layer 22 containing Al _y Ga _1-y N (x<y<1.00) _. The results of a nitride semiconductor stacked structure in which a first layer 21 containing ₂₀ Ga _0.80 N is grown and GaN of a channel layer 30 is grown thereon are shown. Reciprocal lattice mapping is performed on such a nitride semiconductor stacked structure using X-ray diffraction.

The qX _- axis direction of the reciprocal lattice map indicates the lateral lattice constant of the crystal. In FIG. 6, the theoretical value of the lattice constant of AlN of the substrate 10 is shown by a chain line. In FIG. 6, the theoretical value of the lattice constant of Al _0.20 Ga _0.80 N of the buffer layer 20 is shown by a dotted line. In FIG. 6, the theoretical value of the lattice constant of GaN of the channel layer 30 is shown by a chain line.

From FIG. 6, the peak value indicating the lattice constant of AlN of the substrate 10 is equivalent to the theoretical value of the lattice constant of AlN. The peak value indicating the lattice constant of Al _0.20 Ga _0.80 N of the buffer layer 20 is equivalent to the lattice constant (peak value and theoretical value) of AlN of the substrate 10, and the Al It is smaller than the theoretical value of the lattice constant of _0.20 Ga _0.80 N. From this, it can be seen that Al _0.20 Ga _0.80 N of the buffer layer 20 has a lattice constant smaller than its theoretical value and equivalent to that of AlN of the substrate 10, and is in a state where compressive stress is applied, that is, , it can be seen that the film is grown on AlN of the substrate 10 with compressive stress.

Moreover, from FIG. 6, the peak value indicating the lattice constant of GaN of the channel layer 30 is equivalent to the theoretical value of the lattice constant of GaN. From this, it can be seen that the GaN of the channel layer 30 is grown on the buffer layer 20 without stress caused by the underlying buffer layer 20.

Further, FIG. 7 is a diagram showing an example of the relationship between the Al composition of the buffer layer and the electron mobility of the channel layer.
In FIG. 7, the horizontal axis represents the Al composition x[-] of the first layer 21 in the buffer layer 20, and the vertical axis represents the electron mobility [cm ² /V·s] of the channel layer 30.

From FIG. 7, when the Al composition x of Al _x Ga _1-x N used for the first layer 21 of the buffer layer 20 is 0.15 and 1.00 (that is, AlN), The electron mobility of the channel layer 30 is lower than when the value is 0.30 and when the value is 0.30.

When the Al composition x of Al _x Ga _1-x N is 0.15, the actual lattice constant (< The difference from the theoretical value) becomes relatively large, the lattice mismatch becomes large, and lattice relaxation tends to occur. As a result, sufficient compressive stress cannot be obtained, and zero or positive polarization charges cannot be obtained. Therefore, when the Al composition x of Al _x Ga _1-x N is set to 0.15, the conduction band energy E _C of the channel layer 30 increases and its electron mobility decreases. Furthermore, when the Al composition x of Al _x Ga _1-x N is set to 1.00, that is, when AlN is used, a strong negative polarization charge is generated at the junction interface with the channel layer 30, so that the channel layer The conduction band energy E _C of 30 is raised and its electron mobility becomes lower.

Based on this knowledge, the buffer layer 20 has compressive stress as the first layer 21 on the surface 20a side where the channel layer 30 is provided, and the Al composition x is 0.15<x≦0. A range of 30 Al _x Ga _1-x N is used.

Moreover, FIG. 8 is a diagram showing an example of the relationship between the thickness of the channel layer and the electron mobility.
In FIG. 8, the horizontal axis represents the thickness [nm] of the channel layer 30, and the vertical axis represents the electron mobility [cm ² /V·s] of the channel layer 30. Note that the thickness of the channel layer 30 is the thickness in the direction perpendicular to the surface 20a of the buffer layer 20, that is, the thickness in the [0001] direction.

From FIG. 8, it can be seen that when the thickness of the channel layer 30 is 100 nm or less, the electron mobility tends to increase as the thickness increases. On the other hand, when the thickness of the channel layer 30 exceeds 100 nm, no significant increase in electron mobility is observed even if the thickness increases. This is because when the thickness of the channel layer 30 exceeds 100 nm, the energy band structure of the 2DEG1a region cannot be changed even if the polarization charges on the underlying buffer layer 20 side are adjusted. That is, even if the buffer layer 20 is provided, if the thickness of the channel layer 30 exceeds 100 nm, the semiconductor device 100B becomes equivalent to a normal semiconductor device 100B that does not employ a quantum well structure.

Therefore, the method of adjusting the polarization charge of the buffer layer 20 as described above, that is, the method of using Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress in the buffer layer 20, It is not necessary to apply this method to a channel layer 30 having a thickness that does not form a quantum well structure. The method of adjusting the polarization charge of the buffer layer 20 as described above is applied to the channel layer 30 having a thickness such that it has a quantum well structure, so that higher electron mobility can be achieved than when it is not applied. This is effective for realizing the channel layer 30 shown in FIG. In the semiconductor device 1 in which the method of adjusting the polarization charge of the buffer layer 20 as described above is employed, the thickness of the channel layer 30 is desirably set to 100 nm or less.

[Second embodiment]
FIG. 9 is a diagram illustrating an example of a semiconductor device according to the second embodiment. FIG. 9 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.

A semiconductor device 1A shown in FIG. 9 is an example of a HEMT. The semiconductor device 1A includes a substrate 10A, a buffer layer 20A, a channel layer 30A, a barrier layer 40A, a cap layer 80A, a passivation film 90A, a gate electrode 50A, a source electrode 60A, and a drain electrode 70A.

A substrate containing AlN is used as the substrate 10A. The substrate 10A includes a base substrate 11A and a nucleation layer 12A. For example, an AlN substrate is used as the base substrate 11A. Various substrates such as Si, sapphire, SiC, GaN, etc. may be used for the base substrate 11A. Nucleation layer 12A is laminated on base substrate 11A. The nucleation layer 12A is formed using, for example, the MOVPE method. For example, AlN is used for the nucleation layer 12A. A buffer layer 20A and the like are provided on the nucleation layer 12A side of the substrate 10A.

The buffer layer 20A is provided on the surface 10Aa (also referred to as "first surface") on the nucleation layer 12A side of the substrate 10A, which has the base substrate 11A and the nucleation layer 12A laminated thereon. A layer containing AlGaN is used for the buffer layer 20A. The buffer layer 20A includes Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress. The buffer layer 20A has a structure in which multiple layers of AlGaN are stacked. As an example, FIG. 9 shows a structure in which a first layer 21A, a second layer 22A, and a third layer 23A of AlGaN are stacked. In the example of FIG. 9, a third layer 23A is provided on the surface 10Aa of the substrate 10A, a second layer 22A is provided on the third layer 23A (on the surface opposite to the substrate 10A side), The first layer 21A is provided on the second layer 22A (on the surface opposite to the third layer 23A side).

The first layer 21A of the buffer layer 20A is made of Al _x Ga _1-x N (0.15<x≦0.30) having the above compressive stress (also referred to as "first compressive stress"). This is a layer containing "first Al _x Ga _1-x N"). The second layer 22A of the buffer layer 20A is made of Al _y Ga _1-y N (0.30<y≦0.80) (also called “second Al _y Ga _1-y N). The third layer 23A of the buffer layer 20A is made of Al _z Ga _1-z N (0.80<z<1.00) (also called "third Al _z Ga _1-z N).

The channel layer 30A is provided on the surface 20Aa (also referred to as "second surface") of the buffer layer 20A, which is opposite to the substrate 10A side. A layer containing GaN is used for the channel layer 30A.

The barrier layer 40A is provided on the surface 30Aa (also referred to as the "third surface") side of the channel layer 30A, which is opposite to the buffer layer 20A side. A layer containing Al _m Ga _1-m N (0.50≦m≦1.00), that is, a layer containing AlN or AlGaN is used for the barrier layer 40A.

The cap layer 80A is provided on the surface 40Aa side of the barrier layer 40A opposite to the channel layer 30A side. A layer containing GaN is used for the cap layer 80A.
A buffer layer 20A, a channel layer 30A, a barrier layer 40A, and a cap layer 80A are sequentially stacked and grown on the substrate 10A (the nucleation layer 12A stacked on the underlying substrate 11A) using, for example, the MOVPE method, A nitride semiconductor stacked structure as shown in FIG. 9 is obtained. In the semiconductor device 1A, piezoelectric polarization occurs in the barrier layer 40A due to the spontaneous polarization of the barrier layer 40A and the strain caused by the difference in lattice constant with the channel layer 30A. , 2DEG1Aa are generated.

In the semiconductor device 1A, the surface 10Aa of the substrate 10A on which the buffer layer 20A is stacked is a (0001) plane, that is, a group III polar plane. The buffer layer 20A is a layer laminated on the substrate 10A so that its thickness direction is in the [0001] direction, and the surface 20Aa on the side where the channel layer 30A is laminated is the (0001) plane, that is, the group III This layer is a polar surface. The channel layer 30A is a layer laminated on the buffer layer 20A so that its thickness direction is in the [0001] direction, and the surface 30Aa on which the barrier layer 40A is laminated is the (0001) plane, that is, III This is the layer that becomes the group polar plane. The barrier layer 40A is a layer stacked on the channel layer 30A so that its thickness direction is in the [0001] direction, and the surface 40Aa on the opposite side from the channel layer 30A side is the (0001) plane, that is, III This is the layer that becomes the group polar plane. The cap layer 80A is a layer laminated on the barrier layer 40A so that its thickness direction is in the [0001] direction, and the surface 80Aa on the opposite side from the barrier layer 40A side is the (0001) plane, that is, III This is the layer that becomes the group polar plane.

Predetermined metals are used for the gate electrode 50A, the source electrode 60A, and the drain electrode 70A, respectively. The gate electrode 50A is provided to function as a Schottky electrode. Gate electrode 50A is provided on cap layer 80A. The source electrode 60A and the drain electrode 70A are provided to function as ohmic electrodes. The source electrode 60A and the drain electrode 70A penetrate the cap layer 80A and the barrier layer 40A and are connected to the channel layer 30A (for example, its 2DEG1Aa).

The passivation film 90A is provided to cover the cap layer 80A, the source electrode 60A, and the drain electrode 70A. The passivation film 90A is provided with an opening 91A that communicates with the cap layer 80A. The gate electrode 50A is provided on the cap layer 80A in the opening 91A of the passivation film 90A. The passivation film 90A contains oxides, nitrides, and oxides containing at least one of Si, Al (aluminum), Hf (hafnium), Zr (zirconium), Ti (titanium), Ta (tantalum), and W (tungsten). Various insulating materials such as nitrides are used. For example, SiN (silicon nitride) is used for the passivation film 90A.

During operation of the semiconductor device 1A, a predetermined voltage is supplied between the source electrode 60A and the drain electrode 70A, and a predetermined gate voltage is supplied to the gate electrode 50A. An electron transport path is formed in the channel layer 30A between the source electrode 60A and the drain electrode 70A, and the transistor function of the semiconductor device 1A is realized. The semiconductor device 1A has a quantum well structure in which a channel layer 30A is sandwiched between a buffer layer 20A and a barrier layer 40A. In the semiconductor device 1A, the relatively large band offset between the channel layer 30A, the buffer layer 20A, and the barrier layer 40A strengthens the confinement of electrons, restricts electron diffusion to the deep part of the device, and prevents electrons from passing through the deep part of the device. The occurrence of leakage current can be suppressed. In the semiconductor device 1A, high breakdown voltage is achieved due to strong confinement of electrons by its quantum well structure.

In the semiconductor device 1A, a third layer 23A, a second layer 22A, and a first layer 21A of AlGaN are sequentially stacked as a buffer layer 20A on a substrate 10A containing AlN. The Al composition of AlGaN in the third layer 23A is set to a higher value than the Al composition of AlGaN in the second layer 22A. The Al composition of AlGaN in the second layer 22A is set to a higher value than the Al composition of AlGaN in the first layer 21A. The Al composition of AlGaN in the first layer 21A is set in a range of more than 0.15 and less than 0.30.

The third layer 23A is grown while applying compressive stress to achieve lattice matching with AlN of the underlying substrate 10A. As a result, a third layer 23A having compressive stress is formed. The second layer 22A is grown while applying compressive stress to achieve lattice matching with the underlying third layer 23A. As a result, a second layer 22A having compressive stress is formed. The first layer 21A is grown while applying compressive stress to achieve lattice matching with the underlying second layer 22A. As a result, a first layer 21A having compressive stress is formed.

The first layer 21A of the buffer layer 20A, that is, Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress, is provided at the bonding interface between the buffer layer 20A and the channel layer 30A. It will be done. The first layer 21A is provided so that the polarization charge on the surface 20Aa (group III polarity surface) on the side of the channel layer 30A is 0 or positive. As a result, the conduction band energy E _C of the channel layer 30A on the buffer layer 20A side is suppressed from rising, the electron distribution and wave function are widened, and the electron mobility of the channel layer 30A is improved. A high-performance semiconductor device 1A including a channel layer 30A exhibiting excellent electron mobility is realized.

Next, a method for manufacturing the semiconductor device 1A having the above configuration will be described with reference to the following FIGS. 10 to 13 and the above FIG. 9.
10 to 13 are diagrams illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. 10(A), FIG. 10(B), FIG. 11(A), FIG. 11(B), FIG. 12(A), FIG. 12(B), FIG. 13(A) and FIG. 13(B), respectively. , which schematically shows a cross-sectional view of a main part of each process of manufacturing a semiconductor device. Each step will be explained in order below.

FIG. 10A schematically shows a cross-sectional view of a main part of an example of the substrate preparation process.
First, a substrate 10A as shown in FIG. 10(A), that is, a substrate 10A having a base substrate 11A and a nucleation layer 12A laminated thereon is prepared. For example, an AlN free-standing substrate is used as the base substrate 11A. A nucleation layer 12A is formed on the base substrate 11A using, for example, the MOVPE method. For example, AlN with a thickness of 100 nm is formed as the nucleation layer 12A. The nucleation layer 12A is grown on the (0001) plane of the base substrate 11A, that is, the group III polar plane, so that the thickness direction is in the [0001] direction. The surface 10Aa of the nucleation layer 12A on the side opposite to the base substrate 11A is a (0001) plane, that is, a group III polar plane.

FIG. 10(B) schematically shows a cross-sectional view of a main part of an example of the buffer layer forming process.
After preparing the substrate 10A, as shown in FIG. 10(B), a buffer layer 20A is formed on the surface 10Aa of the substrate 10A on the nucleation layer 12A side. The buffer layer 20A is formed using, for example, the MOVPE method. In this example, a stacked structure of three layers of AlGaN is formed as the buffer layer 20A, including a first layer 21A, a second layer 22A, and a third layer 23A in order from the top. For example, Al _x Ga _1-x N (0.15<x≦0.30) with a thickness of 10 nm is formed as the first layer 21A. As the second layer 22A, for example, Al _y Ga _1-y N (0.30<y≦0.80) with a thickness of 50 nm is formed. For example, Al _z Ga _1-z N (0.80<z<1.00) with a thickness of 10 nm is formed as the third layer 23A.

A third layer 23A is first formed on the surface 10Aa of the substrate 10A, a second layer 22A is formed thereon, and a first layer 21A is formed thereon. In the growth of the third layer 23A, the growth of the second layer 22A, and the growth of the first layer 21A, if the theoretical values of the lattice constants are relatively close and the thickness is thin, the crystal has the same lattice constant as the underlying material. The nature of trying to grow is exploited. In the growth of the third layer 23A, the growth of the second layer 22A, and the growth of the first layer 21A, the respective thicknesses as well as the respective Al composition z, Al composition y, and Al composition x are adjusted as appropriate. Ru.

Between the AlN of the substrate 10A and the first layer 21A, which has a relatively low Al composition x and a relatively large difference in theoretical values of composition and lattice constant, an AlN layer 21A having a relatively high Al composition y and a relatively high Al composition z is provided. A second layer 22A and a third layer 23A having a relatively small difference between the theoretical values of composition and lattice constant are provided. A third layer 23A with an Al composition z is provided on the AlN of the substrate 10A, a second layer 22A with an Al composition y lower than the Al composition z is provided on the third layer 23A, and a second layer 22A with an Al composition y lower than the Al composition z is provided on the third layer 23A. A first layer 21A having an Al composition x lower than the Al composition y is provided on the layer 22A. The AlN on the substrate 10A and the third layer 23A grown on it have relatively similar compositions and theoretical values of lattice constants, so the third layer 23A grown on the AlN on the substrate 10A has , the occurrence of lattice relaxation can be suppressed. The third layer 23A and the second layer 22A grown on it have relatively similar compositions and theoretical values of lattice constants, so the second layer 22A grown on the third layer 23A This suppresses the occurrence of lattice relaxation. Since the second layer 22A and the first layer 21A grown on it have relatively similar compositions and theoretical values of lattice constants, the first layer 21A grown on the second layer 22A The occurrence of lattice relaxation in the layer 21A is suppressed.

The third layer 23A is grown while suppressing lattice relaxation and applying compressive stress to achieve lattice matching with AlN of the underlying substrate 10A. As a result, Al _z Ga _1-z N (0.80<z<1.00) having compressive stress is formed as the third layer 23A. The lattice constant of Al _z Ga _1-z N (0.80<z<1.00) having compressive stress in the third layer 23A is greater than the lattice constant of AlN in the substrate 10A. Furthermore, the lattice constant of Al _z Ga _1-z N (0.80<z<1.00) having compressive stress of the third layer 23A is the same as that of Al _z Ga _1-z N (0.80<z< The lattice constant is smaller than the theoretical value of Al _z Ga _1-z N having an Al composition z corresponding to 1.00). Here, the lattice constant of Al _z Ga _1-z N (0.80<z<1.00) having compressive stress in the third layer 23A may match the lattice constant of AlN in the substrate 10A.

The second layer 22A is grown while applying compressive stress to suppress lattice relaxation and achieve lattice matching with the underlying third layer 23A. As a result, Al _y Ga _1-y N (0.30<y≦0.80) having compressive stress is formed as the second layer 22A. The lattice constant of Al _y Ga _1-y N (0.30<y≦0.80) with compressive stress in the second layer 22A is the same as that of Al _z Ga _1-z N with compressive stress in the third layer 23A. The lattice constant is greater than (0.80<z<1.00). Furthermore, the lattice constant of Al _y Ga _1-y N (0.30<y≦0.80) having compressive stress of the second layer 22A is the same as that of Al _y Ga _1-y N (0.30<y≦ The lattice constant is smaller than the theoretical value of Al _y Ga _1-y N having an Al composition y corresponding to 0.80). Here, the lattice constant of Al _y Ga _1-y N (0.30<y≦0.80) having compressive stress in the second layer 22A may match the lattice constant of AlN in the substrate 10A. The lattice constant of Al _y Ga _1-y N (0.30<y≦0.80) with compressive stress in the second layer 22A is the same as that of Al _z Ga _1-z N with compressive stress in the third layer 23A. (0.80<z<1.00).

The first layer 21A is grown while applying compressive stress to suppress lattice relaxation and achieve lattice matching with the underlying second layer 22A. As a result, Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is formed as the first layer 21A. The lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) with compressive stress in the first layer 21A is the same as that of Al _y Ga _1-y N with compressive stress in the second layer 22A. The lattice constant is greater than or equal to (0.30<y≦0.80). Furthermore, the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress of the first layer 21A is the same as that of Al _x Ga _1-x N (0.15<x≦ 0.30), which is smaller than the theoretical value of the lattice constant of Al _x Ga _1-x N having an Al composition x corresponding to 0.30). Here, the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress in the first layer 21A may match the lattice constant of AlN in the substrate 10A. The lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) with compressive stress in the first layer 21A is the same as that of Al _z Ga _1-z N with compressive stress in the third layer 23A. (0.80<z<1.00). The lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) with compressive stress in the first layer 21A is the same as that of Al _y Ga _1-y N with compressive stress in the second layer 22A. (0.30<y≦0.80).

The following can be said about the compressive stress of Al _x Ga _1-x N (0.15<x≦0.30) of the first layer 21A. That is, the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress in the first layer 21A is greater than the lattice constant of AlN in the substrate 10A. Furthermore, the lattice constant of Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress of the first layer 21A is the same as that of Al _x Ga _1-x N (0.15<x≦ 0.30), which is smaller than the theoretical value of the lattice constant of Al _x Ga _1-x N having an Al composition x corresponding to 0.30).

Furthermore, the following can be said about the Al _y Ga _1-y N (0.30<y≦0.80) having compressive stress of the second layer 22A. That is, the lattice constant of Al _y Ga _1-y N (0.30<y≦0.80) having compressive stress of the second layer 22A is greater than or equal to the lattice constant of AlN of the substrate 10A, and The lattice constant is less than or equal to that of Al _x Ga _1-x N (0.15<x≦0.30) having a compressive stress of 21A. Furthermore, the lattice constant of the Al _y Ga _1-y N (0.30<y≦0.80) having compressive stress of the second layer 22A is the same as that of the Al _y Ga _1-y N (x<y<1. 00), which is smaller than the theoretical value of the lattice constant of Al _y Ga _1-y N having an Al composition y corresponding to 00).

Furthermore, the following can be said about the third layer 23A of Al _z Ga _1-z N (0.80<z<1.00) having compressive stress. That is, the lattice constant of Al _z Ga _1-z N (0.80<z<1.00) having compressive stress in the third layer 23A is greater than or equal to the lattice constant of AlN in the substrate 10A, and The lattice constant is less than or equal to that of Al _y Ga _1-y N (0.30<y≦0.80) having a compressive stress of 22A. Furthermore, the lattice constant of Al _z Ga _1-z N (0.80<z<1.00) having compressive stress of the third layer 23A is the same as that of Al _z Ga _1-z N (0.80<z< 1.00), which is smaller than the theoretical value of the lattice constant of Al _z Ga _1-z N having an Al composition z corresponding to 1.00).

The third layer 23A, second layer 22A, and first layer 21A of the buffer layer 20A are grown so that their respective thickness directions are in the [0001] direction. The surface of the third layer 23A opposite to the substrate 10A side becomes the (0001) plane, that is, the group III polar plane. The surface of the second layer 22A opposite to the third layer 23A is the (0001) plane, that is, the group III polar plane. A surface 20Aa of the first layer 21A opposite to the second layer 22A side is a (0001) plane, that is, a group III polar plane.

The Al _x Ga _1-x N (0.15<x≦0.30) of the first layer 21A formed on the top layer of the buffer layer 20A has compressive stress. The first layer 21A of the buffer layer 20A is formed so that the polarization charge on the surface 20Aa (group III polar surface) is 0 or positive.

FIG. 11A schematically shows a cross-sectional view of a main part of an example of the channel layer forming process.
After forming the buffer layer 20A, a channel layer 30A is formed on the surface 20Aa of the buffer layer 20A, that is, on the first layer 21A, as shown in FIG. 11(A). The channel layer 30A is formed on the surface 20Aa of the buffer layer 20A where the polarization charge is 0 or positive. The channel layer 30A is formed so as to be in contact with the surface 20Aa of the buffer layer 20A, that is, the first layer 21A. The channel layer 30A is formed of GaN with a thickness of 100 nm or less, preferably 50 nm or less, for example, 20 nm. The channel layer 30A is formed using, for example, the MOVPE method. The channel layer 30A is grown so that its thickness direction is in the [0001] direction. A surface 30Aa of the channel layer 30A opposite to the buffer layer 20A is a (0001) plane, that is, a group III polar plane.

FIG. 11B schematically shows a cross-sectional view of essential parts of an example of the barrier layer and cap layer forming process.
After forming the channel layer 30A, a barrier layer 40A is formed on the surface 30Aa of the channel layer 30A, as shown in FIG. 11(B). For example, Al _m Ga _1-m N (0.50≦m≦1.00) with a thickness of 10 nm is formed as the barrier layer 40A. The barrier layer 40A is formed using the MOVPE method, for example. The barrier layer 40A is grown so that its thickness direction is in the [0001] direction. A surface 40Aa of the barrier layer 40A opposite to the channel layer 30A is a (0001) plane, that is, a group III polar plane. 2DEG1Aa is generated near the bonding interface between the channel layer 30A and the barrier layer 40A.

Furthermore, as shown in FIG. 11(B), a cap layer 80A is formed on the formed barrier layer 40A. For example, GaN is formed as the cap layer 80A. The cap layer 80A is formed using, for example, the MOVPE method. The cap layer 80A is grown so that its thickness direction is in the [0001] direction. A surface 80Aa of the cap layer 80A opposite to the barrier layer 40A is a (0001) plane, that is, a group III polar plane.

Through the above steps, the buffer layer 20A (third layer 23A, second layer 22A and first layer 21A), channel layer 30A, barrier layer A nitride semiconductor stacked structure in which the cap layer 40A and the cap layer 80A are stacked is formed.

In addition, in the growth of each layer using the MOVPE method, NH ₃ (ammonia), trimethyl gallium (Tri-Methyl-Gallium; TMGa), trimethyl aluminum (Tri-Methyl-Aluminum; TMAl), etc. are used as source gases. . H ₂ (hydrogen) is used as the carrier gas. Depending on the nitride semiconductor to be grown, the supply and stop (switching) of the raw material gas and the flow rate at the time of supply (mixing ratio with other raw materials) are set as appropriate. The growth pressure is approximately 1 kPa to 100 kPa, and the growth temperature is approximately 700°C to 1500°C.

After forming a nitride semiconductor stacked structure in which a buffer layer 20A, a channel layer 30A, a barrier layer 40A, and a cap layer 80A are stacked on a substrate 10A, a photolithography technique is used to cover the active region and open an opening to the outside of the active region. A mask (not shown) having portions is formed. Then, dry etching using a chlorine-based gas or ion implantation of Ar (argon) or the like is performed on the openings of the mask to form inter-element isolation regions (not shown) that define active regions. After forming the isolation regions, the mask is removed.

FIG. 12A schematically shows a cross-sectional view of a main part of an example of the recess forming process.
After forming the nitride semiconductor stacked structure and the element isolation region, as shown in FIG. 12A, a recess 61A and a recess 71A are formed in the regions of the nitride semiconductor stacked structure where the source electrode 60A and the drain electrode 70A are to be formed, respectively. is formed. In that case, first, a mask (not shown) having openings in regions where the source electrode 60A and the drain electrode 70A are to be formed is formed using a photolithography technique. Then, the cap layer 80A and the barrier layer 40A at the openings of the mask are removed by dry etching using chlorine-based gas. During this dry etching, the cap layer 80A and the barrier layer 40A in the openings of the mask are removed, and a portion of the channel layer 30A may also be removed. As a result, a recess 61A and a recess 71A as shown in FIG. 12(A) are formed.

FIG. 12B schematically shows a cross-sectional view of a main part of an example of the source electrode and drain electrode forming process.
After forming the recess 61A and recess 71A, as shown in FIG. 12(B), a source electrode 60A and a drain electrode 70A are formed in the formed recess 61A and recess 71A, respectively. At that time, using photolithography technology, vapor deposition technology, and lift-off technology, electrode metal is formed in the region where the source electrode 60A and the drain electrode 70A are to be formed, that is, in the region where the cap layer 80A and the barrier layer 40A have been removed. be done. For example, a laminate of Ta with a thickness of 20 nm and Al with a thickness of 200 nm is formed as the electrode metal. Thereafter, heat treatment is performed at 400° C. to 1000° C., for example, 550° C., in a nitrogen atmosphere to establish an ohmic connection between the electrode metals. As a result, as shown in FIG. 12B, a source electrode 60A and a drain electrode 70A are formed which penetrate the cap layer 80A and the barrier layer 40A and are connected to the channel layer 30A (for example, its 2DEG1Aa).

Note that a mask having openings in the regions where the source electrode 60A and the drain electrode 70A are to be formed is formed, and after removing the cap layer 80A and the barrier layer 40A in the openings, the channel layer 30A is further removed, and MOVPE is applied thereto. A contact layer of n-type GaN or the like can also be formed using a method. A source electrode 60A and a drain electrode 70A can also be formed on the contact layer thus formed, according to the above example.

FIG. 13A schematically shows a cross-sectional view of a main part of an example of the passivation film forming process.
After forming the source electrode 60A and the drain electrode 70A, as shown in FIG. 13(A), a passivation film 90A is formed to cover the source electrode 60A, the drain electrode 70A, and the cap layer 80A. For example, a passivation film 90A of SiN or the like having a thickness of 2 nm or more and 500 nm or less, for example, 100 nm, is formed using a plasma CVD (Chemical Vapor Deposition) method. In addition to the plasma CVD method, an atomic layer deposition (ALD) method, a sputtering method, or the like may be used to form the passivation film 90A.

FIG. 13(B) schematically shows a cross-sectional view of a main part of an example of the opening forming process.
After forming the passivation film 90A, as shown in FIG. 13(B), the passivation film 90A in the region where the gate electrode 50A is to be formed is removed, and an opening 91A communicating with the cap layer 80A is formed. In this case, first, a mask (not shown) having an opening in a region where the gate electrode 50A is to be formed is formed using photolithography, and then dry etching is performed. By this etching, the passivation film 90A exposed from the opening of the mask is removed, and an opening 91A of the passivation film 90A is formed. Etching of the passivation film 90A is performed, for example, by dry etching using fluorine-based or chlorine-based gas. In addition, the passivation film 90A may be etched by wet etching using hydrofluoric acid, buffered hydrofluoric acid, or the like. After etching the passivation film 90A, the mask is removed.

After the opening 91A of the passivation film 90A is formed, the gate electrode 50A is formed at the position of the opening 91A of the passivation film 90A, as shown in FIG. 9 above. At that time, an electrode metal is formed at the opening 91A of the passivation film 90A using photolithography, vapor deposition, and lift-off technology. For example, a laminate of Ni (nickel) with a thickness of 30 nm and Au (gold) with a thickness of 400 nm is formed as the electrode metal. The electrode metal is formed not only on the upper surface of the passivation film 90A but also so as to enter into the opening 91A. Thereby, a gate electrode 50A functioning as a Schottky electrode is formed.

Through the steps described above, a semiconductor device 1A as shown in FIG. 9 is manufactured.
In the semiconductor device 1A, a third layer 23A, a second layer 22A, and a first layer 21A are formed as a buffer layer 20A on AlN of a substrate 10A (FIGS. 10A and 10B). ). Here, the third layer 23A is Al _z Ga _1-z N (0.80<z<1.00), and the second layer 22A is Al _y Ga _1-y N (0.30< y≦0.80), and the first layer 21A is Al _x Ga _1-x N (0.15<x≦0.30). The third layer 23A is grown while applying compressive stress to achieve lattice matching with AlN of the underlying substrate 10A. The second layer 22A is grown while applying compressive stress to achieve lattice matching with the underlying third layer 23A. The first layer 21A is grown while applying compressive stress to achieve lattice matching with the underlying second layer 22A. As a result, the Al _x Ga _1-x N (0.5%) of the first layer 21A having a compressive stress is deposited on the AlN of the substrate 10A via the third layer 23A and the second layer 22A having a compressive stress. 15<x≦0.30).

The buffer layer 20A is formed so that the polarization charge on the surface 20Aa on the first layer 21A side is 0 or positive. Then, GaN of the channel layer 30A is formed on the surface 20Aa of the buffer layer 20A (FIG. 11(A)). In the channel layer 30A, due to the zero or positive polarization charges on the surface 20Aa of the buffer layer 20A, rise in conduction band energy E _C on the side of the buffer layer 20A is suppressed. As a result, in the semiconductor device 1A, the distribution and wave function of electrons in the channel layer 30A are widened, and the electron mobility of the channel layer 30A is improved. A high performance semiconductor device 1A including a channel layer 30A exhibiting excellent electron mobility is manufactured.

In the above description, the semiconductor device 1A employs a so-called asymmetric structure in which the distance between the gate electrode 50A and the drain electrode 70A is wider than the distance between the gate electrode 50A and the source electrode 60A in order to increase the breakdown voltage. I used it as an example. In addition, the above method can be similarly applied to a device that employs a so-called symmetrical structure in which the distance between the gate electrode 50A and the drain electrode 70A is made equal to the distance between the gate electrode 50A and the source electrode 60A. It is.

Further, the type and layer structure of the electrode metal used for the gate electrode 50A, source electrode 60A, and drain electrode 70A are not limited to the above examples, and the method of forming them is not limited to the above examples either. . The gate electrode 50A, the source electrode 60A, and the drain electrode 70A may each have a single layer structure or a laminated structure. When forming the source electrode 60A and the drain electrode 70A, it is not necessarily necessary to perform the above heat treatment if ohmic contact can be realized by forming the metal for these electrodes. When forming the gate electrode 50A, heat treatment may be further performed after the electrode metal is formed.

Further, in the above description, an example in which the gate electrode 50A functioning as a Schottky electrode is provided in the semiconductor device 1A is shown, but between the gate electrode 50A and the cap layer 80A, an oxide, nitride, oxynitride, etc. It is also possible to provide a gate insulating film using an MIS (Metal Insulator Semiconductor) type gate structure.

[Third embodiment]
FIG. 14 is a diagram illustrating an example of a semiconductor device according to the third embodiment. FIG. 14 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.

A semiconductor device 1B shown in FIG. 14 is an example of a HEMT. The semiconductor device 1B has a structure in which a buffer layer 20B having a stacked structure of four layers of AlGaN is provided between a substrate 10A and a channel layer 30A. The semiconductor device 1B differs from the semiconductor device 1A (FIG. 9) described in the second embodiment in that it has such a configuration. Between the substrate 10A and the channel layer 30A, there is not only the above buffer layer 20A having a stacked structure of three layers of AlGaN, but also a buffer layer 20B having a stacked structure of four layers of AlGaN as in this semiconductor device 1B. may be provided.

The semiconductor device 1B includes a first layer 21B, a second layer 22B, a third layer 23B, and a fourth layer 24B as the buffer layer 20B. Al _x Ga _1-x N (0.15<x≦0.30) is used for the first layer 21B on which the channel layer 30A is stacked. For the second layer 22B on which the first layer 21B is laminated, Al _y2 Ga _1-y2 N (x<y2) having an Al composition y2 higher than the Al composition x of the first layer 21B is used. For the third layer 23B on which the second layer 22B is laminated, Al _y3 Ga _1-y3 N (y2<y3) having an Al composition y3 higher than the Al composition y2 of the second layer 22B is used. For the fourth layer 24B on which the third layer 23B is laminated, Al _y4 Ga _1-y4 N (y3<y4) having an Al composition y4 higher than the Al composition y3 of the third layer 23B is used.

The buffer layer 20B is formed by laminating a fourth layer 24B, a third layer 23B, a second layer 22B, and a first layer 21B in this order on AlN of the substrate 10A using, for example, the MOVPE method. be done. The fourth layer 24B is grown while applying compressive stress to achieve lattice matching with AlN of the underlying substrate 10A. As a result, a fourth layer 24B having compressive stress is formed. The third layer 23B is grown while applying compressive stress to achieve lattice matching with the underlying fourth layer 24B. This forms the third layer 23B having compressive stress. The second layer 22B is grown while applying compressive stress to achieve lattice matching with the underlying third layer 23B. As a result, a second layer 22B having compressive stress is formed. The first layer 21B is grown while applying compressive stress to achieve lattice matching with the underlying second layer 22B. As a result, the first layer 21B having compressive stress is formed. Then, GaN of the channel layer 30A is formed on the first layer 21B of the buffer layer 20B, that is, on the surface 20Ba of the buffer layer 20B.

A first layer 21B, ie, Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress, is provided at the bonding interface between the buffer layer 20B and the channel layer 30A. The first layer 21B is formed so that the polarization charge on the surface 20Ba on the channel layer 30A side is 0 or positive. As a result, the conduction band energy E _C of the channel layer 30A on the buffer layer 20B side is suppressed from rising, the electron distribution and wave function are widened, and the electron mobility of the channel layer 30A is improved. A high-performance semiconductor device 1B including a channel layer 30A exhibiting excellent electron mobility is realized.

As in the semiconductor device 1B, by increasing the number of layers of the buffer layer 20B, it is possible to more effectively suppress the occurrence of lattice relaxation between each layer when layer groups are stacked so that the Al composition becomes lower in order from the substrate 10A side. It becomes possible to suppress the This makes it possible to grow the first layer 21B while applying sufficient compressive stress, form the first layer 21B having sufficient compressive stress, and form the buffer layer 20B including the first layer 21B.

Here, the buffer layer 20B having a stacked structure of four layers of AlGaN is taken as an example, but the same effect as described above can also be obtained by providing a buffer layer having a stacked structure of five or more layers of AlGaN.

[Fourth embodiment]
FIG. 15 is a diagram illustrating an example of a semiconductor device according to the fourth embodiment. FIG. 15 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.

A semiconductor device 1C shown in FIG. 15 is an example of a HEMT. The semiconductor device 1C has a structure in which a buffer layer 20C having a so-called graded Al composition, in which the Al composition gradually decreases from the substrate 10A side to the channel layer 30A side, is provided between the substrate 10A and the channel layer 30A. The semiconductor device 1C differs from the semiconductor device 1A (FIG. 9) described in the second embodiment above in that it has such a configuration. Between the substrate 10A and the channel layer 30A, the buffer layer 20C is not limited to the above-mentioned buffer layer 20A having a stacked structure of three layers of AlGaN, but may be provided with a buffer layer 20C having a gradient Al composition as in this semiconductor device 1C. .

The surface 20Ca on the channel layer 30A side of the buffer layer 20C, in which the Al composition gradually decreases from the substrate 10A side toward the channel layer 30A side, has Al _x whose Al composition x is more than 0.15 and less than 0.30. Ga _1-x N (0.15<x≦0.30) is provided. Such a buffer layer 20C can be formed by growing AlGaN on AlN of the substrate 10A using, for example, the MOVPE method while appropriately adjusting the amount of Al source gas. The AlGaN of the buffer layer 20C is grown on the AlN of the substrate 10A while compressive stress is applied. As a result, Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is formed on the surface 20Ca of the buffer layer 20C. Then, GaN of the channel layer 30A is formed on the surface 20Ca of the buffer layer 20C.

Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is provided at the bonding interface between the buffer layer 20C and the channel layer 30A. Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is formed so that the polarization charge on the surface 20Ca on the channel layer 30A side is 0 or positive. As a result, the conduction band energy E _C of the channel layer 30A on the buffer layer 20C side is suppressed from rising, the electron distribution and wave function are widened, and the electron mobility of the channel layer 30A is improved. A high-performance semiconductor device 1C including a channel layer 30A exhibiting excellent electron mobility is realized.

Even if the buffer layer 20C has a graded Al composition as in the semiconductor device 1C, AlGaN is grown while applying compressive stress, and Al _x Ga _1-x N(0 .15<x≦0.30).

The first to fourth embodiments have been described above.
The semiconductor devices 1, 1A, 1B, 1C, etc. described in the first to fourth embodiments can be applied to various electronic devices. As an example, a case where the semiconductor devices 1, 1A, 1B, 1C, etc. as described above are applied to a semiconductor package, a power factor correction circuit, a power supply device, and an amplifier will be described below.

[Fifth embodiment]
Here, an example of application of a semiconductor device having the above configuration to a semiconductor package will be described as a fifth embodiment.

FIG. 16 is a diagram illustrating an example of a semiconductor package according to the fifth embodiment. FIG. 16 schematically shows a plan view of essential parts of an example of a semiconductor package according to the fifth embodiment.

A semiconductor package 200 shown in FIG. 16 is an example of a discrete package. The semiconductor package 200 includes, for example, the semiconductor device 1 (FIG. 3) described in the first embodiment, a lead frame 210 on which the semiconductor device 1 is mounted, and a resin 220 that seals them.

The semiconductor device 1 is mounted on the die pad 210a of the lead frame 210 using a die attach material or the like (not shown). The semiconductor device 1 is provided with a pad 50a connected to the gate electrode 50, a pad 60a connected to the source electrode 60, and a pad 70a connected to the drain electrode 70. The pads 50a, 60a, and 70a are connected to the gate lead 211, source lead 212, and drain lead 213 of the lead frame 210, respectively, using wires 230 made of Al or the like. The lead frame 210, the semiconductor device 1 mounted thereon, and the wires 230 connecting them are sealed with resin 220 so that parts of the gate lead 211, source lead 212, and drain lead 213 are exposed.

Note that an electrode connected to the source electrode 60 is provided on a surface of the semiconductor device 1 opposite to the surface on which the pad 50a connected to the gate electrode 50 and the pad 70a connected to the drain electrode 70 are provided. Good too. The electrode may be connected to the die pad 210a connected to the source lead 212 using a conductive bonding material such as solder.

For example, the semiconductor device 1 described in the first embodiment is used to obtain the semiconductor package 200 having such a configuration. Although the semiconductor device 1 is taken as an example here, it is possible to similarly obtain a semiconductor package using other semiconductor devices 1A, 1B, 1C, etc.

As described above, in the semiconductor device 1 etc., a buffer layer (containing Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is formed on a substrate (substrate 10 etc.) containing AlN (substrate 10 etc.). A buffer layer 20, etc.) is provided, and a channel layer containing GaN (channel layer 30, etc.) is provided thereon. Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is provided so that the polarization charge on the surface on the channel layer side (surface 20a, etc.) is 0 or positive. As a result, the conduction band energy of the channel layer on the buffer layer side is suppressed from rising, the electron distribution and wave function are broadened, and the electron mobility of the channel layer is improved. A high-performance semiconductor device 1 etc. including a channel layer exhibiting excellent electron mobility is realized. By using such a semiconductor device 1 and the like, a high-performance semiconductor package 200 is realized.

[Sixth embodiment]
Here, an example of application of a semiconductor device having the above configuration to a power factor correction circuit will be described as a sixth embodiment.

FIG. 17 is a diagram illustrating an example of a power factor correction circuit according to the sixth embodiment. FIG. 17 shows an equivalent circuit diagram of an example of the power factor correction circuit according to the sixth embodiment.
A power factor correction (PFC) circuit 300 shown in FIG. 17 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an alternating current power source 370 (AC).

In the PFC circuit 300, the drain electrode of the switch element 310, the anode terminal of the diode 320, and one terminal of the choke coil 330 are connected. A source electrode of switch element 310 is connected to one terminal of capacitor 340 and one terminal of capacitor 350. The other terminal of the capacitor 340 and the other terminal of the choke coil 330 are connected. The other terminal of capacitor 350 and the cathode terminal of diode 320 are connected. Furthermore, a gate driver is connected to the gate electrode of the switch element 310. An AC power source 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a direct current power (DC) is taken out between both terminals of the capacitor 350.

For example, the semiconductor devices 1, 1A, 1B, 1C, etc. described above are used for the switch element 310 of the PFC circuit 300 having such a configuration.
As described above, in the semiconductor device 1 etc., a buffer layer (containing Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is formed on a substrate (substrate 10 etc.) containing AlN (substrate 10 etc.). A buffer layer 20, etc.) is provided, and a channel layer containing GaN (channel layer 30, etc.) is provided thereon. Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is provided so that the polarization charge on the surface on the channel layer side (surface 20a, etc.) is 0 or positive. As a result, the conduction band energy of the channel layer on the buffer layer side is suppressed from rising, the electron distribution and wave function are broadened, and the electron mobility of the channel layer is improved. A high-performance semiconductor device 1 etc. including a channel layer exhibiting excellent electron mobility is realized. By using such a semiconductor device 1 and the like, a high-performance PFC circuit 300 is realized.

[Seventh embodiment]
Here, an example of application of a semiconductor device having the above configuration to a power supply device will be described as a seventh embodiment.

FIG. 18 is a diagram illustrating an example of a power supply device according to the seventh embodiment. FIG. 18 shows an equivalent circuit diagram of an example of a power supply device according to the seventh embodiment.
Power supply device 400 shown in FIG. 18 includes a primary circuit 410, a secondary circuit 420, and a transformer 430 provided between primary circuit 410 and secondary circuit 420.

The primary side circuit 410 includes the PFC circuit 300 as described in the sixth embodiment, and an inverter circuit connected between both terminals of the capacitor 350 of the PFC circuit 300, for example, a full-bridge inverter circuit 440. It will be done. The full-bridge inverter circuit 440 includes a plurality of switch elements 441, 442, 443, and 444, which are four in this example.

The secondary side circuit 420 includes a plurality of switch elements 421, 422, and 423, which are three in this example.
For example, in the power supply device 400 having such a configuration, the switch element 310 of the PFC circuit 300 included in the primary side circuit 410 and the switch elements 441, 442, 443, and 444 of the full-bridge inverter circuit 440 are , 1A, 1B, 1C, etc. are used. For example, the switch elements 421, 422, and 423 of the secondary circuit 420 of the power supply device 400 use normal MIS type FETs using Si.

As described above, in the semiconductor device 1 etc., a buffer layer (containing Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is formed on a substrate (substrate 10 etc.) containing AlN (substrate 10 etc.). A buffer layer 20, etc.) is provided, and a channel layer containing GaN (channel layer 30, etc.) is provided thereon. Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is provided so that the polarization charge on the surface on the channel layer side (surface 20a, etc.) is 0 or positive. As a result, the conduction band energy of the channel layer on the buffer layer side is suppressed from rising, the electron distribution and wave function are broadened, and the electron mobility of the channel layer is improved. A high-performance semiconductor device 1 etc. including a channel layer exhibiting excellent electron mobility is realized. By using such a semiconductor device 1 and the like, a high-performance power supply device 400 is realized.

[Eighth embodiment]
Here, an example of application of the semiconductor device having the above configuration to an amplifier will be described as an eighth embodiment.

FIG. 19 is a diagram illustrating an example of an amplifier according to the eighth embodiment. FIG. 19 shows an equivalent circuit diagram of an example of an amplifier according to the eighth embodiment.
Amplifier 500 shown in FIG. 19 includes a digital predistortion circuit 510, mixer 520, mixer 530, and power amplifier 540.

Digital predistortion circuit 510 compensates for nonlinear distortion of the input signal. The mixer 520 mixes the nonlinear distortion compensated input signal SI and the AC signal. The power amplifier 540 amplifies a signal obtained by mixing the input signal SI with an AC signal. In the amplifier 500, for example, by switching a switch, the output signal SO can be mixed with an alternating current signal in the mixer 530 and sent to the digital predistortion circuit 510. Amplifier 500 can be used as a high frequency amplifier or a high power amplifier.

The semiconductor devices 1, 1A, 1B, 1C, etc. described above are used in the power amplifier 540 of the amplifier 500 having such a configuration.
As described above, in the semiconductor device 1 etc., a buffer layer (containing Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is formed on a substrate (substrate 10 etc.) containing AlN (substrate 10 etc.). A buffer layer 20, etc.) is provided, and a channel layer containing GaN (channel layer 30, etc.) is provided thereon. Al _x Ga _1-x N (0.15<x≦0.30) having compressive stress is provided so that the polarization charge on the surface on the channel layer side (surface 20a, etc.) is 0 or positive. As a result, the conduction band energy of the channel layer on the buffer layer side is suppressed from rising, the electron distribution and wave function are broadened, and the electron mobility of the channel layer is improved. A high-performance semiconductor device 1 etc. including a channel layer exhibiting excellent electron mobility is realized. By using such a semiconductor device 1 and the like, a high-performance amplifier 500 is realized.

Various electronic devices (semiconductor package 200, PFC circuit 300, power supply device 400, amplifier 500, etc. described in the fifth to eighth embodiments) to which the semiconductor devices 1, 1A, 1B, 1C, etc. are applied are various. It can be installed in electronic equipment or devices. For example, various electronic devices such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio equipment, measurement equipment, inspection equipment, manufacturing equipment, transmitters, receivers, radar equipment, etc. It can be mounted on equipment or electronic devices.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Additional Note 1) A substrate containing AlN,
a buffer layer provided on the first surface side of the substrate and containing a first Al _x Ga _1-x N (0.15<x≦0.30) having a first compressive stress;
a channel layer provided on a second surface side of the buffer layer opposite to the substrate side and containing GaN;
A semiconductor device having

(Additional Note 2) The lattice constant of the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress is greater than or equal to the lattice constant of the AlN included in the substrate. is lower than the theoretical value of the lattice constant of Al _x Ga _1-x N having an Al composition x corresponding to the first Al _x Ga 1 _- x N (0.15<x≦0.30). The semiconductor device according to appendix 1, which is small.

(Additional Note 3) The lattice constant of the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress is the same as the lattice constant of the AlN included in the substrate. The semiconductor device according to supplementary note 1.

(Additional Note 4) The channel layer is made of any one of Appendices 1 to 3, which is in contact with the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress. The semiconductor device described in .

(Additional Note 5) The buffer layer is
a first layer containing the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress;
a second layer provided closer to the substrate than the first layer and containing a second Al _y Ga _1-y N (x<y<1.00) having a second compressive stress;
5. The semiconductor device according to any one of Supplementary Notes 1 to 4, comprising:

(Additional Note 6) The lattice constant of the second Al _y Ga _1-y N (x<y<1.00) having the second compressive stress is greater than or equal to the lattice constant of the AlN included in the substrate, and , the lattice constant of the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress, and the second Al _y Ga _1-y N The semiconductor device according to appendix 5, wherein the semiconductor device has a lattice constant smaller than the theoretical value of Al _y Ga _1-y N having an Al composition y corresponding to (x<y<1.00).

(Additional Note 7) The buffer layer is provided closer to the substrate than the second layer, and includes a third Al _z Ga _1-z N (y<z<1.00) having a third compressive stress. 7. The semiconductor device according to appendix 5 or 6, comprising a third layer comprising:

(Additional Note 8) The lattice constant of the third Al _z Ga _1-z N (y<z<1.00) having the third compressive stress is greater than or equal to the lattice constant of the AlN included in the substrate, and , the lattice constant of the second Al _y Ga _1-y N (x<y<1.00) having the second compressive stress, and the third Al _z Ga _1-z N (y The semiconductor device according to appendix 7, wherein the lattice constant of Al _z Ga _1-z N having an Al composition z corresponding to <z<1.00) is smaller than the theoretical value.

(Additional Note 9) A barrier layer provided on the third surface side of the channel layer opposite to the buffer layer side and containing Al _m Ga _1-m N (0.00<m≦1.00). , the semiconductor device according to any one of Supplementary Notes 1 to 8.

(Additional Note 10) The semiconductor device according to any one of Additional Notes 1 to 9, wherein the channel layer has a thickness of 100 nm or less in a direction perpendicular to the second surface of the buffer layer.
(Additional Note 11) A buffer layer containing a first Al _x Ga _1-x N (0.15<x≦0.30) having a first compressive stress is formed on the first surface side of the substrate containing AlN. The process of
forming a channel layer containing GaN on a second surface side of the buffer layer opposite to the substrate side;
A method for manufacturing a semiconductor device having the following.

(Additional Note 12) The lattice constant of the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress is greater than or equal to the lattice constant of the AlN included in the substrate. is lower than the theoretical value of the lattice constant of Al _x Ga _1-x N having an Al composition x corresponding to the first Al _x Ga 1 _- x N (0.15<x≦0.30). The method for manufacturing a small semiconductor device according to appendix 11.

(Additional Note 13) The step of forming the buffer layer includes:
forming a first layer containing the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress;
forming a second layer containing a second Al _y Ga _1-y N (x<y<1.00) having a second compressive stress closer to the substrate than the first layer;
The method for manufacturing a semiconductor device according to appendix 11 or 12, comprising:

(Additional Note 14) The lattice constant of the second Al _y Ga _1-y N (x<y<1.00) having the second compressive stress is greater than or equal to the lattice constant of the AlN included in the substrate, and , the lattice constant of the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress, and the second Al _y Ga _1-y N The method for manufacturing a semiconductor device according to appendix 13, wherein the lattice constant of Al _y Ga _1-y N having an Al composition y corresponding to (x<y<1.00) is smaller than the theoretical value.

(Additional Note 15) A substrate containing AlN,
a buffer layer provided on the first surface side of the substrate and containing a first Al _x Ga _1-x N (0.15<x≦0.30) having a first compressive stress;
a channel layer provided on a second surface side of the buffer layer opposite to the substrate side and containing GaN;
An electronic device comprising a semiconductor device.

1, 1A, 1B, 1C, 100A, 100B Semiconductor device 1a, 1Aa, 101A, 101B 2DEG
10, 10A, 110A, 110B Substrate 10a, 10Aa, 20a, 20Aa, 20Ba, 20Ca, 30a, 30Aa, 40a, 40Aa, 80Aa Surface 11A Base substrate 12A Nucleation layer 20, 20A, 20B, 20C, 120B Buffer layer 21, 21A, 21B First layer 22, 22A, 22B Second layer 23A, 23B Third layer 24B Fourth layer 30, 30A, 130A, 130B Channel layer 40, 40A, 140A, 140B Barrier layer 50, 50A, 150 Gate electrode 50a, 60a, 70a Pad 60, 60A, 160 Source electrode 61A, 71A Recess 70, 70A, 170 Drain electrode 80A Cap layer 90A Passivation film 91A Opening 200 Semiconductor package 210 Lead frame 210a Die pad 211 Gate lead 212 Source lead 213 Drain lead 220 Resin 230 Wire 300 PFC circuit 310, 421, 422, 423, 441, 442, 443, 444 Switch element 320 Diode 330 Choke coil 340, 350 Capacitor 360 Diode bridge 370 AC power supply 400 Power supply device 410 Primary side circuit 420 Secondary circuit 430 Transformer 440 Full bridge inverter circuit 500 Amplifier 510 Digital predistortion circuit 520, 530 Mixer 540 Power amplifier

Claims (9)

a substrate containing AlN;
a buffer layer provided on the first surface side of the substrate and containing a first Al _x Ga _1-x N (0.15<x≦0.30) having a first compressive stress;
a channel layer provided on a second surface side of the buffer layer opposite to the substrate side and containing GaN;
A semiconductor device having The lattice constant of the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress is greater than or equal to the lattice constant of the AlN included in the substrate, A lattice constant smaller than a theoretical value of Al _x Ga _{1- x} N having an Al composition x corresponding to the first Al _x Ga 1-x N (0.15<x≦0.30). 1. The semiconductor device according to 1. The buffer layer is
a first layer containing the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress;
a second layer provided closer to the substrate than the first layer and containing a second Al _y Ga _1-y N (x<y<1.00) having a second compressive stress;
The semiconductor device according to claim 1 or 2, comprising: The lattice constant of the second Al _y Ga _1-y N (x<y<1.00) having the second compressive stress is greater than or equal to the lattice constant of the AlN included in the substrate, and The lattice constant of the first Al _x Ga 1 _{- x} N (0.15< _x ≦0.30) having a compressive stress of 4. The semiconductor device according to claim 3, wherein the lattice constant is smaller than the theoretical value of Al _y Ga _1-y N having an Al composition y corresponding to <1.00). The buffer layer is provided closer to the substrate than the second layer, and includes a third layer containing a third Al _z Ga _1-z N (y<z<1.00) having a third compressive stress. The semiconductor device according to claim 3 or 4, comprising a layer. The lattice constant of the third Al _z Ga _1-z N (y<z<1.00) having the third compressive stress is greater than or equal to the lattice constant of the AlN included in the substrate, and The lattice constant of the second _{Al y} Ga 1 _{- y} N (x<y<1.00) having a compressive stress of 6. The semiconductor device according to claim 5, wherein the lattice constant is smaller than the theoretical value of Al _z Ga _1-z N having an Al composition z corresponding to .00). forming a buffer layer containing a first Al _x Ga _1-x N (0.15<x≦0.30) having a first compressive stress on the first surface side of the substrate containing AlN;
forming a channel layer containing GaN on a second surface side of the buffer layer opposite to the substrate side;
A method for manufacturing a semiconductor device having the following. The lattice constant of the first Al _x Ga _1-x N (0.15<x≦0.30) having the first compressive stress is greater than or equal to the lattice constant of the AlN included in the substrate, A lattice constant smaller than a theoretical value of Al _x Ga _{1- x} N having an Al composition x corresponding to the first Al _x Ga 1-x N (0.15<x≦0.30). 7. The method for manufacturing a semiconductor device according to 7. a substrate containing AlN;
a buffer layer provided on the first surface side of the substrate and containing a first Al _x Ga _1-x N (0.15<x≦0.30) having a first compressive stress;
a channel layer provided on a second surface side of the buffer layer opposite to the substrate side and containing GaN;
An electronic device comprising a semiconductor device.

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