JP2023135724A - Correction apparatus, correction system, correction method, and program - Google Patents

Abstract

To provide a correction apparatus that can appropriately correct an offset voltage even when a direct current component is removed by an AC coupling circuit and the offset voltage is generated.SOLUTION: A correction apparatus includes: sampling means that samples a voltage in between pulse signals in digital signals; and correction means that corrects an offset voltage for the pulse signals.SELECTED DRAWING: Figure 8

Description

The present disclosure relates to a correction device, a correction system, a correction method, and a program.

In signal processing, when a process in which a DC component is removed is performed, an offset may occur due to the removed signal component. Patent Document 1 discloses, as a related technique, a technique related to offset voltage correction.

Japanese Patent Application Publication No. 11-220572

By the way, if an offset occurs due to processing to remove a DC component in signal processing, the offset may have an adverse effect on subsequent signal processing. Therefore, in signal processing, there is a need for a technique that can compensate for offsets.

One of the objectives of each aspect of the present disclosure is to provide a correction device, a correction system, a correction method, and a program that can solve the above problems.

In order to achieve the above object, according to one aspect of the present disclosure, a correction device includes a sampling means for sampling a voltage between pulse signals in a digital signal, and a correction means for correcting an offset voltage for the pulse signal. Be prepared.

In order to achieve the above object, according to another aspect of the present disclosure, the correction system includes an AC coupling circuit that is capable of transmitting an alternating current signal of a predetermined frequency or higher, and cannot transmit an alternating current signal and a direct current signal of less than the predetermined frequency. and an AD conversion circuit that generates a digital signal by quantizing an AC signal having a frequency equal to or higher than the frequency outputted by the AC coupling circuit, and the correction device described above.

To achieve the above object, according to another aspect of the present disclosure, a correction method includes sampling a voltage between pulse signals in a digital signal, and correcting an offset voltage for the pulse signal. .

In order to achieve the above object, according to another aspect of the present disclosure, a program causes a computer to sample a voltage between pulse signals in a digital signal, and to correct an offset voltage for the pulse signal. Execute.

According to each aspect of the present disclosure, even if a DC component is removed by the AC coupling circuit and an offset voltage occurs, the offset voltage can be appropriately corrected.

FIG. 1 is a diagram illustrating an example of a configuration of a correction system according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a processing flow of a correction system according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating an example of timing of sampling processing by an offset value calculation circuit according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating an example of a first combination in an embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of a second combination in an embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of a third combination in an embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of a fourth combination in an embodiment of the present disclosure. FIG. 2 is a diagram showing the minimum configuration of a correction device according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a processing flow of a correction device with a minimum configuration according to an embodiment of the present disclosure. FIG. 1 is a schematic block diagram showing the configuration of a computer according to at least one embodiment.

Hereinafter, embodiments will be described in detail with reference to the drawings.
<Embodiment>
FIG. 1 is a diagram illustrating an example of the configuration of a correction system 1 according to an embodiment of the present disclosure. As shown in FIG. 1, the correction system 1 includes an AC (Alternating Current) coupling circuit 10, an AD (Analog to Digital) conversion circuit 20, and a correction device 30.

The AC coupling circuit 10 is a circuit that is capable of transmitting alternating current signals of a predetermined frequency or higher, and cannot transmit alternating current signals and direct current signals of less than a predetermined frequency. The AC coupling circuit 10 outputs an AC signal having a predetermined frequency or higher to the AD conversion circuit 20.

The AD conversion circuit 20 converts the AC signal, which is an analog signal, output by the AC coupling circuit 10 into a digital signal. The AD conversion circuit 20 outputs a digital signal to the correction device 30.

The correction device 30 corrects the offset caused by the DC signal that the AC coupling circuit 10 cannot transmit. As shown in FIG. 1, the correction device 30 includes a peak search circuit 301, a pulse signal extraction circuit 302, an offset value calculation circuit 303 (an example of a sampling means), a sampling period calculation section 304, and an adder 305 (of a correction means). Equipped with

A peak search circuit 301 searches for a peak in a pulse signal that is a received signal. Specifically, the peak search circuit 301 samples the received signal finely and identifies a signal with a high voltage level.

A pulse signal extraction circuit 302 extracts a pulse signal. Specifically, the pulse signal extraction circuit 302 determines that the received signal sampled by the peak search circuit 301 has the highest voltage level as the center of the pulse signal, and extracts it as a pulse signal.

The offset value calculation circuit 303 calculates an offset value from a voltage value near 0V generated between pulse signals. Since the pulse signal is a periodic signal, the distance between the pulse signals is ideally close to 0V. After the sampling period calculation unit 304 specifies the period of the pulse signal, the offset value calculation circuit 303 calculates the offset value by sampling the voltage between the pulse signals.

A sampling period calculation unit 304 determines the sampling period of the pulse signal (ie, digital signal). Since the pulse signal is a periodic signal, for example, the sampling period calculation unit 304 identifies the period by receiving the first plurality of pulses. Then, the sampling period calculation unit 304 determines the sampling period according to the identified period.

The adder 305 adds the offset voltage calculated by the offset value calculation circuit 303 to the pulse signal extracted by the pulse signal extraction circuit 302.

Next, processing performed by the correction system 1 according to an embodiment of the present disclosure will be described. FIG. 2 is a diagram illustrating an example of a processing flow of the correction system 1 according to an embodiment of the present disclosure.

An input signal is input to AC coupling circuit 10 . The AC coupling circuit 10 outputs an AC signal having a predetermined frequency or higher to the AD conversion circuit 20. The AD conversion circuit 20 continuously quantizes an AC signal having a predetermined frequency or higher and converts it into a digital signal. The AD conversion circuit 20 outputs a digital signal to the correction device 30. Note that the sampling rate of the AD conversion circuit 20 needs to be faster than the sampling period determined by the sampling period calculating section 304.

The peak search circuit 301 searches for a sampling point where the absolute value of the voltage of the digital signal outputted by the AD conversion circuit 20 is maximum (step S1). The peak search circuit 301 outputs the searched sampling points to the sampling period calculation section 304.

The sampling period calculation unit 304 calculates the period between peaks of the pulse signal (that is, the digital signal) (step S2). Then, the sampling period calculation unit 304 identifies the sampling period of the pulse signal to the calculated period. The sampling period calculation section 304 outputs the fixed period to the pulse signal extraction circuit 302 and the offset value calculation circuit 303.

The pulse signal extraction circuit 302 uses the sampling period fixed by the sampling period calculating section 304 to extract only the pulse signal from the digital signal output from the AD conversion circuit 20 (step S3). Pulse signal extraction circuit 302 outputs the extracted pulse signal to adder 305.

The offset value calculation circuit 303 uses the sampling period fixed by the sampling period calculation section 304 to obtain the voltage value of the digital signal between the pulse signals output by the AD conversion circuit 20. The offset value calculation circuit 303 calculates a voltage offset value for the pulse signal (step S4). Offset value calculation circuit 303 outputs the calculated offset value to adder 305.

FIG. 3 is a diagram illustrating an example of the timing of sampling processing by the offset value calculation circuit 303 according to an embodiment of the present disclosure. The offset value calculation circuit 303 samples at the peak point of the pulse signal and the midpoint between the pulse signals.

The adder 305 adds the pulse signal extracted by the pulse signal extraction circuit 302 and the offset value calculated by the offset value calculation circuit 303 (step S5). For example, the adder 305 calculates the voltage offset based on the results sampled by the offset value calculation circuit 303. Specifically, the offset is calculated in the following cases based on the combination of the positive/negative of the pulse signal and the positive/negative of the midpoint voltage of the pulse signal.

(For the first combination)
FIG. 4 is a diagram illustrating an example of a first combination in an embodiment of the present disclosure. In this case, the adder 305 determines the voltage c of the negative pulse signal from the reference voltages a and b between the pulse signals. Specifically, the adder 305 offsets the absolute value of the reference voltage a (an example of the second reference voltage) before the pulse signal to the reference voltage b (an example of the first reference voltage) after the pulse signal. By adding as follows, a negative pulse signal c is obtained.

(For the second combination)
FIG. 5 is a diagram illustrating an example of a second combination in an embodiment of the present disclosure. In this case, the adder 305 obtains a negative pulse signal c by adding an offset value obtained by multiplying the absolute value of the reference voltage a before the pulse signal by -1 to the reference voltage b after the pulse signal. .

(For the third combination)
FIG. 6 is a diagram illustrating an example of a third combination in an embodiment of the present disclosure. In this case, the adder 305 obtains a positive pulse signal c by adding an offset value obtained by multiplying the absolute value of the reference voltage a before the pulse signal by -1 to the reference voltage b after the pulse signal. .

(For the fourth combination)
FIG. 7 is a diagram illustrating an example of a fourth combination in an embodiment of the present disclosure. In this case, the adder 305 obtains a positive pulse signal c by adding the absolute value of the reference voltage a before the pulse signal as an offset value to the reference voltage b after the pulse signal.

Then, the adder 305 outputs the obtained pulse signal c as an output signal.

(advantage)
As described above, in the correction system 1, the correction device 30 includes an offset value calculation circuit 303 and an adder 305. The offset value calculation circuit 303 samples the voltage between pulse signals in the digital signal. Adder 305 corrects the offset voltage for the pulse signal. Therefore, in the correction system 1, the correction device 30 can appropriately correct the offset voltage even when the DC component is removed by the AC coupling circuit 10 and an offset voltage is generated.

FIG. 8 is a diagram showing the minimum configuration of the correction device 30 according to the embodiment of the present disclosure. The correction device 30 includes an offset value calculation circuit 303 and an adder 305, as shown in FIG. The offset value calculation circuit 303 samples the voltage between pulse signals in the digital signal. Adder 305 corrects the offset voltage for the pulse signal.

FIG. 9 is a diagram illustrating an example of a processing flow of the correction device 30 with the minimum configuration according to the embodiment of the present disclosure. Next, processing of the correction device 30 with the minimum configuration according to the embodiment of the present disclosure will be described with reference to FIG. 9.

The offset value calculation circuit 303 samples the voltage between pulse signals in the digital signal (step S101). The adder 305 corrects the offset voltage of the pulse signal (step S102).

The correction device 30 with the minimum configuration according to the embodiment of the present disclosure has been described above. With this correction device 30, even if a DC component is removed by the AC coupling circuit and an offset voltage occurs, it is possible to appropriately correct the offset voltage.

Note that the order of the processing in the embodiment of the present disclosure may be changed as long as appropriate processing is performed.

Although the embodiment of the present disclosure has been described, the above-described correction system 1, correction device 30, and other control devices may include a computer system therein. The above-described processing steps are stored in a computer-readable recording medium in the form of a program, and the above-mentioned processing is performed by reading and executing this program by the computer. A specific example of a computer is shown below.
FIG. 10 is a schematic block diagram showing the configuration of a computer according to at least one embodiment.
The computer 5 includes a CPU 6, a main memory 7, a storage 8, and an interface 9, as shown in FIG.
For example, each of the above-described correction system 1, correction device 30, and other control devices is implemented in the computer 5. The operations of each processing section described above are stored in the storage 8 in the form of a program. The CPU 6 reads the program from the storage 8, expands it to the main memory 7, and executes the above processing according to the program. Further, the CPU 6 reserves storage areas corresponding to each of the above-mentioned storage units in the main memory 7 according to the program.

Examples of the storage 8 include HDD (Hard Disk Drive), SSD (Solid State Drive), magnetic disk, magneto-optical disk, CD-ROM (Compact Disc Read Only Memory), and DVD-ROM (Digital Versatile). (Disc Read Only Memory) , semiconductor memory, etc. Storage 8 may be an internal medium directly connected to the bus of computer 5, or may be an external medium connected to computer 5 via interface 9 or a communication line. Furthermore, when this program is distributed to the computer 5 via a communication line, the computer 5 that receives the program may develop the program in the main memory 7 and execute the above processing. In at least one embodiment, storage 8 is a non-transitory tangible storage medium.

Further, the program may realize some of the functions described above. Furthermore, the program may be a file that can realize the above-described functions in combination with a program already recorded in the computer system, a so-called difference file (difference program).

Although several embodiments of the disclosure have been described, these embodiments are examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and changes may be made to these embodiments without departing from the spirit of the disclosure.

1... Correction system 5... Computer 6... CPU
7... Main memory 8... Storage 9... Interface 10... AC coupling circuit 20... AD conversion circuit 30... Correction device 301... Peak search circuit 302... Pulse signal extraction Circuit 303...Offset value calculation circuit 304...Sampling period calculation unit 305...Adder

In order to achieve the above object, according to one aspect of the present disclosure, a correction device includes a sampling means for sampling a voltage at a peak point of a pulse signal in a digital signal and a voltage at an intermediate point between the pulse signals; The apparatus includes case dividing means for performing case classification based on the sampling result by the sampling means, and correction means for correcting the offset voltage of the pulse signal according to the result of the case dividing performed by the case dividing means.

In order to achieve the above object, according to another aspect of the present disclosure, the correction system includes an AC coupling circuit that is capable of transmitting an alternating current signal of a predetermined frequency or higher, and cannot transmit an alternating current signal and a direct current signal of less than the predetermined frequency. and an AD conversion circuit that generates a digital signal by quantizing an AC signal having a frequency equal to or higher than the predetermined frequency output by the AC coupling circuit, and the correction device described above.

In order to achieve the above object, according to another aspect of the present disclosure, a correction method includes sampling a voltage at a peak point of a pulse signal in a digital signal and a voltage at an intermediate point between the pulse signals; The method includes dividing the case based on the result, and correcting the offset voltage of the pulse signal according to the result of the case division.

In order to achieve the above object, according to another aspect of the present disclosure, a program causes a computer to sample a voltage at a peak point of a pulse signal in a digital signal and a voltage at an intermediate point between the pulse signals. , perform case classification based on the sampling result, and correct the offset voltage of the pulse signal according to the result of the case separation.

Claims (9)

Sampling means for sampling the voltage between pulse signals in the digital signal;
a correction means for correcting an offset voltage for the pulse signal;
A correction device comprising: Case dividing means for classifying cases according to the positive or negative sign of the pulse signal;
Equipped with
The correction means is
correcting the offset voltage for the pulse signal according to the result of the case classification performed by the case classification means;
A correction device according to claim 1. The correction means is
When the case classification means performs case classification using a first combination, adding an absolute value of a second reference voltage before the pulse signal to the first reference voltage after the pulse signal as an offset value. correcting the pulse signal by;
A correction device according to claim 2. The correction means is
When the case dividing means performs a second combination of cases, an offset is obtained by multiplying the first reference voltage after the pulse signal by -1 by the absolute value of the second reference voltage before the pulse signal. correcting the pulse signal by adding values;
A correction device according to claim 2. The correction means is
When the case dividing means performs a third combination of cases, an offset is obtained by multiplying the first reference voltage after the pulse signal by -1 by the absolute value of the second reference voltage before the pulse signal. correcting the pulse signal by adding values;
A correction device according to claim 2. The correction means is
When the case dividing means performs a fourth combination of cases, adding the absolute value of a second reference voltage before the pulse signal to the first reference voltage after the pulse signal as an offset value. correcting the pulse signal by;
A correction device according to claim 2. an AC coupling circuit that is capable of transmitting alternating current signals of a predetermined frequency or higher, and cannot transmit alternating current signals and direct current signals of less than the predetermined frequency;
an AD conversion circuit that generates a digital signal by quantizing an AC signal having a frequency equal to or higher than the frequency outputted by the AC coupling circuit;
A correction device according to any one of claims 1 to 6,
A correction system equipped with. sampling the voltage between pulse signals in the digital signal;
correcting an offset voltage for the pulse signal;
Correction methods including. to the computer,
sampling the voltage between pulse signals in the digital signal;
correcting an offset voltage for the pulse signal;
A program to run.

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