CN109633228B

CN109633228B - Sampling method and device in oscilloscope and oscilloscope

Info

Publication number: CN109633228B
Application number: CN201811625852.4A
Authority: CN
Inventors: 郑文明; 李振军; 王永添
Original assignee: Shenzhen Siglent Technologies Co Ltd
Current assignee: Shenzhen Siglent Technologies Co Ltd
Priority date: 2018-12-28
Filing date: 2018-12-28
Publication date: 2021-06-15
Anticipated expiration: 2038-12-28
Also published as: CN109633228A

Abstract

The embodiment of the invention provides a sampling method in an oscilloscope, which is used for synchronizing a multi-channel digital level signal to obtain a synchronized signal; sampling the synchronized signals to obtain sampling signals, wherein sampling is carried out according to the sampling period determined at the current time in each sampling process; and decoding the sampling signal to obtain a decoded signal. Based on the scheme, the sampling is carried out according to the sampling period determined at the current time in each sampling process, and the sampling is not carried out according to the same sampling period all the time, so that the sampling period can be reasonably set in each sampling process, the reasonable segmentation of the sampling points is realized, and the problem of inaccurate sampling result is solved. The embodiment of the invention also provides a sampling device in the oscilloscope and the oscilloscope.

Description

Sampling method and device in oscilloscope and oscilloscope

Technical Field

The invention relates to the technical field of data decoding, in particular to a sampling method and device in an oscilloscope and the oscilloscope.

Background

In the field of modern test measurement, in order to cope with the increasing complexity of electronic product design, oscilloscopes are developing towards high bandwidth, high sampling rate and high storage depth. In addition, the prior oscilloscopes integrate the triggering and decoding functions of serial protocols, and the common serial protocols include I2C, UART, SPI, CAN, LIN and the like, which greatly facilitates the debugging of users.

The processing flow diagram of the existing serial protocol decoding is shown in fig. 1, and may include the following steps:

1) reading decoded data;

since the decoded data is cached in the DDR3 where the programmable logic device resides, the first step requires that the original data be read from the programmable logic device to the memory of the CPU.

2) Converting 0/1 the decoded data into digital levels according to the set threshold level;

this step may be omitted when the decoded data source is a digital channel;

3) determining sampling points according to the relation between the sampling rate and the baud rate;

only certain protocols such as UART/LIN/CAN, etc. are applicable;

4) analyzing according to a specific protocol to obtain a decoding result;

the decoding result comprises the content of each field, the position information and the like;

5) and displaying the decoding result.

However, the above technical solutions have at least the following disadvantages:

the first, existing scheme employs software for decoding. The original point data needs to be read firstly, and when the storage depth is large, the link needs to spend much time. And the above 5 steps are performed serially, limiting the efficiency of decoding. When the storage depth is large, in order to increase the processing speed, the decoded data is usually compressed properly and then sent to the CPU, which inevitably loses a part of the information.

Secondly, aiming at the serial protocol with baud rate parameters, the position of a sampling point is determined according to the sampling rate of the current time base and the baud rate set by a user. When the ratio of the sampling rate to the baud rate is not an integer, only the integer part is usually considered, but this tends to result in serial bit errors being recovered. For example, when the ratio of the sampling rate to the baud rate is 3.5, each bit is sampled 3 or 4 times by an integer. However, in this way, accumulation over time produces an error of 1 sample (1 more or 1 less), which often results in decoding errors for subsequent sub-modules.

Taking fig. 2 and fig. 3 as an example, each serial bit lasts for 7 clk (0-6), and the sampling period is 2 clk, i.e. the sampling rate is 3.5 times the baud rate. The sampled sequence is 111_0000_111_0000_ 111. If the decoding process is performed at a sampling rate 3 times the baud rate (fig. 2), the recovered serial bit is 10_10_01 (the middle bit is taken). Similarly, if the decoding process is performed at a sampling rate 4 times the baud rate (fig. 3), an error result 10_10 (the 2 nd bit is obtained).

Disclosure of Invention

In order to at least partially solve the problems in the prior art, embodiments of the present invention are intended to provide a sampling method and apparatus in an oscilloscope, and an oscilloscope.

According to a first aspect, an embodiment provides a sampling method in an oscilloscope, comprising:

synchronizing the multi-channel digital level signals to obtain synchronized signals;

and sampling the synchronized signal to obtain a sampling signal, wherein sampling is carried out according to the determined sampling period in each sampling process.

According to a second aspect, there is provided in one embodiment a sampling apparatus in an oscilloscope, the apparatus comprising: a synchronization module and a sampling module; wherein the content of the first and second substances,

the synchronization module is used for synchronizing the multi-channel digital level signals to obtain synchronized signals;

and the sampling module is used for sampling the synchronized signals to obtain sampling signals, wherein sampling is carried out according to the sampling period determined at the current time in each sampling process.

According to a third aspect, there is provided in an embodiment an oscilloscope, comprising:

a memory for storing a program;

a processor for implementing the method according to the first aspect by executing a program stored in the memory.

According to a fourth aspect, an embodiment provides a computer-readable storage medium comprising a program for execution by a processor to implement the method according to the first aspect as described above.

Compared with the prior art, the embodiment of the invention at least has the following advantages:

the sampling method in the oscilloscope provided by the embodiment of the invention comprises the following steps: synchronizing the multi-channel digital level signals to obtain synchronized signals; sampling the synchronized signals to obtain sampling signals, wherein sampling is carried out according to the sampling period determined at the current time in each sampling process; and decoding the sampling signal to obtain a decoded signal.

Based on the technical scheme provided by the embodiment of the invention, the method at least has the following beneficial effects:

when the ratio of the sampling rate to the baud rate is not an integer, the sampling is carried out according to the sampling period determined at the current time in each sampling process, rather than the sampling is carried out according to the same sampling period all the time, so that the sampling period can be reasonably set in each sampling process, the reasonable segmentation of the sampling points is realized, and the problem of inaccurate sampling result is solved.

Drawings

FIG. 1 is a flow diagram of a prior art serial protocol decoding process;

FIG. 2 is a diagram illustrating a conventional serial decoding result;

FIG. 3 is a diagram illustrating a conventional serial decoding result;

FIG. 4 is a flow chart of a sampling method in an oscilloscope of the present invention in one embodiment;

FIG. 5 is a first exemplary diagram of sampling according to the sampling method in an oscilloscope according to the present invention;

FIG. 6 is an exemplary graph one of sampling according to the prior art;

FIG. 7 is an exemplary graph two of sampling according to the prior art;

FIG. 8 is a second exemplary diagram of sampling in an oscilloscope according to the sampling method of the present invention;

FIG. 9 is a block diagram of a sampling device in an oscilloscope according to an embodiment of the present invention;

FIG. 10 is a block diagram of a sampling device in an oscilloscope according to a second embodiment of the present invention;

fig. 11 is a block diagram showing the configuration of a sampling apparatus in an oscilloscope according to a third embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).

Example one

The embodiment of the invention provides a sampling method in an oscilloscope, and with reference to fig. 4, the method comprises the following steps:

step 401, synchronizing the multi-channel digital level signal to obtain a synchronized signal;

step 402, sampling the synchronized signal to obtain a sampling signal, wherein sampling is performed according to a sampling period determined at the current time in each sampling process;

when the ratio of the sampling rate to the baud rate of the synchronized signal is not an integer, if the prior art scheme is adopted, sampling is always performed according to the same sampling period, it is inevitable that, in the sampling process, a value on a transition edge of the synchronized signal is located in the middle of a plurality of sampling points obtained by current sampling, so that when a sampling output value of current sampling is determined, if the middle is just two different values (0 and 1), one value is randomly selected according to the situation, a large deviation of a sampling result occurs, and as sampling is performed, errors are gradually accumulated, and the deviation of the sampling result is increased, so that in order to avoid the deviation, a proper sampling period needs to be determined in each sampling process, and sampling is performed according to the sampling period determined at the current time.

Even when the ratio of the sampling rate and the baud rate of the synchronized signal is an integer, there may be a case where the sampling timing is at a transition edge of the synchronized signal, so that the sampling result deviation is large.

In practical application, how to ensure that a point on a transition edge of a synchronized signal in each sampling process is a point of an edge position in a plurality of sampling points obtained by sub-sampling is realized in the following two ways:

the first mode is as follows:

detecting a transition edge of the synchronized signal;

when the count value of the sampling bit counter is 0, starting to detect each bit of data in the synchronized signal until a jump edge is detected;

adding 1 to the count value of the sampling bit counter every time 1bit data is detected;

when the jumping edge of the synchronized signal is detected, clearing a counter of the sampling bit;

determining the count value before the sampling bit counter is cleared to be the current sampling period;

and reads the sampling result from the data detected at the current time according to the current sampling period.

The data detected at this time as described above means data detected from when the count value of the sampling bit counter is 0 until the count value of the sampling bit counter is set to 0 again.

For example, assuming that the count value of the sampling bit counter is 5 before the count value of the sampling bit counter is set to 0 again from the time when the count value of the sampling bit counter is set to 0, the 5 is determined as the sampling period of the current sampling, the first 5 data from the 6 data detected at the current time are read as the sampling data of the current sampling, and the sampling result of the current sampling is read therefrom. The sampling result of the current sample is typically determined by determining the intermediate data value as the current sampling result.

Fig. 5 is an exemplary diagram of sampling according to the first mode, and as shown in fig. 5, a transition edge (from 0 to 1 or from 1 to 0) of the synchronized signal is detected, and the counter of the sampling bit is cleared again once the transition edge is detected. Referring to fig. 5, in this example, the data corresponding to the time when the count value is equal to 1 is taken as the recovered serial data by default, and the finally recovered serial data is: 10_10_ 1.

The second mode is as follows:

and determining a sampling period which enables the accumulated sampling error to be smaller according to the ratio of the sampling rate and the baud rate of the synchronized signal, and sampling according to the sampling period.

Specifically, the determining, according to a ratio of a sampling rate to a baud rate of the synchronized signal, a sampling period in which an accumulated sampling error is small, and sampling according to the sampling period includes:

determining the ratio of the sampling rate and the baud rate of the synchronized signal, and determining an integer part in the ratio;

before a sampling period begins, determining a current accumulated sampling error, respectively determining sampling errors when the sampling period is equal to the value of the integer part and equal to the value of the integer part plus one, and respectively adding the two determined sampling errors with the current accumulated sampling error to obtain new accumulated sampling errors;

determining a sampling period corresponding to the sampling error which enables the new accumulated sampling error to be smaller as a current sampling period;

sampling is carried out once according to the current sampling period, and the next sampling period is entered.

In the above method, when two new accumulated sampling errors are equal, randomly determining the value of the integer part as a sampling error or determining the value of the integer part plus one as a sampling error; or, determining the value of the integer part as a sampling error; alternatively, the value of the integer part plus one is determined as the sampling error.

In one embodiment, the process of calculating the sampling period in the second way is as follows:

and calculating an integer part (i _ ratio _ integer) and a fractional part (i _ ratio _ remaining) of the ratio of the sampling rate and the baud rate set by a user. Where the fractional part is quantized with 7 bits (. 2^ 7). Calculating the error (taking the absolute value) under the two conditions that the sampling period is equal to i _ ratio _ integer and i _ ratio _ integer +1 in real time

The calculation process is as follows:

1) initial state value:

left＝～i_ratio_remainder+1

right ═ i _ ratio _ remaining (1< <7) >; // positive number

sum＝0

2) Calculation process

offset_left＝sum+left

offset_right＝sum+right

sum＝(abs(offset_left)<＝abs(offset_right))？offset_left:offset_right

sample_period＝(abs(offset_left)<＝abs(offset_right))？i_ratio_integral:(i_ratio_int egral+1)

Where left represents an error introduced when the ratio of the sampling rate to the baud rate is not an integer, and the sampling period is rounded down. If the ratio of the sampling rate to the baud rate is 3.5 and the sampling period is rounded down to 3, the error introduced is-0.5. In the specific implementation, the decimal is quantized and then processed;

right denotes the error introduced by rounding up the sampling period when the ratio of the sampling rate to the baud rate is not an integer. If the ratio of the sampling rate to the baud rate is 3.5, and the sampling period is rounded up to 4, the error introduced is + 0.5. In the specific implementation, the decimal is quantized and then processed;

offset _ left represents the accumulated error introduced when the sampling period is rounded down;

offset _ right represents the cumulative error introduced when the sampling period is rounded up.

sum represents the final accumulated error. The absolute values of offset _ left and offset _ right are compared, and the smaller absolute value is taken as the accumulated error.

In an optional implementation manner of the present invention, the sampling the synchronized signal to obtain a sampled signal includes:

when the ratio of the sampling rate to the baud rate is more than or equal to 10, carrying out parallel sampling on the synchronized signals; when the ratio of the sampling rate to the baud rate is less than 10, serially sampling the synchronized signals; when the ratio of the sampling rate to the baud rate is more than or equal to 10, 1bit sampling point is output by 1 clock, and when the ratio of the sampling rate to the baud rate is equal to 10, 1 sampling point is output by each clock;

in the parallel sampling process, synchronous signals to be sampled and decoded are processed in parallel, for example, 10-bit data is input by each clock; in the serial sampling process, signals to be sampled and decoded after synchronization are processed in a serial mode, firstly, 10-bit data input by each clock are converted into 1-bit serial data, and then serial data streams are sampled.

When the synchronized signal is subjected to serial sampling, data is cached through the FIFO, and a busy signal is sent to the data sending end when the FIFO is full, the data sending end is informed to suspend sending the data, and when the FIFO is empty, the data sending end is informed to send the data.

In an alternative embodiment of the invention, the method further comprises: and decoding the sampling signal to obtain a decoded signal.

Specifically, the decoding the sampling signal includes: receiving a decoding instruction input by a user, wherein the decoding instruction comprises a decoding mode and decodes a sampling signal according to the decoding mode contained in the decoding instruction; wherein the decoding mode comprises at least one of the following decoding modes:

UART decoding, LIN decoding, CAN decoding, SPI decoding, and I2C decoding.

To sum up, a sampling method in an oscilloscope according to a first embodiment of the present invention includes: synchronizing the multi-channel digital level signals to obtain synchronized signals; sampling the synchronized signal to obtain a sampling signal, wherein when the ratio of the sampling rate to the baud rate of the synchronized signal is not an integer, a point on a jump edge of the synchronized signal is ensured to be a point at an edge position in a plurality of sampling points obtained by sub-sampling in each sampling process.

when the ratio of the sampling rate to the baud rate is not an integer, the sampling is carried out according to the sampling period determined at the current time in each sampling process, rather than the sampling is carried out according to the same sampling period all the time, so that the sampling period can be reasonably set in each sampling process, the reasonable segmentation of the sampling points is realized, the problem of inaccurate sampling result is solved, and the accuracy of the subsequent decoding process is ensured.

The sampling method in the oscilloscope provided by the invention is described in detail by a specific example.

This example illustrates an input signal that lasts 5 high levels, with a ratio of sample rate to baud rate of 3.5. In this example, the ratio of the sampling rate to the baud rate is 3.5, and if only the integer part of the ratio is considered and the sampling period is determined to be 3 or 4, there is a problem that the recovered serial data is more or less than the true value. Conversely, in the second way described above, this problem can be avoided.

Fig. 6 is a schematic diagram of the processing according to the sampling period equal to 3, and 6 pieces of 1 are recovered as shown in fig. 6. Fig. 7 is a schematic diagram of the processing according to the sampling period equal to 4, and as shown in fig. 7, 4 1 s are recovered. While the actual input signal is 5 1 s. Therefore, when the ratio of the sampling rate to the baud rate is a fraction, if the processing is performed only in an integer part, the number of bits of the recovered data is always more or less than the true value as time accumulates (no level jump occurs for a long time).

Fig. 8 is a schematic diagram of processing by using a dynamic sampling period variation mode, and as shown in fig. 8, the recovery result is: 5, 1.

The following describes the calculation process of the sampling period in detail:

because the ratio of the sampling rate to the baud rate is 3.5, the errors introduced with a sampling period equal to 3 and equal to 4 are 3-3.5-0.5 and right-4-3.5 +0.5, respectively.

Sampling for the first time: the initial error is 0, so offset _ left and offset _ right are-0.5 and +0.5, respectively, corresponding to index 1 in Table 1. Since the absolute values of both are equal, a sampling period equal to 3 or 4 is sufficient, 3 being chosen in this example, this time with an introduced error sum of-0.5.

Serial number	offse_left	offset_right	sum	Sampling period
					1	-0.5	+0.5	-0.5	3
2	-1	0	0	4
					3	-0.5	+0.5	-0.5	3
4	-1	0	0	4

TABLE 1

And (3) second sampling: if a sampling period of 3 is still selected, the error introduced is offset _ left + left-0.5 + (-0.5) — 1; if a sampling period of 4 is chosen, the error introduced is offset _ right + sum-0.5 + 0.5-0; since the absolute value of the accumulated error when the sampling period is selected to be equal to 4 is smaller than the absolute value when the sampling period is selected to be equal to 3, the sampling period is selected to be equal to 4 this time.

By analogy, it can be seen that with this approach the sampling period varies continuously between 3 and 4, so that the error remains within 1 sample point at all times.

Example two

Referring to fig. 9, a second embodiment of the present invention provides a sampling apparatus in an oscilloscope, where the apparatus includes: a synchronization module 91, a sampling module 92 and a decoding module 93; wherein the content of the first and second substances,

the synchronization module 91 is configured to synchronize the multi-channel digital level signal to obtain a synchronized signal;

the sampling module 92 is configured to sample the synchronized signal to obtain a sampled signal, where sampling is performed according to a current determined sampling period in each sampling process.

Specifically, the signal synchronized by the synchronization module 91 is a digital level signal, referring to fig. 1, the synchronization module 91 may receive a plurality of channel data, where ch1 to ch4 are analog channels, MSO is a digital channel, data in the analog channel needs to be converted into a digital signal by a level comparison module before entering the synchronization module 91, and a signal in the digital channel is directly sent to the synchronization module 91.

Because the data of ch1, ch2, ch3, ch4 and MSO channels have different time to enter the following modules, it is necessary to use RAM or FIFO buffer in the synchronization module 91 and then read them at the same time to ensure that the data output from the synchronization module 91 is synchronized.

Specifically, the sampling module 92 includes: a first judgment unit 9201, a parallel sampling unit 9202 and a serial sampling unit 9203; wherein the content of the first and second substances,

the first judging unit 9201 is configured to send the synchronized signal to the parallel sampling unit 9202 for parallel sampling when a ratio of a sampling rate to a baud rate is greater than or equal to 10; when the ratio of the sampling rate to the baud rate is less than 10, sending the synchronized signal to a serial sampling unit 9203 for serial sampling; wherein the content of the first and second substances,

when the synchronized signal is sent to the serial sampling unit 9203 for serial sampling, data is buffered through the FIFO, and a busy signal is sent to the synchronization module 91 when the FIFO is full, so that the data sending end is notified to suspend sending data, and when the FIFO is empty, the synchronization module 91 is notified to send data.

Specifically, the parallel sampling unit 9202 or the serial sampling unit 9203 in the sampling module 92 is configured to perform sampling in the following manner:

Correspondingly, when the sampling bit counter is set to 0 again, the next sampling is carried out, and the specific sampling mode is the same as the above.

Specifically, the parallel sampling unit 9202 or the serial sampling unit 9203 in the sampling module 92 is configured to perform sampling according to the following manner:

The parallel sampling unit 9202 or the serial sampling unit 9203 in the sampling module 92 is further configured to randomly determine the value of the integer part as a sampling error or determine the value of the integer part plus one as a sampling error when two new accumulated sampling errors are equal; or, determining the value of the integer part as a sampling error; alternatively, the value of the integer part plus one is determined as the sampling error.

In an alternative embodiment of the present invention, referring to fig. 10, the apparatus further comprises: and the decoding module 93 is configured to decode the sampling signal to obtain a decoded signal.

The decoding module 93 includes: a second judging unit 9301 and a plurality of different types of decoding modules 9302; wherein the content of the first and second substances,

the second judging module 9301 is configured to receive a decoding instruction input by a user, where the decoding instruction includes a decoding manner, determine the decoding manner included in the decoding instruction, and send the sampling signal to a decoding unit corresponding to the decoding manner for decoding;

each different type of decoding unit 9302 is configured to decode the sampling signal according to a respective decoding method to obtain a decoded signal; wherein the different types of decoding units 9302 include but are not limited to the following:

a UART decoding unit, a LIN decoding unit, a CAN decoding unit, an SPI decoding unit and an I2C decoding unit.

In an alternative embodiment of the present invention, referring to fig. 11, the apparatus further comprises: and a memory control module 94 for reading the decoded signal into the memory, and reading and displaying the decoded signal by the CPU.

Since a large number of frames of serial data are included in one frame of decoded signal, it is necessary to store the decoded result in the DDR3, and read and display the decoded result by software.

In a specific implementation process, the synchronization module 91, the sampling module 92, the decoding module 93, and the storage control module 94 may be implemented by a Central Processing Unit (CPU), a Micro Processing Unit (MPU), a Digital Signal Processor (DSP), or a Programmable logic Array (FPGA) in an oscilloscope.

EXAMPLE III

An embodiment of the present invention provides an oscilloscope, including:

a memory for storing a program;

a processor for implementing the method according to the first embodiment by executing the program stored in the memory.

Example four

A fourth embodiment of the present invention provides a computer-readable storage medium, which includes a program for execution by a processor to implement the method according to the first embodiment.

Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by computer programs. When all or part of the functions of the above embodiments are implemented by a computer program, the program may be stored in a computer-readable storage medium, and the storage medium may include: a read only memory, a random access memory, a magnetic disk, an optical disk, a hard disk, etc., and the program is executed by a computer to realize the above functions. For example, the program may be stored in a memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above may be implemented. In addition, when all or part of the functions in the above embodiments are implemented by a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a removable hard disk, and may be downloaded or copied to a memory of a local device, or may be version-updated in a system of the local device, and when the program in the memory is executed by a processor, all or part of the functions in the above embodiments may be implemented.

The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims

1. A method of sampling in an oscilloscope, the method comprising:

sampling the synchronized signals to obtain sampling signals, wherein sampling is carried out according to the sampling period determined at the current time in each sampling process;

ensuring that a point on a transition edge of the synchronized signal is a point of an edge position in a plurality of sampling points obtained by current sampling in each sampling process, wherein the points comprise:

2. The method of claim 1, wherein sampling at each sampling process according to the current determined sampling period comprises:

3. The method of claim 1, wherein when two new accumulated sampling errors are equal, randomly determining the value of the integer part as a sampling error or the value of the integer part plus one as a sampling error; or, determining the value of the integer part as a sampling error; alternatively, the value of the integer part plus one is determined as the sampling error.

4. The method according to any one of claims 1 to 3, wherein sampling the synchronized signal to obtain a sampled signal comprises:

when the ratio of the sampling rate to the baud rate is more than or equal to 10, carrying out parallel sampling on the synchronized signals; when the ratio of the sampling rate to the baud rate is less than 10, serially sampling the synchronized signals; wherein the content of the first and second substances,

5. The method of claim 4, further comprising: and decoding the sampling signal to obtain a decoded signal.

6. The method of claim 5, wherein decoding the sampled signal comprises: receiving a decoding instruction input by a user, wherein the decoding instruction comprises a decoding mode and decodes a sampling signal according to the decoding mode contained in the decoding instruction; wherein the decoding mode comprises at least one of the following decoding modes:

UART decoding, LIN decoding, CAN decoding, SPI decoding, and I2C decoding.

7. A sampling device in an oscilloscope, the device comprising: a synchronization module and a sampling module; wherein the content of the first and second substances,

the sampling module is used for sampling the synchronized signals to obtain sampling signals, wherein sampling is carried out according to the sampling period determined at the current time in each sampling process; ensuring that a point on a transition edge of the synchronized signal is a point of an edge position in a plurality of sampling points obtained by current sampling in each sampling process, wherein the points comprise:

8. An oscilloscope, comprising:

a memory for storing a program;

a processor for implementing the method of any one of claims 1-6 by executing a program stored by the memory.