JP2023133093A - time digital converter - Google Patents

Abstract

To provide a time digital converter with which it is possible to realize high accuracy, high resolution and high speed.SOLUTION: The present invention comprises reference count means that counts a main time interval TM as an integral multiple of a reference clock cycle, fraction count means that measures a fraction time interval TF as a surplus or shortage of the main time interval TM with respect to the time interval T, first signal generation means that generates a first signal for a first point of time t1, and second signal generation means that generates a second signal for a second point of time t2. The fraction count means includes a multiplication means group that connects to the first and second signal generation means, and phase shift means. The multiplication means group is composed of n multiplication means that generate a signal for sampling the signal corresponding to the fraction time interval TF at a multiply-by-m of the reference clock. The phase shift means shifts the phases of the signals respectively outputted by the n multiplication means by 360°/n at a time.SELECTED DRAWING: Figure 2

Description

The present invention relates to a time-to-digital converter, and particularly to a time-to-digital converter suitable for use in semiconductor inspection equipment (semiconductor tester).

2. Description of the Related Art Conventionally, there has been known a semiconductor testing apparatus for testing an object to be tested, such as an IC or an LSI, which measures the time of a signal (for example, see Patent Document 1).

By the way, various methods have been proposed to measure time and frequency, and representative ones include the universal count method, time expansion method, time-voltage conversion method, and time vernier method. .

For example, in the universal count method, time is measured by measuring a built-in reference clock input signal for a specified time. In addition, the time expansion method is a method of measuring time by converting it into voltage, and expands the pulse width by charging and discharging the pulse width of a fractional time using an integrating circuit.

Japanese Patent Application Publication No. 2003-139817

However, when measuring time as a function of a semiconductor inspection device, conventional methods have limitations.

In other words, semiconductor inspection equipment can measure time by being equipped with a time-to-digital converter, but in this case, FPGA (field field The adoption of time-to-digital converters using -programmable gate arrays has become common. Here, in a normal FPGA, the clock frequency is several 100 MHz, and the minimum measurable amount is limited to the nanosecond order.

On the other hand, for time-to-digital converters used in semiconductor inspection equipment, high measurement resolution, wide measurement dynamic range, and high measurement speed are important, and currently, for example, about 100 ps It is desirable to measure with a resolution of . In this case, 10 GHz is required as the reference clock, and in order to achieve high precision, high resolution, and high speed, it becomes necessary to create an ASIC or separately design an analog circuit, and the time-to-digital converter is required. There is a problem of high cost. This applies not only to the universal count method but also to time-to-digital converters employing other conventionally known methods.

Further, although it is possible to perform high-precision, high-resolution measurements using an oscilloscope and a PC (personal computer), there is a limit to high-speed processing in this case.

In view of these circumstances, the present invention aims to provide a time-to-digital converter that can achieve high precision, high resolution, and high speed without requiring ASIC or analog circuit design.

The present invention is a time-to-digital converter that measures a time interval between a first time point and a second time point in an input waveform, the reference counting device counting the main time interval relative to the time interval as an integer multiple of the period of a reference clock. means, fraction counting means for counting a fractional time interval as an excess or deficiency of the main time interval with respect to the time interval; a first signal generating means for generating a first signal that triggers the first time point; a second signal generating means for generating a second signal that triggers two points in time; the fraction counting means includes a multiplier group connected to the first signal generating means and the second signal generating means; Shifting means, and the multiplication means group includes n (n is an integer of 2 or more), and the phase shift means shifts the phase of each of the signals generated by the n multiplication means by 360°/n. This relates to a time-to-digital converter.

According to the present invention, an excellent effect can be achieved in that a time-to-digital converter that can realize high precision, high resolution, and high speed can be provided without requiring ASIC or analog circuit design.

FIG. 1 is a diagram illustrating a time-to-digital converter according to the present embodiment, and includes (A) a schematic block diagram showing an example of a circuit configuration of the time-to-digital converter, and (B) a schematic diagram of time measurement in the time-to-digital converter. Moreover, FIG. 2 is a partially enlarged view of FIG. 1(C). It is a schematic diagram of time measurement in the time digital converter of this embodiment, and is a partially enlarged view of FIG. 1(C). FIG. 2 is a circuit block schematic diagram showing an example of a calculation means of the present embodiment. FIG. 2 is a circuit block schematic diagram showing an example of a fraction counting means of the present embodiment. 1 is a circuit block schematic diagram showing an example of a sampling circuit according to the present embodiment. FIG. It is an example of the sampling clock in the fraction counting means of this embodiment. This is an image taken of the state of the wiring from the signal generation means to the multiplication means in this embodiment. This is an image taken of the state of the wiring from the signal generation means to the multiplication means in this embodiment.

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings of this embodiment, parts denoted by the same reference numerals represent the same parts.

FIG. 1 is a diagram showing an outline of a time-to-digital converter 10 of this embodiment, and FIG. 1(A) is a schematic block diagram showing an example of the circuit configuration of the time-to-digital converter 10, and FIG. is a schematic diagram of time measurement in the time-to-digital converter 10 of this embodiment. Moreover, FIG. 2 is a partially enlarged view of FIG. 1(C).

Referring to FIG. 1A, the time-to-digital converter 10 of the present embodiment includes, for example, an attenuator 11, a filter circuit (for example, a low-pass filter) 12, a first signal generating means 13, and a second signal generating means 13. It has a generating means 14 and a calculating means 20. The calculation means 20 includes a counting means 15 (a reference counting means 16 and a fraction counting means 17), a counting/conversion means 19, and the like.

Referring to FIG. 3B, the time-to-digital converter 10 calculates the time interval T between the first time point t1 and the second time point t2 in the input waveform input via the attenuator 11 and the filter circuit 12. It is something to be measured. The time-to-digital converter 10 of this embodiment is connected, for example, to a not-shown DUT (object to be measured, such as a semiconductor device) upstream of the attenuator 11 (via a buffer circuit as necessary). In other words, in this example, the input waveform is, for example, a voltage waveform output from a semiconductor element to be measured. An example of time measurement in this case is between a first time t1 when the voltage (waveform) output by the DUT reaches va% (e.g. 20%) and a second time t2 when the voltage (waveform) output by the DUT reaches vb% (e.g. 80%). measurement of the time interval T, and so on. The time-to-digital converter 10 constitutes a semiconductor inspection device together with, for example, another information processing device (such as a PC).

The first time point t1 and the second time point t2 are each time points triggered by the generation of a predetermined signal (timing signal, trigger signal). The time-to-digital converter 10 includes, for example, a first signal generating means 13 and a second signal generating means 14, and the predetermined signal is a signal generated by the two signal generating means 13 and 14. That is, the first signal generating means 13 is a means for generating a first signal (timing signal, trigger signal) that is a trigger for the first time t1, and the second signal generating means 14 is a means for generating a first signal (timing signal, trigger signal) that is a trigger for the second time t2. This is means for generating a second signal (timing signal, trigger signal). The first signal generating means 13 and the second signal generating means 14 are, for example, a comparator A and a comparator B, respectively.

As an example, the first signal generating means 13 compares the first reference voltage Vref1 and the voltage Vin of the input waveform, and outputs "L" (turns off) when the voltage Vin of the input waveform is lower than the first reference voltage Vref1. ), when the voltage Vin of the input waveform becomes higher than the first reference voltage Vref1, the first signal "H" is output (turned on). The second signal generating means 14 compares the second reference voltage Vref2 and the voltage Vin of the input waveform, and outputs "L" (turns off) when the voltage Vin of the input waveform is lower than the second reference voltage Vref2, and inputs When the waveform voltage Vin becomes higher than the second reference voltage Vref2, the second signal "H" is output (turned on). That is, the output timing of the first signal ("H") is the first time t1, and the output timing of the second signal ("H") is the second time t2.

In the example shown in FIG. 3C, the timing at which the first signal generation means becomes "H" (first time point t1) is the timing to start measurement, and the timing at which the second signal generation means becomes "H" (second time point t1). Time t2) is the timing at which the measurement ends, and the time interval T from the first time t1 to the second time t2 is the measurement target.

The counting means 15 is a means for counting the time interval T based on a reference clock, and has a reference counting means 16 and a fraction counting means 17. Here, the reference clock is an internal clock generated by, for example, a phase locked loop (PLL) circuit based on an external clock input from, for example, a crystal oscillator. The reference counting means 16 is a means for counting the time interval T as an integral multiple of one cycle of the generated reference clock as the main sampling clock Main CLK. Specifically, referring to FIG. 2, the reference counting means 16 uses, for example, a reference clock (internal clock) with a frequency of 125 MHz (one period of 8 ns) as the sampling clock Main CLK, and calculates the number of clocks (integer number) included in the time interval T. ) is counted. Here, the arbitrary time interval T is not necessarily a time that is an integral multiple of one period of the sampling clock Main CLK (reference clock).

For example, when the starting point of the time interval T and the sampling clock Main CLK are synchronized, the reference counting means 16 uses the sampling clock Main CLK as the starting clock (first clock), and sets the sampling clock Main CLK as the starting point of the time interval T. If the sampling clock Main CLK is asynchronous, the first sampling clock Main CLK that arrives after the start time is set as the start clock (first clock). In addition, if the end point of the time interval T and the sampling clock Main CLK are synchronized, the main sampling clock CLK is set as the end clock (Nth clock, N is an integer), and the end point of the time interval T and the sampling clock If Main CLK is asynchronous, the first sampling clock Main CLK that arrives after the end point is set as the end clock (Nth clock, N is an integer). Then, the number of clocks (N-1 clocks) included in the time interval T is counted, and the time corresponding to the number of clocks is measured as the main time interval TM.

In the example shown in FIG. 2, both the first time point t1 and the second time point t2 are in the middle of one cycle of the sampling clock Main CLK, that is, the start time (t1) and the end time (t2) of the time interval T. Both are asynchronous with the sampling clock Main CLK. In this case, the reference counting means 16 converts the start clock (sampling clock Main CLK (“1” clock) which arrives first after the start point) to the end clock (sampling clock Main CLK (“1”) which arrives first after the end point). The number of clocks included up to the 12th clock (11=12-1) is counted as the sampling clock Main CLK included in the time interval T (corresponding to the main time interval TM).

Further, the fractional counting means 17 is means for counting the fractional time interval TF as the excess or deficiency of the main time interval TM with respect to the time interval T. That is, the time period less than one period of the sampling clock Main CLK (fractional time interval TF shown by hatching in FIG. 4(C)) is counted at a period shorter than one period of the sampling clock Main CLK (high resolution).

In the example shown in FIG. 5C, when the time interval T of the measurement target and the main time interval TM are compared, the time interval from the first time t1 to the rise of the start clock (first sampling clock Main CLK) (measurement start There is a time interval (fractional time interval on the measurement end side) TF1 from the second time point t2 to the rising timing of the end clock (12th sampling clock Main CLK) (fractional time interval on the measurement end side) TF2. The fraction counting means 17 counts the number of clocks corresponding to the fractional time interval TF1 and the fractional time interval TF2, but one cycle of the clock in this case is shorter than one cycle of the sampling clock Main CLK. will be described later.

The counting/converting means 19 calculates a time interval based on the counting result of the reference counting means and the counting result of the fractional counting means, and converts it into a digital value. Specifically, the time interval T is calculated by adding or subtracting the fractional time interval TF1 to the main time interval TM, and subtracting or adding (basically, subtracting) the fractional time interval TF2. In this example, time interval T = main time interval TM + fractional time interval TF1 - fractional time interval TF2. Further, the counting/converting means 19 digitally converts the calculated time interval T and outputs it.

The fraction counting means 17 will be explained with reference to FIGS. 3 to 6. 3 is a circuit block diagram schematically showing an example of the calculation means 20, FIG. 4 is a circuit block diagram schematically showing an example of the fraction counting means 17, and FIG. 5 is a circuit block diagram schematically showing an example of the fraction counting circuit 170. FIG. 6 is a circuit block diagram schematically showing an example of the sampling clock Main CLK in the fraction counting means 17.

As shown in FIG. 3, the calculation means 20 of this embodiment includes a reference counting means 16, a fraction counting means 17, and a counting/conversion means 19, and is configured by an FPGA (field-programmable gate array) application as an example. . The fraction counting means 17 receives data from the first signal generating means 13 and the second signal generating means 14 . The fraction counting means 17 is, for example, an element of an FPGA application, and is capable of executing processes such as frequency division, multiplication, and phase shift of a clock. Note that these processes may be configured by a digital clock manager (DCM).

In this embodiment, the fraction counting means 17 includes a multiplier group consisting of n multipliers 171 (n is an integer of 2 or more) and a phase shift means 172. Further, in this embodiment, the first signal generating means 13 and the second signal generating means 14 are each connected to a group of multiplying means. Since the structure of the multiplier group is the same, the multiplier group (multiplier means 171A to 171H) connected to the first signal generation means 13 will be explained below as an example, but the multiplier group connected to the second signal generation means 14 will be explained below. The same applies to the groups (multipliers 171I to 171P).

The multiplication means group is composed of a plurality of multiplication means 171 (for example, multiplication means 171A to 171H), and each of the multiplication means 171 is composed of, for example, a SERDES circuit (SERializer/DESerializer: serial-parallel mutual conversion circuit). The multiplier 171 multiplies the signal (data corresponding to fractional time intervals TF1, TF2) input from the first signal generating means 13 (second signal generating means 14) by m (m) the reference clock (sampling clock Main CLK). is an integer greater than or equal to 2).

Further, the n phase shift means 172 shift the phase of the multiplied sampling clock MCLK generated by the n multipliers 171 by 360°/n (the number of multipliers 171), for example, phase synchronization. This means includes a circuit (PLL circuit).

Here, as an example, n is 8 and m is also 8 (note that n and m may not be the same number). In other words, in the example shown in FIG. 3, the fraction counting means 17 is composed of a multiplication means group consisting of eight multiplication means (SERDES circuits) 171A to 171H and eight multiplication means (SERDES circuits) 171I to 171P. and a multiplier group. Each of the multipliers 171A to 171P generates a signal (multiplyed sampling clock MCLK (see FIG. 2)) that samples data corresponding to fractional time intervals TF1 and TF2 at 8 times the reference clock (sampling clock Main CLK). .

The phase shift means 172 shifts the phase of each multiplied sampling clock MCLK generated by one multiplier group (multipliers 171A to 171H) by 45° (=360/8°). The phase shift means 172 is provided corresponding to the multiplier means 171A to 171H, but in this embodiment, as an example, an inversion circuit (not shown) is provided for each of the four phase shift means (PLL circuits) 172 (172A to 172D). ) are provided as phase inversion circuits (phase shift means) 172E to 172H, thereby providing means for shifting the phase of the multiplied sampling clock MCLK generated by the multipliers 171A to 171H. Note that eight phase shift means (PLL circuits) 172A to 172H corresponding to the multipliers 171A to 171H may be provided without using the phase inversion circuit.

Further, in the circuit diagram shown in FIG. 3, as an example, a group of multiplying means (multiplying means 171A to 171H) connected to the first signal generating means 13 and a group of multiplying means (multiplying means 171I) connected to the second signal generating means 14 are shown. 171P), phase shift means 172A to 172H, reference counting means 16, and counting/conversion means 19 are shared. However, the structure is not limited to this, and the phase shift means 172, the reference counting means 16, and the counting/converting means 19 may be provided corresponding to each group of multiplier means.

This will be explained in detail with reference to FIG. 4. This figure is a circuit block diagram showing an extracted fraction counting means 17 (a group of multiplier means connected to the first signal generating means 13) of FIG. 3.

The phase shift means 172A shifts the multiplied sampling clock MCLK generated by the multiplication means 171A to the same phase (phase 0°) as the rising timing (hereinafter referred to as reference timing) of one cycle of the reference clock (sampling clock Main CLK). and generates (generates, outputs) the multiplied sampling clock MCLK1.

The phase shifter 172C shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171C by 45 degrees from the reference timing to generate the multiplied sampling clock MCLK3.

The phase shifter 172E shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171E by 90 degrees from the reference timing, and generates the multiplied sampling clock MCLK5.

The phase shifter 172G shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171G by 135 degrees from the reference timing, and generates the multiplied sampling clock MCLK7.

The phase shift means 172B shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171B. In this example, the phase shift means 172B inverts the output of the phase shift means 172A by 180 degrees using an inversion circuit (not shown), thereby generating a multiplied sampling clock MCLK2 whose phase is shifted by 180 degrees from the reference timing. .

The phase shift means 172D shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171D. In this example, the phase shift means 172D inverts the output of the phase shift means 172C by 180 degrees using an inversion circuit (not shown), thereby generating a multiplied sampling clock MCLK4 whose phase is shifted by 225 degrees from the reference timing. .

The phase shift means 172F shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171F. In this example, the phase shift means 172F inverts the output of the phase shift means 172E by 180 degrees using an inversion circuit (not shown), thereby generating a multiplied sampling clock MCLK6 whose phase is shifted by 270 degrees from the reference timing. .

The phase shift means 172H shifts the phase of the multiplied sampling clock MCLK generated by the multiplier 171H. In this example, the phase shift means 172H uses an inversion circuit (not shown) to invert the output of the phase shift means 172G by 180 degrees, thereby generating a multiplied sampling clock MCLK8 whose phase is shifted by 315 degrees from the reference timing. .

In this way, a set of multiplication means 171 and phase shift means 172 constitute a sampling circuit 170, and fraction counting means 17 has a plurality of (eight here) sampling circuits 170A to 170H.

FIG. 5 is a schematic block diagram showing an example of the configuration of the sampling circuit 170 (for example, a sampling circuit 170A consisting of a multiplier 171A and a phase shifter 172A).

The multiplier 171 (for example, the multiplier 171A) includes a receiving circuit (for example, a flip-flop circuit) 201, a 1/m frequency divider 202, and a 1:m demultiplexer (Demux) 203. As described above, m is a multiplication number (multiplying rate; here, as an example, m=8). Further, the phase shift means 172 (for example, the phase shift means 172A) includes a PLL circuit 204 that multiplies the input signal and a phase adjuster 15.

The phase shift means 172 receives an input of an external clock CLK (here, for example, a 50 MHz crystal oscillator clock) and multiplies it by a factor of 20, for example, in the PLL path 204 to generate a 1 GHz clock RCLK. Further, the phase adjuster 205 generates a multiplication sampling clock MCLK by shifting (delaying) the phase of the clock RCLK by 360°/n (in this case, n=8) from the reference timing, and transmits the multiplication sampling clock MCLK to the reception circuit 201 of the multiplier 171. Output.

Here, the phase shift means 172A sets the phase shift amount from the reference timing to 0°, and the other phase shift means 172B to 172H shift the phase by 45° (=360°/8) from the reference timing.

The receiving circuit 201 of the multiplier 171 receives input data Din (data corresponding to the fractional time interval TF based on the first signal or the second signal) from the comparator (comparator A or comparator B), and A serial data signal having the number of bits (here, 8 bits) corresponding to the multiplication rate (here, 8) is transmitted bit by bit to the Demux 203 in synchronization with the multiplication sampling clock MCLK. That is, in this case, the input data Din is sampled at a cycle of 1 GHz.

The 1/n (hereinafter referred to as 1/8) frequency divider 202 divides the multiplied sampling clock MCLK (1 GHz) generated by the phase adjuster 205 by the reciprocal of the multiplication rate (1/8) to generate a divided clock (125 MHz). ) is generated. Moreover, this frequency (125 MHz) becomes an internal clock (sampling clock Main CLK).

The Demux 203 converts the serial data signal into an 8-bit parallel data signal based on the serial data signal output by the receiving circuit 201 and the frequency-divided clock (125MHz), and converts the serial data signal into an 8-bit parallel data signal in synchronization with the frequency-divided clock. It is output as a signal Dout. In other words, the output from the Demux 203 has the number of data multiplied (eight times) for one input of Din.

In each sampling circuit 170, the multiplied sampling clock MCLK whose phase is shifted by the phase adjuster 205, the parallel data signal Dout which is the output of the Demux 203, and the 125 MHz frequency divided clock (sampling clock Main CLK) whose frequency is divided by 1/8 are input. Both are generated from the 1 GHz clock RCLK and have the same phase.

Further, in each sampling circuit 170 (170A to 170H), the phase shift amount (phase change rate) by the phase adjuster 205 is 360°/n, and n in this case is the number of inputs to the receiving circuit 201. . The number of phase adjusters 205 required is equivalent to this number of inputs or this number of inputs/2 (if an inverting circuit is used).

With such a configuration, the fraction counting means 17 of this embodiment can obtain the sampling number (resolution) expressed by the following equation 1.

Number of sampling (resolution) =
Reciprocal of reference clock (sampling clock Main CLK)/(number of multipliers 171 (number of inputs) x multiplication number) (Formula 1)

Specifically, in the example of this embodiment, resolution=(1/125 MHz)/(8×8)=125 ps.

As a result, as shown in FIG. 6, the fraction counting means 17 artificially (apparently) multiplies the sampling clock Main CLK (125 MHz, resolution 1 cycle 8 ns) by 64 (1 GHz, resolution 1 cycle 125 ps). Fractional time intervals TF (signals based on the first signal and second signal) inputted by the sampling clocks MCLK1 to MCLK8 can be measured, and high-resolution sampling becomes possible.

In other words, the fractional time interval TF1 (the number of clocks corresponding to) based on the generation of the first signal shown in FIG. The number of clocks corresponding to 1) is similarly counted by the multiplied sampling clocks MCLK1 to MCLK8 of the fraction counting means 17.

The counting/conversion means 19 calculates the time interval T by calculating the number of clocks corresponding to the main time interval TM and the number of clocks corresponding to the fractional time intervals TF1 and TF2. In this example, time interval T=main time interval TM+fractional time interval TF1-fractional time interval TF2 (see FIG. 2). Further, the counting/converting means 19 digitally converts the calculated time interval T and outputs it.

Although detailed illustrations are omitted, for example, data sampled by shifting the phase (data acquired with multiplied sampling clocks MCLK1 to MCLK8 with phases of 45° to 315°) is processed by, for example, a counting/converting means. In step 19, all the signals are arranged (restored) to have the same phase (phase 0°) based on the sampling clock Main CLK (125 MHz), and are arranged (rearranged in order) before calculation is performed.

As described above, in this embodiment, n (eight in this example) multipliers 171 are provided that can generate a multiplier sampling clock that multiplies the reference clock (sampling clock Main CLK) by m (for example, by 8). As a result, for example, the sampling clock Main CLK of 125 MHz (one period of 8 ns) can be multiplied by 64 to obtain a multiplied sampling clock of 125 ps. Thereby, it is possible to count the fractional time intervals TF1 and TF2 with high resolution (high precision), and it is possible to provide a time-to-digital converter 10 suitable for use in a semiconductor inspection device that measures time of a DUT.

In addition, since the calculation means 20 (multiplication means 171, phase shift means 172, counting/conversion means 19, etc.) can be configured with FPGA, there is no need for ASIC analog circuit design, and high resolution ( high accuracy) can be achieved. Furthermore, conventionally, it has been possible to perform high-precision, high-resolution measurements by using an oscilloscope and a PC (personal computer), but there has been a limit to high-speed processing. According to this embodiment, since the calculation means 20 can be configured with an FPGA, not only high resolution (high precision) but also high-speed processing is possible.

Here, the structure of the multiplying means group (multiplier means 171A to 171H) connected to the first signal generating means 13 and the multiplying means group (171I to 171P) connected to the second signal generating means 14 is the same, and each multiplier In the means group, each wiring has the same length when connected to the multiplier means 171 that generates the multiplied sampling clock MCLK of the same phase.

Specifically, the first signal generating means 13 is connected to the multiplying means 171A (phase shift 0°) by the first wiring WA1, and the second signal generating means 14 is connected to the multiplying means 171I (phase shift 0°) and the second Connected by wiring WA2. The first wiring WA1 and the second wiring WA2 have the same length. Here, in this embodiment, the term "equal length" of the wirings means that the plurality of wirings (for example, the first wiring WA1 and the second wiring WA2) have the same design length and are substantially (almost) the same length. (there may be design errors, but the length has not been intentionally changed).

Similarly, the first signal generating means 13 is connected to the multiplying means 171B (phase shift 180°) by the first wiring WB1, and the second signal generating means 14 is connected to the multiplying means 171J (phase shift 180°B and the second wiring WB1). The first wiring WB1 and the second wiring WB2 have the same length.

Further, the first signal generating means 13 is connected to the multiplying means 171C (phase shift 45°) by the first wiring WC1, and the second signal generating means 14 is connected to the multiplying means 171K (phase shift 45°) C and the second wiring WC1. Connect via WC2. The first wiring WC1 and the second wiring WC2 have the same length.

Further, the first signal generating means 13 is connected to the multiplying means 171D (phase shift 225°) by the first wiring WD1, and the second signal generating means 14 is connected to the multiplying means 171L (phase shift 225°) and the second wiring WD2. Connect by. The first wiring WD1 and the second wiring WD2 have the same length.

Further, the first signal generating means 13 is connected to the multiplying means 171E (phase shift 90°) by the first wiring WE1, and the second signal generating means 14 is connected to the multiplying means 171M (phase shift 90°) and the second wiring WE2. Connect by. The first wiring WE1 and the second wiring WE2 have the same length.

Further, the first signal generating means 13 is connected to the multiplying means 171F (phase shift 270°) by the first wiring WF1, and the second signal generating means 14 is connected to the multiplying means 171N (phase shift 270°) F and the second wiring WF1. Connect via WF2. The first wiring WF1 and the second wiring WF2 have the same length.

Further, the first signal generating means 13 is connected to the multiplying means 171G (phase shift 135°) by the first wiring WG1, and the second signal generating means 14 is connected to the multiplying means 171O (phase shift 135°) and the second wiring WG2. Connect by. The first wiring WG1 and the second wiring WG2 have the same length.

Further, the first signal generating means 13 is connected to the multiplying means 171H (phase shift 315°) by the first wiring WH1, and the second signal generating means 14 is connected to the multiplying means 171P (phase shift 315°) and the second wiring WH2. Connect by. The first wiring WH1 and the second wiring WH2 have the same length.

7 and 8 are images taken of the actual state of wiring from the first signal generating means 13 and the second signal generating means 14 to the multiplying means 171. For example, FIG. 7(A) shows the multiplying means 171A, 171I, the first wiring WA1 and second wiring WA2 near the multipliers 171I, FIG. 1 wiring WC1 and second wiring WC2, Figure (B) is an image showing the first wiring WD1 and second wiring WD2 near the multipliers 171D and 171L. Note that, as described above, the multipliers 171A to 171D and 171I to 171L are incorporated in, for example, an FPGA.

By doing this, when counting the fractional time interval TF1 on the measurement start side and the fractional time interval TF2 on the measurement end side, the wiring lengths to the multiplying sampling clock generation means (multiplying means 171) having the same phase are made equal. That is, when measuring time triggered by the first signal outputted by the first signal generation means 13 and the second signal outputted from the second signal generation means 14, it is possible to avoid signal delays due to differences in wiring length.

In this embodiment, by apparently multiplying the sampling clock Main CLK by 64, sampling at one period of 125 ps is possible. On the other hand, the time interval T to be measured is the time between the timing triggered by the first signal and the timing triggered by the second signal (because two signals are used). The input delay of two signals becomes a fatal problem in measurements on the order of picoseconds.

Specifically, for example, if the wiring lengths of the first wiring WA1 and the second wiring WA2 are different, an unintended timing shift occurs in the first signal and/or the second signal input to the multiplier 171A (extreme In this example, the arrival timings of the first signal and the second signal are reversed, etc.), making accurate time measurement impossible.

In this embodiment, since the first signal and the second signal are inputted with the same wiring length to the multiplier group (171A to 171H, 171I to 171P) that generates multiplied sample clocks of the same phase, the hardware It can also guarantee absolute accuracy of time without any errors. More specifically, by arranging wires of equal length, it is possible to measure time with a length of one cycle or less of the reference clock, and it is possible to suppress errors in time delay (time measurement) to below the minimum resolution. Specifically, it changes depending on the reference clock frequency and the multiplier, but in this embodiment, by arranging the wires of equal length, the measurement error can be suppressed to the minimum resolution of 125 ps or less (in the case of one period of 8 ns).

In addition, since the phase shift means 172 and the counting/conversion means 19 are shared by the first signal generation means 13 and the second signal generation means 14 (the same means (circuit) is used), the device can be made smaller and lower in cost. This makes it possible to avoid variations in circuit performance and to perform highly accurate measurements.

Although the time-to-digital converter 10 of this embodiment has been described above, the number of signal generating means may be singular. That is, the timing of the rise and fall of a signal (first signal) of one signal generating means may be used as an opportunity to measure the time between the two timings. Further, the number of signal generating means may be three or more (for example, four).

Furthermore, in the above embodiment, the case where the number of input waveforms is one is illustrated, but there may be a plurality of input waveforms. For example, the first signal is a signal that specifies a certain timing of the input waveform a (for example, the first time t1 at which the input voltage a becomes 50%, etc.), and the second signal is a signal that specifies a certain timing of the input waveform b (for example, the first time point t1 when the input voltage a becomes 50%). The second time point t2 at which the voltage b becomes 50%, etc.) may be a signal that specifies the time interval T between the first time point t1 and the second time point t2.

Further, the first signal and/or the second signal may be triggered by a rising edge or may be triggered by a falling edge. In this way, this embodiment is applicable regardless of the time measurement method.

Further, in the above example, the phase shift means 172 and the counting/conversion means 19 connected to the first signal generation means 13 and the second signal generation means 14 are used, but the phase shift means 172 is It may be provided in each of the first signal generating means 13 and the second signal generating means 14.

In the above embodiment, the counting means 15 has a reference counting means 16 and a fraction counting means 17, and the fraction counting means 17 calculates a fraction as an excess or deficiency of the main time interval TM counted by the reference counting means 16. The configuration for counting the time interval TF is illustrated. However, the present invention is not limited to this, and may be configured such that the fraction counting means 17 performs counting during all periods of the time interval T to be measured (high-resolution counting is performed during all periods). In that case, in order to prevent malfunction due to noise in the vicinity of the first reference voltage Vref1 of the first signal generating means 13 (the same applies to the second signal generating means 14) due to high sensitivity (high resolution) measurement by the fraction counting means 17, It is desirable to adjust the sensitivity of the signal generating means 13. On the other hand, as in the above embodiment, by using the reference counting means 16 and the fractional counting means 17 together as the counting means 15, it is possible to save the capacity of the FPGA.

Also, for example, the frequency between a certain timing when the input voltage rises from 0% (for example, the timing when it becomes 50%) and a certain timing when it falls from 100% (for example, when it becomes 50%) is counted (used as a frequency counter). It may be something that does

Further, in the above embodiment, the multiplier group (multipliers 171A to 171H) connected to the first signal generating means 13 and the multiplier group (multipliers 171I to 171P) connected to the second signal generating means 14 have different multipliers. Although the case where they are a group of means has been exemplified, they may share one multiplier group.

It should be noted that the time-to-digital converter 10 of the present invention is not limited to the above-described embodiments, and it goes without saying that various changes may be made without departing from the gist of the present invention.

The time-to-digital converter of the present invention can be used, for example, in the field of semiconductor inspection equipment.

10 Time digital converter 11 Attenuator 12 Filter circuit 13 First signal generating means 14 Second signal generating means 15 Counting means 16 Reference counting means 17 Fractional counting means 19 Arithmetic means 171, 171A to 171H Multiplier means 172, 172A to 172H Phase Shift means TF, TF1, TF2 Fractional time interval TM Main time interval

Claims (7)

A time-to-digital converter that measures a time interval between a first time point and a second time point in an input waveform, the time-to-digital converter comprising:
reference counting means for counting the main time interval relative to the time interval as an integer multiple of the period of the reference clock;
Fractional counting means for counting fractional time intervals as an excess or deficiency of the main time interval with respect to the time interval;
a first signal generating means for generating a first signal that triggers the first point in time;
a second signal generating means for generating a second signal that triggers the second point in time;
Equipped with
The fraction counting means includes:
a group of multiplying means connected to the first signal generating means and the second signal generating means;
and a phase shift means;
The multiplier group includes n multipliers (n is an integer of 2 or more) that generates a signal for sampling the signal corresponding to the fractional time interval by m multiplication of the reference clock (m is an integer of 2 or more). Consists of means;
The phase shift means shifts the phase of each of the signals generated by the n multiplication means by 360°/n,
A time-to-digital converter characterized by: A plurality of the phase shift means are provided corresponding to the n multiplication means, and at least one of the phase shift means includes an inversion circuit and is shared by at least two multiplication means.
The time-to-digital converter according to claim 1, characterized in that: The number of the phase shift means is n/2,
3. The time-to-digital converter according to claim 2. each of the first signal generating means and the second signal generating means is a comparator;
The time-to-digital converter according to any one of claims 1 to 3, characterized in that: The input waveform is a voltage waveform output by the device under test,
The time-to-digital converter according to any one of claims 1 to 4, characterized in that: The m is 8,
The time-to-digital converter according to any one of claims 1 to 5, characterized in that: the n is 8;
The time-to-digital converter according to any one of claims 1 to 6, characterized in that: