JP2023119420A - wiring board - Google Patents

Abstract

To improve quality of a wiring board.SOLUTION: A wiring boar 1 of the embodiment has a first interlayer insulating layer 2, a first conductor layer 3 formed on the first interlayer insulating layer 2 and including a conductor pad 3a, a second conductor layer 4 formed on the opposite side of the first conductor layer 3 through the first interlayer insulating layer 2, and a solder resist layer 7 formed on the first interlayer insulating layer 2. The solder resist layer 7 has apertures 7a to expose the surface 3f1 and side surface 3f2 on the opposite side of the first interlayer insulating layer 2 in the conductor pad 3a. The wiring board 1 of the embodiment is further provided with a conductor pattern 5 formed between the first conductor layer 3 and the second conductor layer 4 so as to overlap the outer edge of the conductor pad 3a.SELECTED DRAWING: Figure 1

Description

The present invention relates to wiring boards.

Japanese Laid-Open Patent Publication No. 2004-100000 discloses a multilayer wiring board having a pad portion formed on an insulating layer and bonded to a semiconductor element. A solder resist is provided on the insulating layer, and the pads are arranged in the openings of the solder resist so as to be separated from the solder resist.

Japanese Patent Application Laid-Open No. 2004-22713

As in the pad portion disclosed in Patent Document 1, a conductor pad formed on an insulating layer and an underlying insulating layer have a difference in coefficient of thermal expansion between the conductor pad and the insulating layer, and an external contact connected to the conductor pad. Stress may be generated by the external force applied from other parts. Therefore, it is considered that problems such as cracks due to this stress are likely to occur in the conductor pads and the insulating layer in the vicinity thereof.

A wiring board according to the present invention comprises a first interlayer insulating layer, a first conductor layer formed on the first interlayer insulating layer and including a conductor pad, and the first conductor layer via the first interlayer insulating layer. and a solder resist layer formed on the first interlayer insulating layer. The solder resist layer has an opening that exposes a surface and a side surface of the conductor pad opposite to the first interlayer insulating layer, and the wiring board further overlaps the outer edge of the conductor pad. and a conductor pattern formed between the first conductor layer and the second conductor layer.

According to the embodiments of the present invention, it is possible to provide a high-quality wiring board in which defects such as cracks are less likely to occur in the insulating layer around the conductor pads provided on the wiring board.

1 is a cross-sectional view showing an example of a wiring board according to one embodiment of the present invention; FIG. The enlarged view of the II section of FIG. The arrow directional view seen from the A direction of FIG. FIG. 4 is a cross-sectional view showing an example of a state during a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a state during a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a state during a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a state during a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a state during a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a state during a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a state during a manufacturing process of a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a state during a manufacturing process of a wiring board according to one embodiment of the present invention;

A wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing an example of a wiring board according to one embodiment of the present invention. FIG. 2 is an enlarged view of part II of FIG. FIG. 3 is a view in the direction of arrow A in FIG. 3, illustration of the solder resist layer 7 is omitted for the sake of convenience.

In this specification, the side farther from the core insulating layer 20 in the thickness direction of the wiring board 1 to be described later is also referred to as "upper" or "outer", "upper", or simply "upper", and is closer to the core insulating layer 20. The side is also referred to as "underside" or "inside", "lower", or simply "lower". Further, in each conductor layer and each interlayer insulating layer, the surface facing away from the core insulating layer 20 is also called "upper surface", and the surface facing the core insulating layer 20 side is also called "lower surface". Further, the thickness direction of the wiring board 1 is also called "thickness direction Z" or simply "Z direction".

As shown in FIG. 1, the wiring board 1 has two surfaces extending in a direction perpendicular to the thickness direction Z of the wiring board 1, namely a first surface 11 and a surface opposite to the first surface 11. a certain second surface 12;

First, a schematic configuration of the wiring board 1 will be described. In the example shown in FIG. 1, the wiring board 1 includes an insulating layer 20 (hereinafter also referred to as a core insulating layer 20) located in the central portion of the wiring board 1 in the thickness direction Z, and both sides of the core insulating layer 20 (core insulating layer 20). Two main surfaces (first main surface 20a and second main surface 20b) of insulating layer 20 facing each other in thickness direction Z include conductor layers and insulating layers alternately laminated. On the first main surface 20a of the core insulating layer 20, each of three conductor layers 31 and each of two insulating layers 21 (hereinafter also referred to as interlayer insulating layers 21) are alternately laminated, and thereon, Furthermore, an insulating layer 23 (hereinafter also referred to as an interlayer insulating layer 23 ) is laminated, and a conductor layer 33 is formed on the interlayer insulating layer 23 . A solder resist layer 70 is formed on the interlayer insulating layer 23 . The number of conductor layers and insulating layers laminated on the first main surface 20a of the core insulating layer 20 is not limited to the number of layers described above, and may be an arbitrary number. .

On the other hand, on the second main surface 20b of the core insulating layer 20 opposite to the first main surface 20a, the two conductor layers 32 and the second conductor layer 4 and the two insulating layers 22 (hereinafter referred to as , and an interlayer insulating layer 22) are laminated alternately, and an insulating layer (first interlayer insulating layer) 2 is further laminated thereon, and a conductor layer (first conductor layer) 3 is formed. A solder resist layer 7 is formed on the first interlayer insulating layer 2 . The number of conductor layers and insulating layers laminated on the second main surface 20b of the core insulating layer 20 is not limited to the number of layers described above, and may be an arbitrary number. .

Through-hole conductors 20 c are formed in the core insulating layer 20 to connect the conductor layers 31 and 32 . Core insulating layer 20 , conductor layer 31 on first main surface 20 a , and conductor layer 32 on second main surface 20 b constitute a core substrate of wiring board 1 . Via conductors 6 (hereinafter also referred to as vias 6) for connecting the conductor layers sandwiching the first interlayer insulating layer 2 and the interlayer insulating layers 21 to 23 are provided in the first interlayer insulating layer 2 and the interlayer insulating layers 21 to 23, respectively. is formed.

Core insulating layer 20, first interlayer insulating layer 2 and interlayer insulating layers 21-23 are each formed using an insulating resin such as epoxy resin, bismaleimide triazine resin (BT resin), or phenol resin. The core insulating layer 20, the first interlayer insulating layer 2, and the interlayer insulating layers 21 to 23 contain a reinforcing material (core material) such as glass fiber, aramid fiber, or aramid nonwoven fabric and/or an inorganic filler such as silica. You can stay.

In this embodiment, the first conductor layer 3, the second conductor layer 4, the conductor layers 31 to 33, the vias 6, the through-hole conductors 20c, and the conductor pattern 5 described later are made of any metal such as copper or nickel. formed by, for example, a metal foil such as a copper foil and/or a metal film formed by plating, sputtering, or the like. Although the first conductor layer 3, the second conductor layer 4 and the conductor layers 31-33, the via 6, the through-hole conductor 20c and the conductor pattern 5 are shown in FIG. can have a multi-layered structure with For example, the conductor layer 31 and the conductor layer 32 formed on the first main surface 20a and the second main surface 20b sides of the core insulating layer 20 respectively include a metal foil, an electroless plated film, and an electrolytic plated film. It can have a layered structure. Also, the first conductor layer 3, the second conductor layer 4, the conductor layers 31 to 33, the vias 6, the through-hole conductors 20c, and the conductor pattern 5 each have a two-layer structure or a three-layer structure including, for example, an electroless plated film and an electrolytic plated film. It may have a layered structure (see Figure 2).

In this embodiment, the first interlayer insulating layer 2, the conductor layer 3, and the solder resist layer 7 are formed on the second surface 12 side of the wiring board 1, and the surface layer portion on the second surface 12 side of the wiring board 1 forming The second surface 12 is composed of exposed surfaces orthogonal to the Z direction in each of the first interlayer insulating layer 2, the conductor layer 3, and the solder resist layer 7. As shown in FIG.

In wiring board 1 , interlayer insulating layer 23 , conductor layer 33 , and solder resist layer 70 are formed on first surface 11 side of wiring board 1 . forming. The first surface 11 is composed of exposed surfaces orthogonal to the Z direction in each of the interlayer insulating layer 23, the conductor layer 33, and the solder resist layer 70. As shown in FIG.

Next, the wiring board 1 according to this embodiment will be described in more detail. As shown in FIGS. 1 and 2, a wiring board 1 according to this embodiment includes a first conductor layer 3, a first interlayer insulating layer 2, a second conductor layer 4, and a conductor pattern 5. there is Further, in this embodiment, the wiring board 1 further includes vias (via conductors) 6 . Moreover, in this embodiment, the wiring board 1 is provided with the solder resist layer 7 .

The first conductor layer 3 is formed on the first interlayer insulating layer 2 and includes conductor pads 3a. In this embodiment, the first conductor layer 3 includes a plurality of conductor pads 3a. Therefore, in this embodiment, the wiring board 1 is provided with a plurality of contact pads 3a on the second surface 12 thereof. The first conductor layer 3 is patterned to have conductor pads 3a of a predetermined shape and size. In the wiring board 1 shown in FIGS. 1 and 3, the first conductor layer 3 is patterned to have a plurality of conductor pads 3a. The conductor pad 3a has a substantially circular planar shape in the example shown in FIG. The "planar shape" is the shape of an object such as the contact pad 3a in plan view, and the "planar view" means viewing the object with a line of sight parallel to the Z direction. In addition, the shape of the conductor pad 3a is not limited to a substantially circular shape, and may be formed in a substantially rectangular shape, for example.

In the wiring board 1 of the example shown in FIG. 1, the second surface 12 may be a component mounting surface on which electronic components such as a semiconductor integrated circuit device are mounted, like the first surface 11 described later. good. Also, the second surface 12 may be a connection surface that is connected to an external element S1 when the wiring board 1 itself is mounted on an external element S1 such as an external wiring board, for example, a motherboard of any electrical equipment. . That is, the wiring board 1 may form part of a package for a component E1 such as a semiconductor integrated circuit mounted on the first surface 11, for example. In that case, the wiring board 1 may be mounted together with the component E1 on the external element S1 with the second surface 12 facing the external element S1 as shown in FIG.

When the second surface 12 is the connection surface with the external element S1, the second surface 12 may comprise a connection with the external element S1. The wiring board 1 in the example shown in FIG. 1 is connected to the external element S1 at the conductor pads 3a. Accordingly, the conductor pad 3a in the example shown in FIG. 1 is a connection pad that is connected to the external element S1 on the wiring substrate 1.

In the example shown in FIG. 1, the conductor pad 3a is not directly connected to other conductor pads and/or wiring patterns included in the first conductor layer 3 other than the conductor pad 3a. That is, the conductor pad 3a in the example shown in FIG. 1 is a so-called independent pad. In the example shown in FIG. 1, the conductor pads 3a are connected to via conductors 6 that connect the conductor layers (the first conductor layer 3 and the second conductor layer 4) sandwiching the first interlayer insulating layer 2. . Therefore, the conductor pad 3a in the example shown in FIG. 1 is also a so-called via pad.

Conductive pad 3a can be electrically and mechanically connected to electrode S11 of external element S1 by a bonding material such as solder, for example. The external element S<b>1 may be, as described above, a motherboard constituting any electrical device, or any electronic component having a package size larger than that of the wiring board 1 . The contact pads 3a can be connected to any substrate, electrical component, mechanical component, or the like, but not limited to these.

In the example shown in FIG. 2, the conductor pad 3a is composed of the conductive film that constitutes the first conductor layer 3. As shown in FIG. Specifically, the conductor pad 3 a includes an electroless plated film 111 formed in a predetermined pattern on the first interlayer insulating layer 2 and an electrolytic plated film 112 formed on the electroless plated film 111 . there is In the example shown in FIG. 2, the conductor pad 3a further includes the metal film 113 formed to cover the exposed portions of the electroless plated film 111 and the electrolytic plated film 112. It doesn't have to be.

In this embodiment, on the first surface 11 side (see FIG. 1) of the wiring board 1, the conductor layer 33 is formed on the interlayer insulating layer 23 and includes a plurality of component mounting pads 33a. Also, each conductor layer 31, 32, 33 is patterned to have a conductor pad and/or wiring pattern of a predetermined shape and size. Each component mounting pad 33a is a conductor pad on which a component E1 to be mounted on the wiring board 1 is mounted when the wiring board 1 is used. That is, the first surface 11 is the component mounting surface of the wiring board 1 . The electrode E2 of the component E1 is electrically and mechanically connected to the component mounting pad 33a via a bonding material (not shown) such as solder.

Examples of the components E1 include active components such as semiconductor integrated circuit devices and transistors, and electronic components such as passive components such as electrical resistors, but the components E1 are not limited to these. The component E1 may be, for example, a wiring material including fine wiring formed on a semiconductor substrate.

The first interlayer insulating layer 2 is a layer on which the first conductor layer 3 is formed on the outer side (upper side). In the present embodiment, the outermost (uppermost) interlayer insulating layer (first interlayer insulating layer 2) among one or more interlayer insulating layers on the second surface 12 side of the wiring board 1 has a two-layer structure. have. The first interlayer insulating layer 2 includes a second insulating layer 202 laminated on the interlayer insulating layer 22 under the first interlayer insulating layer 2 and a first insulating layer 201 on the second insulating layer 202 . I'm in. That is, the second insulating layer 202 is located on the second conductor layer 4 side in the thickness direction Z of the wiring board 1 . The first insulating layer 201 is located on the first conductor layer 3 side in the thickness direction Z of the wiring board 1 . The conductor pattern 5 is formed on the second insulating layer 202 and covered with the first insulating layer 201 . That is, the first insulating layer 201 is provided so as to cover the conductor pattern 5 formed on the second insulating layer 202 . The first insulating layer 201 and the second insulating layer 202 may be made of the same resin material, or may be made of different resin materials.

Further, in the present embodiment, the outermost (uppermost) interlayer insulating layer 23 among one or more interlayer insulating layers on the first surface 11 side of the wiring substrate 1 has a two-layer structure. . The two-layer structure includes a second insulating layer 232 laminated on the interlayer insulating layer 21 under the interlayer insulating layer 23 and a first insulating layer 231 on the second insulating layer 232 . In the example shown in FIG. 1, no conductor pattern is formed on the interlayer insulating layer 23 . A conductor pattern may be formed in the interlayer insulating layer 23 . For example, a conductor pattern may be formed on the second insulating layer 232 .

The second conductor layer 4 is formed on the side opposite to the first conductor layer 3 with the first interlayer insulating layer 2 interposed therebetween. In the example shown in FIGS. 1 and 2 , the second conductor layer 4 is formed on the interlayer insulating layer 22 under the first interlayer insulating layer 2 . The second conductor layer 4 is formed on the interlayer insulating layer 22 as a pattern continuous with the vias 6 formed in the interlayer insulating layer 22 below the first interlayer insulating layer 2 . The second conductor layer 4 is electrically connected to the first conductor layer 3 through vias 6 formed in the first interlayer insulating layer 2 .

A via 6 integrally formed with the first conductor layer 3 connects the first conductor layer 3 and the second conductor layer 4 . In this embodiment, vias 6 are formed in through-holes penetrating through first interlayer insulating layer 2 . In this embodiment, the vias 6 are formed in a frustum shape such that the diameter gradually decreases from the outside to the inside in the thickness direction Z of the wiring board 1 . The shape of the vias 6 is not limited to this. For example, the vias 6 may be formed in a columnar shape having a substantially constant width in the thickness direction Z of the wiring board 1 . The same applies to vias 6 formed in other interlayer insulating layers.

In this embodiment, the via 6 is formed inside the ring of the conductor pattern 5 . That is, in the present embodiment, the diameter (outer diameter) of the via 6 in the thickness direction Z of the wiring board 1 is smaller than the inner diameter of the conductor pattern 5 formed in a substantially annular shape.

The conductor pattern 5 is formed between the first conductor layer 3 and the second conductor layer 4 so as to overlap the outer edge of the conductor pad 3a. In the conductor pattern 5, when stress is generated in the first interlayer insulating layer 2 and cracks are generated in the first interlayer insulating layer 2 around the conductor pads 3a, the cracks are generated in the first interlayer insulating layer 2. Works not to expand. The stress generated in the first interlayer insulating layer 2 is caused by, for example, the difference in thermal expansion coefficient between the first interlayer insulating layer 2 and the conductor pads 3a formed on the first interlayer insulating layer 2, or the It is stress caused by an external force applied from an external component (for example, an external element S1 such as a motherboard of an electric device).

In other words, the conductor pattern 5 functions as a stopper that prevents the crack from expanding when the crack occurs in the first interlayer insulating layer 2 positioned around the conductor pad 3a. For example, due to the stress described above, a crack occurs in the first interlayer insulating layer 2 from the position in contact with the outer edge of the conductive pad 3a toward the inner side (toward the core insulating layer 20) in the thickness direction Z of the wiring board 1. Even in such a case, the wiring board 1 can prevent the crack from expanding by providing the conductor pattern 5 .

That is, the above-mentioned stress is applied to the boundary between the region in contact with the conductor pad 3a and the region not in contact with the conductor pad 3a in the first interlayer insulation layer 2, that is, the conductor stress in the first interlayer insulation layer 2. It is conceivable that it tends to occur intensively at the position where it contacts the outer edge of the pad 3a. Then, the first interlayer insulating layer 2 cannot withstand the concentrated stress, and cracks may occur from the portion in contact with the outer edge of the conductor pad 3a. However, in this embodiment, the conductor pattern 5 is formed between the first conductor layer 3 and the second conductor layer 4 so as to overlap the outer edge of the conductor pad 3a. When a crack occurs in the , it is possible to dam the expansion of the crack.

The configuration of the conductor pattern 5 will be described in more detail. The conductor pattern 5 is formed between the first conductor layer 3 and the second conductor layer 4 in the thickness direction Z of the wiring board 1 so as to overlap the outer edge of the conductor pad 3a in the thickness direction Z of the wiring board 1. It is In the examples shown in FIGS. 1 to 3, the conductor pattern 5 is formed with a predetermined gap from the first conductor layer 3 in the thickness direction Z of the wiring board 1. As shown in FIG. That is, the conductor pattern 5 is formed with a predetermined gap from the conductor pad 3a in the thickness direction Z of the wiring board 1 . The predetermined spacing is, for example, the distance required for insulation between the conductor pattern 5 and the first conductor layer 3 .

In the examples shown in FIGS. 1 to 3, the conductor pattern 5 is formed in a substantially ring shape. If the conductor pattern 5 is formed between the first conductor layer 3 and the second conductor layer 4 so as to overlap the outer edge of the conductor pad 3a, the shape and size of the conductor pattern 5 are It is not particularly limited. When viewed from the direction along the thickness direction Z of the wiring board 1 (for example, the direction A), the outer edge portion of the conductor pad 3a may be positioned between the inner circumference and the outer circumference of the conductor pattern 5 . For example, in the conductor pattern 5, when viewed from the direction along the thickness direction Z of the wiring board 1, the central portion of the conductor pattern 5 in the width direction of the ring (the central portion between the inner peripheral edge and the outer peripheral edge of the ring) is It may have a shape along the outer edge of the conductor pad 3a. For example, when the conductor pad 3a is substantially circular, the conductor pattern 5 may be substantially circular (see FIG. 3), or may be circular with polygonal outer and/or inner circumferences. good too. Moreover, the conductor pattern 5 may be formed so as to be continuous in the entire circumferential direction of the ring, or may be formed so as to be discontinuous (intermittently) in a part of the circumferential direction of the ring. .

1 to 3, the conductor pattern 5 is formed with a predetermined gap from the second conductor layer 4 in the thickness direction Z of the wiring board 1. As shown in FIG. The predetermined interval is, for example, the distance required for insulation between the conductor pattern 5 and the second conductor layer 4 . That is, in this embodiment, the conductor pattern 5 is formed so as not to be electrically connected to other conductors (first conductor layer 3, second conductor layer 4 and via 6). In addition, the conductor pattern 5 may be electrically connected to other conductors (for example, a part of either one of the first conductor layer 3 and the second conductor layer 4 or a part of both of them) if no particular electrical problem occurs. It may be formed so as to be directly connectable. Also, in the example shown in FIG. 3, the first conductor layer 3 includes a plurality of conductor pads 3a. The conductor pattern 5 is provided for each conductor pad 3a. The conductor patterns 5 provided for each conductor pad 3a are independent of each other. That is, in this embodiment, a plurality of conductor patterns 5 each overlapping the outer edge of each conductor pad 3a are formed without being connected to each other.

Solder resist layer 7 is formed on first interlayer insulating layer 2 . Solder resist layer 7 has a function of protecting first interlayer insulating layer 2 by being formed on first interlayer insulating layer 2 . Solder resist layer 7 is formed using, for example, epoxy resin or polyimide resin. The solder resist layer 7 has openings 7a that expose the conductor pads 3a, as shown in FIGS. Specifically, as shown in FIG. 2, the solder resist layer 7 has openings 7a that expose a surface (front surface) 3f1 of the conductor pad 3a opposite to the first interlayer insulating layer 2 and a side surface 3f2. there is In the example shown in FIG. 2, the solder resist layer 7 is spaced apart from the periphery (outer edge) of each conductor pad 3a so as not to cover the periphery. As a result, the surface 3f1 and the side surface 3f2 of each conductor pad 3a opposite to the first interlayer insulating layer 2 are exposed at the opening 7a. Therefore, the wiring board 1 and the external element S1 can be firmly connected over a large area.

Similarly, the solder resist layer 70 (see FIG. 1) has openings 70a that expose the component mounting pads 33a. Specifically, the solder resist layer 70 has openings 70a that expose only the surface (front surface) of the surface of the component mounting pad 33a opposite to the interlayer insulating layer 23. As shown in FIG. In the example shown in FIG. 1, the solder resist layer 70 is provided so as to cover the periphery of each component mounting pad 33a. As a result, only a part of the surface of each component mounting pad 33a opposite to the interlayer insulating layer 23 is exposed in the opening 70a.

Next, a method for manufacturing the wiring board 1 according to this embodiment will be described with reference to FIGS. 1 to 11. FIG. 4 to 11 are cross-sectional views showing an example of the state during the manufacturing process of the wiring board according to one embodiment of the present invention.

The wiring board 1 shown in FIGS. 1 to 3 can be manufactured by a general wiring board manufacturing method. For example, a double-sided copper-clad laminate including a core insulating layer 20 (see FIG. 1) is prepared. Then, by a subtractive method or the like, a conductor layer 31 including a predetermined wiring pattern is formed on the first main surface 20a of the core insulating layer 20, and a conductor layer 32 including a predetermined wiring pattern is formed on the second main surface of the core insulating layer 20. 20b. At the same time, the through-hole conductors 20c are formed by filling the through-holes provided in the core insulating layer 20 with conductors, and the core substrate of the wiring substrate 1 is prepared.

An interlayer insulating layer 21 is laminated on the first main surface 20 a side of the core insulating layer 20 , and a conductor layer 31 is formed on the interlayer insulating layer 21 . Similarly, an interlayer insulation layer 22 is laminated on the second main surface 20 b side of the core insulation layer 20 , and a conductor layer 32 is formed on the interlayer insulation layer 22 . Lamination of each interlayer insulating layer and formation of a conductor layer are repeated on both surfaces of the core substrate. Interlayer insulating layer 21 and conductor layer 31 thereon, interlayer insulating layer 22 and conductor layer 32 thereon, and conductor layer 4 are each formed by, for example, a general buildup board manufacturing method. For example, each interlayer insulation layer is formed by thermocompression bonding a film-like epoxy resin onto the core substrate or each interlayer insulation layer and each conductor layer formed in advance. Moreover, each conductor layer is formed by using any method of forming a conductor pattern, such as a semi-additive method or a full-additive method including formation of a plating resist and pattern plating. In forming each conductor layer using a method for forming a conductor pattern such as a semi-additive method, vias 6 can be formed in each interlayer insulating layer.

Outermost insulating layers (interlayer insulating layer 23 and first interlayer insulating layer 2) are formed on the first main surface 20a side and the second main surface 20b side of core insulating layer 20, respectively. In this embodiment, the conductor pattern 5 is formed in the formation of the first interlayer insulating layer 2 . The conductor pattern 5 is formed between the first conductor layer 3 and the second conductor layer 4 so as to overlap the outer edge of the conductor pad 3a formed in a step after the formation of the conductor pattern 5. As shown in FIG.

In the example shown in FIG. 1, no conductor pattern is formed on the interlayer insulating layer 23, but a conductor pattern may be formed on the interlayer insulating layer 23. FIG. When a conductor pattern is formed on the interlayer insulating layer 23, the conductor pattern is placed between the conductor layer 31 and the conductor layer so that the conductor pattern overlaps with the outer edge of the component mounting pad 33a formed in a step subsequent to the formation of the conductor pattern. 33.

Specifically, as shown in FIG. 4, the outermost interlayer insulating layer 22 in the wiring board 1 is formed, the vias 6 are formed in the interlayer insulating layer 22, and the second conductor layer 4 is formed on the interlayer insulating layer 22. is formed.

In the example shown in FIG. 4, an electroless plated film 111, which serves as a seed metal film, is formed by electroless plating or the like on the interlayer insulating layer 22 including through holes for via formation and on the inner surfaces of the through holes. Electroplated film 112 is filled in the through hole for via formation. Electroplated film 112 is formed on electroless plated film 111 on interlayer insulating layer 22 . The electrolytic plated film 112 on the interlayer insulating layer 22 and the electrolytic plated film 112 inside the through hole for via formation are integrally formed. A via 6 is formed by the electroless plated film 111 and the electrolytic plated film 112 in the through hole for via formation. Electroless plated film 111 and electrolytic plated film 112 on interlayer insulating layer 22 form second conductor layer 4 .

After that, as shown in FIG. 5 , a second insulating layer 202 which is a part of the first interlayer insulating layer 2 is formed on the interlayer insulating layer 22 and the second conductor layer 4 . After that, a conductor pattern 5 is formed on the second insulating layer 202, as shown in FIG. The conductor pattern 5 is formed on the second insulating layer 202 so as to overlap the outer edge of the conductor pad 3a (see FIGS. 9 to 11) formed in a step after the formation of the conductor pattern 5. FIG. In this embodiment, the conductor pattern 5 is formed in a substantially annular shape. In addition, the conductor pattern 5 has a via 6 (a via connecting the first conductor layer 3 and the second conductor layer 4, see FIGS. 9 to 11) formed in a step after the formation of the conductor pattern 5. It is formed in a region that is formed inside the ring of the conductor pattern 5 .

Specifically, the conductor pattern 5 is formed using any conductor pattern formation method such as a semi-additive method using a plating resist (not shown) having an appropriate opening pattern to include the conductor pattern 5 . That is, the electroless plated film 111 serving as the seed metal film is formed on the entire surface of the second insulating layer 202 by electroless plating or the like. After that, a plating resist having the opening pattern is formed on the electroless plated film 111 . After that, an electrolytic plated film 112 is formed by electrolytic plating in a region on the electroless plated film 111 where the plating resist is not formed. After that, the plating resist is removed. After that, the electroless plated film 111 exposed by removing the plating resist is removed by etching. Electroless plated film 111 and electrolytic plated film 112 remaining on second insulating layer 202 form conductor pattern 5 .

After that, the first insulating layer 201 is formed on the second insulating layer 202 and the conductor pattern 5, as shown in FIG. First insulating layer 201 and second insulating layer 202 constitute first interlayer insulating layer 2 . The first insulating layer 201 and the second insulating layer 202 may be made of the same resin material, or may be made of different resin materials.

After that, as shown in FIG. 8, a through hole 203 is formed in the first interlayer insulating layer 2 by laser light irradiation or the like. The through hole 203 is formed to expose the second conductor layer 4 . After that, as shown in FIG. 9, a first conductor layer 3 is further formed on the first interlayer insulating layer 2 . The first conductor layer 3 is formed using any conductor pattern forming method such as a semi-additive method using a plating resist 8 having an appropriate opening pattern to include the conductor pads 3a. An electroless plated film 111 is formed on the inner surface of the through hole 203 by electroless plating or the like. Electroplated film 112 is filled in through hole 203 . Electroplated film 112 is formed on electroless plated film 111 on interlayer insulating layer 22 . Vias 6 are formed by electroless plated film 111 and electrolytic plated film 112 in through hole 203 . Electroless plated film 111 and electrolytic plated film 112 are formed on first interlayer insulating layer 2 so that their outer edges overlap conductor pattern 5 when viewed from the direction along thickness direction Z of wiring board 1 . .

Similarly, the outermost conductor layer 33 is further formed on the outermost interlayer insulating layer 23 (see FIG. 1). The outermost conductor layer 33 is formed using any conductor pattern forming method such as a semi-additive method using a plating resist (not shown) having an appropriate opening pattern to include component mounting pads 33a.

After that, as shown in FIG. 10, the plating resist 8 is removed. After that, the electroless plated film 111 exposed by removing the plating resist 8 is removed by an etching process. Thereafter, as shown in FIG. 11, solder resist layer 7 is formed on first interlayer insulating layer 2 . The solder resist layer 7 is provided with openings 7a. Solder-resist layer 7 is formed by, for example, applying or spraying a photosensitive epoxy resin or polyimide resin, or laminating it in the form of a film. Then, opening 7a is formed by, for example, exposure and development, laser processing, or the like. The opening 7a covers the entire exposed surface of the electroless plated film 111 and the electrolytic plated film 112 in FIG. is formed to expose the

Similarly, a solder resist layer 70 (see FIG. 1) is formed on the outermost interlayer insulating layer 23 . The solder resist layer 70 is provided with openings (70a). The solder-resist layer 70 can be formed by a method similar to the method for forming the solder-resist layer 7 .

After that, as shown in FIG. 2, a metal film 113 is formed on the surface of the exposed portions of electrolytic plated film 112 and electroless plated film 111 . Metal film 113 is formed, for example, by electroless plating. Thereby, the first conductor layer 3 including the conductor pads 3a is formed. Through the above steps, the wiring board 1 including the conductor pattern 5 illustrated in FIG. 2 is completed.

The wiring board of this embodiment is not limited to the structure illustrated in each drawing, or the structure and materials illustrated in this specification. The wiring board of this embodiment may have any laminated structure. Also, the wiring board of the present embodiment may be a coreless board that does not include a core board. The wiring substrate of this embodiment can include any number of conductor layers and insulating layers. For example, the first conductor layer 3 may include different conductor patterns in addition to the conductor pads 3a.

REFERENCE SIGNS LIST 1 wiring board 2 first interlayer insulation layer 3 first conductor layer 3a conductor pad 3f1 surface of the conductor pad opposite to the first interlayer insulation layer 3f2 side surface 4 second conductor layer 5 conductor pattern 6 via conductor (via)
7 solder resist layer 7a opening 231 first insulating layer 232 second insulating layer Z thickness direction of wiring board

Claims (6)

a first interlayer insulating layer;
a first conductor layer formed on the first interlayer insulating layer and including a conductor pad;
a second conductor layer formed on the side opposite to the first conductor layer with the first interlayer insulating layer interposed therebetween;
A wiring board comprising a solder resist layer formed on the first interlayer insulating layer,
The solder resist layer has an opening that exposes a surface and a side surface of the conductor pad opposite to the first interlayer insulating layer,
The wiring board further includes a conductor pattern formed between the first conductor layer and the second conductor layer so as to overlap the outer edge of the conductor pad. The wiring board according to claim 1,
A via connecting the first conductor layer and the second conductor layer is further provided. The wiring board according to claim 2,
The conductor pattern is formed in a substantially annular shape,
The via is formed inside the ring of the conductor pattern. The wiring board according to claim 1,
The first interlayer insulating layer is
a second insulating layer located on the second conductor layer side in the thickness direction of the wiring board;
a first insulating layer located on the first conductor layer side in the thickness direction of the wiring board,
The conductor pattern is formed on the second insulating layer and covered with the first insulating layer. The wiring board according to claim 4,
The first insulating layer and the second insulating layer are made of the same resin material. The wiring board according to claim 1,
The first conductor layer includes a plurality of the conductor pads,
The conductor pattern is provided for each conductor pad,
The conductor patterns provided for each conductor pad are independent of each other.

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