JP2023111608A - wiring board - Google Patents

Abstract

To provide a wiring board including a core substrate having excellent connection reliability.SOLUTION: A wiring board 1 in an embodiment includes a core substrate including a core insulating layer 100 having a first surface 100A and a second surface 100B, a first conductive layer 101 including a first land part 101L, a second conductive layer 102 including a second land part 102L, a first insulating layer 111, a second insulating layer 112, a third conductive layer 103, and a fourth conductive layer 104. The first land part 101L and the second land part 102L are connected through a through-hole conductor 100tc. The first land part 101L and the third conductive layer 103 are connected through a plurality of first via conductors 111v. The second land part 102L and the fourth conductive layer 104 are connected through a plurality of second via conductors 112v. In a plan view, bottom parts of the first via conductors 111v exist in an outer peripheral part of a penetration hole 100th on an upper surface of the first land part 101L.SELECTED DRAWING: Figure 1

Description

The present invention relates to wiring boards.

Patent Document 1 discloses a multilayer wiring board. A core substrate included in the multilayer wiring board is formed with a through hole formed in the core substrate. On the upper and lower surfaces of the core substrate, only land-like portions are formed, which are composed of a through-hole conductor covering the inner wall surface of the through-hole, a hardened filler filling the inside of the through-hole conductor, and a lid-like conductor. It is An interlayer insulating layer covering the upper and lower surfaces is formed outside the core substrate, and a wiring layer is formed on the surface of the interlayer insulating layer opposite to the core substrate. The lid-shaped conductor and the wiring layer are connected by one filled via that fills the via recess formed in the interlayer insulating layer.

JP 2005-203764 A

In the multilayer wiring board disclosed in Patent Document 1, the wiring layer and the land-like portion of the through hole are connected by one filled via. It is considered that the stress that can be applied to the upper surface of the land-like portion of the through-hole concentrates on the interface between the filled via and the lid-like conductor.

A wiring board of the present invention comprises: a core insulating layer having a first surface and a second surface opposite to the first surface; a first conductor layer formed on the first surface and including a first land portion; A second conductor layer formed on the second surface and including a second land portion, a first insulating layer covering the first surface and the first conductor layer, and covering the second surface and the second conductor layer and a core substrate including a second insulating layer formed on the first insulating layer, a third conductive layer formed on the first insulating layer, and a fourth conductive layer formed on the second insulating layer. The first land portion and the second land portion are connected by a through-hole conductor formed inside a through-hole penetrating the core insulating layer, and the first land portion and the third conductor layer are connected to each other. are connected by a plurality of first via conductors penetrating the first insulating layer, and the second land portion and the fourth conductor layer are connected by a plurality of second via conductors penetrating the second insulating layer. The bottoms of the plurality of first via conductors are located on the upper surface of the first land in the periphery outside the through hole in plan view.

According to the embodiment of the present invention, the first land portion and the third conductor layer, and the second land portion and the fourth conductor layer are connected by a plurality of via conductors located in the peripheral portion outside the through hole. , the stress that may be applied to the land surface can be distributed to a plurality of via conductors. A wiring board including a core substrate having good connection reliability can be provided.

1 is a cross-sectional view showing an example of a wiring board according to one embodiment of the present invention; FIG. FIG. 2 is a plan view of a core substrate included in the wiring substrate of FIG. 1 as viewed from one side; FIG. 2 is a partial enlarged view of the area indicated by II in FIG. 1; FIG. 4 is a cross-sectional view showing another example of the wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing still another example of the wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board; FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a wiring board;

A wiring board according to one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a wiring board 1 that is an example of a wiring board according to one embodiment. The wiring board 1 has a laminate (core substrate) 10 having one surface 10A and the other surface 10B opposite to the one surface 10A.

The laminate 10 has a core insulating layer 100 having a first surface 100A and a second surface 100B opposite to the first surface 100A. A first conductor layer 101 is formed on the first surface 100A, and a second conductor layer 102 is formed on the second surface 100B. A first insulating layer 111 is formed on the first surface 100A exposed from the first conductor layer 101 and the conductor pattern of the first conductor layer 101, and a third conductor layer 103 is formed on the first insulating layer 111. . A second insulating layer 112 is formed on the second surface 100B exposed from the conductor patterns of the second conductor layer 102 and the first conductor layer 102, and a fourth conductor layer 104 is formed on the second insulating layer 112. there is

One surface 10A of the laminate 10 is configured by the upper surface of the first insulating layer 111 exposed from the third conductor layer 103 and the conductor pattern of the third conductor layer 103 . The upper surface of the second insulating layer 112 exposed from the fourth conductor layer 104 and the conductor pattern of the fourth conductor layer 104 constitutes the other surface 10B of the laminate 10 . The laminate 10 included in the wiring board of the present embodiment includes a core insulating layer 100, first and second conductor layers 101 and 102, first and second insulating layers 111 and 112, third and fourth conductor layers 103, 104 included.

The illustrated wiring board 1 has a first buildup portion 11 formed on one surface 10A of the laminate 10 and a second buildup portion 12 formed on the other surface 10B. are doing. The wiring board 1 has first and second buildup parts 11 and 12 laminated on both sides of the laminate 10, and the laminate 10 has the form of a core substrate. Therefore, the laminate 10 is also called a core substrate 10 in the description of this embodiment.

In the description of the wiring board of the present embodiment, the side far from the core insulating layer 100 is referred to as "upper", "upper", "outside", or "outside", and the side closer to the core insulating layer 100 is referred to as Referred to as "lower", "lower", "inner" or "inside". Further, in each insulating layer and conductor layer, the surface facing away from the core insulating layer 100 is also referred to as the "upper surface", and the surface facing the core insulating layer 100 side is also referred to as the "lower surface". Therefore, for example, in the description of each element constituting the core substrate 10, the first buildup section 11, and the second buildup section 12, the side farther from the core insulating layer 100 is referred to as "upper", "upper", and "upper layer side". , “outer”, or simply “upper” or “outer”, and the side closer to the core insulating layer 100 is the “lower side”, “lower”, “lower layer side”, “inner”, or simply “lower” or “outer”. Also called 'inside'. Further, in the description of the embodiments, the thickness direction of the wiring board is also simply referred to as the "Z direction".

The first conductor layer 101 and the second conductor layer 102 forming the core substrate 10 are connected by a through-hole conductor 100tc passing through the core insulating layer 100 in the thickness direction. The through-hole conductor 100tc is composed of a conductor covering the inner wall of the through-hole 100th, as will be described in detail later with reference to FIG. Further inside of the through-hole conductor 100tc covering the inside of the through-hole 100th is filled with a filler 100tr.

The first conductor layer 101 forming the core substrate 10 has a first land portion 101L formed integrally with the through-hole conductor 100tc. The first land portion 101L is connected to the third conductor layer 103 via a first via conductor 111v penetrating the first insulating layer 111 . The second conductor layer 102 forming the core substrate 10 has a second land portion 102L formed integrally with the through-hole conductor 100tc. The second land portion 102L is connected to the fourth conductor layer 104 via a second via conductor 112v penetrating the second insulating layer 112 . The first land portion 101L and the third conductor layer 103 are connected by a plurality of first via conductors 111v, and the second land portion 102L and the fourth conductor layer 104 are connected via a plurality of second via conductors 112v. It is As will be described in detail with reference to FIGS. 2 and 3, land portions 101L and 102L and conductor layers 103 and 104 are connected to the land portions 101L and 102L by connecting positions of the plurality of via conductors 111v and 112v to the land portions 101L and 102L. connections may be more reliable.

In the wiring board 1 of the example shown in FIG. 1, the first conductor layer 101 has only the first land portion 101L as a conductor pattern, and does not have any conductor pattern other than the first land portion 101L. Also, the second conductor layer 102 has only the second land portion 102L as a conductor pattern, and does not have any conductor pattern other than the second land portion 102L. A conductor pattern having relatively fine pattern wiring for signal transmission, which should be included in the outermost conductor layer of the core substrate 10, for example, is not formed on the surface of the core insulating layer 100, and is not formed on the core insulating layer 100. It is formed on the insulating layers 111 and 112 to be formed. With such a configuration, as will be described in detail with reference to FIG. A pattern may be formed on the outermost conductor layer of the core substrate 10 .

The first buildup section 11 is composed of insulating layers 113 and 115 and conductor layers 105 and 107 alternately laminated on one surface 10A of the core substrate 10 . The second buildup section 12 is composed of insulating layers 114 and 116 and conductor layers 106 and 108 alternately laminated on the other surface 10B of the core substrate 10 . The insulating layers 113 and 115 constituting the first buildup portion 11 are also referred to as the third insulating layer 113 and the fifth insulating layer 115, and the conductor layers 105 and 107 are the fifth conductor layer 105 and the seventh insulating layer 115. Also referred to as conductor layer 107 . Also, the insulating layers 114 and 116 constituting the second buildup section 12 are also referred to as a fourth insulating layer 114 and a sixth insulating layer 116, and the conductor layers 106 and 108 are also referred to as the sixth conductor layer 106 and Also referred to as the eighth conductor layer 108 .

Insulating layers 113 and 115 forming first buildup portion 11 include via conductors 11v that connect conductor layers 103, 105 and 107 formed on opposite sides in the thickness direction, respectively. The insulating layers 114, 116 forming the second buildup portion 12 respectively include via conductors 12v connecting the conductor layers 104, 106, 108 formed on opposite sides in the thickness direction.

A solder resist layer 11 s is formed on the first buildup portion 11 . A solder resist layer 12 s is formed on the second buildup portion 12 . An opening 11so is formed in the solder resist layer 11s, and the conductor pad 107p of the outermost conductor layer 107 in the first buildup section 11 is exposed from the opening 11so. An opening 12so is formed in the solder resist layer 12s, and the conductor pad 108p of the outermost conductor layer 108 in the second buildup section 12 is exposed from the opening 12so.

The contact pads 107p may be connection pads used for mounting external electronic components (not shown). On the other hand, the conductor pads 108p may be connection pads used for connection with an external motherboard (not shown) or the like. A surface protection film (not shown) made of Au, Ni/Au, Ni/Pd/Au, solder, heat-resistant preflux, or the like may be formed on the exposed surfaces of the conductor pads 107p and 108p.

The insulating layers 100, 111 to 116 constituting the wiring board 1 are each formed using an insulating resin such as epoxy resin, bismaleimide triazine resin (BT resin), or phenol resin. Each insulating layer may contain a reinforcing material (core material) such as glass fiber and/or an inorganic filler such as silica or alumina. In the illustrated example, the core insulating layer 100 contains a core material, and the other insulating layers 111-116 do not contain a core material. In particular, when the first insulating layer 111 and the second insulating layer 112 are formed using a film-like resin that does not contain a core material, the first insulating layer 111 and the second insulating layer 112 may contain a core material. In comparison, the first conductor layer 101 and the second conductor layer 102 may be formed as conductor layers having relatively narrow-pitch wiring patterns. The solder resist layers 11s and 12s are formed using, for example, photosensitive epoxy resin or polyimide resin.

Conductive layers 101-108, via conductors 111v, 112v, 11v, 12v, and through-hole conductors 100tc can be formed using any metal such as copper or nickel. For example, the conductor layers 101-108 may be formed of metal foils such as copper foils and/or metal films formed by plating or sputtering. Conductor layers 101 to 108, via conductors 111v, 112v, 11v, 12v, and through-hole conductor 100tc are shown in FIG. can have a structure The first and second conductor layers 101 and 102, which will be described in detail later with reference to FIG. It may have a 5-layer structure containing layers. Conductor layers 103-108 and via conductors 111v, 112v, 11v, and 12v may have a two-layer structure including, for example, a metal film layer (electroless plated film) and an electrolytic plated film layer.

Each conductor layer 101-108 of the wiring board 1 is patterned to have a predetermined conductor pattern. As described above, in the core substrate 10 included in the wiring substrate 1 of the illustrated example, the first conductor layer 101 and the second conductor layer 102 are formed integrally with the through-hole conductors 100tc. land portion 101L and second land portion 102L). A third conductor layer 103 forming one surface 10A of the core substrate 10 includes a land portion (third land portion) 103L connected to the first land portion 101L via via conductors 111v, a signal wiring SW, and a plane portion. (third plane portion) P3. The fourth conductor layer 104 forming the other surface 10B of the core substrate 10 includes a land portion (fourth land portion) 104L connected to the second land portion 102L via via conductors 112v, a signal wiring SW, and a plane portion. (Fourth plane portion) P4.

In the illustrated example, the land portions (the third land portion 103L, the fourth land portion 104L) formed on the outermost surface of the core substrate 10 are the land portions ( The first land portion 101L and the second land portion 102L have patterns that substantially match each other in a plan view. Note that "planar view" means viewing an object with a line of sight parallel to the Z direction (the thickness direction of the wiring board 1). The plane portions (the third plane portion P3 and the fourth plane portion P4) formed on the outermost surface of the core substrate 10 are arranged in a predetermined plane direction orthogonal to the thickness direction (Z direction) of the core substrate 10. This is a so-called solid pattern extending over the area. The signal wiring SW formed on the outermost surface of the core substrate 10 has the smallest wiring width and inter-wiring distance among the conductor patterns of the conductor layers 101 to 104 forming the core substrate 10 . For example, the wiring width of the signal wiring SW can be formed to be 30 μm or less, and the distance between the wirings can be formed to be 30 μm or less. For example, the wiring width of the signal wiring SW can have a value of 8 μm to 30 μm. For example, the inter-wiring distance of the signal wiring SW can have a value of 10 μm to 30 μm.

Next, referring to FIG. 2, the configuration of the third conductor layer 103 forming the outermost surface (one surface 10A) of the core substrate 10, the third land portion 103L of the third conductor layer 103 and its A connection relationship with the first land portion 101L immediately below will be described. FIG. 2 is a plan view of the area indicated by area II in FIG. 1 of the core substrate 10 as seen from one surface 10A side. That is, in FIG. 2, the core substrate 10 is removed from one surface 10A of the wiring board 1 from above one surface 10A with the upper components (the first buildup portion 11 and the solder resist layer 11s) removed from the one surface 10A. It is a plan view when viewed in plan.

One surface 10A shown in FIG. It consists of the upper surface of layer 111 . As described with reference to FIG. 1, the third land portion 103L shown in FIG. 2 substantially coincides with the first land portion 101L directly thereunder in plan view, and the peripheral edge 103Lp of the third land portion 103L is , coincides with the periphery of the first land portion 101L located directly below. A circular dashed line positioned in the center of the land portion 103L in FIG. Regions 111vb indicated by a plurality of circular dashed lines arranged around through-hole 100th are the bottom surface of via conductor 111v connecting first land portion 101L and third land portion 103L (the top surface of first land portion 101L). connection area).

In the plan view of FIG. 2, a plurality of regions 111vb corresponding to the bottom surfaces of via conductors 111v are located in regions outside through-holes 100th. That is, the plurality of via conductors 111v connecting the third land portion 103L and the first land portion 101L are arranged to at least partially avoid the region immediately above the through hole 100th in the connection portion with the first land portion 101L. is formed in

Since the first land portion 101L and the third land portion 103L are connected through the plurality of via conductors 111v, the stress that may be applied to the upper surface of the first land portion 101L is effectively transferred through the plurality of via conductors 111v. can be distributed in Occurrence of peeling between the upper surface of the first land portion 101L and the components (via conductor 111v, first insulating layer 111) on the first land portion 101L may be suppressed.

In particular, since the bottoms (regions 111vb) of the plurality of via conductors 111v are located outside the through holes 100th in plan view, the stress that may be exerted on the upper surface of the first land portion 101L may be effectively dispersed. be. In particular, the stress that may occur in the region directly above the filler 100tr may be effectively dispersed through the plurality of via conductors 111v. Specifically, from the viewpoint of effective stress distribution, it is desirable that the region 111vb is positioned within twice the radius of the through hole 100th from the center 100thc of the through hole 100th in plan view. For example, the through hole 100th is formed with a diameter of 150 μm, and in this case, the region 111vb is preferably formed within 300 μm from the center 100thc outside the through hole 100th.

The shape of the through-hole 100th in plan view is not limited to a circle, and the "radius of the through-hole 100th" means the distance from the center of the through-hole 100th in plan view to the peripheral edge of the most distal through-hole 100th. In this specification, a region outside the through-hole 100th within twice the radius of the through-hole 100th from the center 100thc of the through-hole 100th is referred to as "outer periphery of the through-hole 100th". Also, the plurality of regions 111vb corresponding to the bottom surfaces of the via conductors 111v may be partially positioned inside the through holes 100th in plan view. In other words, the plurality of via conductors 111v may be located at least partially outside the through-hole 100th at the connection position with the first land portion 101L.

More specifically, from the viewpoint of effective stress distribution, it is preferable that each of the plurality of regions 111vb be positioned at substantially equal distances from the center 100thc in plan view. From a similar point of view, the plurality of regions 111vb are arranged along the periphery of the through-hole 100th at substantially equal intervals (that is, the intervals between adjacent regions 111vb among the plurality of regions 111vb are equal). desirable. Note that the example shown in FIG. 2 shows an example in which the first land portion 101L and the third land portion 103L are connected by four via conductors 111v. The number of via conductors 111v connecting with 103L is not limited to this. In addition, the connection position of the first via conductor 111v on the upper surface of the first land portion 101L described above with reference to FIGS. can also be applied to

Next, referring to FIG. 3, the layer structure of first conductor layer 101 (first land portion 101L), through-hole conductor 100tc, and second conductor layer 102 (second land portion 102L), and the third conductor layer 103, the structures of the first via conductor 111v, the fourth conductor layer 104, and the second via conductor 112v will be described in detail. FIG. 3 is an enlarged view of a region III surrounded by a dashed line shown in FIG. The first land portion 101L, the second land portion 102L, and the through-hole conductor 100tc are integrally formed, and the inside of the through-hole conductor 100tc in the through-hole 100th is filled with the filler 100tr. The filler 100tr can be, for example, an insulating material containing resin such as epoxy, acrylic, or phenol, or a solidified conductive paste or conductive ink containing conductive particles such as silver particles.

The through-hole conductor 100tc formed on the inner wall of the through-hole 100th provided in the core insulating layer 100 includes a metal film layer 1b that is, for example, an electroless copper plating film and an electrolytic plating film layer that is, for example, an electrolytic copper plating film. Contains two layers of 1c. Each of the first conductor layer 101 and the second conductor layer 102 has a five-layer structure including a metal foil 1a such as copper foil, a metal film layer 1b, an electrolytic plated film layer 1c, a metal film layer 1d, and an electrolytic plated film layer 1e. have. Two layers, a metal film layer 1d and an electrolytic plated film layer 1e, are formed immediately above the filler 100tr. The metal film layer 1b and the electrolytic plated film layer 1c forming the through-hole conductor 100tc and the metal film layer 1b and the electrolytic plated film layer 1c forming the first and second land portions 101L and 102L are continuous.

As illustrated, the third conductor layer 103 and the first via conductor 111v formed on the first insulating layer 111, and the fourth conductor layer 104 and the second via conductor formed on the second insulating layer 112 112v all have a two-layer structure including a metal film layer 1b and an electrolytic plated film layer 1c. That is, the outermost conductor layers 103 and 104 of the core substrate 10 have a two-layer structure that does not contain metal foil, and can be formed thinner than the conductor layers 101 and 102 formed on the surface of the core insulating layer 100 . Therefore, finer patterns than those of the first and second conductor layers 101 and 102 can be formed on the third and fourth conductor layers 103 and 104 . In the illustrated example, the signal wiring SW is formed as the finest conductor pattern that the core substrate 10 has.

A conductor pattern including, for example, wiring for signal transmission, which should be included in the outermost conductor layer of the core substrate 10, is not formed in the conductor layers 101 and 102 of the five-layer structure formed on the surface of the core insulating layer 100, and is insulated. By forming conductor layers 103 and 104 having a two-layer structure on layers 111 and 112, core substrate 10 can have a relatively fine pattern on its outermost conductor layer.

The thickness of each of the first and second conductor layers 101 and 102 having the five-layer structure and having the metal foil 1a is, for example, 20 μm or more and 40 μm or less. The thickness of the third and fourth conductor layers 103 and 104, which may have a two-layer structure including the metal film layer 1b and the electroplating film layer 1c, is, for example, 12 μm or more and 18 μm or less. Each of the third and fourth conductor layers 103, 104, which can have such thicknesses, has conductor patterns arranged according to a wiring rule of 9 μm/12 μm in terms of minimum line width/minimum line width (L/S). can contain.

In the wiring board of the embodiment, in addition to the configuration of the wiring board 1 described with reference to FIGS. It can have a plane part. FIG. 4 shows an example in which a first plane portion P1 having a pattern that substantially matches the third plane portion P3 in a plan view is formed in a region of the first conductor layer 101 directly below the third plane portion P3. is shown as Further, in the wiring board 2, a second plane portion P2 is formed in a region directly below the fourth plane portion P4 in the second conductor layer 102, and has a pattern that substantially matches the fourth plane portion P4 in plan view. In the illustrated example, the first conductor layer 101 including the first plane portion P1 does not include a conductor pattern in the region immediately below the signal wiring SW formed on the third conductor layer 103, and the second plane The second conductor layer 102 including the portion P2 does not have a conductor pattern in the region immediately below the signal wiring SW formed in the fourth conductor layer 104. FIG.

The first plane portion P1 and the third plane portion P3, and the second plane portion P2 and the fourth plane portion P4 can be connected by via conductors. The first plane portion P1 and the third plane portion P3 can be connected by a third via conductor 3v, and the second plane portion P2 and the fourth plane portion P4 can be connected by a fourth via conductor 4v. By being connected by via conductors, the first plane portion P1 and the third plane portion P3, and the second plane portion P2 and the fourth plane portion P4 can be configured as plane portions extending over a plurality of layers. With such a configuration, the core substrate 10 can have reinforced power or ground planes. The first plane portion P1 and the third plane portion P3, and the second plane portion P2 and the fourth plane portion P4 may have a configuration in which they are not connected by via conductors.

Moreover, the wiring board of the embodiment can also have a configuration in which the signal wiring SW is surrounded by a plane portion, like the wiring board 3 shown in FIG. In the example shown in FIG. 5, a plane included in the fifth conductor layer 105 formed via an insulating layer (third insulating layer) 113 is provided in a region directly above the signal wiring SW of the third conductor layer 103. A portion (fifth plane portion) P5 is located. Also, the first plane portion P1 included in the first conductor layer 101 is located in the region immediately below the signal wiring SW with the first insulating layer 111 interposed therebetween. The mode in which the plane portions P1 and P5 are positioned immediately below and directly above the signal wiring SW can improve the transmission quality of the signal carried by the signal wiring SW. Since the signal wiring SW overlaps with the plane portions P1 and P5 used for the ground pattern and the like on both the upper layer side and the lower layer side, it is possible to transmit signals that are not easily affected by external noise in the signal wiring SW. Conceivable.

In addition, as shown in the figure, the wiring substrate 3 includes the signal wiring SW included in the fourth conductor layer 104, the second conductor layer 102, and the sixth conductor layer 106 as well as the above-described signal wiring SW. It has a structure in which a plane part is located in the lower layer. A sixth plane portion P6 included in the sixth conductor layer is located directly above the signal wiring SW included in the fourth conductor layer 104, and a second plane included in the second conductor layer is located directly below the signal wiring SW. Part P2 is located.

Next, an example of a method for manufacturing a wiring board according to one embodiment will be described with reference to FIGS. 6A to 6I, taking the case of manufacturing the wiring board 1 of FIG. 1 as an example. 6A to 6D, similar to FIG. 3, the structure of each conductor layer is drawn in detail, but in FIGS. 6E to 6I, similar to FIG. 1, the structure of each conductor layer is simplified. are shown to have a single layer structure.

First, as shown in FIG. 6A, an insulating layer 100 and a substrate (for example, a double-sided copper-clad laminate) provided with metal foils 1a on both sides of the insulating layer 100 are prepared. 6B to 6D show enlarged views corresponding to the region B surrounded by the dashed line in FIG. 6A.

Next, through holes 100th are formed in the insulating layer 100, as shown in FIG. 6B. The through hole 100th is formed by drilling with a cutting device such as a drill. The through hole 100th may be formed by irradiating a laser beam such as a carbon dioxide laser or a YAG laser.

Subsequently, the metal film layer 1b is formed on the inner wall surface of the through hole 100th and on the metal foil 1a by, for example, electroless plating or sputtering. The metal film layer 1b is, for example, an electroless plated film made of copper, but the material of the metal film layer 1b is not limited to copper. Subsequently, an electrolytic plated film layer 1c is formed on the metal film layer 1b by electrolytic plating using the metal film layer 1b as a power feeding layer. The electrolytic plated film layer 1c is made of a metal such as copper deposited on the metal film layer 1b. However, the material of the metal film layer 1c is not limited to copper. On the inner wall surface of the through-hole 100th, a through-hole conductor 100tc having a two-layer structure including a metal film layer 1b and an electrolytic plated film layer 1c and responsible for electrical conductivity between conductor layers formed on both surfaces of the insulating layer 100 is provided. It is formed.

Next, as shown in FIG. 6C, the cavity inside the through-hole conductor 100tc of the through-hole 100th is filled with the filler 100tr. For example, resin such as epoxy, acrylic or phenol is injected from one opening of the through hole 100th. The filled filler 100tr is solidified by heating or the like. The end face of the solidified filler 100tr is polished by any method such as chemical mechanical polishing, if necessary. By this polishing, the end face of the filler 100tr and the surface of the electrolytic plated film layer 1c are preferably made substantially flush.

Next, as shown in FIG. 6D, a metal film layer 1d and an electrolytic plated film layer 1e are formed in this order on the electrolytic plated film layer 1c and the filler 100tr. The metal film layer 1d and the electrolytic plated film layer 1e are formed, for example, by the same method as the metal film layer 1b and the electrolytic plated film layer 1c. As a result, on both surfaces of the insulating layer 100, the first and second conductor layers having a five-layer structure of the metal foil 1a, the metal film layer 1b, the electrolytic plated film layer 1c, the metal film layer 1d, and the electrolytic plated film layer 1e. 101, 102 are formed.

The first and second conductor layers 101, 102 are then patterned, for example by etching using an etch mask with openings at appropriate locations, as shown in FIG. 6E. The first conductor layer 101 is formed in a pattern including the first land portion 101L, and the second conductor layer 102 is formed in a pattern including the second land portion 102L. The first and second conductor layers 101, 102 can thus be formed using a subtractive method.

Next, as shown in FIG. 6F , the first insulating layer 111 is laminated on the first conductor layer 101 and the surface of the insulating layer 100 exposed from the first conductor layer 101 . A second insulating layer 112 is laminated on the second conductor layer 102 and the surface of the insulating layer 100 exposed from the second conductor layer 102 . For example, a film-like insulating resin (for example, epoxy resin) is thermally compressed, and through holes vh are formed at positions where via conductors are to be formed in this insulating resin by irradiating carbon dioxide laser light, for example.

A plurality of through holes vh are formed for one land portion 101L, 102L. The through hole vh is formed such that at least a part of the bottom thereof is positioned outside the through hole 100th on the upper surfaces of the lands 101L and 102L in plan view. Specifically, the through hole vh is formed so as to have the positional relationship between the region 111vb corresponding to the bottom surface of the via conductor 111v and the through hole 100th described with reference to FIG.

Then, as shown in FIG. 6G, third and fourth conductor layers 103, 104 and via conductors 111v, 112v are formed. The third and fourth conductor layers 103, 104 and the via conductors 111v, 112v are formed by forming metal film layers in the through holes vh and on the upper surfaces of the insulating layers 111, 112 by electroless plating, sputtering, or the like. It is formed by electroplating using a metal film as a power supply layer and using a plating resist with appropriate openings. That is, conductor layers 103 and 104 and via conductors 111v and 112v are formed by a semi-additive (SAP: Semi-Additive Process) method that does not use metal foil. The third conductor layer 103 is formed in a pattern having a third land portion 103L, a signal wiring SW, and a third plane portion P3. A pattern having a fourth plane portion P4 is formed. Formation of the core substrate 10 having one surface 10A and the other surface 10B opposite to the one surface 10A is completed.

Next, as shown in FIG. 6H, the first buildup portion 11 is formed on one surface 10A of the core substrate 10, and the second buildup portion 12 is formed on the other surface 10B. By repeating the same process as the formation of the insulating layer 111 and the conductor layer 103 described above, the insulating layers 113 and 115 and the conductor layers 105 and 107 are formed on the upper side of the one surface 10A, and the other surface 10B is formed. Insulating layers 114, 116 and conductor layers 106, 108 are formed on the upper side. Formation of the first and second buildup portions 11 and 12 is completed.

Next, as shown in FIG. 6I, a solder-resist layer 11s is formed on the first buildup portion 11, and a solder-resist layer 12s is formed on the second buildup portion 12. Next, as shown in FIG. The solder resist layers 11s and 12s are formed by, for example, forming a resin layer containing a photosensitive epoxy resin or polyimide resin, and exposing and developing using a mask having an appropriate opening pattern. The solder resist layers 11s, 12s are formed to have openings 11sa, 12sa exposing the conductor pads 107p, 108p. Surface protective films (such as Au, Ni/Au, Ni/Pd/Au, solder, or heat-resistant preflux) are formed on the exposed surfaces of the conductor pads 107p and 108p by electroless plating, solder leveler, or spray coating. not shown) may be formed. The wiring board 1 shown in FIG. 1 is completed through the above steps.

The wiring substrates of the embodiments are not limited to those having the structures illustrated in each drawing, and the structures, shapes, and materials illustrated in this specification. In the wiring boards 1 to 3 described, the first buildup section 11 and the second buildup section 12 each consist of two conductor layers 105, 107, 106, 108 and two insulating layers 113, 115, 114. , 116, but the number of insulating layers and conductor layers included in the first and second buildup portions 11 and 12 is not limited to this. The first buildup section 11 and the second buildup section 12 may include three or more conductor layers and three or more insulation layers, or may include only one conductor layer and one insulation layer. . Also, the first buildup section 11 and the second buildup section 12 may have different numbers of insulating layers and conductor layers. In addition, the third and fourth conductor layers 103 and 104 are formed, for example, using a semi-additive (MSAP: Modified Semi-Additive Process) method using metal foil, and have a three-layer structure including the metal foil. good too.

Reference Signs List 1, 2, 3 wiring board 10 core substrate 10A one surface 10B other surface 100 core insulating layer 100A first surface 100B second surface 101 conductor layer (first conductor layer)
102 conductor layer (second conductor layer)
103 conductor layer (third conductor layer)
104 conductor layer (fourth conductor layer)
105 conductor layer (fifth conductor layer)
106 conductor layer (sixth conductor layer)
11 first buildup portion 12 second buildup portion 100th through hole 111v via conductor (first via conductor)
112v via conductor (second via conductor)
101L land part (first land part)
102L land part (second land part)
103L land part (third land part)
104L land (fourth land)
SW signal wiring P1 plane part (first plane part)
P2 plane part (second plane part)
P3 plane part (third plane part)
P4 plane part (fourth plane part)

Claims (13)

a core insulation layer having a first surface and a second surface opposite the first surface;
a first conductor layer formed on the first surface and including a first land;
a second conductor layer formed on the second surface and including a second land;
a first insulating layer covering the first surface and the first conductor layer;
a second insulating layer covering the second surface and the second conductor layer;
a third conductor layer formed on the first insulating layer;
a fourth conductor layer formed on the second insulating layer;
A wiring board having a core substrate containing
the first land portion and the second land portion are connected by a through-hole conductor formed inside a through-hole penetrating the core insulating layer,
the first land portion and the third conductor layer are connected by a plurality of first via conductors penetrating the first insulating layer;
the second land portion and the fourth conductor layer are connected by a plurality of second via conductors penetrating the second insulating layer;
The bottoms of the plurality of first via conductors are positioned on the upper surface of the first land in the periphery outside the through hole in plan view. 2. The wiring board according to claim 1, wherein the bottoms of the plurality of second via conductors are positioned on the upper surface of the second land in a peripheral portion outside the through hole in a plan view. 3. The wiring board according to claim 2, wherein the plurality of first via conductors and the plurality of second via conductors are positioned at substantially equal distances from the center of the through hole in plan view. 4. The wiring board according to claim 3, wherein distances between adjacent first via conductors of said plurality of first via conductors along the periphery of said through-hole are substantially equal, and said plurality of second via conductors The distance between the second via conductors adjacent to each other along the periphery of the through hole is substantially equal. 2. The wiring board according to claim 1, wherein said first conductor layer is composed only of said first land portion, and said second conductor layer is composed only of said second land portion. The wiring board according to claim 1,
the third conductor layer includes a third land portion substantially coinciding with the first land portion in plan view, the third land portion and the first land portion being connected by the plurality of first via conductors;
The fourth conductor layer includes a fourth land portion substantially coinciding with the second land portion in plan view, and the fourth land portion and the second land portion are connected by the plurality of second via conductors. . 2. The wiring board according to claim 1, wherein said third conductor layer and said fourth conductor layer further include signal wiring. 8. The wiring board according to claim 7, wherein the signal wiring has a wiring width of 30 [mu]m or less and a wiring distance of 30 [mu]m or less. 2. The wiring board according to claim 1, wherein said first conductor layer further includes a first plane portion, and said second conductor layer further includes a second plane portion. 10. The wiring board according to claim 9, wherein the third conductor layer includes a third plane portion substantially coinciding with the first plane portion in plan view, and the fourth conductor layer includes the second plane portion in plan view. and a fourth plane portion substantially coinciding with . The wiring board according to claim 9,
The third conductor layer and the fourth conductor layer further include signal wiring,
the first conductor layer does not have a conductor pattern in a region immediately below the signal wiring included in the third conductor layer;
The second conductor layer does not have a conductor pattern in a region immediately below the signal wiring included in the fourth conductor layer. The wiring board according to claim 9,
The third conductor layer and the fourth conductor layer further include signal wiring,
The first plane portion is positioned directly below the signal wiring included in the third conductor layer,
The second plane portion is positioned directly below the signal wiring included in the fourth conductor layer. 13. The wiring board according to claim 12,
further comprising a fifth insulating layer on the upper side of the third conductive layer and a fifth conductive layer formed on the fifth insulating layer;
further comprising a sixth insulating layer on the upper side of the fourth conductive layer and a sixth conductive layer formed on the sixth insulating layer;
A plane layer included in the fifth conductor layer is positioned directly above the signal wiring included in the third conductor layer,
A plane layer included in the sixth conductor layer is positioned directly above the signal wiring included in the fourth conductor layer.

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