JP2023107182A - Semiconductor device and physical quantity sensor device - Google Patents

Abstract

To reduce the time required when selecting an optimum resistance value from series resistors connected to a thermistor, and acquire the data to be measured on the basis of the selected resistance value to improve the accuracy of measurement.SOLUTION: A series resistor selection circuit 1b includes a series resistor group Rg which is connected in series to an NTC thermistor and selects a series resistor from the series resistor group Rg on the basis of a selection signal sel. An A/D converter 1c converts from analog to digital a divided voltage V1 that is derived by dividing an internal supply voltage V0 by the NTC thermistor Rt and the series resistor selected by the series resistor selection circuit 1b and outputs divided voltage data V1d. A control circuit 1d selects a series resistor by actuating the A/D converter 1c in a low-bit-count mode in a period in which a series resistor is selected from within the series resistor group Rg, and actuates the A/D converter 1c in a high-bit-count mode after selecting an optimum series resistor whose divided voltage data V1d falls within a prescribed voltage range.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device for detecting temperature and a physical quantity sensor device for detecting a physical quantity having temperature dependence.

In-vehicle electronic devices are required to be highly reliable in response to environmental changes. Therefore, the importance of technology for detecting physical quantities such as temperature with sensors, communicating the detection results based on in-vehicle communication standards, and controlling objects to be controlled according to environmental changes is increasing.

FIG. 17 is a diagram showing the configuration of a conventional temperature sensor device. The temperature sensor device 100 is a device that detects temperature and transmits the detected temperature information to a control device using the SENT (Single Edge Nibble Transmission) protocol, which is one of the in-vehicle communication standards.

The temperature sensor device 100 has a power supply terminal VCC, a reference power supply terminal VSS, an output terminal SENT and a thermistor connection terminal THERM. The temperature sensor device 100 also includes an internal power supply generation circuit 101, a digital circuit 102, an output circuit 103, a digital circuit power supply generation circuit 111, and a resistor R10. The digital circuit 102 includes an A/D converter 102a. The A/D converter 102a is a circuit in which an analog circuit and a digital circuit are mixed. Therefore, the internal power supply voltage generated by the internal power supply generation circuit 101 is supplied to the analog circuit in the A/D converter 102a.

An internal power supply generation circuit 101 generates an internal power supply voltage from a power supply voltage input to a power supply terminal VCC, and supplies the internal power supply voltage to components within the apparatus. The digital circuit power supply generation circuit 111 generates a power supply voltage to be supplied to the digital circuit 102 based on the internal power supply voltage. A reference power supply terminal VSS is connected to a reference power supply voltage such as ground (GND), and the reference power supply voltage is connected to a digital circuit 102, a terminal VL of an A/D converter 102a and an output circuit 103 in the apparatus.

An NTC (Negative Temperature Coefficient) thermistor Rt is externally attached to the thermistor connection terminal THERM and the reference power supply terminal VSS, and a resistor R10 in the device is connected in series to the NTC thermistor Rt. An internal power supply voltage is input to one end of the resistor R10, and a divided voltage is generated by dividing the internal power supply voltage by the NTC thermistor Rt and the resistor R10, and is divided to the terminal VIN of the A/D converter 102a. A voltage is input.

A reference voltage VREF generated from an internal power supply voltage is input to a terminal VH of the A/D converter 102a, and a clock signal AD-CLK generated within the digital circuit 102 is input to the A/D converter 102a. be.

The A/D converter 102a converts an analog divided voltage indicating temperature information input to the terminal VIN into a digital value in synchronization with the clock signal AD-CLK, and transmits the converted digital value to the output circuit 103. . The output circuit 103 converts the received digital value into the SENT protocol format and transmits the temperature data to the opposite control device.

As a related technique, for example, a technique of performing communication between a physical quantity sensor and a control device according to an in-vehicle communication standard has been proposed (Patent Document 1). Also, a technique for adjusting the characteristics of physical quantities based on adjustment information has been proposed (Patent Document 2). Furthermore, a technique has been proposed in which a variable resistance means is provided whose resistance value is variable according to a control signal, and a divided voltage value is obtained from the resistance value of the variably controlled variable resistance means and the equivalent resistance value of the thermistor (Patent Reference 3).

JP 2016-111501 A JP 2018-119972 A JP-A-4-109132

FIG. 18 is a diagram showing temperature dependence of an NTC thermistor. The vertical axis is the resistance value (kΩ) and the horizontal axis is the temperature (°C). A thermistor has a large temperature coefficient and is a resistor whose resistance value k0 changes according to temperature. In particular, an NTC thermistor is a resistor whose resistance value k0 decreases as temperature rises.

FIG. 19 is a diagram showing an example of a circuit using an NTC thermistor. As a general circuit using the NTC thermistor Rt, there is one that divides the power supply voltage with the resistor R10 and the NTC thermistor Rt to generate a divided voltage.

Since the resistance value of the NTC thermistor Rt changes with sensitivity to temperature changes, the divided voltage generated by the NTC thermistor Rt and the resistor R10 also fluctuates according to temperature changes. Therefore, the temperature can be detected based on the fluctuation value of the divided voltage. In such a circuit, it is important to set the resistance value of the resistor R10 connected to the NTC thermistor Rt so that the divided voltage is output in the desired temperature range to be measured.

FIG. 20 is a diagram showing the temperature dependence of the divided voltage. The vertical axis is divided voltage (V) and the horizontal axis is temperature (°C). As the temperature around the NTC thermistor Rt increases, the resistance value of the NTC thermistor Rt decreases, so the divided voltage also decreases.

However, when the temperature range to be measured is wide, the temperature dependence of the divided voltage saturates at both ends of the temperature range. Therefore, the amount of change in the divided voltage for the temperature change ranges H1 and H3 on both ends of the temperature range is smaller than the amount of change in the divided voltage for the temperature change range H2 on the center side of the temperature range. , H3, the temperature measurement accuracy is reduced.

That is, in the temperature change ranges H1 and H3, the temperature dependence is saturated and the slope of the divided voltage is small and gentle, so the temperature measurement accuracy is low. is large and steep, so temperature measurement accuracy is high.

In order to improve such problems, it is conceivable to adjust the resistance value of the series resistor R10 connected in series with the NTC thermistor Rt according to the temperature range to be measured. For example, in Patent Document 3 mentioned above, a predetermined resistance value is selected by making the resistance value of the series resistor variable using a switched capacitor.

However, in Patent Document 3, the divided voltage is converted into a digital value by an A/D converter, and the converted digital value is compared with the value stored in the table to select the resistance value. When the A/D converter has a high number of bits and a high resolution, the A/D conversion time is long. It may take some time to obtain it.

In particular, successive approximation register (SAR) type A/D converters and delta-sigma (ΔΣ) type A/D converters have high resolution, but the A/D conversion time is long, so the above resistors are required. In value selection control, there is a possibility that appropriate temperature data may not be obtained in time for the entire process.

In one aspect, the present invention shortens the selection time when selecting the optimum resistance value from among the resistance values of the series resistors connected to the thermistor, and obtains the data to be measured based on the selected resistance value. An object of the present invention is to provide a semiconductor device and a physical quantity sensor device that acquire and improve measurement accuracy.

A semiconductor device is provided to solve the above problems. A semiconductor device has a thermistor for temperature detection, a series resistance selection circuit, an analog/digital converter and a control circuit.
The series resistance selection circuit includes a series resistance group connected in series with the thermistor, and selects a series resistance from the series resistance group based on the selection signal. The analog/digital converter analog/digital converts the divided voltage obtained by dividing the internal power supply voltage by the thermistor and the series resistor, and outputs the divided voltage data. The control circuit operates the analog/digital converter in a low bit number mode during the series resistance selection period, selects the optimum series resistance in which the divided voltage data falls within a predetermined voltage range, and selects the optimum series resistance. Operate the digital converter in high-bit-count mode.

Also, in order to solve the above problems, a physical quantity sensor device is provided. The physical quantity sensor device has a thermistor for temperature detection, a physical quantity sensor, a series resistance selection circuit, a multiplexer, an analog/digital converter and a control circuit.

A physical quantity sensor detects a physical quantity and outputs a physical quantity detection signal. The series resistance selection circuit includes a series resistance group connected in series with the thermistor, and selects a series resistance from the series resistance group based on the selection signal. The multiplexer switches and outputs a divided voltage obtained by dividing the internal power supply voltage by the thermistor and the series resistor and the physical quantity detection signal based on the switching signal. The analog/digital converter analog/digital converts the divided voltage and the physical quantity detection signal output from the multiplexer.

Further, the control circuit causes the multiplexer to output the physical quantity detection signal by the switching signal, operates the analog/digital converter in the high bit number mode, analog/digital converts the physical quantity detection signal in the high bit number mode, and converts the physical quantity detection signal into the first physical quantity detection data is acquired, and in the series resistor selection period, a switching signal is used to output the divided voltage from the multiplexer, the analog / digital converter is operated in the low bit number mode, and the divided voltage is output in the low bit number mode. First temperature data obtained by analog/digital conversion selects an optimum series resistance that falls within a predetermined voltage range, and after selecting the optimum series resistance, the analog/digital converter is operated in a high bit number mode to obtain Second temperature data is acquired by analog-to-digital conversion of the divided voltage in the numerical mode, and the second physical quantity is obtained by calculating the first physical quantity detection data based on the second temperature data and the correction coefficient. Generate detection data.

According to one aspect, the selection time is shortened when selecting the optimum resistance value from among the series resistors connected to the thermistor, and the measurement accuracy is improved by acquiring the data to be measured based on the selected resistance value. can be improved.

It is a figure for demonstrating the semiconductor device of this invention. It is a figure which shows an example of a structure of a semiconductor device. FIG. 4 is a diagram showing an example of a configuration of a series resistance selection circuit; FIG. 4 is a diagram showing an example of a configuration of a series resistance selection circuit; It is a figure which shows the temperature dependence of the voltage division voltage for every series resistance. 4 is a flow chart showing the operation of the series resistance determination circuit; It is a figure which shows an example of a structure of a physical quantity sensor apparatus. FIG. 4 is a diagram showing the relationship between stress and gauge resistance in a physical quantity sensor; 4 is a timing chart showing the operation of the physical quantity sensor device; 4 is a timing chart showing the operation of the physical quantity sensor device; FIG. 4 is a diagram showing the relationship between ideal pressure data and measured pressure data; It is a figure which shows the relationship between a correction coefficient and temperature data. FIG. 3 is a diagram showing a range of operating voltages of an A/D converter; FIG. 3 is a diagram showing a range of operating voltages of an A/D converter; It is a figure which shows an example of a structure of a semiconductor device. It is a figure which shows an example of a structure of a physical quantity sensor apparatus. 1 is a diagram showing a configuration of a conventional temperature sensor device; FIG. FIG. 4 is a diagram showing temperature dependence of an NTC thermistor; FIG. 2 is a diagram showing an example of a circuit using an NTC thermistor; FIG. It is a figure which shows the temperature dependence of voltage-dividing voltage.

Hereinafter, this embodiment will be described with reference to the drawings. Elements having substantially the same configuration in the present specification and drawings may be denoted by the same reference numerals, thereby omitting redundant description.

FIG. 1 is a diagram for explaining the semiconductor device of the present invention. The semiconductor device 1 has a temperature detection thermistor (NTC thermistor, hereinafter) Rt, an internal power supply generation circuit 1a, a series resistance selection circuit 1b, an analog/digital (A/D, hereinafter) converter 1c, and a control circuit 1d. Note that the NTC thermistor Rt may be provided within the device. Also, the A/D converter 1c may be included in the control circuit 1d.

A power supply voltage is input to a power supply terminal VCC of the semiconductor device 1, and the internal power supply generation circuit 1a generates an internal power supply voltage V0 from the power supply voltage. A reference power supply voltage is connected to the reference power supply terminal VSS of the semiconductor device 1 .

The series resistance selection circuit 1b includes a series resistance group Rg connected in series with the NTC thermistor Rt, and selects a series resistance out of the series resistance group Rg based on the selection signal sel. The A/D converter 1c A/D-converts the divided voltage V1 obtained by dividing the internal power supply voltage V0 by the NTC thermistor Rt and the series resistor selected by the series resistor selection circuit 1b, and converts it into temperature information. It outputs the corresponding divided voltage data V1d. The A/D converter 1c is, for example, a SAR type A/D converter or a ΔΣ type A/D converter.

The control circuit 1d operates the A/D converter 1c at a low resolution in a low bit number mode according to the bit number switching signal d1 during the period in which the series resistor is selected from the series resistor group Rg, and divides the voltage data V1d. The selection signal sel is output to sequentially change the series resistors until the V falls within a predetermined voltage range (state St1).

After the control circuit 1d selects the series resistance (optimum series resistance) in which the divided voltage data V1d falls within the predetermined voltage range, the bit number switching signal d1 causes the A/D converter 1c to switch to the high mode in the high bit number mode. Operate at the resolution (state St2).

Thus, in the semiconductor device 1, the A/D converter 1c is operated in the low bit number mode during the period of selecting the series resistor connected to the NTC thermistor Rt, and after selecting the optimum series resistor, the A/D The converter 1c is operated in high bit number mode. Needless to say, the SAR type A/D converter and the ΔΣ type A/D converter require a longer conversion time as the number of bits increases.

As a result, it is possible to shorten the selection time when selecting the optimum resistance value from among the series resistors connected to the NTC thermistor Rt, and to respond to the temperature information based on the resistance value of the selected series resistor. Since the divided voltage data V1d can be acquired, it is possible to improve the measurement accuracy.

<Structure of semiconductor device>
Next, the configuration and operation of the semiconductor device of the present invention will be described in detail. FIG. 2 is a diagram showing an example of the configuration of a semiconductor device. The semiconductor device 10 detects temperature and transmits the detected temperature information to the control device using the SENT protocol. PSI5 (Peripheral Sensor Interface 5) or DSI (Distributed System Interface) may be used as an in-vehicle communication standard other than the SENT protocol. Also, the control device is, for example, an ECU (Electronic Control Unit).

The semiconductor device 10 has a power supply terminal VCC, a reference power supply terminal VSS, an output terminal SENT, and a thermistor connection terminal THERM. Based on the internal power supply voltage V0, which is the output of the circuit 1a, a reference voltage generating circuit 11a for generating a reference voltage and a digital circuit power supply generating circuit 11b for generating a power supply for the digital circuit are provided.

Further, the semiconductor device 10 includes a series resistance selection circuit 12, a digital circuit 13 and an output buffer 14. FIG. The digital circuit 13 has the function of the control circuit 1d of FIG. 1, and includes a series resistance determination circuit 13a, an oscillator 13b, an A/D converter 13c, a logic circuit 13d, a memory 13e and an encoder 13f. Incidentally, the series resistance determination circuit 13a may be included in the logic circuit 13d. Also, the A/D converter 13c is a circuit in which an analog circuit and a digital circuit are mixed. Therefore, the A/D converter 13c is supplied with the internal power supply voltage V0 as the power supply for the internal analog circuit.

An internal power supply generation circuit 1a is connected to the power supply terminal VCC. The reference power supply terminal VSS is connected to a reference power supply voltage such as GND, and the reference power supply voltage is connected to the digital circuit 13, the terminal VL of the A/D converter 13c and the output buffer 14 in the device.

The internal power supply generation circuit 1a protects the circuits in the device from surge damage against the power supply voltage applied from the power supply terminal VCC and generates an internal power supply voltage V0. It is supplied to the voltage generating circuit 11a, the digital circuit power source generating circuit 11b, the A/D converter 13c and the output buffer .

The reference voltage generation circuit 11a generates a reference voltage VREF from the internal power supply voltage V0 and supplies the reference voltage VREF to the A/D converter 13c. The digital circuit power supply generation circuit 11 b generates a digital circuit power supply voltage from the internal power supply voltage V 0 and supplies the digital circuit power supply voltage to the digital circuit 13 .

An NTC thermistor Rt is externally attached to the thermistor connection terminal THERM and the reference power supply terminal VSS. One end of the NTC thermistor Rt connected to the thermistor connection terminal THERM is connected to the series resistance selection circuit 12 and the terminal VIN of the A/D converter 13c.

The series resistance determination circuit 13a transmits a selection signal sel-x (x=0, 1, 2, . . . ) to the series resistance selection circuit 12 for selecting a series resistance. Series resistor selection circuit 12 includes a series resistor group consisting of a plurality of series resistors, and selects a series resistor to be connected to NTC thermistor Rt from the series resistor group based on selection signal sel-x. Oscillator 13b oscillates a reference clock and a clock signal AD-CLK synchronized with the reference clock.

In the A/D converter 13c, the reference voltage VREF is input to the terminal VH, and the divided voltage V1 is input to the terminal VIN. The A/D converter 13c is, for example, a SAR type A/D converter or a ΔΣ type A/D converter, and converts the analog divided voltage V1 input to the terminal VIN in synchronization with the clock signal AD-CLK. , into temperature data, which is digital divided voltage data, and transmits the temperature data to the logic circuit 13d.

The logic circuit 13d operates in synchronization with a reference clock, and performs a correction operation on the data output from the A/D converter 13c based on the parameter values and correction coefficients of various characteristics stored in the memory 13e, The calculation result is output to the encoder 13f. In addition, the logic circuit 13d performs communication according to, for example, I2C (Inter Integrated Circuit) as a communication standard via an access port (not shown).

The logic circuit 13d is connected to the test terminal via I2C, for example, and rewrites the parameter values and correction coefficients stored in the memory 13e based on I2C format data transmitted from the test terminal. can be done.

The encoder 13f converts the temperature data into the format of the SENT protocol and transmits it to the output buffer 14. FIG. The output buffer 14 includes a PMOS transistor m1 that is a P-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and an NMOS transistor m2 that is an N-channel MOSFET.

The gate of PMOS transistor m1 is connected to the gate of NMOS transistor m2 and the output terminal of encoder 13f. An internal power supply voltage V0 is input to the source of the PMOS transistor m1, and the source of the NMOS transistor m2 is connected to the reference power supply terminal VSS.

The drain of the PMOS transistor m1 is connected to the drain of the NMOS transistor m2 and the output terminal SENT. The output buffer 14 having such a configuration buffers the temperature data output from the encoder 13f and outputs the temperature data to the control device via the output terminal SENT.

<Structure of series resistor selection circuit>
FIG. 3 is a diagram showing an example of the configuration of a series resistance selection circuit. The series resistor selection circuit 12-1 includes resistors R0, . . . , R4 and analog switches sw0, . The resistors R0, . . . , R4 are series resistors that can be connected to the NTC thermistor Rt, and have different resistance values.

Analog switch sw0 includes PMOS transistor Mp0, NMOS transistor Mn0 and inverter IC0, analog switch sw1 includes PMOS transistor Mp1, NMOS transistor Mn1 and inverter IC1, and analog switch sw2 includes PMOS transistor Mp2, NMOS transistor Mn2 and inverter. Includes IC2.

Similarly, analog switch sw3 includes PMOS transistor Mp3, NMOS transistor Mn3 and inverter IC3, and analog switch sw4 includes PMOS transistor Mp4, NMOS transistor Mn4 and inverter IC4.

The connection relationship of each component will be described. One end of the resistor R0 is connected to one end of the resistors R1, . . . , R4. An internal power supply voltage V0 is input to one end of the resistors R0, . . . , R4. The other end of resistor R0 is connected to the source of PMOS transistor Mp0 and the drain of NMOS transistor Mn0. The gate of NMOS transistor Mn0 is connected to the input terminal of inverter IC0, and the gate of PMOS transistor Mp0 is connected to the output terminal of inverter IC0. A selection signal sel-0 output from the series resistance determination circuit 13a is input to the gate of the NMOS transistor Mn0 and the input terminal of the inverter IC0.

The other end of resistor R1 is connected to the source of PMOS transistor Mp1 and the drain of NMOS transistor Mn1. The gate of the NMOS transistor Mn1 is connected to the input terminal of the inverter IC1, and the gate of the PMOS transistor Mp1 is connected to the output terminal of the inverter IC1. A selection signal sel-1 output from the series resistance determination circuit 13a is input to the gate of the NMOS transistor Mn1 and the input terminal of the inverter IC1.

The other end of resistor R2 is connected to the source of PMOS transistor Mp2 and the drain of NMOS transistor Mn2. The gate of the NMOS transistor Mn2 is connected to the input terminal of the inverter IC2, and the gate of the PMOS transistor Mp2 is connected to the output terminal of the inverter IC2. A selection signal sel-2 output from the series resistance determination circuit 13a is input to the gate of the NMOS transistor Mn2 and the input terminal of the inverter IC2.

The other end of resistor R3 is connected to the source of PMOS transistor Mp3 and the drain of NMOS transistor Mn3. The gate of the NMOS transistor Mn3 is connected to the input terminal of the inverter IC3, and the gate of the PMOS transistor Mp3 is connected to the output terminal of the inverter IC3. A selection signal sel-3 output from the series resistance determination circuit 13a is input to the gate of the NMOS transistor Mn3 and the input terminal of the inverter IC3.

The other end of resistor R4 is connected to the source of PMOS transistor Mp4 and the drain of NMOS transistor Mn4. The gate of NMOS transistor Mn4 is connected to the input terminal of inverter IC4, and the gate of PMOS transistor Mp4 is connected to the output terminal of inverter IC4. A selection signal sel-4 output from the series resistance determination circuit 13a is input to the gate of the NMOS transistor Mn4 and the input terminal of the inverter IC4.

Furthermore, the node OUT is connected to the drain of the PMOS transistor Mp0 and the source of the NMOS transistor Mn0, connected to the drain of the PMOS transistor Mp1 and the source of the NMOS transistor Mn1, and connected to the drain of the PMOS transistor Mp2 and the source of the NMOS transistor Mn2. be.

Furthermore, the node OUT is connected to the drain of the PMOS transistor Mp3 and the source of the NMOS transistor Mn3, and is connected to the drain of the PMOS transistor Mp4 and the source of the NMOS transistor Mn4. A divided voltage V1 is output from the node OUT.

A plurality of series resistors R0, . . . , R4 are prepared as described above, and the analog switches sw0, . , any one of the series resistors R0, . . . , R4 can be selected.

For example, when the selection signal sel-4 is at H level and the selection signals sel-0, . Therefore, the divided voltage V1 obtained by dividing the internal power supply voltage V0 by the NTC thermistor Rt and the resistor R4 is output from the node OUT.

FIG. 4 is a diagram showing an example of the configuration of a series resistance selection circuit. The series resistance selection circuit 12-2 has the same basic configuration as the series resistance selection circuit 12-1 shown in FIG. , R4 among the resistors R0, . . . , R4 are weighted based on the resistance value of the resistor R0.

Also, in FIG. 3, only one selection signal sel-x is set to H level to select one resistor, but in the configuration of FIG. 4, one or more selection signals sel-x are set to H level to select one or Multiple resistors can be selected.

For example, if the resistance value of the resistor R0 is R, the resistance value of the resistor R1 is 2R, which is twice R, the resistance value of the resistor R2 is 4R, which is ²² times R, and the resistance value of the resistor R3 is ²³ R. The resistance value of the resistor R4 is 16R, which is ²⁴ times the value of R.

If the selection signals sel-0 and sel-1 are set to H level and the selection signals sel-2, sel-3 and sel-4 are set to L level, the combined resistance of resistors R0 and R1 is selected. Become. With such a configuration, as the resistance value of the series resistor connected to the NTC thermistor Rt, it is possible to set the resistance value more subdivided at equal intervals than in the configuration of FIG.

<Temperature dependence of divided voltage for each series resistor>
FIG. 5 is a diagram showing the temperature dependence of the divided voltage for each series resistor. The vertical axis is divided voltage (V) and the horizontal axis is temperature (°C). Graphs k1, .

Here, the range of the divided voltage from the threshold value A to the threshold value B (hereinafter sometimes referred to as the temperature dependent unsaturated region) is the temperature dependent voltage with respect to the temperature change. change is large. Therefore, in the temperature range to be measured, the temperature measurement accuracy is improved by selecting a series resistor that has a resistance value that allows the divided voltage to fall within the temperature-dependent unsaturated region between threshold A and threshold B. can be made

<Operation of Series Resistance Determining Circuit>
FIG. 6 is a flow chart showing the operation of the series resistance determination circuit.
[Step S1] The series resistance determination circuit 13a transmits to the series resistance selection circuit 12 a selection signal sel-x for selecting a series resistance Rx from a plurality of series resistances included in the series resistance selection circuit 12. FIG.

[Step S2] The series resistance determination circuit 13a sends a bit number switching signal d1 to the A/D converter 13c to change the bit number mode of the A/D converter 13c to a low bit number mode (for example, a 2-bit number mode). set to

[Step S3] The series resistance determination circuit 13a determines whether or not the temperature data after A/D conversion of the divided voltage V1 is included in the temperature dependent unsaturated region between the threshold A and the threshold B. If the temperature data is not included in the voltage range corresponding to the temperature dependent desaturation region, the process proceeds to step S4, and if the temperature data is included in the voltage range corresponding to the temperature dependent desaturation region, the processing is performed in step S5. proceed to

[Step S4] The series resistance determination circuit 13a increments x to generate and output a selection signal sel-(x+1) for selecting a new series resistance R(x+1). Return to the process of step S1.

[Step S5] The series resistance determination circuit 13a determines and fixes the selected series resistance as the optimum series resistance.
[Step S6] The series resistance determination circuit 13a sends a bit number switching signal d1 to the A/D converter 13c to change the bit number mode of the A/D converter 13c to a normal high bit number mode (for example, 12 bits). number mode).

As described above, the series resistance determination circuit 13a causes the A/D converter 13c to operate at high speed in the low bit number mode during the period of selecting the series resistance connected to the NTC thermistor Rt. While sequentially changing the series resistance of , determination is made to select the optimum series resistance.

In this case, the A/D converter 13c A/D-converts the divided voltage V1 output from the series resistance selection circuit 12 each time the series resistance is sequentially changed in the low bit number mode, and the digital conversion value (temperature data ) is within the voltage range between the threshold A and the threshold B or not.

As shown in FIG. 5, if the resistance value of the series resistor is appropriately set in a predetermined temperature range, a region in which the divided voltage resistance temperature dependence is large (accurate) can be used. Also, when selecting the series resistor, the threshold A and the threshold B are appropriately set, and the bit number mode of the A/D converter 13c is set to 2 bits, 3 bits, etc. during the determination of the selection of the series resistor. High-speed A/D conversion is performed in the low bit number mode.

This allows the selection of series resistors to be completed in a short period of time. In addition, after the optimum series resistance is selected, A/D conversion is performed in the original high bit number mode, so it is possible to acquire temperature data with high accuracy.

<Physical quantity sensor device>
Next, a case where the semiconductor device 1, 10 of the present invention is applied to a physical quantity sensor device will be described in detail. In addition, the same code|symbol may be attached to the structure already mentioned henceforth, and description of the same structure may be abbreviate|omitted.

FIG. 7 is a diagram showing an example of the configuration of a physical quantity sensor device. The physical quantity sensor device 10 a includes a physical quantity sensor 15 and a multiplexer (MUX) 16 as new components to the semiconductor device 10 . Other components are the same as those of the semiconductor device 10 .

The physical quantity sensor 15 includes a constant current source I0, resistors R11, . . . , R14 and an operational amplifier 15a. The internal power supply voltage V0 is input to the input end of the constant current source I0, and the output end of the constant current source I0 is connected to one end of the resistor R11 and one end of the resistor R12. The other end of the resistor R11 is connected to one end of the resistor R14 and the inverting terminal of the operational amplifier 15a. The other end of the resistor R12 is connected to one end of the resistor R13 and the non-inverting terminal of the operational amplifier 15a. The other end of the resistor R13 and the other end of the resistor R14 are connected to the reference power supply terminal VSS.

One input terminal of the multiplexer 16 receives the divided voltage V1, and the other input terminal of the multiplexer 16 receives the pressure detection signal V2 output from the operational amplifier 15a. An input switching terminal of the multiplexer 16 receives a physical quantity switching signal d2 output from the logic circuit 13d. The output signal of the multiplexer 16 is input to the terminal VIN of the A/D converter 13c.

The physical quantity sensor 15 is a sensor that detects, for example, pressure as a temperature-dependent physical quantity. Based on the physical quantity switching signal d2 output from the logic circuit 13d, the multiplexer 16 time-divisionally switches the divided voltage V1 representing the temperature information or the pressure detection signal V2 detected by the physical quantity sensor 15, and performs A/D conversion. output to the device 13c.

<Pressure detection by physical quantity sensor>
FIG. 8 is a diagram showing the relationship between stress and gauge resistance in a physical quantity sensor. The resistors R11, . A constant current is supplied from the constant current source I0. . . , R14 caused by the deflection of the diaphragm 15-1 due to pressure are amplified by the operational amplifier 15a and output as an analog value.

Specifically, it is assumed that the current from the constant current source I0 flows through the resistors R11, . . . , R14 in the arrow direction. The fact that the diaphragm 15-1 bends in a downward convex shape means that the resistors R11 and R13 are stretched in the width direction of the resistors, so that the current path is widened and the resistance value is lowered.

Conversely, since the resistors R12 and R14 extend in the direction in which the current flows, the current path is extended and the resistance value increases. The operational amplifier 15a amplifies the voltage change caused by such a change in the resistance value to detect the pressure.

<Operation of Physical Quantity Sensor Device>
FIG. 9 is a timing chart showing the operation of the physical quantity sensor device. Before showing the operation timing chart of the present invention, an operation timing chart in a configuration that does not have the function of the present invention will be described with reference to FIG. 9 (the operation timing chart of the present invention will be described later with reference to FIG. 10).

[Period t1] The multiplexer 16 enters the pressure information output state based on the physical quantity switching signal d2. The A/D converter 13c A/D-converts the pressure detection signal V2 detected by the physical quantity sensor 15 in a high bit number mode, and outputs pressure data pd1 after A/D conversion.

[Period t2] The multiplexer 16 enters the temperature information output state based on the physical quantity switching signal d2. The A/D converter 13c A/D-converts the divided voltage V1 generated by the NTC thermistor Rt and the fixed series resistor in a high bit number mode, and outputs temperature data td1 after A/D conversion. The logic circuit 13d also performs a temperature characteristic correction operation using the pressure data pd1, the temperature data td1, and the correction coefficient stored in the memory 13e to generate corrected pressure data p1.

[Period t3] The encoder 13f converts the pressure data p1 into the format of the SENT protocol, and the output buffer 14 starts outputting the pressure data p1 based on the SENT protocol.

On the other hand, the multiplexer 16 is put into a pressure information output state based on the physical quantity switching signal d2. The A/D converter 13c A/D-converts the pressure detection signal V2 detected by the physical quantity sensor 15 in a high bit number mode, and outputs pressure data pd2 after A/D conversion.

[Period t4] The multiplexer 16 enters the temperature information output state based on the physical quantity switching signal d2. The A/D converter 13c A/D-converts the divided voltage V1 generated by the NTC thermistor Rt and the fixed series resistor in a high bit number mode, and outputs temperature data td2 after A/D conversion. The logic circuit 13d also performs a temperature characteristic correction operation using the pressure data pd2, the temperature data td2, and the correction coefficient stored in the memory 13e to generate corrected pressure data p2.

On the other hand, the output of the pressure data p1 is terminated. Also, the encoder 13f converts the pressure data p2 into the format of the SENT protocol, and the output buffer 14 starts outputting the pressure data p2 based on the SENT protocol. This is repeated in the same way.

FIG. 10 is a timing chart showing the operation of the physical quantity sensor device. 8 is an operation timing chart of the physical quantity sensor device 10a of the present invention shown in FIG. 7;
[Period t1] The multiplexer 16 enters the pressure information output state based on the physical quantity switching signal d2. The A/D converter 13c A/D-converts the pressure detection signal V2 (physical quantity detection signal) detected by the physical quantity sensor 15 in a high bit number mode, and converts the A/D-converted pressure data Pd1 (first physical quantity detection data).

[Period t2] The multiplexer 16 enters the temperature information output state based on the physical quantity switching signal d2.
(Period t2a) The A/D converter 13c enters the low bit number mode based on the bit number switching signal d1, and outputs the first temperature data obtained by A/D converting the divided voltage V1 in the low bit number mode. . Also, the series resistance determination circuit 13a determines the optimum series resistance such that the first temperature data falls within the temperature dependent non-saturation region, and selects the optimum series resistance.

(Period t2b) The A/D converter 13c switches to the high bit number mode based on the bit number switching signal d1, and converts the divided voltage V1 generated by the NTC thermistor Rt and the selected optimum series resistor into an A/D converter. The temperature data Td1 (second temperature data) after D conversion and A/D conversion is output.

Further, the logic circuit 13d performs a temperature characteristic correction operation using the pressure data Pd1, the temperature data Td1, and the correction coefficient stored in the memory 13e, and the corrected pressure data P1 (second physical quantity detection data).

[Period t3] The encoder 13f converts the pressure data P1 into the format of the SENT protocol, and the output buffer 14 starts outputting the pressure data P1 based on the SENT protocol.

On the other hand, the multiplexer 16 is put into a pressure information output state based on the physical quantity switching signal d2. The A/D converter 13c A/D-converts the pressure detection signal V2 detected by the physical quantity sensor 15 in a high bit number mode, and outputs pressure data Pd2 after A/D conversion.

[Period t4] The multiplexer 16 enters the temperature information output state based on the physical quantity switching signal d2.
(Period t4a) The A/D converter 13c enters the low bit number mode based on the bit number switching signal d1, and outputs the first temperature data obtained by A/D converting the divided voltage V1 in the low bit number mode. . Also, the series resistance determination circuit 13a determines the optimum series resistance such that the first temperature data falls within the temperature dependent non-saturation region, and selects the optimum series resistance.

(Period t4b) The A/D converter 13c switches to the high bit number mode based on the bit number switching signal d1, and converts the divided voltage V1 generated by the NTC thermistor Rt and the selected optimum series resistance to A/D. It is D-converted and outputs temperature data Td2 after A/D conversion.

The logic circuit 13d also performs a temperature characteristic correction operation using the pressure data Pd2, the temperature data Td2, and the correction coefficient stored in the memory 13e to generate corrected pressure data P2.

On the other hand, the output of the pressure data P1 is terminated. Further, the encoder 13f converts the pressure data P2 into the SENT protocol format, and the output buffer 14 starts outputting the pressure data P2 based on the SENT protocol. This is repeated in the same way.

Thus, in the present invention, by switching the physical quantity of the multiplexer 16, the logic circuit 13d sequentially acquires the pressure data and the temperature data, and corrects the pressure data based on the temperature data and the correction coefficient. The corrected pressure data is then converted into the SENT format and transmitted to, for example, the ECU.

In this case, when acquiring the temperature data, the A/D converter 13c was operated in the low bit number mode according to the flowchart shown in FIG. After that, the A/D converter 13c is operated in the high bit number mode to obtain the temperature data. Therefore, in the physical quantity sensor device 10a, processing from selection of the optimum series resistance to acquisition of temperature data can be performed efficiently in a short time compared to the case of always operating in the high bit number mode as shown in FIG. be possible.

For example, the SENT protocol stipulates the transmission time for one message, so when operating in the high bit number mode as shown in FIG. is difficult to implement. On the other hand, in the present invention, which operates in the low-bit number mode when selecting the optimum series resistance, by selecting the optimum series resistance, it is possible to use a region in which the division voltage resistance temperature dependence is large (accuracy is obtained). Therefore, it is possible to correct the temperature characteristic with high accuracy.

<Correction calculation>
Next, correction calculation will be described. For the correction calculation of the physical quantity having temperature dependence, for example, the following correction calculation described in Patent Document 2 can be used.

FIG. 11 is a diagram showing the relationship between ideal pressure data and measured pressure data. The vertical axis is ideal pressure data, and the horizontal axis is measured pressure data. Graph k11 shows the relationship between ideal pressure data and measured pressure data at low temperatures, graph k12 shows the relationship between ideal pressure data and measured pressure data at medium temperatures, and graph k13 shows the ideal pressure data and measured pressure data at high temperatures. It shows the relationship with the data.

By approximating the graphs k11, k12, and k13 to quadratic curves by the method of least squares, the following equations (1a), (1b), and (1c) are obtained. Formula (1a) is the quadratic curve of graph k11 at low temperature, formula (1b) is the quadratic curve of graph k12 at medium temperature, and formula (1c) is the quadratic curve of graph k13 at high temperature. . Note that an, _bn , and _cn (n=1, 2, 3) are correction coefficients _.

y= _a1x2 + _b1x + _c1 ⁽ 1a)
y ⁼ _a2x2 + _b2x + _c2 (1b)
y ⁼ _a3x2 + _b3x + _c3 (1c)
FIG. 12 is a diagram showing the relationship between correction coefficients and temperature data. The vertical axis is the correction coefficient value, and the horizontal axis is the temperature data. Graph k21 shows changes in temperature data with correction coefficient _an , graph k22 shows changes in temperature data with correction coefficient _bn , and graph k23 shows changes in temperature data with correction coefficient _cn . ing.

Approximating each correction coefficient to a quadratic curve by the method of least squares yields the following equations (2a), (2b), and (2c). Equation (2a) is the quadratic curve a _(Temp) with respect to the second-order correction factor an, Equation (2b) is the quadratic curve b _(Temp) with respect to the first-order correction factor bn, and Equation (2c) is the constant cn is a quadratic curve c _(Temp) for .

a _(Temp) = a _T2 x ² + a _T1 x + a _Tc (2a)
b _(Temp) = b _T2 x ² + b _T1 x + b _Tc (2b)
c _(Temp) = _cT2x2 + _cT1x + ^cTc ₍ 2c)
Nine correction coefficients obtained from the above equations (2a), (2b) and (2c) are held. Then, the pressure data is obtained by back calculation. For example, a _(Temp) , b _(Temp) and c _(Temp) are calculated from temperature data, and desired pressure data is obtained from a _(Temp) , b _(Temp) and c _{(Temp) and} measured pressure data values. Desired.

<Variable control of operating voltage range of A/D converter according to low/high bit number mode>
Next, control for variably switching the operating voltage range of the A/D converter according to the low bit number mode or the high bit number mode will be described.

FIG. 13 is a diagram showing the operating voltage range of the A/D converter. The operating voltage range Hv1 of the A/D converter 13c in the semiconductor device 10 shown in FIG. 2 is shown with respect to the graph showing the temperature dependence of the divided voltage for each series resistor shown in FIG.

In the semiconductor device 10, as described above, the A/D converter 13c is operated in the low bit number mode during the period of selecting the optimum series resistance, and after the selection of the optimum series resistance, the A/D converter 13c is operated in the high mode. It's running in bit mode.

Further, when performing such control, in the semiconductor device 10, the operating voltage range Hv1 of the A/D converter 13c is set from the reference power supply voltage (eg, GND (0V)) input to the reference power supply terminal VSS. The range is up to the reference voltage VREF (eg, 5 V) generated by the voltage generation circuit 11a.

That is, in the semiconductor device 10, A/D conversion is performed in the same operating voltage range Hv1 from 0 V to 5 V in both the A/D conversion in the low bit number mode and the A/D conversion in the high bit number mode. ing.

However, after selecting an optimum series resistor with a resistance value such that the divided voltage falls into the temperature dependent desaturation region between threshold A and threshold B, the high bit number mode of operation in A/D converter 13c Then, the voltage in the range from the threshold A to the threshold B should be input to the A/D converter 13c as the operating voltage.

Here, it is assumed that the bit resolution of the A/D converter 13c is 12 bits, for example. In this case, since there are 4096 (=2 ¹² ) gradations, the voltage width (quantization error) of one gradation is 1.2 mV (=5V/4096).

Assuming that the voltage of the threshold A is 1.25 V and the voltage of the threshold B is 3.75 V, when the A/D converter 13c operates in the high bit number mode, 0 V to 1.25 V corresponding to 0 V to 1.25 V The gradation of 1023LSB (Least Significant Byte) and the gradation of 3072 to 4095LSB corresponding to 1.25V to 5V are not used in the first place.

Therefore, when the A/D converter 13c operates in the high bit number mode, it is not necessary to input the operating voltage in the range Hv1 of 0 V to 5 V to the A/D converter 13c. ) to the threshold value B (the upper limit voltage of the predetermined voltage range) may be input to the A/D converter 13c as the operating voltage.

Therefore, in the variable control of the operating voltage range of the A/D converter 13c in the present invention, A/D conversion is performed according to the A/D conversion in the low bit number mode and the A/D conversion in the high bit number mode. The range of the operating voltage input to the device 13c is efficiently switched and controlled.

FIG. 14 is a diagram showing the operating voltage range of the A/D converter. Ranges Hv1 and Hv2 of the operating voltage of the A/D converter 13c that vary according to the low/high bit number mode are shown in the graph showing the temperature dependence of the divided voltage for each series resistor shown in FIG. It is

When the A/D converter 13c operates in the low bit number mode, an operating voltage in the range Hv1 of 0 V to 5 V is input to the A/D converter 13c, and the A/D converter 13c operates in the high bit number mode. In this case, the A/D converter 13c is controlled to receive an operating voltage in the range Hv2 from the threshold A to the threshold B (1.25 V to 3.75 V).

FIG. 15 is a diagram showing an example of the configuration of a semiconductor device. The semiconductor device 10-1 is a device that further has a variable control function of the operating voltage range for the A/D converter 13c, in contrast to the semiconductor device 10 of FIG. The semiconductor device 10-1 includes a reference voltage generation circuit 11a1 and a digital circuit 13-1. The digital circuit 13-1 includes multiplexers 13g1 and 13g2. Other components are the same as those of the semiconductor device 10 of FIG.

The reference voltage generation circuit 11a1 generates reference voltages VREF1, VREF2 and VREF3 from the internal power supply voltage V0, supplies the reference voltages VREF1 and VREF2 to the multiplexer 13g1, and supplies the reference voltage VREF3 to the multiplexer 13g2. Note that the reference voltage VREF1 is, for example, 5V. Also, the reference voltage VREF2 is the voltage of the threshold B, for example, 3.75V. The reference voltage VREF3 is the voltage of the threshold A and is, for example, 1.25V.

In the multiplexer 13g1, the reference voltage VREF1 is input to one input terminal a of the multiplexer 13g1, and the reference voltage VREF2 is input to the other input terminal b. A bit number switching signal d1 output from the series resistance determination circuit 13a is input to the input switching terminal of the multiplexer 13g1. The output signal of the multiplexer 13g1 is input to the terminal VH (high potential side operating voltage input terminal) of the A/D converter 13c.

In the multiplexer 13g2, one input terminal a of the multiplexer 13g2 is connected to GND, and the reference voltage VREF3 is input to the other input terminal b. Further, the bit number switching signal d1 output from the series resistance determination circuit 13a is input to the input switching terminal of the multiplexer 13g2. The output signal of the multiplexer 13g2 is input to the terminal VL (low potential side operating voltage input terminal) of the A/D converter 13c.

(Operating voltage range of A/D converter 13c in low bit number mode)
The series resistance determination circuit 13a transmits the bit number switching signal d1 to the A/D converter 13c to set the bit number mode of the A/D converter 13c to the low bit number mode. When the multiplexer 13g1 receives the bit number switching signal d1 when the low bit number mode is set, it selects the reference voltage VREF1 (5V) input to the input terminal a, and applies the reference voltage to the terminal VH of the A/D converter 13c. Output VREF1 (5V).

When the multiplexer 13g2 receives the bit number switching signal d1 when the low bit number mode is set, it selects the GND (0 V) input to the input terminal a and applies 0 V to the terminal VL of the A/D converter 13c. Output. Therefore, when performing A/D conversion in the low bit number mode, the A/D converter 13c performs A/D conversion with an operating voltage in the range of 0V to 5V (range Hv1 in FIG. 14). .

(Operating voltage range of A/D converter 13c in high bit number mode)
After the optimum series resistance is determined, the series resistance determination circuit 13a transmits the bit number switching signal d1 to the A/D converter 13c to set the bit number mode of the A/D converter 13c to the high bit number mode. . When the multiplexer 13g1 receives the bit number switching signal d1 when the high bit number mode is set, the multiplexer 13g1 selects the reference voltage VREF2 (3.75 V: threshold value B) input to the input terminal b, and the A/D converter 13c A reference voltage VREF2 (3.75 V: threshold B) is output to the terminal VH.

When the multiplexer 13g2 receives the bit number switching signal d1 when the high bit number mode is set, the multiplexer 13g2 selects the reference voltage VREF3 (1.25 V: threshold value A) input to the input terminal b, and the A/D converter A reference voltage VREF3 (1.25 V: threshold value A) is output to the terminal VL of 13c. Therefore, when performing A/D conversion in the high bit number mode, the A/D converter 13c performs A/D conversion with an operating voltage in the range of 1.25 V to 3.75 V (range Hv2 in FIG. 14). will do.

FIG. 16 is a diagram showing an example of the configuration of a physical quantity sensor device. The physical quantity sensor device 10a-1 is a device that, in contrast to the physical quantity sensor device 10a of FIG. 7, further has a variable control function for the operating voltage range for the A/D converter 13c.

A physical quantity sensor device 10a-1 includes a reference voltage generation circuit 11a1 and a digital circuit 13-1. The digital circuit 13-1 includes multiplexers 13g1 and 13g2. Other components are the same as those of the physical quantity sensor device 10a of FIG. Note that the switching control of the operating voltage range of the A/D converter 13c in the low/high bit number mode in the physical quantity sensor device 10a-1 is the same as the switching control described above with reference to FIG. 15, so the description thereof will be omitted.

Here, in the semiconductor device 10-1, in the stage of selecting the optimum resistance from among the series resistances connected to the NTC thermistor Rt, the internal power supply voltage is determined by the NTC thermistor Rt and the series resistance selected by the series resistance selection circuit 13a. It is necessary to A/D convert a wide input range of the divided voltage V1 obtained by dividing V0. Also, in the stage of selecting the optimum resistance, the A/D converter 13c operates in the low bit number mode.

Therefore, as described above, in the semiconductor device 10-1, when the A/D converter 13c operates at high speed in the low bit number mode, a voltage lower than the threshold A and a voltage higher than the threshold B are converted into A/D converters. The voltage is input to the D converter 13c to widen the operating voltage range of the A/D converter 13c as the range Hv1 (0 V to 5 V).

On the other hand, after selecting the optimum series resistance, it is determined that the divided voltage V1 is within the range from threshold A to threshold B, which is the temperature dependent non-saturation region. Also, after selecting the optimum series resistance, the A/D converter 13c operates in the high bit number mode.

Therefore, as described above, in the semiconductor device 10-1, when the A/D converter 13c operates at low speed in the high bit number mode, the operating voltage range of the A/D converter 13c is set from the threshold A to the threshold The range of B is narrowed to Hv2. The same control is applied to the physical quantity sensor device 10a-1.

Thus, according to the present invention, by variably controlling the operating voltage range of the A/D converter according to the low/high bit number mode, the quantization error is reduced and the A/D conversion is performed with high accuracy. conversion can be done. For example, when the bit resolution of the A/D converter 13c is 12 bits, there are 4096 (=2 ¹² ) gradations, the voltage of threshold A is 1.25 V, and the voltage of threshold B is 3.75 V. .

At this time, when the A/D converter 13c operates in the high bit number mode, the voltage width (quantization error) of one gradation is 0.6 mV (=(3.75V-1.25V)/4096). The resolution is twice as high as the above 1.2 mV (=5V/4096).

Although the embodiment has been exemplified above, the configuration of each part shown in the embodiment can be replaced with another one having the same function. Also, any other components or steps may be added. Furthermore, any two or more configurations (features) of the above-described embodiments may be combined.

1 semiconductor device 1a internal power supply generation circuit 1b series resistor selection circuit 1c A/D converter 1d control circuit Rg series resistor group Rt NTC thermistor VCC power supply terminal VSS reference power supply terminal V0 internal power supply voltage V1 divided voltage V1d divided voltage data sel Selection signal d1 Bit number switching signal St1, St2 State

Claims (19)

a thermistor for temperature detection;
a series resistor selection circuit including a series resistor group connected in series with the thermistor and selecting a series resistor from the series resistor group based on a selection signal;
an analog/digital converter that analog/digital converts a divided voltage obtained by dividing the internal power supply voltage by the thermistor and the series resistor and outputs divided voltage data;
In the series resistor selection period, the analog/digital converter is operated in a low bit number mode to select an optimum series resistance in which the divided voltage data falls within a predetermined voltage range, and after the selection of the optimum series resistance, the analog a control circuit for operating the /digital converter in a high bit number mode;
A semiconductor device having 2. The semiconductor device according to claim 1, wherein said predetermined voltage range is a voltage range corresponding to a non-saturated region in which the temperature dependence of the divided voltage is non-saturated within the temperature range to be measured. 2. The semiconductor device according to claim 1, wherein said series resistance selection circuit comprises said series resistance group and a switch group for selecting said series resistance from said series resistance group based on said selection signal. The series resistor group includes a plurality of series resistors having resistance values that are weighted by multiplying the resistance value of the unit series resistor by 2 squared, and the series resistor selection circuit selects the switch group based on the selection signal. 4. The semiconductor device according to claim 3, wherein a combined resistance of said series resistors is selected by a combination of . An output unit for converting the divided voltage data output from the analog/digital converter operating in the high bit number mode after the selection of the optimum series resistance into a format corresponding to a communication standard and outputting the data, 2. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 5, wherein said communication standard is one of SENT (Single Edge Nibble Transmission), PSI5 (Peripheral Sensor Interface 5), and DSI (Distributed System Interface). 2. The semiconductor device according to claim 1, wherein said analog/digital converter has a successive approximation type or delta-sigma type analog/digital conversion function. The control circuit sets the first operating voltage range when operating the analog/digital converter in the high bit number mode to be higher than the second operating voltage range when operating the analog/digital converter in the low bit number mode. 2. The semiconductor device of claim 1, narrowed. The control circuit is
inputting an upper limit voltage and a lower limit voltage of the predetermined voltage range as the first operating voltage range to the analog/digital converter;
inputting a voltage higher than the upper limit voltage and a voltage lower than the lower limit voltage to the analog/digital converter as the range of the second operating voltage;
9. The semiconductor device according to claim 8. a thermistor for temperature detection;
a physical quantity sensor that detects a physical quantity and outputs a physical quantity detection signal;
a series resistor selection circuit including a series resistor group connected in series with the thermistor and selecting a series resistor from the series resistor group based on a selection signal;
a multiplexer that switches and outputs a divided voltage obtained by dividing the internal power supply voltage by the thermistor and the series resistor and the physical quantity detection signal based on a switching signal;
an analog/digital converter that analog/digital converts the divided voltage and the physical quantity detection signal output from the multiplexer;
The switching signal causes the multiplexer to output the physical quantity detection signal, the analog/digital converter is operated in the high bit number mode, the physical quantity detection signal is analog/digital converted in the high bit number mode, and the first Get the physical quantity detection data of
During the selection period of the series resistor, the switching signal causes the multiplexer to output the divided voltage, the analog/digital converter is operated in the low bit number mode, and the divided voltage is converted to analog in the low bit number mode. / Selecting the optimum series resistance in which the first temperature data obtained by digital conversion falls within a predetermined voltage range,
After selecting the optimum series resistance, the analog/digital converter is operated in the high bit number mode to analog/digital convert the divided voltage in the high bit number mode to obtain second temperature data. ,
a control circuit that calculates the first physical quantity detection data based on the second temperature data and a correction coefficient to generate second physical quantity detection data;
A physical quantity sensor device having 11. The physical quantity sensor device according to claim 10, wherein said predetermined voltage range is a voltage range corresponding to a non-saturated region in which the temperature dependency of the divided voltage is non-saturated within the temperature range of the object to be measured. 11. The physical quantity sensor device according to claim 10, wherein said physical quantity sensor detects pressure as said physical quantity having temperature dependence. 11. The physical quantity sensor device according to claim 10, wherein said series resistance selection circuit comprises said series resistance group and a switch group for selecting said series resistance from said series resistance group based on said selection signal. The series resistor group includes a plurality of series resistors having resistance values that are weighted by multiplying the resistance value of the unit series resistor by 2 squared, and the series resistor selection circuit selects the switch group based on the selection signal. 14. The physical quantity sensor device according to claim 13, wherein a combined resistance of said series resistors is selected by a combination of . 11. The physical quantity sensor device according to claim 10, further comprising an output unit that converts the second physical quantity detection data into a format corresponding to a communication standard and outputs the format. 16. The physical quantity sensor device according to claim 15, wherein said communication standard is one of SENT (Single Edge Nibble Transmission), PSI5 (Peripheral Sensor Interface 5), and DSI (Distributed System Interface). 11. The physical quantity sensor device according to claim 10, wherein said analog/digital converter has a successive approximation type or delta sigma type analog/digital conversion function. The control circuit sets the first operating voltage range when operating the analog/digital converter in the high bit number mode to be higher than the second operating voltage range when operating the analog/digital converter in the low bit number mode. 11. The physical quantity sensor device according to claim 10, narrowed. The control circuit is
inputting an upper limit voltage and a lower limit voltage of the predetermined voltage range as the first operating voltage range to the analog/digital converter;
inputting a voltage higher than the upper limit voltage and a voltage lower than the lower limit voltage to the analog/digital converter as the range of the second operating voltage;
19. The physical quantity sensor device according to claim 18.

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