JP2023103470A - game machine - Google Patents

Abstract

To provide a game machine capable of efficiently executing control related to a performance image.SOLUTION: A game machine capable of executing processing for switching functions between a drawing output destination buffer and a frame buffer includes: registration means for registering image information in the drawing output destination buffer; performance image display control means for controlling a performance image on the basis of the registered image information; first light emission means; operation means for changing the brightness of the first light emission means; first light emission control means for changing the brightness of the first light emission means on the basis of the operation of the operation means; second light emission means; and second light emission control means for changing the brightness of the second light emission means. When temporary stop image information is registered in the switched frame buffer, the registration means registers the temporary stop image information in the switched drawing output destination buffer. When the brightness of the first light emission means is changed, the second light emission control means changes the brightness of the second light emission means at a timing different from that of the first light emission means.SELECTED DRAWING: Figure 52

Description

The present invention relates to a game machine such as a pachinko machine.

2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed, for example, on a liquid crystal display based on the result of the lottery.

As this type of gaming machine, there is known a gaming machine that decodes compressed image data, appropriately converts the decoded image data, stores it in a frame buffer, and outputs it to a display device (see, for example, Patent Document 1).

JP 2014-87402 A

By the way, in recent years, there has been an increase in variations in the effect images displayed on the display device, and the control of the effect images tends to be complicated. In such a case, it is desirable to efficiently control the effect image.

The present invention has been made in view of such a point, and an object of the present invention is to provide a gaming machine capable of efficiently performing control related to effect images.

The game machine according to the present invention is
A gaming machine capable of executing processing (e.g., bank flip) to switch functions between a drawing output destination buffer having a drawing function and a frame buffer having a display function,
a registration means (for example, a display control circuit 2300 capable of executing steps S1448 and S1457) capable of registering image information (for example, composition) relating to an effect image to be displayed on a predetermined display means in the drawing output destination buffer;
effect image display control means (for example, a display control circuit 2300) for controlling display of a effect image on the predetermined display means based on the image information registered by the registration means after the drawing output destination buffer is switched to the frame buffer (for example, after the processing of step S1446 is performed);
a first light emitting means (e.g., backlight) capable of emitting light in a predetermined manner;
an operation means (for example, a luminance setting screen displayed on a liquid crystal display device used as the display device 13) capable of changing the luminance of the first light emitting means;
a first light emission control means (for example, the host control circuit 210 that executes the process of step S384) capable of changing the luminance of the first light emission means based on the operation of the operation means;
a second light-emitting means (for example, a board-side LED or a frame-side LED) provided separately from the first light-emitting means;
a second light emission control means (for example, a host control circuit 210 that executes the process of step S385) capable of changing the luminance of the second light emission means;
with
The registration means
When the image information is registered in the drawing output destination buffer, it is possible not to register the new image information,
When the image information registered in the frame buffer switched from the drawing output destination buffer is pause image information for pausing an image (for example, if the determination in step S1447 is YES), the pause image information can be registered in the drawing output destination buffer switched from the frame buffer,
The second light emission control means is
When the luminance of the first light emitting means is changed based on the operation of the operating means, the luminance of the second light emitting means can be changed at a timing different from the timing at which the luminance of the first light emitting means is changed.

According to the present invention, it is possible to provide a gaming machine capable of efficiently performing control related to effect images.

It is a diagram showing a functional flow of the pachinko gaming machine according to one embodiment of the present invention. 1 is an external perspective view of a pachinko game machine according to an embodiment of the present invention; FIG. 1 is an exploded perspective view of a pachinko game machine according to an embodiment of the present invention; FIG. It is a front view showing the configuration of the game board of the pachinko game machine according to one embodiment of the present invention. 1 is a block diagram showing a circuit configuration of a pachinko game machine according to one embodiment of the present invention; FIG. It is a block diagram showing the internal configuration of the sub-control circuit of the pachinko game machine according to one embodiment of the present invention. It is a block diagram showing the internal configuration of the sound / LED control circuit of the pachinko game machine according to one embodiment of the present invention. It is a figure for demonstrating an example of the output signal of the audio|voice / LED control circuit in the pachinko game machine which concerns on one Embodiment of this invention. It is a control block diagram for explaining an example of volume control by the host control circuit in the pachinko game machine according to one embodiment of the present invention. It is a schematic connection configuration diagram between the built-in relay board and the speaker of the pachinko game machine according to one embodiment of the present invention. It is a block diagram showing the internal configuration of the display control circuit of the pachinko game machine according to one embodiment of the present invention. 1 is a schematic connection configuration diagram between a sub-board and a CGROM board (NOR type) of a pachinko game machine according to one embodiment of the present invention; FIG. 1 is a schematic connection configuration diagram between a sub-board and a CGROM board (NAND type) of a pachinko game machine according to one embodiment of the present invention; FIG. It is a truth table for demonstrating operation|movement of the AND circuit provided in the sub-board of the pachinko game machine which concerns on one Embodiment of this invention. 4 is a truth table for explaining the operation of the two-way balance transceiver provided on the sub-board of the pachinko game machine according to one embodiment of the present invention. It is a diagram showing an example of a jackpot random number determination table (at the time of winning the first start opening) in the pachinko gaming machine according to one embodiment of the present invention. It is a diagram showing an example of a jackpot random number determination table (at the time of winning the second start opening) in the pachinko gaming machine according to one embodiment of the present invention. It is a figure which shows an example of the design determination table (at the time of 1st starting entrance winning a prize) in the pachinko game machine which concerns on one Embodiment of this invention. It is a diagram showing an example of a symbol determination table (at the time of winning the second start opening) in the pachinko gaming machine according to one embodiment of the present invention. It is a figure which shows an example of the jackpot kind determination table (part 1) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of a jackpot kind determination table (part 2) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the jackpot kind determination table (the 3) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of a jackpot kind determination table (part 4) in the pachinko game machine which concerns on one Embodiment of this invention. It is a diagram showing an example of a prize-winning effect information determination table in the pachinko gaming machine according to one embodiment of the present invention. It is a diagram showing an example of a variation effect pattern determination table in the pachinko gaming machine according to one embodiment of the present invention. It is a diagram showing an example of a variable effect table in the pachinko gaming machine according to one embodiment of the present invention. It is a figure for demonstrating the outline|summary of the drawing process in the pachinko game machine which concerns on one Embodiment of this invention. In the pachinko gaming machine according to one embodiment of the present invention, it is a flowchart showing an example of main control main processing executed by the main CPU. It is a flow chart showing an example of special symbol control processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart showing an example of special symbol memory check processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart showing an example of a special symbol display time management process in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart showing an example of jackpot end interval processing in the pachinko gaming machine according to one embodiment of the present invention. In the pachinko gaming machine according to one embodiment of the present invention, it is a flow chart showing an example of system timer interrupt processing executed by the main CPU. It is a flow chart showing an example of switch input detection processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart showing an example of the start opening winning detection processing in the pachinko gaming machine according to one embodiment of the present invention. In the pachinko gaming machine according to one embodiment of the present invention, it is a flow chart showing an example of a sub-control main process executed by the host control circuit (sub-control circuit). It is a flowchart showing an example of timer interrupt processing executed by the host control circuit (sub-control circuit) in the pachinko gaming machine according to one embodiment of the present invention. In the pachinko game machine according to one embodiment of the present invention, it is a diagram showing an example for explaining sub-device input determination information to be created. It is a flow chart showing an example of sub-device input processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart showing an example of sub-device input ON edge information (with repeat function) processing in the pachinko gaming machine according to one embodiment of the present invention. 40 and continuing from FIG. 40, showing an example of sub-device input ON edge information (with repeat function) processing in the pachinko gaming machine according to the embodiment of the present invention. It is a diagram for conceptually explaining the backlight control process in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart showing an example of backlight control processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart showing an example of timer interrupt processing accompanying a modification of the backlight control processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flowchart showing a modification of the backlight control process in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart showing an example of timer interrupt processing showing the backlight control processing in the pachinko gaming machine according to one embodiment of the present invention. In the pachinko game machine according to one embodiment of the present invention, it is a sub-control main processing (overall flow) executed by the host control circuit for explaining the first example of the brightness adjustment processing of the backlight and various LEDs. In the pachinko gaming machine according to one embodiment of the present invention, sub-control main processing (overall flow) executed by the host control circuit for explaining a second example of the brightness adjustment processing of the backlight and various LEDs. In the pachinko game machine according to one embodiment of the present invention, sub-control main processing (overall flow) executed by the host control circuit for explaining the third embodiment of the brightness adjustment processing of the backlight and various LEDs. It is a flow chart showing an example of RTC acquisition processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart which shows an example of animation control main processing in the pachinko game machine concerning one embodiment of the present invention. It is a flow chart showing an example of composition reproduction control processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart showing an example of sound amplifier check processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart showing an example of normal amplifier check processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flow chart which shows an example of amplifier check processing for deep bass in the pachinko game machine according to one embodiment of the present invention. In the pachinko game machine according to one embodiment of the present invention, it is a flowchart showing an example of a sound amplifier check process of performing a normal amplifier / deep bass amplifier (batch) check process. It is a flow chart showing an example of a more preferable form of sound amplifier check processing in the pachinko gaming machine according to one embodiment of the present invention. It is a flowchart which shows an example of the more preferable form of the amplifier check process for normal amplifiers and deep bass in the pachinko game machine which concerns on one Embodiment of this invention. FIG. 59 is a flowchart continued from FIG. 58, showing an example of a more preferable form of normal amplifier/heavy bass amplifier check processing in the pachinko game machine according to one embodiment of the present invention. In the pachinko gaming machine according to one embodiment of the present invention, it is a flowchart showing an example of sound request control processing when there are a plurality of sound requests for the same channel. In the pachinko gaming machine according to one embodiment of the present invention, it is a flowchart showing a first example of sound request control processing when volume adjustment is performed. In the pachinko gaming machine according to one embodiment of the present invention, it is a flow chart showing a second example of sound request control processing when volume adjustment is performed. In the pachinko gaming machine according to one embodiment of the present invention, it is a flow chart showing a third example of sound request control processing when volume adjustment is performed. In the pachinko gaming machine according to one embodiment of the present invention, it is a flowchart showing a fourth example of sound request control processing when volume adjustment is performed. In the pachinko gaming machine according to one embodiment of the present invention, it is a flowchart showing a fifth example of sound request control processing when volume adjustment is performed. In the pachinko game machine according to one embodiment of the present invention, it is an attenuation table showing an example of the luminance attenuation value of each color (red, green, blue) according to the light emission intensity of the strong, medium, and weak LEDs. 1 is a block diagram showing an example of a connection state between an LED port, an LED and a solenoid in a pachinko gaming machine according to an embodiment of the present invention; FIG. In the pachinko gaming machine according to one embodiment of the present invention, it is a flow chart showing an example of data load processing executed as one of various initialization processing by the host control circuit. In the pachinko game machine according to one embodiment of the present invention, it is a flowchart showing an example of random number initialization processing that is executed as one of various initialization processing by the host control circuit. It is a flow chart showing an example of random number periodical update processing in the pachinko gaming machine according to one embodiment of the present invention. 1 is a flowchart showing an example of a random number 1 acquisition process, (b) an example of a random number 2 acquisition process, (c) an example of a random number 3 acquisition process, and (d) a flowchart showing an example of a random number 4 acquisition process in a pachinko gaming machine according to an embodiment of the present invention. In the pachinko gaming machine according to one embodiment of the present invention, it is a flowchart showing an example of random number acquisition processing that is executed when a random number is used. In the pachinko game machine according to one embodiment of the present invention, sub-control main processing (overall flow) executed by the host control circuit for explaining a modification of the sub-random number processing. 4 is a flowchart showing an example of reception interrupt processing executed by a host control circuit in the pachinko gaming machine according to one embodiment of the present invention.

Hereinafter, the configuration and various operations of a pachinko game machine (game machine) according to one embodiment of the present invention will be described with reference to the drawings.

<Function flow>
First, with reference to FIG. 1, the functions of the pachinko gaming machine according to this embodiment will be described. FIG. 1 is a diagram showing the functional flow of the pachinko gaming machine according to this embodiment.

As shown in FIG. 1, the pachinko game is a game in which a game ball is shot by a user's operation, and game ball payout control processing is performed when the game ball wins various prizes. The pachinko game includes a special symbol game using special symbols and a normal symbol game using normal symbols. When a ``big hit'' is achieved in a special pattern game or when a ``hit'' is achieved in a normal pattern game, the possibility of the game balls winning a prize is relatively increased and the payout control processing of the game balls is facilitated.

In addition, various prizes include a special pattern start prize which is one condition for performing variable display of special patterns in a special pattern game, and a normal pattern start prize which is one condition for performing variable display of normal patterns in a normal pattern game.

The term “variable display” as used in this specification is a concept of variably displayed, and for example, it enables “variable display” in which the display is actually changed, “stop display” in which the display is actually stopped, and the like. Further, in the "variable display", for example, it is possible to perform a "derivation display" in which a special symbol (identification information) is displayed as a result of the special symbol game. That is, in this specification, the operation from the start of the "variable display" to the "derived display" is referred to as one "variable display". Furthermore, in this specification, "identification information" means "symbols" used in pachinko games such as special patterns, normal patterns, decorative patterns, and identification patterns, and patterns used in displaying or suggesting the results of games when players play games, such as identification patterns and decorative patterns used in pachislot or slot games, and may also include various patterns in the embodiments and various modifications described below.

The outline of the processing flow of the special symbol game and the normal symbol game will be described below.

(1) Special symbol game When there is a special symbol start winning in the special symbol game, random numbers (big hit determination random number and symbol determination random number) are extracted from the big hit determination counter and symbol determination counter, respectively, and each extracted random number is stored (refer to the flow of special symbol start winning processing during the special symbol game shown in FIG. 1).

Further, as shown in FIG. 1, in the special symbol control process during the special symbol game, first, it is determined whether or not the condition for starting the variable display of the special symbol is established. In this determination processing, it is determined that the condition for starting the variable display of the special pattern is satisfied by referring to whether or not the random number is stored by the special symbol starting prize, and with the fact that the random number is stored as one condition.

Next, when the variable display of the special symbols is started, the big-hit judgment random number extracted from the big-hit judgment counter is referred to, and the big-hit judgment is made as to whether or not to make it a "big-hit". After that, stop symbol determination processing is performed. In this process, the random number for symbol determination extracted from the counter for symbol determination and the result of the above-described big hit determination are referred to, and the special symbols to be stopped and displayed are determined.

Then, a variation pattern determination process is performed. In this process, a random number is extracted from a variation pattern determination counter, and the random number, the result of the above-mentioned big hit determination, and the above-mentioned special symbols to be stopped and displayed are referred to determine the variation pattern of the special symbols.

Next, effect pattern determination processing is performed. In this processing, a random number is extracted from a performance pattern determining counter, the random number, the result of the above-mentioned big hit determination, the above-mentioned special symbols to be stopped and displayed, and the above-mentioned variation pattern of the special symbols are referred to, and the performance pattern to be executed with the variable display of the special symbols is determined.

Next, the special symbols to be stopped and displayed, the variation pattern of the special symbols, and the performance pattern associated with the variable display of the special symbols are referred to as a result of the determined big hit determination, and the variable display control processing for controlling the variable display of the special symbols and the performance control processing for performing the predetermined performance are executed.

Then, when the variable display control process and the performance display control process are completed, it is determined whether or not a "jackpot" will be achieved. In this determination process, when it is determined that the "jackpot" has occurred, a jackpot game control process for performing a jackpot game is executed. Incidentally, in the jackpot game, the possibility of winning various prizes described above increases. On the other hand, when it is determined that the "jackpot" was not achieved, the jackpot game control process is not executed.

When it is determined that the "jackpot" is not achieved, or when the jackpot game control process is completed, a game state shift control process for shifting the game state is performed. In this game state transition control process, management of the normal game state different from the jackpot game state is performed. The normal game state includes, for example, a game state in which the probability of being determined as a "jackpot" increases in the above-described jackpot determination (hereinafter referred to as "probability variable game state"), and a game state in which special symbol start winning is easily obtained (hereinafter referred to as "time-saving game state"). After that, the determination processing of whether or not to start the variable display of the special symbols is performed again, and after that, various kinds of processing of the special symbol control processing described above are repeated.

In the pachinko gaming machine of the present embodiment, when a game ball starts winning during variable display of special symbols, various data (random number for judging a big hit, random number for determining a symbol, etc.) acquired at the time of starting winning is reserved. That is, when the game ball starts winning during the variable display of the special symbols, the variable display (variable display) of the special symbols corresponding to the starting winning is suspended, and the variable display of the suspended special symbols is started after the variable display of the currently executed special symbols ends. Below, the variable display of the reserved special symbol is also referred to as "reserved ball".

In addition, in the pachinko gaming machine of the present embodiment, as will be described later, two types of special symbol start prizes (first start prize and second start prize) are provided, and a maximum of four reserved balls can be acquired for each special symbol start prize. That is, in this embodiment, a maximum of 8 held balls can be obtained.

Furthermore, although not shown in FIG. 1, the pachinko game machine of the present embodiment has a function of judging whether or not a held ball wins or loses (whether or not a "jackpot" is won) based on the information of the above-mentioned held ball, and furthermore, has a function of executing a predetermined production based on the judgment result, that is, a look-ahead performance function.

(2) Normal symbol game When there is a normal symbol start winning in the normal symbol game, a random number is extracted from the hit determination counter and stored (refer to the flow of normal symbol start winning processing in the normal symbol game shown in FIG. 1).

Further, as shown in FIG. 1, in the normal symbol control process during the normal symbol game, first, it is determined whether or not the conditions for starting the variable display of the normal symbols are established. In this determination processing, it is determined that a condition for starting variable display of normal symbols is established by referring to whether or not the random number is stored by the normal symbol start winning, and with the storage of the random number as one condition.

Next, when the variable display of normal symbols is started, the random number value extracted from the hit determination counter is referred to, and a hit determination is made as to whether or not it is a "hit". After that, a variation pattern determination process is performed. In this process, the result of hit determination is referred to, and the variation pattern of normal symbols is determined.

Then, with reference to the determined result of hit determination and the variation pattern of normal symbols, a variable display control process for controlling variable display of normal symbols and an effect control process for performing a predetermined effect are executed.

When the variable display control process and effect display control process are completed, it is determined whether or not a "win" is achieved. In this determination process, when it is determined that it becomes a "hit", a winning game control process for performing a winning game is executed. In the winning game control process, the possibility of various prizes mentioned above, especially the possibility of the special symbol starting prize of the game ball in the special symbol game increases. On the other hand, when it is determined that it does not become a "hit", the winning game control process is not executed. After that, the process of determining whether or not to start the variable display of normal symbols is performed again, and thereafter, the various processes of the normal symbol control process described above are repeated.

As described above, in the pachinko game, the easiness of the game ball payout control process to be performed changes depending on conditions such as whether or not the special symbol game results in a "big hit", the transition state of the game state, and whether or not the normal symbol game results in a "win".

In this embodiment, as a method for extracting various random numbers, a soft random number method for generating random numbers by executing a program is used. However, the present invention is not limited to this. For example, if the pachinko game machine includes a random number generator that updates random numbers at a predetermined cycle, a hard random number method for extracting random numbers from a counter (so-called ring counter) in the random number generator may be employed as the extraction method for various random numbers described above. When the hard random number method is used, it is possible to prevent the same random number from being extracted in the predetermined period by determining the initial value of the random number at a timing different from the predetermined period.

<Pachinko machine structure>
Next, with reference to FIGS. 2 and 3, the structure of the pachinko game machine according to this embodiment will be described. Note that FIG. 2 is a perspective view showing the appearance of the pachinko game machine. Also, FIG. 3 is an exploded perspective view of the pachinko game machine.

As shown in FIGS. 2 and 3, the pachinko game machine 1 includes a main body 2, a base door 3 attached to the main body 2 so as to be openable and closable, and a glass door 4 attached to the base door 3 so as to be openable and closable.

[Body]
The main body 2 is composed of a frame member having a rectangular opening 2a (see FIG. 3). The main body 2 is made of a material such as wood, for example.

[Base door]
The base door 3 is composed of a plate member having a rectangular outer shape substantially equal to the outer shape of the main body 2 . The base door 3 is arranged in front of the main body 2 (on the front side of the pachinko game machine 1), and the opening 2a of the main body 2 is opened and closed by rotating the base door 3 about one side edge of the main body 2. - 特許庁The base door 3 is provided with a rectangular opening 3a as shown in FIG. The opening 3a is formed over the upper area from the substantially central portion of the base door 3, and is formed in a size that occupies most of the area.

A speaker 11 , a game board 12 , a display device 13 , a plate unit 14 , a launching device 15 , a payout device 16 and a board unit 17 are attached to the base door 3 .

The speaker 11 is arranged above the base door 3 (near the upper end). The game board 12 is arranged in front of the base door 3 (on the front side of the pachinko game machine 1) so as to cover the opening 3a of the base door 3.

The game board 12 is made of a plate-shaped resin member having optical transparency. As the light-transmitting resin, for example, acrylic resin, polycarbonate resin, methacrylic resin, or the like can be used.

In addition, on the front surface of the game board 12 (surface on the front side of the pachinko game machine 1), a game area 12a is formed in which game balls shot from the shooting device 15 roll. The game area 12a is an area surrounded by guide rails 41 (specifically, outer rails 41a shown in FIG. 4, which will be described later), and has a substantially circular outer peripheral shape. Furthermore, a plurality of game nails (see FIG. 4, which will be described later) are driven into the game area 12a. The configuration of the game board 12 (game area 12a) will be described later in detail with reference to FIG.

The display device 13 is attached to the back side of the game board 12 (the side opposite to the front side of the pachinko game machine 1). This display device 13 has a display area 13a for displaying an image. The size of the display area 13 a is set so as to occupy all or part of the surface of the game board 12 . In the display area 13a of the display device 13, various images such as an identification design for performance, a performance image, and an image for decoration (decorative design) are displayed based on the result of lottery processing for special symbols, which will be described later. A player can view various images displayed in the display area 13 a of the display device 13 through the game board 12 .

In addition, in this embodiment, a liquid crystal display device is used as the display device 13 . However, the present invention is not limited to this, and display devices such as a plasma display, a rear projection display, and a CRT (Cathode Ray Tube) display may be applied as the display device 13, for example.

A spacer 19 is provided on the back side of the game board 12 (the side opposite to the front side of the pachinko game machine 1). The spacer 19 is provided between the back surface of the game board 12 (the surface on the back side of the pachinko game machine 1) and the front surface of the display device 13 (the surface on the front side of the pachinko game machine 1), and forms a space serving as a flow path for game balls rolling in the game area 12a of the game board 12.例文帳に追加The spacer 19 is made of a material having optical transparency. Note that the present invention is not limited to this, and the spacer 19 may be partially formed of a material having optical transparency, or may be formed of a material that does not have optical transparency.

The plate unit 14 is arranged below the game board 12 . The plate unit 14 has an upper plate 21 and a lower plate 22 arranged therebelow. As shown in FIG. 2, the upper tray 21 and the lower tray 22 are formed with a payout opening 21a and a payout opening 22a for renting game balls and paying out game balls (prize balls), respectively. When a predetermined payout condition is established, game balls are discharged from the payout port 21a and the payout port 22a and stored in the upper tray 21 and the lower tray 22, respectively. Also, the game balls stored in the upper tray 21 are shot by the shooting device 15 to the game area 12a.

Also, the plate unit 14 is provided with a performance button 23. - 特許庁This performance button 23 is attached on the upper plate 21.例文帳に追加A dial operation unit (jog dial) 24 is rotatably attached to the performance button 23 on the periphery of the performance button 23 . The pachinko game machine 1 of the present embodiment has a predetermined performance function performed by using the performance button 23 and/or the dial operation unit 24, and when performing the predetermined performance, an image prompting the operation of the performance button 23 and/or the dial operation unit 24 is displayed in the display area 13a of the display device 13.

The launcher 15 is arranged in the lower right area (near the lower right corner) on the front surface of the base door 3 . The shooting device 15 has a shooting handle 25 that can be operated by the player, and a panel body 26 that engages with the lower right portion of the dish unit 14 . The firing handle 25 is arranged on the front side of the panel body 26 and is rotatably supported by the panel body 26 .

Although not shown in FIGS. 2 and 3, a solenoid actuator (driving device) is provided on the back side of the panel body 26 for controlling the shooting operation of the game ball. Also, although not shown in FIGS. 2 and 3 , a touch sensor is provided on the periphery of the firing handle 25 and a firing volume is provided inside the firing handle 25 . The firing volume changes the resistance value according to the amount of rotation of the firing handle 25, and changes the electric power supplied to the solenoid actuator.

In the pachinko gaming machine 1 of this embodiment, when the player's hand touches the touch sensor of the shooting handle 25, the touch sensor outputs a detection signal. As a result, it is detected that the player has gripped the shooting handle 25, and the game ball can be shot by the solenoid actuator. When the player grips the shooting handle 25 and rotates it clockwise (right when viewed from the player's side), the resistance value of the shooting volume changes according to the rotation angle of the shooting handle 25, and electric power corresponding to the resistance value is supplied to the solenoid actuator. As a result, the game balls stored in the upper tray 21 are sequentially shot, and the shot game balls are guided by the guide rails 41 (see FIG. 4 described later) and released to the game area 12a of the game board 12.

Also, although not shown in FIGS. 2 and 3, a firing stop button is provided on the side of the firing handle 25 . The shooting stop button is a button provided to stop the shooting of the game ball by the solenoid actuator. When the player presses the firing stop button, the shooting of the game ball is stopped even when the shooting handle 25 is gripped and rotated.

The dispensing device 16 and the board unit 17 are arranged on the back side of the base door 3 . Game balls are supplied to the payout device 16 from a storage unit (not shown). A payout device 16 pays out a predetermined number of game balls to an upper tray 21 or a lower tray 22 based on establishment of a payout condition out of the game balls supplied from the storage unit. The board unit 17 has various control boards. Various control boards are provided with a main control circuit 70 and a sub-control circuit 200, which will be described later (see FIG. 5, which will be described later).

[Glass door]
The glass door 4 is composed of a plate member having a substantially square surface. Also, the glass door 4 is arranged on the front side of the game board 12 and has a size to cover the game board 12 . A speaker cover 29 is provided in an upper region facing the speaker 11 on the front surface of the glass door 4 .

In addition, in the central portion of the glass door 4, an opening 4a having a size that exposes at least the game area 12a is formed in the area facing the game area 12a of the game board 12. As shown in FIG. The opening 4a of the glass door 4 is fitted with a protective glass 28 having optical transparency, thereby closing the opening 4a. Therefore, when the glass door 4 is closed with respect to the base door 3 , the protective glass 28 is arranged to face at least the game area 12 a of the game board 12 .

[game board]
Next, the configuration of the game board 12 will be described with reference to FIG. FIG. 4 is a front view showing the configuration of the game board 12. As shown in FIG.

As shown in FIG. 4, the front surface of the game board 12 is provided with a guide rail 41, a ball passing detector 43, a first starting port 44, a second starting port 45 (starting area), and an ordinary electric accessory 46. In addition, on the front surface of the game board 12, general winning ports 51 and 52, a first big winning port 53 (variable winning device), a second big winning port 54 (variable winning device), an out port 55 and a plurality of game nails 56 are provided. Further, on the front surface of the game board 12, a special symbol display device 61, a normal symbol display device 62, a normal symbol reservation display device 63, a first special symbol reservation display device 64, and a second special symbol reservation display device 65 are provided above the display area 13a of the display device 13 arranged substantially in the center.

Although not shown in FIG. 4, a 7-segment counter for presentation is also provided on the front surface of the game board 12 . The 7-segment counter for presentation is composed of a display counter capable of displaying a two-digit number or two alphabetic characters. In addition, in this embodiment, a notification LED (Light Emitting Diode) that lights up when the result of the stop display of the special symbol is "big hit", a round number display LED that displays the number of rounds during the big win game, etc. may be provided.

[Various components of the game area]
The guide rail 41 is composed of an outer rail 41a extending in an arc that defines the game area 12a, and an inner rail 41b extending in an arc that is disposed inside (inner peripheral side) of the outer rail 41a. The game area 12a is formed inside the outer rail 41a. The outer rail 41a and the inner rail 41b are arranged to face each other in the vicinity of the left end of the game area 12a when viewed from the player side, thereby forming a guide path 41c between the outer rail 41a and the inner rail 41b for guiding the game ball shot by the shooting device 15 to the upper part of the game area 12a.

At the tip of the inner rail 41b located on the upper left side of the game area 12a, a ball outlet 41d is formed by the tip of the inner rail 41b and a part of the outer rail 41a facing it. A ball return prevention piece 42 is provided at the tip of the inner rail 41b so as to block the ball discharge port 41d. This ball return prevention piece 42 prevents the game ball discharged from the ball discharge port 41d into the game area 12a from passing through the ball discharge port 41d again and entering the guide path 41c.

The game ball discharged from the ball discharge port 41d flows down from the upper part of the game area 12a toward the lower part. At this time, the game ball collides with various members provided in the game area 12a such as a plurality of game nails 56, the first start port 44, the second start port 45, etc., and flows down from the upper part of the game area 12a toward the lower part while changing the traveling direction.

A display area 13a of the display device 13 is provided substantially in the center of the game area 12a. An obstacle 13b is provided at the upper end of the display area 13a. By providing the obstacle 13b, the game ball does not pass over the area overlapping the display area 13a in the game area 12a.

The ball passing detector 43 is arranged near the right end of the display area 13a as viewed from the player side. The ball passing detector 43 is provided with a passing ball sensor 43a (see later-described FIG. 5) for detecting a game ball passing through the ball passing detector 43. As shown in FIG. Also, when the game ball passes through the ball passage detector 43, a lottery as to whether or not it is a "hit" is performed, and based on the result of the lottery, the variable display of normal symbols is started.

The first starting port 44 is arranged below the display area 13 a , and the second starting port 45 is arranged below the first starting port 44 . The first starting port 44 and the second starting port 45 are composed of members capable of receiving game balls. Hereinafter, the game ball entering or passing through the first starting port 44 or the second starting port 45 is referred to as "winning". When the game ball wins the first starting hole 44 or the second starting hole 45, a first predetermined number (three in this embodiment) of game balls are paid out. Also, when the game ball enters the first starting port 44, a lottery is conducted as to whether it is a ``big win'' or a ``minor win'', and the variable display of the special pattern is started based on the result of the lottery. Furthermore, when a game ball enters the second starting port 45, a lottery is conducted as to whether it is a "big hit" or not, and the variable display of special symbols is started based on the result of the lottery.

The first starting hole 44 is provided with a first starting hole winning ball sensor 44a (see FIG. 5 described later) for detecting a game ball that has won the first starting hole 44 . In addition, the second starting hole 45 is provided with a second starting hole winning ball sensor 45a (see FIG. 5 described later) for detecting a game ball that has won the second starting hole 45 . The game balls that have won the first start port 44 and the second start port 45 pass through a recovery port (not shown) provided in the game board 12 and are transported to a game ball recovery section (not shown).

The ordinary electric accessory 46 is provided at the second starting port 45 . The normal electric accessory 46 has a pair of wing members rotatably attached to both sides of the second starting port 45, and a normal electric accessory solenoid 46a (see FIG. 5 described later) for driving the pair of wing members. This ordinary electric accessory 46 is driven by an ordinary electric accessory solenoid 46a to generate one of an open state in which a pair of wing members are spread to make it easier for a game ball to enter a second starting port 45, and a closed state in which a pair of wing members are closed to make it impossible for a game ball to enter the second starting port 45.例文帳に追加In the present embodiment, when the normal electric accessory 46 is in the closed state, the opening form of the pair of blade members may be changed to make it difficult for the game ball to win, instead of making it impossible to win.

The general winning opening 51 is arranged near the lower left portion of the game area 12a as viewed from the player side. In addition, the general prize winning opening 52 is arranged below the ball passage detector 43 and near the lower right portion of the game area 12a when viewed from the player side. The general prize winning port 51 and the general prize winning port 52 are composed of members capable of receiving game balls. In the following, the entry or passage of the game ball into or through the general winning opening 51 or the general winning opening 52 is also referred to as "winning". When game balls enter the general winning hole 51 or the general winning hole 52, a second predetermined number (10 in this embodiment) of game balls are paid out.

The general winning hole 51 is provided with a general winning ball sensor 51a (see FIG. 5 to be described later) for detecting a game ball that has won the general winning hole 51 . Further, the general winning hole 52 is provided with a general winning ball sensor 52a (see FIG. 5 described later) for detecting a game ball that has won the general winning hole 52 .

The first big winning hole 53 and the second big winning hole 54 are arranged below the ball passing detector 43 and between the first starting hole 44 and the general winning hole 52 . The first big winning hole 53 and the second big winning hole 54 are arranged vertically along the flow path of the game balls, and the first big winning hole 53 is arranged above the second big winning hole 54 . Both the first big winning opening 53 and the second big winning opening 54 are so-called attacker-type opening/closing devices, and have shutters 53a and 54a that can be opened and closed, and solenoid actuators that drive the shutters (the first big winning opening solenoid 53b and the second big winning opening solenoid 54b in FIG. 5 to be described later).

Each of the first big winning hole 53 and the second big winning hole 54 accepts the game ball when the corresponding shutter is open (open state), and does not accept the game ball when the shutter is closed (closed state). In the following, the entry or passage of the game ball into or through the first big winning hole 53 or the second big winning hole 54 is also referred to as "winning". When a game ball wins in the first big winning hole 53, a third predetermined number of game balls (10 in this embodiment) are paid out. On the other hand, when a game ball wins in the second big winning hole 54, a fourth predetermined number of game balls (15 in this embodiment) are paid out.

Further, the first big winning hole 53 is provided with a count sensor 53c (see FIG. 5 described later) for counting the game balls that have won the first big winning hole 53 . Further, the second big winning hole 54 is provided with a count sensor 54c (see FIG. 5 described later) for counting the game balls that have won the second big winning hole 54 .

The out port 55 is provided at the bottom of the game area 12a. The out port 55 accepts a game ball that has not won any of the first starting port 44, the second starting port 45, the general winning port 51, the general winning port 52, the first big winning port 53 and the second big winning port 54.例文帳に追加

When the arrangement of the various components in the game area 12a of the present embodiment is arranged as shown in FIG. 4, when the game ball is hit in the right area of the game area 12a by the player (when hit to the right), the game ball is guided to the second starting port 45 by the game nail 56 or the like. In this case, the possibility of winning the first starting port 44 is almost eliminated. In the present embodiment, as will be described later, winning the second starting hole 45 makes it easier for the player to receive a "big win" lottery that is advantageous to the player than winning the first starting hole 44.例文帳に追加Therefore, in the later-described "time-saving game state" in which winning to the second starting port 45 is relatively easy, the possibility of winning to the first starting port 44 (the possibility of becoming a disadvantageous game state for the player) can be reduced by hitting to the right.

[Special pattern display device]
As shown in FIG. 4, the special symbol display device 61 is arranged substantially in the center of the upper portion of the display area 13a of the display device 13. As shown in FIG.

The special symbol display device 61 is a display device that variably displays (fluctuation display and stop display) special symbols in the special symbol game. In the present embodiment, as shown in FIG. 4, a special symbol display device 61 is configured by a device that displays special symbols with symbols such as numbers and symbols. In addition, the present invention is not limited to this, and the special symbol display device 61 may be composed of, for example, a plurality of LEDs. In this case, a display pattern configured by turning on/off a plurality of LEDs is represented as a special symbol.

The special symbol display device 61 performs variable display of special symbols (identification information) when the game ball has entered the first start port 44 or the second start port 45 (special symbol start win). Then, the special symbol display device 61 performs the stop display of the special symbols after performing the variable display of the special symbols for a predetermined time. Below, when the game ball wins the first starting hole 44, the special symbol that is variably displayed on the special symbol display device 61 is referred to as a first special symbol. In addition, when the game ball wins the second starting hole 45, the special symbol that is variably displayed on the special symbol display device 61 is referred to as a second special symbol.

In the special pattern display device 61, when the stop-displayed first special pattern or the second special pattern is in a specific mode ("big hit" mode), the game state shifts from the normal game state to the big win game state which is advantageous to the player. That is, in the special symbol display device 61, the stop display of the first special symbol or the second special symbol in a state of shifting to the big win game state is the "big hit".

In the jackpot game state, the first big winning hole 53 or the second big winning hole 54 is opened. Specifically, in the present embodiment, when the game ball wins the first starting port 44 and the first special symbol is stopped and displayed in a specific manner in the special symbol display device 61, the first big winning port 53 is opened. On the other hand, when the game ball wins the second starting port 45 and the second special symbol is stopped and displayed in a specific manner on the special symbol display device 61, the second big winning port 54 is opened.

The open state of each big winning opening is maintained until a predetermined number of game balls are won or until a certain period of time (for example, 30 seconds) elapses. Then, when the elapsed period of the open state of each big winning hole satisfies any one of these conditions, the big winning hole that was in the open state will be closed.

Hereinafter, a game in which the first big winning hole 53 or the second big winning hole 54 is in a state (open state) in which game balls are easily received is referred to as a round game. During the round game, the big winning opening is closed. A round game is counted as the number of rounds such as 1 round, 2 rounds, or the like. For example, the first round game is called the first round, and the second round game is called the second round.

In the special symbol display device 61, when the stopped special symbol is in a mode other than the specific mode ("losing" mode), the game state does not shift except when the falling lottery is won. That is, the special symbol game is a game in which special symbols are variably displayed by the special symbol display device 61, then the special symbols are stopped and displayed, and the game state is shifted or maintained depending on the result.

In addition, in the pachinko game machine 1 of the present embodiment, when a game ball wins the first starting port 44 during variable display of the first special symbol or the second special symbol, the variable display (holding ball) of the first special symbol corresponding to the winning is reserved. Then, when the first special symbol or the second special symbol that is currently being variably displayed is stopped and displayed, the variably displayed first special symbol that has been suspended is started. In the present embodiment, the number of variable displays of the first special symbol to be reserved (so-called "reserved number (number of reserved balls)") is defined to be four times (pieces) at maximum.

Furthermore, in the present embodiment, when the game ball wins the second starting port 45 during the variable display of the first special symbol or the second special symbol, the variable display of the second special symbol (reserved ball) corresponding to the winning is suspended. Then, when the first special symbol or the second special symbol that is currently being variably displayed is stopped and displayed, the variably displayed second special symbol that has been suspended is started. In this embodiment, the number of variable displays of the second special symbol to be reserved (the number of reserved symbols) is defined to be four times (pieces) at maximum. Therefore, in this embodiment, the maximum number of reserved variable display of special symbols is eight in total.

In addition, in this embodiment, when the reserved ball of the first special symbol and the reserved ball of the second special symbol are mixed, the variable display of one special symbol is preferentially executed over the variable display of the other special symbol. In addition, the present invention is not limited to this, and when the first special symbol reserved ball and the second special symbol reserved ball are mixed, the variable display of the special symbols may be executed in the reserved order.

[Normal pattern display device]
The normal symbol display device 62 is arranged substantially in the center of the upper portion of the display area 13a of the display device 13, as shown in FIG. In this embodiment, the normal symbol display device 62 is arranged on the right side of the special symbol display device 61 when viewed from the player side.

The normal symbol display device 62 is a display device that variably displays normal symbols (fluctuation display and stop display) in the normal symbol game. In this embodiment, as shown in FIG. 4, the normal symbol display device 62 is composed of two vertically arranged LEDs (normal symbol display LEDs). Then, in the normal symbol display device 62, a display pattern formed by turning on/off each normal symbol display LED is represented as a normal symbol.

The normal symbol display device 62 alternately lights and extinguishes two normal symbol display LEDs when the game ball passes through the ball passage detector 43, and performs variable display of normal symbols. Then, the normal symbol display device 62 performs the normal symbol stop display after performing the variable display of the normal symbols for a predetermined time.

In the normal symbol display device 62, when the stopped and displayed normal symbols are in a predetermined mode ("win" mode), the normal electric accessory 46 changes from the closed state to the open state for a predetermined period. On the other hand, when the stopped and displayed normal symbol is in a mode other than the predetermined mode (a mode of "loss"), the normal electric accessory 46 maintains the closed state. That is, the normal design game is a game in which the normal design is variably displayed by the normal design display device 62, then the normal design is stopped and displayed, and the normal electric accessory 46 operates according to the result.

Incidentally, when the game ball passes through the ball passage detector 43 during the variable display of the normal symbols, the variable display of the normal symbols is suspended. Then, when the normal symbols that are currently being variably displayed are stopped and displayed, the variably displayed normal symbols that have been suspended are started. In the present embodiment, the number of variable display of normal symbols to be reserved (that is, "number of reserved symbols") is defined to be four (pieces) at maximum.

[Normal symbol holding display device]
As shown in FIG. 4, the normal symbol reservation display device 63 is arranged substantially in the center of the upper portion of the display area 13a of the display device 13. As shown in FIG. And, in this embodiment, the normal design reservation display device 63 is arranged below the special design display device 61 and the normal design display device 62 .

The normal symbol reservation display device 63 is a device for displaying the number of reserved variable display of normal symbols. In the present embodiment, as shown in FIG. 4, the normal symbol reservation display device 63 is composed of four LEDs (normal symbol reservation display LEDs) arranged in the horizontal direction. Then, the normal symbol reservation display device 63 displays the number of normal symbol variable display reserved numbers by turning on/off each normal symbol reservation display LED.

Specifically, when the reserved number of variable display of the normal pattern is one, the normal pattern reserved display LED (the first normal pattern reserved display LED from the left) located on the leftmost side as viewed from the player side lights up, and the other normal pattern reserved display LEDs go out. When the number of reserved variable display of normal symbols is two, the first and second normal symbol reserved display LEDs from the left are lit, and the other normal symbol reserved display LEDs are extinguished. When the number of reserved variable display of normal symbols is 3, the first to third normal symbol reserved display LEDs from the left are lit, and the other normal symbol reserved display LEDs are extinguished. When the number of reserved variable display of normal symbols is four, all the normal symbol reserved display LEDs are lit.

[First special symbol holding display device]
As shown in FIG. 4, the first special symbol holding display device 64 is arranged on the left side of the special symbol display device 61 in the upper part of the display area 13a of the display device 13 as viewed from the player side.

The first special symbol reservation display device 64 is a device that displays information about variable display of the first special symbol that is being reserved (retained ball of the first special symbol). In this embodiment, as shown in FIG. 4, the first special symbol reservation display device 64 is composed of a first special symbol reservation number display portion 64a and a first special symbol reservation information display portion 64b. The first special symbol reserved information display portion 64b is arranged on the left side of the special symbol display device 61, and the first special symbol reserved number display portion 64a is arranged on the left side of the first special symbol reserved information display portion 64b.

The first special symbol reserved number display portion 64a has four LEDs (first special symbol reserved display LEDs) arranged in the horizontal direction. In addition, the display mode of the first special symbol reserved number display section 64 a is the same as the display mode of the normal symbol reserved display device 63 . That is, when the variable display of the first special symbol is suspended, the first special symbol suspension display LEDs from the first special symbol suspension display LED located on the leftmost side to the suspension number are lit up as viewed from the player side.

In addition, the first special symbol reserved information display section 64b displays information about the reserved ball of the first special symbol. For example, the first special symbol reserved information display unit 64b displays information (identification information) regarding the reserved ball of the first special symbol to be next displayed in a pattern composed of numbers, symbols, and the like. The configuration of the first special symbol reservation display device 64 is not limited to the example shown in FIG. 4, and can be arbitrarily configured as long as it can display at least the number of variable display of the first special symbol.

[Second special symbol holding display device]
As shown in FIG. 4, the second special symbol reservation display device 65 is arranged on the right side of the normal symbol display device 62 in the upper part of the display area 13a of the display device 13 as viewed from the player side.

The second special symbol reservation display device 65 is a device that displays information regarding variable display of the second special symbol that is being reserved (second special symbol reservation ball). In this embodiment, as shown in FIG. 4, the second special symbol reservation display device 65 is composed of a second special symbol reservation number display portion 65a and a second special symbol reservation information display portion 65b. The second special symbol reserved information display portion 65b is arranged on the right side of the normal symbol display device 62, and the second special symbol reserved number display portion 65a is arranged on the right side of the second special symbol reserved information display portion 65b.

The second special symbol reserved number display portion 65a has four LEDs (second special symbol reserved display LEDs) arranged in the horizontal direction. In addition, the display mode of the second special symbol reserved number display portion 65a is the same as the display mode of the normal symbol reserved display device 63. That is, when the variable display of the second special symbol is suspended, the second special symbol suspension display LEDs from the second special symbol suspension display LED located on the leftmost side to the second special symbol suspension display LED are lit up as viewed from the player side.

In addition, the second special symbol reserved information display section 65b displays information about the second special symbol reserved ball. For example, the second special symbol reserved information display unit 65b displays information (identification information) regarding the second special symbol reserved ball to be displayed next in a pattern consisting of numbers, symbols, and the like. In addition, the configuration of the second special symbol reservation display device 65 is not limited to the example shown in FIG. 4, and can be arbitrarily configured as long as it can display at least the number of variable display of the second special symbol.

[Display device]
The display device 13 is composed of a liquid crystal display device as described above, and performs various image display effects in its display area 13a.

Specifically, in this embodiment, an effect image related to the special symbol displayed on the special symbol display device 61 is displayed in the display area 13a. At this time, for example, when the special pattern is being variably displayed in the special pattern display device 61, except for a specific case, for example, a plurality of performance identification patterns (decoration patterns) consisting of numbers from 1 to 8 and various characters are variably displayed in the display area 13a. When the special symbol is stopped and displayed on the special symbol display device 61, a plurality of decorative symbols (jackpot symbols, etc., which will be described later) corresponding to the special symbol are also stopped and displayed in the display area 13a.

Then, when the special pattern stopped and displayed in the special pattern display device 61 is in a specific mode (the result of the stop display is ``big hit''), a performance image is displayed in the display area 13a for making the player grasp that it is ``big hit''. As a performance for making the player grasp that it is a ``big hit'', for example, first, a plurality of statically displayed decorative patterns become a specific mode (for example, a mode in which the same decorative patterns are arranged along a predetermined direction), and then, there is a presentation of displaying an image informing the ``big win''.

Further, in the present embodiment, the display area 13a of the display device 13, the effect image related to the display content of the first special symbol reservation display device 64 and the second special symbol reservation display device 65 is displayed. For example, the display area 13a displays pending information (for example, the same number of pending symbols as the pending number) for informing the pending number of variable display of special symbols. Further, for example, in the pachinko gaming machine 1 of the present embodiment, the pre-reading effect is performed based on the information of the reserved ball of the special symbol, and the advance notice at this time is also displayed in the display area 13a.

In addition, in the present embodiment, when the normal symbol stopped and displayed on the normal symbol display device 62 is in a predetermined mode, a function of displaying an effect image for letting the player grasp the information in the display area 13a of the display device 13 may be further provided.

<Configuration of circuits provided in pachinko machines>
Next, with reference to FIG. 5, the configuration of various circuits provided in the pachinko gaming machine 1 of this embodiment will be described. 5 is a block diagram showing the circuit configuration of the pachinko game machine 1. As shown in FIG.

As shown in FIG. 5, the pachinko game machine 1 has a main control circuit 70 that mainly controls game operations, a payout/fire control circuit 123, and a sub-control circuit 200 that controls performance operations in accordance with the progress of the game.

[Main control circuit]
The main control circuit 70 includes a one-chip microcomputer 77 , a clock generation circuit 74 and an initial reset circuit 75 . As described above, in the present embodiment, the special symbol lottery process is performed when the first starting port 44 or the second starting port 45 is won. That is, the main control circuit 70 also serves as means (lottery means) for performing lottery processing to determine whether or not the game state is to be shifted to a state advantageous to the player.

The one-chip microcomputer 77 is composed of a main CPU (Central Processing Unit) 71 , a main ROM (Read Only Memory) 72 , a main RAM (Random Access Memory) 73 and a serial communication section 76 . The main CPU 71, main ROM 72, main RAM 73, and serial communication section 76 may be provided separately.

Also, in this embodiment, a configuration in which the main ROM 72 is built in the substrate of the main control circuit 70 will be described, but the present invention is not limited to this. For example, a ROM board on which the main ROM 72 is mounted may be connected to the board of the main control circuit 70 . Furthermore, in the present embodiment, various circuits within the main control circuit 70 may be formed integrally or separately. Further, the main ROM 72 may not be installed in the gaming machine, and may be configured to be able to communicate with the gaming machine.

A clock generation circuit 74 and an initial reset circuit 75 are connected to the one-chip microcomputer 77 . The main ROM 72 stores various programs for controlling the operation of the pachinko gaming machine 1 by the main CPU 71 (see FIGS. 28 to 35 described later), various data tables (see FIGS. 16 to 26 described later), and the like.

The main CPU 71 executes various processes according to programs stored in the main ROM 72 . The main RAM 73 acts as a temporary storage area when the main CPU 71 executes various processes, and stores various flags and variable values necessary for the main CPU 71 to perform various processes. In this embodiment, the main RAM 73 is used as a temporary storage area for the main CPU 71, but the present invention is not limited to this, and any readable/writable storage medium can be used as a temporary storage area.

A clock generation circuit 74 generates a clock pulse at a predetermined cycle (for example, 2 msec) in order to execute system timer interrupt processing, which will be described later. The initial reset circuit 75 generates a reset signal when power is turned on. The serial communication unit 76 then supplies commands to the sub control circuit 200 .

5, connected to the main control circuit 70 are various devices that operate according to output signals sent from the main control circuit 70. FIG.

Specifically, the main control circuit 70 is connected with a special symbol display device 61, a normal symbol display device 62, a normal symbol reservation display device 63, a first special symbol reservation display device 64 and a second special symbol reservation display device 65. Each of these devices performs a predetermined operation based on the output signal sent from the main control circuit 70 . For example, when a predetermined output signal is transmitted from the main control circuit 70 to the special symbol display device 61, the special symbol display device 61 controls the variable display of special symbols in the special symbol game based on the output signal.

In addition, the main control circuit 70 is connected to the normal electric accessory solenoid 46a, the first big winning opening solenoid 53b and the second big winning opening solenoid 54b. Then, the main control circuit 70 drives and controls the normal electric accessory solenoid 46a to bring the pair of blade members of the normal electric accessory 46 into the open state or the closed state. In addition, the main control circuit 70 drives and controls the first and second large winning opening solenoids 53b and 54b, respectively, to open or close the first and second large winning openings 53 and 54, respectively.

Furthermore, as shown in FIG. 5, the main control circuit 70 is connected to various sensors to receive output signals from the various sensors. Specifically, the main control circuit 70 is connected with count sensors 53c and 54c, general winning ball sensors 51a and 52a, passing ball sensor 43a, first starting opening winning ball sensor 44a, second starting opening winning ball sensor 45a, backup clear switch 121, and the like.

The count sensor 53c counts the number of game balls that have entered the first big winning hole 53, and outputs to the main control circuit 70 a predetermined output signal indicating the result. The count sensor 54c counts the number of game balls that have entered the second big winning hole 54, and outputs to the main control circuit 70 a predetermined output signal indicating the result. A general winning ball sensor 51a outputs a predetermined detection signal to a main control circuit 70 when a game ball enters the general winning hole 51, and a general winning ball sensor 52a outputs a specified detection signal to the main control circuit 70 when a game ball enters the general winning hole 52.例文帳に追加

Further, the passing ball sensor 43a outputs a predetermined detection signal to the main control circuit 70 when the game ball passes through the ball passing detector 43. FIG. The first start hole winning ball sensor 44a outputs a predetermined detection signal to the main control circuit 70 when the game ball wins the first start hole 44. FIG. The second starting hole winning ball sensor 45a outputs a predetermined detection signal to the main control circuit 70 when the game ball wins the second starting hole 45. FIG. In addition, the backup clear switch 121 outputs a predetermined detection signal to the main control circuit 70 and the payout/emission control circuit 123 when the backup data is cleared according to the operation of the manager of the game parlor, etc. at the time of power failure or the like.

Further, a payout/launch control circuit 123 is connected to the main control circuit 70 . Details of the payout/launch control circuit 123 and various peripheral devices connected thereto will be described later.

[Payout/launch control circuit and its peripheral devices]
The payout/emission control circuit 123 is connected to the prize ball case unit 170 , the payout state notification display device 178 , the lower tray full switch 179 , the launcher 15 , the external terminal plate 140 and the card unit 150 . Also, the external terminal board 140 is connected to the data display 141, and the card unit 150 is connected to the rental operating section 151. FIG.

The payout/launch control circuit 123 inputs and outputs signals and the like to these peripheral devices based on various commands and the like transmitted from the main control circuit 70, and controls the operation of each peripheral device. For example, the payout/launch control circuit 123 receives a prize ball control command transmitted from the main control circuit 70 and a ball rental control signal (to be described later) transmitted from the card unit 150, and transmits a predetermined signal to the prize ball case unit 170. Thereby, the prize ball case unit 170 pays out game balls.

The prize ball case unit 170 is a device for dispensing game balls, and has a first 15-ball collateral switch 172a, a second 15-ball collateral switch 172b, a first counting switch 181a, a second counting switch 181b, and a payout motor 174. These components included in the prize ball case unit 170 are connected to the payout/emission control circuit 123, respectively.

Although not shown here, inside the prize ball case unit 170, two ball supply passages are provided. Then, the first 15-ball collateral switch 172a detects game balls supplied to one ball supply passage, and outputs a predetermined output signal indicating the detection result to the payout/launch control circuit 123. Also, the second 15-ball collateral switch 172b detects game balls supplied to the other ball supply passage, and outputs a predetermined output signal indicating the detection result to the payout/launch control circuit 123.

Furthermore, although not shown here, two payout passages are provided inside the prize ball case unit 170 . Then, the first counting switch 181a detects the game balls paid out to one of the payout passages, and outputs a predetermined output signal indicating the detection result to the payout/emission control circuit 123. In addition, the second counting switch 181b detects the game ball put out to the other payout passage, and outputs a predetermined output signal indicating the detection result to the payout/emission control circuit 123.

The payout motor 174 is composed of a stepping motor and driven according to a control signal input from the payout/launch control circuit 123 . The payout motor 174 rotates a sprocket (rotating member) (not shown) provided in the prize ball case unit 170 . By rotating the sprocket, the game balls accumulated in each ball supply path are moved one by one to the corresponding payout path.

The payout state notification display device 178 is a device for notifying the type of abnormality when an abnormality occurs in the payout of game balls, and is composed of a 7-segment display. The payout state notification display device 178 is attached at a position that can be visually recognized only by the manager of the gaming parlor (game hall), for example, at a predetermined location on the back surface of the pachinko gaming machine 1 .

A lower tray full switch 179 detects when the game balls stored in the lower tray 22 are full, and outputs the detection result to the payout/launch control circuit 123 .

When a signal indicating the lower tray full state is input from the lower tray full state switch 179, the payout/fire control circuit 123 notifies the lower tray full state using the payout state notification display device 178, and outputs a signal indicating the lower tray full state to the main control circuit 70. After that, when the effect control command is transmitted from the main control circuit 70 to the sub-control circuit 200, the sub-control circuit 200 notifies that the lower tray 22 is full using the speaker 11, the lamp group 18, the display device 13, etc., for example.

The shooting device 15 has a shooting handle 25 that can be rotated by the player when shooting the game balls stored in the upper tray 21 to the game area 12a. The payout/shooting control circuit 123 supplies power to a solenoid actuator (not shown) of the shooting device 15 according to the rotation angle when the shooting handle 25 is gripped by the player and rotated clockwise. Thereby, the shooting device 15 shoots a game ball. A motor may be used instead of the solenoid actuator as the driving means for the launching device 15 .

The external terminal board 140 is used to transmit data to a hall computer that manages all pachinko gaming machines in the amusement arcade. The data display device 141 is installed, for example, in the upper part of the pachinko game machine 1 as ancillary equipment of the game parlor, and has a function of calling a hall attendant and a function of displaying the number of hits.

The lending operation unit 151 outputs a signal requesting the lending of game balls to the card unit 150 when operated by the player. The card unit 150 determines the number of game balls to be paid out through the prize ball case unit 170 (the number of rental balls) based on the signal output from the rental operation unit 151 requesting the rental of game balls. When the card unit 150 receives a signal requesting the lending of game balls from the lending operation unit 151 , the card unit 150 transmits to the payout/launch control circuit 123 a ball rental control signal including information on the determined number of rental balls.

[Sub control circuit]
The sub control circuit 200 is connected to the serial communication section 76 of the main control circuit 70 . The sub-control circuit 200 (host control circuit 210 to be described later) controls the sub-control circuit 200 as a whole according to various commands (information about progress of the game) transmitted from the main control circuit 70 . Then, based on various commands sent from the main control circuit 70, the sub-control circuit 200 controls the sound reproduction operation by the speaker 11, the image display operation by the display device 13, the lamp lighting/extinguishing operation by the lamp group 18 including the LED, and the performance operation by the accessory 20 (decorative member). That is, the sub-control circuit 200 controls various production devices based on commands from the main control circuit 70, and executes various productions in accordance with the progress of the game. In this embodiment, the sub-control circuit 200 is configured to not supply a signal to the main control circuit 70, but the present invention is not limited to this, and a configuration that allows signal transmission from the sub-control circuit 200 to the main control circuit 70 may be provided.

Next, the internal configuration of the sub-control circuit 200 will be described in more detail with reference to FIG. FIG. 6 is a block diagram showing the circuit configuration inside the sub-control circuit 200 and the connection relationship between the sub-control circuit 200 and its various peripheral devices.

As shown in FIG. 6, the sub-control circuit 200 includes a relay board 201, a sub-board 202 (first board), a control ROM board 203, and a CGROM (Character Generator ROM) board 204 (second board). The sub board 202 is connected to the relay board 201 , the control ROM board 203 and the CGROM board 204 . In the sub-control circuit 200, the sub-board 202 and various ROM boards (control ROM board 203 and CGROM board 204) are connected via board-to-board connectors (not shown).

The relay board 201 is a relay board for receiving a command transmitted from the main control circuit 70 and transmitting the received command to the sub-board 202 .

The sub board 202 is provided with a host control circuit 210 , an audio/LED control circuit 220 , a display control circuit 230 , an SDRAM (Synchronous Dynamic RAM) 250 and an internal relay board 260 . Among them, at least the host control circuit 210, the audio/LED control circuit 220, and the display control circuit 230 are configured as one board substrate.

The host control circuit 210 is a circuit that controls the overall operation of the sub-control circuit 200 based on various commands sent from the main control circuit 70, and includes a CPU processor, sub-work RAM 210a, SRAM 210b, RTC (real-time clock), and a watchdog timer. The host control circuit 210 is connected to the audio/LED control circuit 220 , the display control circuit 230 and the built-in relay board 260 in the sub-board 202 . Also, the host control circuit 210 is connected to the control ROM board 203 .

The host control circuit 210 also has a sub-work RAM 210a and an SRAM (Static RAM) 210b. The sub-work RAM 210a is a storage device that acts as a working temporary storage area when the host control circuit 210 executes various processes, and stores various flags and variable values required when the host control circuit 210 executes various processes. The SRAM 210b is a storage device that backs up predetermined data in the sub-work RAM 210a. In this embodiment, a RAM is used as a temporary storage area for the host control circuit 210, but the present invention is not limited to this, and any readable/writable storage medium may be used as a temporary storage area.

The sound/LED control circuit 220 is connected to the speaker 11 and the lamp group 18 via the built-in relay board 260, and controls the sound reproduction operation by the speaker 11 and the light emission operation by the lamp group 18 based on control signals (sound request and lamp request described later) input from the host control circuit 210. Functionally, therefore, the audio and LED control circuit 220 includes an audio controller 220a and a lamp controller 220b. Sound controller 220a and lamp controller 220b are substantially included in sound and lamp control module 226, described below. The internal configuration of the audio/LED control circuit 220 will be described later in detail with reference to the drawings.

In the present embodiment, when control signals and data (for example, LED data to be described later) output from the audio/LED control circuit 220 are transmitted to the lamp group 18 via the built-in relay board 260, communication between the audio/LED control circuit 220 and the lamp group 18 is performed using an SPI (Serial Peripheral Interface) communication method (a type of serial communication method). Also, in this embodiment, the lamp group 18 includes one or more LEDs and one or more LED drivers for controlling each LED.

The display control circuit 230 is connected to the display device 13, and is a circuit for controlling various processing operations when the display device 13 displays images related to effects (decorative pattern images, background images, effects images, etc.) based on control signals (drawing requests) input from the host control circuit 210. The display control circuit 230 has a display controller (a first display controller 238 and a second display controller 239 which will be described later) and a built-in VRAM (Video RAM) 237 .

Also, the display control circuit 230 is connected to the SDRAM 250 within the sub-board 202 . Furthermore, the display control circuit 230 is connected to the CGROM board 204 . Also, the display controller in the display control circuit 230 is directly connected to the display device 13 without a relay board. The internal configuration of the display control circuit 230 will be detailed later with reference to the drawings.

The SDRAM 250 is composed of a DDR2 (Double-Date Rate 2) SDRAM. Further, the SDRAM 250 is provided with various buffers for temporarily storing various image data in drawing processing of images (moving images and still images) displayed by the display device 13 . Specifically, for example, the SDRAM 250 is provided with a texture buffer, a movie buffer, a blend buffer, two frame buffers (a first frame buffer and a second frame buffer), a motion buffer, and the like.

The internal relay board 260 receives various signals and various data output from the host control circuit 210 and the audio/LED control circuit 220, and transmits the received various signals and various data to the speaker 11, the lamp group 18, and the accessory 20.

The built-in relay board 260 also has an I2C (Inter-Integrated Circuit) controller 261 and a digital audio power amplifier 262 (amplifying means). In the present embodiment, an example in which the I2C controller 261 and the digital audio power amplifier 262 are mounted on the same relay board is shown, but the present invention is not limited to this, and the relay board on which the I2C controller 261 is mounted may be provided separately from the relay board on which the digital audio power amplifier 262 is mounted.

The I2C controller 261 is connected to the host control circuit 210 and the motor controller 270 of the accessory 20 . That is, the host control circuit 210 is connected to the accessory 20 via the I2C controller 261 and the motor controller 270 . Control signals and data (for example, excitation data described later) output from the host control circuit 210 are input to the accessory 20 via the I2C controller 261 and the motor controller 270 .

In this embodiment, communication between the I2C controller 261 and the motor controller 270 is performed using an I2C communication method (a type of serial communication method). In this embodiment, the accessory 20 includes one or more motors, and the motor controller 270 includes one or more motor drivers for driving each motor. Although FIG. 6 shows an example in which only one accessory 20 is provided, the present invention is not limited to this, and a plurality of accessory 20 may be provided.

In the configuration of this embodiment, the host control circuit 210 may directly drive the motor of the accessory 20 without using the motor controller 270, or a control circuit for motor control may be provided separately. Furthermore, in this embodiment, one control circuit controls a plurality of motor drivers (motors), but the present invention is not limited to this. In the present embodiment, one or more (one or more) control circuits may control one or more (one or more) motors (motor drivers), one or more (one or more) control circuits may control one motor (motor driver), or one control circuit may control one motor (motor driver).

Also, the digital audio power amplifier 262 is connected to the audio/LED control circuit 220 and the speaker 11 . That is, the audio/LED control circuit 220 is connected to the speaker 11 via the digital audio power amplifier 262 . Therefore, an audio signal or the like output from the audio/LED control circuit 220 is input to the speaker 11 via the digital audio power amplifier 262 .

A sub-main ROM 205 is provided on the control ROM board 203 . The sub-main ROM 205 stores various programs for controlling the performance operation of the pachinko gaming machine 1 by the host control circuit 210, and various data tables (for example, see FIG. 26, which will be described later). The host control circuit 210 then executes various processes according to the programs stored in the sub-main ROM 205 .

In this embodiment, the sub-main ROM 205 is used as storage means for storing programs and various tables used in the host control circuit 210, but the present invention is not limited to this. As such a storage means, a computer-readable storage medium having a control means may be used, and a storage medium such as a hard disk device, a CD-ROM, a DVD-ROM, and a ROM cartridge may be used. Also, each of the programs may be recorded on separate storage media. Furthermore, the program may be recorded in a recording medium in advance, or may be downloaded from an external source or the like after the power is turned on and recorded in the sub-main ROM 205 .

A CGROM 206 is provided on the CGROM board 204 . The CGROM 206 is composed of a NOR type or NAND type flash memory. The CGROM 206 also stores, for example, image data displayed on the display device 13, audio data reproduced by the speaker 11 (also referred to as sound data in this specification), and the like. At this time, various data are compressed (encoded) and stored in the CGROM 206, but the present invention is not limited to this, and the various data may be stored in the CGROM 206 without being compressed.

In the present embodiment, various ROM boards (the control ROM board 203 and the CGROM board 204) and the sub board 202 are connected by board-to-board connectors in the sub control circuit 200. However, the present invention is not limited to this. For example, various ROMs may be directly inserted into ports such as sockets provided on the sub-board 202, and the sub-board 202 may be configured by a single board having a ROM function or a ROM itself. That is, the sub-board 202 and various ROMs may be configured integrally. Further, when the sub-board 202 is composed of a single board having a ROM function or a ROM itself, the sub-control circuit 200 may include switching means for physically or electrically switching the circuit on the sub-board to be used according to the type of memory used as CGROM, or switching means for switching the information of the circuit on the sub-board to be used according to the type of memory.

Further, in this embodiment, the data communication speed between each of the various storage means (sub-main ROM 205, CGROM 206, built-in VRAM 237, SDRAM 250) and the corresponding control circuit is such that built-in VRAM 237>SDRAM 250>sub-main ROM 205≈CGROM 206. That is, in this embodiment, the communication speed between the built-in VRAM 237 and various circuits in the display control circuit 230 is the fastest, and the communication speed between the SDRAM 250 and the display control circuit 230 is second fastest. Then, the communication speed between the sub-main ROM 205 and the host control circuit 210 and the communication speed between the CGROM 206 and the display control circuit 230 are slowest. However, the present invention is not limited to this, and it is possible to arbitrarily set the magnitude relationship of the communication speed between each of the various storage means and the corresponding control circuit. For example, the magnitude relationship of the communication speed between each of the various storage means and the corresponding control circuit may be different from that of the present embodiment, or the communication speed between each storage means and the corresponding control circuit may be the same.

Possible configurations of the various storage means described above will now be described. In this embodiment, a configuration example is described in which the storage means for information (compressed (encoded) image data) on image data is the same as the storage means (CGROM 206) for information on transparency data (an alpha table to be described later) that can be used when setting the transparency of image data. That is, the configuration example in which the "first information storage means" is physically the same as the "second information storage means" has been described. However, the invention is not so limited. For example, the "first information storage means" may be composed of a storage means (storage medium) physically different from the "second information storage means".

Further, the "information storage means" as used in this specification may mean not only a storage means such as the CGROM 206, but also a table stored in the storage means, a data storage area in the storage means, and the like. Therefore, for example, the "first information storage means" and the "second information storage means" may be different data storage areas within the same storage means, may be different tables, or may be stored at different register addresses. In other words, the term "different information storage means" as used in this specification means not only the case where the storage means (storage media) are physically different, but also the case where the data areas (storage areas distinguished by addresses, registers, tables, structures, etc.) in the storage means are different although they are physically the same storage means (eg, ROM, RAM, etc.).

The meaning of the "information storage means" in this specification can also be applied to the "third information storage means" (SDRAM 250) and the "fourth information storage means" (built-in VRAM 237). Therefore, for example, the ``first information storage means'' to the ``fourth information storage means'' may be composed of physically different storage means (storage media), or the ``first information storage means'' to the ``fourth information storage means'' may be composed of mutually different data areas (storage areas distinguished by addresses, registers, tables, structures, etc.) within one storage means.

Further, in the present embodiment, the "first information storage means" and the "second information storage means" are composed of different data areas in one storage means (CGROM 206), the "third information storage means" is composed of the storage means (CGROM 206) that includes the "first information storage means" and the "second information storage means" and the storage means (SDRAM 250) physically different from the storage means (CGROM 206), and the "fourth information storage means" is composed of the "first information storage means" and the "second information storage means". An example has been described in which the storage means (CGROM 206) including the "information storage means" and the storage means (built-in VRAM 237) physically different from the "third information storage means" (SDRAM 250) are used, but the present invention is not limited to this. Whether the ``information storage means'' is composed of a data area or a storage means, and how the ``information storage means'' defined as the data area and the ``information storage means'' defined as the storage means are combined can be appropriately set according to, for example, the configuration (number, type, etc.) of the storage means provided in the gaming machine. For example, in the present embodiment, the "first information storage means" to "third information storage means" may be composed of mutually different data areas in one storage means, and the "fourth information storage means" may be composed of storage means physically different from the storage means including the "first information storage means" to "third information storage means".

[Audio/LED control circuit]
Next, the internal configuration of the audio/LED control circuit 220 will be described with reference to FIG. FIG. 7 is a block diagram showing the internal circuit configuration of the audio/LED control circuit 220 and the connection relationship between the audio/LED control circuit 220 and its various peripheral devices and peripheral circuit units. In addition, in FIG. 7, for the sake of simplification of explanation, illustration of relay boards and the like provided between the audio/LED control circuit 220 and various peripheral devices and circuit units is omitted.

As shown in FIG. 7, the audio/LED control circuit 220 includes an LSI (Large-Scale Integration) interface 221, a memory interface 222, a digital audio interface 223, a peripheral interface 224, a command register 225, a sound/lamp control module 226, a main generator 227, and a multi-effector 228. The connection relation of each part in the audio/LED control circuit 220 is as follows.

Within the audio/LED control circuit 220 , a sound/lamp control module 226 is connected to a memory interface 222 , a peripheral interface 224 , a command register 225 , a main generator 227 and a multi-effector 228 . Also, the command register 225 is connected to the LSI interface 221 in addition to the sound/lamp control module 226 . The main generator 227 is also connected to the memory interface 222 and the multi-effector 228 in addition to the sound/lamp control module 226 . Furthermore, the multi-effector 228 is connected to the memory interface 222 and the digital audio interface 223 in addition to the sound/lamp control module 226 and the main generator 227 .

Next, the configuration of each part in the audio/LED control circuit 220 will be described.

The LSI interface 221 is an interface circuit used when inputting/outputting control signals (for example, sound request, lamp request, etc.) between the host control circuit 210 and the command register 225 . That is, command register 225 is connected to host control circuit 210 via LSI interface 221 .

The memory interface 222 is an interface circuit used when inputting/outputting audio data between the sub-main ROM 205 and the sound/lamp control module 226, main generator 227 and multi-effector 228, respectively.

The digital audio interface 223 is an interface circuit used when outputting an audio signal or the like from the multi-effector 228 to the speaker 11 . Also, the digital audio interface 223 outputs the audio input signal to the multi-effector 228 .

The peripheral interface 224 is an interface circuit used when inputting/outputting lamp signals and the like (LED data and the like to be described later) between the lamp group 18 and the sound/lamp control module 226 . The peripheral interface 224 is provided with three physical systems (SPI channels) for outputting data to the LED drivers included in the lamp group 18 . In this embodiment, two physical systems (physical system 0 (SPI channel 0) and physical system 1 (SPI channel 1)) are used as described later.

The command register 225 consists of a large group of registers (eg, a large number of voice control registers) accessed by the host control circuit 210 . The command register 225 sets the function control of the sound/lamp control module 226 , the main generator 227 and the multi-effector 228 . The command register 225 also sets operating conditions for each interface (LSI interface 221, memory interface 222, digital audio interface 223, peripheral interface 224).

Each register constituting the command register 225 is equipped with an IC (Integrated Circuit), and each register is composed of a memory chip whose operation is stabilized by memory access control. When registers with such a configuration are used, the load on the signal bus to which each register is connected is reduced, so that the capacity per memory module (capacity of the command register 225) can be easily increased by increasing the number of memory chips (registers).

The sound/lamp control module 226 comprehensively controls the sound reproduction operation and the like, and controls the operation of each component (each block) in the sound/LED control circuit 220 according to the setting contents of the command register 225 . The sound/lamp control module 226 includes a simple access controller 226a, a sequencer 226b, a lamp control section 226c and a peripheral control section 226d, as shown in FIG.

The simple access controller 226a is a circuit unit that collectively processes commands. The sequencer 226b has various sequencers (automatic reproduction function units) for controlling automatic reproduction operations such as lamp lighting and sound. Each sequencer controls various operations according to timers and step conditions (for example, conditions set for each step process during sequence reproduction such as LED animation and sound, which will be described later).

The lamp control unit 226c calculates luminance values to be set in all channels (eight channels) for which LED data, which will be described later, can be set, and transmits the calculation results to the outside (LED driver). Further, the peripheral control unit 226d performs physical transmission control when transmitting the data of the calculation result output from the lamp control unit 226c to the LED driver.

The main generator 227 is a circuit section that generates an audio signal. Specifically, the main generator 227 acquires predetermined audio data stored in the CGROM 206 based on the control signal input from the sound/lamp control module 226, and converts the acquired audio data into a predetermined audio signal. The main generator 227 includes a decoder 227a that reproduces compressed data divided into reproduction channels CH1 to CH32, a channel volume 227b (V1 to V4) that adjusts the sound volume, a channel mix section 227c that mixes the reproduced sound of the decoder 227a, and a remix section 227d that executes a final mixing operation.

The multi-effector 228 has a mixer for synthesizing an audio signal input from the main generator 227 and an audio input signal input from the digital audio interface 223, and various effectors for applying various acoustic effects to audio. The multi-effector 228 outputs the audio signal synthesized by the mixer, the output signal from the effector, and the like to the speaker 11 via the digital audio interface 223 .

FIG. 8 is a drawing for explaining the output signal of the audio/LED control circuit. The CGROM 206 stores up to 8192 types of sequence code groups and up to 8192 types of SAC data groups. The sequence code and SAC data are specified by a 13-bit sequence code number and SAC number, respectively, and have a relationship of 8192= ²¹³ .

In this embodiment, 16 lines (SQ0 to SQ15) operating in parallel are provided as the sequencer 226b, and 4 lines (SAC0 to SAC3) operating in parallel are provided as the simple accelerator controller 226a. Corresponding to this configuration, the command register 225 is provided with an audio control register RGj2 for controlling the sequencers (SQ0 to SQ15) and an audio control register RGj1 for controlling the SACs (SAC0 to SAC3).

Then, when the host control circuit 210 composed of the CPU processor writes the SAC number and its attached information to a predetermined voice control register RGj1 for SAC control based on the voice command transmission operation, the corresponding simple access controller 226a starts functioning, and the simple access controller 226a writes a group of setting data specified by the SAC number to a group of voice control registers indicated by the SAC data. In this embodiment, a complicated setting operation can be completed by transmitting one SAC number and its associated information.

On the other hand, when the host control circuit 210 constituted by the CPU processor writes the sequence code number and its attached information to the predetermined voice control register RGj2 for controlling the sequencer 226b (SQ0 to SQ7) based on the voice command transmission operation, the corresponding sequencer SQi starts functioning and writes the group of setting data specified by the sequence code to the group of voice control registers indicated by the sequence code.

Here, a predetermined voice control register RGj2 for controlling the sequencers (SQ0 to SQ7) can be written with a plurality of (up to 8) sequence code numbers and loop information for the performance of each sequence code number for an arbitrary sequencer SQi. Therefore, for example, when n+1 sequence code numbers (X0, X1, . . . , Xn) are specified for the sequencer SQi, the sequence code number setting operation→sequence code number X1 setting operation→ .

Also, since loop information such as the number of repetitions can be specified for each sequence code number, the voice performance specified by the sequence code number can be shifted to the voice performance specified by the next sequence code number after repeating the voice performance specified by the sequence code number for a predetermined number of times.

Thus, the data to be set in the sequencer SQi is diverse, and it is necessary to appropriately set the sequence code number and associated data in the voice control register RGj2 for controlling the sequencer. Therefore, in this embodiment, the entire sequence code number and accompanying data are divided into 1-byte units, and a group of SAC data consisting of the divided 1-byte data and the register address of the sequencer control register RGj2 to which the 1-byte data is to be set is secured in the CGROM 206 (hereinafter referred to as sequencer start-up SAC data).

The host control circuit 210 activates the simple access controller 226a by specifying a predetermined SAC number in the voice control register RGj1 for SAC control. Here, of course, the SAC number specifies the SAC data for starting the sequencer. Based on the operation of the SAC (Simple Access Controller), necessary data is developed in the sequencer control register RGj2. Therefore, it is easy to set the activation data for the sequencers SQ0 to SQ15.

By the way, as described above with reference to FIG. 8, a group of sequence codes specified by one sequence code number describes a plurality of operation units (sequence steps) separated by a step end code (FFFEH). Consequently, after all the plurality of sequence steps specified by one sequence code number are executed, the plurality of sequence steps specified by the next sequence code number are executed.

Since a waiting time can be set for each sequencer, the first sequence step (the operation of writing a group of setting data) is started after the waiting time pointed out by the host control circuit 210 constituted by the CPU processor, and when the step end code (FFFEH) is executed, the next group of setting data is written to the group of voice control registers after the waiting time. As for the standby time, a single piece of time information can be set for each sequencer (SQ0 to SQ7). For example, in the preceding sequence step, by setting the standby time applied to the following sequence step, the standby time for each sequence step can be arbitrarily set.

Continuing the description of the internal configuration of the audio/LED control circuit 220, as shown in FIG. 7, the 6-channel output signals (Mixed L0, Mixed R0, Mixed L1, Mixed R1, Mixed SUB0, Mixed SUB1) of the channel mixing section 227c are digitally filtered in the multi-effector 228 based on the operating parameters specified in the predetermined audio control register of the command register 225, and then supplied to the total volume 229 (TV0 to TV3). and amplified based on the total volume value TV.

The total volume value TV is defined by the operation parameter written in the corresponding audio control register, and as described above, in this embodiment, in principle, the setting switch (hardware switch) operated by the attendant is used to define the operation parameter. However, when the player operates the volume switch (screen operation) during the game operation (however, while waiting for the sound effect), the total volume TV is defined (changed) based on the set value. When the player operates the volume switch, the channel volume 227b (V1 to V4) may be defined (changed) instead of or in addition to the total volume TV being defined based on the set value.

[Speaker volume control]
Next, volume control of each speaker 11 executed by the host control circuit 210 will be described with reference to FIG. FIG. 9 is a control block diagram for explaining an example of volume control by the host control circuit.

Sounds such as game sounds output from each speaker 11 (L0/R0/L1/R1, SUB0, SUB1) are volume-controlled by a volume transition operation that transitions the volume value of the audio signal step by step by multiplying the audio signal of the total volume TV0 to 3 output to all channels by the audio signal of each reproduction channel output to each individual channel among all channels.

The "audio signal" has volume information (for example, information such as wattage), and can be simply referred to as "volume". For example, in this specification, "audio signal for each playback channel" may be referred to as "volume for each playback channel".

The audio signal of the total volume TV0-3 is defined by multiplying the total value of the audio signal output by the volume control 281 by the hardware switch and the audio signal output by the user volume control 282 by the volume setting screen, and the audio signal output by the debug volume control 283 during debugging. The host control circuit 210 that executes the volume control 281 by the hardware switch, the user volume control 282 by the volume setting screen, and the debug volume control 283 during debugging corresponds to the "first volume control means" of the present invention.

Also, the volume of each playback channel is obtained by multiplying the audio signal of the primary volume by the audio signal of the secondary volume. The primary volume audio signal is defined by the combined value of the audio signal output by the first playback channel primary control 284 affected by the volume adjustment and the audio signal output by the second playback channel primary control 285 not affected by the volume adjustment. In the first playback channel primary control 284, for example, control is performed to change the volume of normal game sounds (i.e., voice signals (hereinafter the same)) based on the operation of changing the volume by the player or the like. In the second playback channel primary control 285, control is performed to output a specific game sound (for example, an error sound or a warning sound for illegal activity) at a constant volume regardless of whether or not an operation to change the volume has been performed. This constant volume may always be the maximum volume. In this way, the second reproduction channel primary control 285, which is not affected by the volume adjustment, is controlled so that the specific game sound is output at a constant volume, so that it is possible to perform control to make the volume of the specific game sound constant only in the specific reproduction channel instead of the whole. The secondary volume audio signal is the volume incorporated in the audio data specified by the SAC number, and is output by volume controls 286, 287, and 288. FIG. The host control circuit 210 that executes the first reproduction channel primary control 284, the second reproduction channel primary control 285, and the volume controls 286, 287, 288 incorporated in the audio data corresponds to the "second volume control means" of the present invention.

In this way, the sound output from each speaker 11 (L0/R0/L1/R1, SUB0, SUB1) is defined by multiplying the volume of the total volume TV0 to TV3 with the volume of the primary volume and the volume of the secondary volume, which are volumes for each reproduction channel. Therefore, it is possible to give diversity to the volume of the game sound. In particular, since the volume of the total volume TV0 to TV3 is also specified by the volume output by the debug volume control 283 at the time of debugging, the game sound data used in the game can be used as it is at the time of debugging, and the work efficiency at the time of debugging can be improved.

In addition, the volume of normal game sounds can be changed based on the operation of changing the volume by the player or the like, but the second playback channel primary control 285 outputs a constant volume of specific game sounds such as error sounds and alarm sounds for illegal activities, regardless of whether or not an operation to change the volume is performed. Therefore, the occurrence of an error or an illegal act cannot be hidden, and security can be enhanced.

In the pachinko game machine 1 of the present embodiment, the volume control 281 by the hardware switch has three stages of large, medium, and small, for example. Also, the user volume control 282 on the volume setting screen has seven levels, and is interlocked with hardware switches to [small]=[1], [medium]=“4”, and [large]=“7”.

As described above, in the pachinko gaming machine 1 of the present embodiment, the volume of a specific sound such as an error sound can be maintained only by the control by the second reproduction channel primary control 285. Therefore, it is possible to easily perform volume control such as maintaining the volume of the specific sound and changing the volume of other normal sounds according to the volume adjustment. Processing by the host control circuit 210 when volume adjustment is performed will be described later with reference to FIGS. 61 to 65. FIG.

[Connection configuration between digital audio power amplifier and speaker]
Next, the connection configuration between the digital audio power amplifier 262 and its peripheral circuits provided in the built-in relay board 260 and the speaker 11 will be described with reference to FIG. FIG. 10 is a connection configuration diagram between the built-in relay board 260 and the speaker 11. As shown in FIG. Note that FIG. 10 shows a state in which the speaker 11 is not connected to the built-in relay board 260 in order to clarify the configuration of the connecting portion.

In the pachinko game machine 1 of this embodiment, as shown in FIG. 10, the speaker box 11a provided with the speaker 11 is connected to the built-in relay board 260 via the harness 300. As shown in FIG.

The built-in relay board 260 has a digital audio power amplifier 262, an LC circuit 263, a connection terminal group 264 including four connection terminals (first to fourth connection terminals), two resistors 265 and 266, a capacitor 267, and a NOT circuit (logic circuit) 268.

The digital audio power amplifier 262 amplifies the input audio signal (audio data) and outputs the amplified audio signal to the speaker 11 to drive the speaker 11 . The LC circuit 263 is composed of a resonance circuit including a coil and a capacitor. The NOT circuit 268 is a logic circuit that inverts the level of the input signal and outputs it.

A clock input terminal (MCK) and a data input terminal (SDATA) of the digital audio power amplifier 262 are connected to the audio/LED control circuit 220 . A clock signal (master clock signal) output from the audio/LED control circuit 220 is input to the clock input terminal (MCK) of the digital audio power amplifier 262, and an audio signal (audio data) output from the audio/LED control circuit 220 is input to the data input terminal (SDATA).

Also, the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 are connected to the first connection terminal and the second connection terminal in the connection terminal group 264 of the built-in relay board 260 via the LC circuit 263, respectively. In this embodiment, an example in which two output terminals are provided for the digital audio power amplifier 262 is shown, but the present invention is not limited to this, and can be changed as appropriate according to the functions and specifications of the speaker 11, for example.

Furthermore, the digital audio power amplifier 262 has a mute terminal (MUTE: audio output control terminal). The digital audio power amplifier 262 has a function (hereinafter referred to as a mute function) that stops the output of the audio signal from the first output terminal (OUTM1) and the second output terminal (OUTM2) or grounds these output terminals via a high resistance when the level (amplitude value) of the voltage signal applied to the mute terminal is LOW. That is, the digital audio power amplifier 262 has the function of generating a state in which the output of the audio signal from the first output terminal (OUTM1) and the second output terminal (OUTM2) to the first connection terminal and the second connection terminal of the built-in relay board 260 is stopped when the level of the voltage signal applied to the mute terminal is at the LOW level.

On the other hand, when the level (amplitude value) of the voltage signal applied to the mute terminal (MUTE) is HIGH, the digital audio power amplifier 262 outputs audio signals from the first output terminal (OUTM1) and the second output terminal (OUTM2).

A third connection terminal in the connection terminal group 264 of the built-in relay board 260 is connected to an input terminal of a NOT circuit 268 via a resistor 266 . Also, the output terminal of the NOT circuit 268 is connected to the mute terminal (MUTE) of the digital audio power amplifier 262 . The signal wiring between the third connection terminal of the built-in relay board 260 and the resistor 266 is connected via the resistor 265 to a power supply voltage (+5 V) terminal provided inside the built-in relay board 260 . A signal wiring between the input terminal of the NOT circuit 268 and the resistor 266 is connected (grounded) to a ground (GND) terminal provided in the built-in relay board 260 via a capacitor 267 . Furthermore, the fourth connection terminal of the built-in relay board 260 is connected to the ground (GND) terminal.

The speaker 11 is attached to a speaker box 11a made of a wooden frame, as shown in FIG. Further, the speaker box 11a is provided with a connection terminal group 11b including four connection terminals (first to fourth connection terminals). A first connection terminal and a second connection terminal of the speaker box 11a are connected to the speaker 11 via signal wiring. Also, the third connection terminal (specific connection terminal) of the speaker box 11a is electrically connected to the fourth connection terminal by the signal wiring W1.

The harness 300 is configured by bundling four signal wirings, as shown in FIG. Four connection terminals (first to fourth connection terminals) of one of the four signal wirings are connected to the first to fourth connection terminals of the built-in relay board 260, respectively. On the other hand, the other four connection terminals (fifth to eighth connection terminals) of the four signal wires are connected to the first to fourth connection terminals of the speaker box 11a, respectively. That is, the first connection terminal of the internal relay board 260 and the first connection terminal of the speaker box 11a are connected by the signal wiring between the first connection terminal and the fifth connection terminal in the harness 300, and the second connection terminal of the built-in relay board 260 and the second connection terminal of the speaker box 11a are connected by the signal wiring between the second connection terminal and the sixth connection terminal in the harness 300. Further, the third connection terminal of the internal relay board 260 and the third connection terminal of the speaker box 11a are connected by the signal wiring between the third connection terminal and the seventh connection terminal in the harness 300, and the fourth connection terminal of the built-in relay board 260 and the fourth connection terminal of the speaker box 11a are connected by the signal wiring between the fourth connection terminal and the eighth connection terminal in the harness 300. Thereby, the speaker 11 is connected to the built-in relay board 260 via the harness 300 .

Note that the number of signal wirings included in the harness 300 is not limited to four, and can be changed as appropriate according to the specifications of the digital audio power amplifier 262 and the speaker 11, the connection configuration between them, and the like. The harness 300 may include at least signal wiring for connecting the output terminal of the digital audio power amplifier 262 and the speaker 11, and signal wiring for grounding the mute terminal of the digital audio power amplifier 262 via the speaker box 11a.

When the built-in relay board 260 and the speaker 11 are connected via the harness 300 as described above, the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 are connected to the speaker 11 via the harness 300. A mute terminal (MUTE) of the digital audio power amplifier 262 is grounded through the NOT circuit 268, the harness 300, and the signal wiring W1 between the third and fourth connection terminals of the speaker box 11a.

As a result, when the speaker 11 is connected to the built-in relay board 260 (digital audio power amplifier 262) via the harness 300, a LOW level voltage signal is input to the NOT circuit 268, so that the level (amplitude value) of the voltage signal input to the mute terminal (MUTE) of the digital audio power amplifier 262 is HIGH. In this case, audio signals are output to the speaker 11 from the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 .

On the other hand, when the speaker 11 is not connected to the built-in relay board 260 (digital audio power amplifier 262), the third connection terminal of the built-in relay board 260 is open. In this case, since the power supply voltage (+5V) is input to the NOT circuit 268, the level (amplitude value) of the voltage signal input to the mute terminal (MUTE) of the digital audio power amplifier 262 is LOW, and the above-described mute function of the digital audio power amplifier 262 operates.

That is, when the speaker 11 is detached from the built-in relay board 260 (digital audio power amplifier 262), a state is generated in which the output of audio signals from the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 to the first connection terminal and the second connection terminal of the built-in relay board 260 is stopped. As a result, it is possible to suppress the occurrence of a resonance phenomenon between the digital audio power amplifier 262 (output terminal) and the first and second connection terminals of the built-in relay board 260, thereby preventing problems such as failure of the digital audio power amplifier 262.

As described above, in this embodiment, the mute function of the digital audio power amplifier 262 can be operated independently of software control by the host control circuit 210 and the audio/LED control circuit 220 . Therefore, for example, in a situation where the speaker 11 is detached from the built-in relay board 260, even if the host control circuit 210 and the audio/LED control circuit 220 recognize that the output stop control of the audio signal is being performed, the audio signal is erroneously output due to a bug (malfunction) in the program. Even if the door is closed without connection and the audio output is started, the mute function of the digital audio power amplifier 262 described above is activated in terms of hardware. In this case, the digital audio power amplifier 262 can be reliably protected, and the safety of the pachinko game machine 1 can be improved.

Furthermore, in the present embodiment, as described above, the third connection terminal of the built-in relay board 260 is connected to the ground (GND) terminal provided inside the built-in relay board 260 via the harness 300 and the signal wiring W1 between the third and fourth connection terminals of the speaker box 11a. With such a configuration, when the signal level of the third connection terminal of the built-in relay board 260 is LOW, it is possible to determine whether or not this is due to the grounding of the fourth connection terminal of the built-in relay board 260 by measuring the signal level of the fourth connection terminal of the built-in relay board 260, so that the digital output operation from the digital audio power amplifier 262 can be managed more accurately.

[Display control circuit]
Next, the internal configuration of the display control circuit 230 will be described with reference to FIG. FIG. 11 is a block diagram showing the circuit configuration inside the display control circuit 230 and the connection relationship between the display control circuit 230 and its various peripheral devices and peripheral circuit units.

As shown in FIG. 11, the display control circuit 230 includes a memory controller 231, a command memory 232, a command parser 233, a moving image decoder 234, a still image decoder 235, an SDRAM controller 236, an internal VRAM 237, a first display controller 238, a second display controller 239, a 3D (Dimension) geometry engine 240, and a rendering engine 241. The connection relation of each part in the display control circuit 230 and the connection relation between the display control circuit 230 and its various peripheral devices and peripheral circuits are as follows.

Within the display control circuit 230 , the memory controller 231 is connected to the command parser 233 , moving image decoder 234 and still image decoder 235 . The command parser 233 is connected to the command memory 232 , the moving image decoder 234 , the still image decoder 235 and the 3D geometry engine 240 in addition to the memory controller 231 . The video decoder 234 is connected to the SDRAM controller 236 in addition to the memory controller 231 and command parser 233 . The still image decoder 235 is connected to the built-in VRAM 237 in addition to the memory controller 231 and command parser 233 .

Also, in the display control circuit 230 , the SDRAM controller 236 is connected to a built-in VRAM 237 , a first display controller 238 and a second display controller 239 in addition to the video decoder 234 . The built-in VRAM 237 is connected to a first display controller 238 , a second display controller 239 and a rendering engine 241 in addition to the still image decoder 235 and SDRAM controller 236 . Additionally, the 3D geometry engine 240 is connected to the rendering engine 241 in addition to the command parser 233 .

The SDRAM 250 is connected to the memory controller 231 and SDRAM controller 236 in the display control circuit 230 . The CGROM board 204 is also connected to a memory controller 231 within the display control circuit 230 . The host control circuit 210 is also connected to a memory controller 231 and a command memory 232 within the display control circuit 230 . Further, the display device 13 is connected to a first display controller 238 and a second display controller 239 within the display control circuit 230 .

Next, the configuration of each part in the display control circuit 230 will be described.

The memory controller 231 mainly performs communication control between various external memories (the CGROM board 204 and the SDRAM 250) and the display control circuit 230. FIG. For example, the memory controller 231 performs processing such as transmission and reception of an address designation signal for an external memory to be controlled, memory ready and busy management, and data (effect data, command data, etc.) stored at a designated address for various memories.

Command memory 232 is a built-in memory that stores a command list. The command list can also be stored in the SDRAM 250 and the CGROM board 204 (CGROM 206) in addition to the command memory 232. FIG.

The command parser 233 acquires a command list from the designated memory (command memory 232, SDRAM 250 or CGROM 206). Specifically, in the present embodiment, the host control circuit 210 sets the type of memory (command memory 232, SDRAM 250, or CGROM 206) in which the command list is arranged and its start address in a system control register (not shown) in the display control circuit 230. The command parser 233 then accesses the start address in memory specified in the system control register (not shown) to obtain the command list.

Also, the command parser 233 analyzes the obtained command list to generate a specific control code, and outputs the control code to the moving image decoder 234 , still image decoder 235 and 3D geometry engine 240 . In this embodiment, each image processing module in the display control circuit 230 operates based on the control code output by the command parser 233 .

The moving picture decoder 234 decodes compressed moving picture data acquired from the CGROM board 204 or the SDRAM 250 . Then, the video decoder 234 outputs the decoded video data to the SDRAM 250 (external RAM). The moving image data (decoding result) output from the moving image decoder 234 is stored in a movie buffer provided within the SDRAM 250 .

The still image decoder 235 decodes still image compressed data acquired from the CGROM board 204 or the SDRAM 250 . Still image decoder 235 then outputs the decoded still image data to built-in VRAM 237 . The still image data (result of decoding) output from the still image decoder 235 is temporarily stored in a sprite buffer provided in the built-in VRAM 237, which will be described later.

The SDRAM controller 236 is a controller that controls operations such as storage processing of decoded moving image data and still image data in RAM and transfer processing of image data between the built-in VRAM 237 and the CGROM board 204 or SDRAM 250 .

The built-in VRAM 237 operates as a work RAM when executing various processes such as decoding and rendering in the drawing process by the display control circuit 230 . Various image data are temporarily stored in the built-in VRAM 237 in image data transfer processing between the built-in VRAM 237 and the CGROM board 204 or the SDRAM 250, which is performed in each process in the drawing processing described later.

Each of the first display controller 238 and the second display controller 239 acquires rendering results (drawing results) generated by the rendering engine 241 and outputs the rendering results to the display device 13 . Thereby, a predetermined image is displayed on the display screen of the display device 13 . When two display controllers are provided as in the pachinko game machine 1 of the present embodiment, two screens are provided in the display device 13 by one display control circuit 230 (one chip), and each screen can be controlled independently.

Based on the control code input from the command parser 233, the 3D geometry engine 240 performs processing for converting three-dimensional information into two-dimensional information (projection conversion processing), and affine transformation (graphic conversion) processing such as enlargement, reduction, rotation, and movement of graphics. The 3D geometry engine 240 then outputs the result of conversion processing to the rendering engine 241 .

The rendering engine 241 refers to the texture source (SDRAM 250 in this embodiment) in which the decompressed still image data and moving image data are stored, and renders (drawing) the image data. The rendering engine 241 then writes the rendering result to the rendering target (the built-in VRAM 237 or SDRAM 250 in this embodiment).

In this specification, "rendering (drawing)" means to edit decoded data according to specified information (in this embodiment, information output from the 3D geometry engine 240) such as scaling and rotation of the moving image. Further, the "rendering engine" here also includes, for example, a "rasterizer" and a "pixel shader". Therefore, in the rendering engine 241, similarly to the pixel shader, arithmetic processing of ARGB values (A: alpha value indicating transparency (opacity), R: brightness value of red component, G: brightness value of green component, B: brightness value of blue component) is also performed for each pixel of image data.

[Connection configuration between display control circuit and CGROM]
The pachinko game machine 1 of this embodiment has a configuration that can cope with different types of CGROMs (NOR type or NAND type) connected to the display control circuit 230 . Here, the connection configuration between the display control circuit 230 and its peripheral circuits provided in the sub-board 202 and the CGROM mounted on the CGROM board will be described with reference to FIGS. 12 and 13. FIG.

FIG. 12 is a connection configuration diagram between the sub-board 202 and the CGROM board 204a when the CGROM is a NOR-type CGROM 206a (NOR-type flash memory). FIG. 13 is a connection configuration diagram between the sub board 202 and the CGROM board 204b when the CGROM is a NAND type CGROM 206b (NAND type flash memory). 12 and 13 show the CGROM board separated from the sub-board 202 in order to clarify the structure of the connecting portion, but in reality the two boards are connected via a board-to-board connector.

(1) Configuration of Sub-Board First, the internal configuration of the sub-board 202 will be described. 12 and 13, the configuration of the sub-board 202 when the NOR-type CGROM 206a is mounted on the CGROM board 204a is the same as that when the NAND-type CGROM 206b is mounted on the CGROM board 204b.

As shown in FIGS. 12 and 13, the sub-board 202 is provided with a display control circuit 230 and, as its peripheral circuits, a bidirectional balance transceiver 301 and an AND circuit 302 (AND gate). Also, the sub-board 202 is provided with various signal wirings (buses) and a terminal group 303 including a plurality of connection terminals directly or indirectly connected to the display control circuit 230 via various buses.

The bidirectional balanced transceiver 301 has four input/output terminals (terminals A0 to A3 in FIG. 12) and four input/output terminals (terminals B0 to B3 in FIG. 12) connected to the four input/output terminals (terminals A0 to A3). The bi-directional balanced transceiver 301 also has two control terminals (terminal OE and terminal DIR in FIG. 12) for switching and controlling the communication direction of signals between the input/output terminals A0 to A3 and between the input/output terminals B0 to B3.

The bidirectional balanced transceiver 301 switches the signal communication direction between the input/output terminals A0 to A3 and the input/output terminals B0 to B3 according to the combination of the signal levels of the voltage signals applied to the control terminals OE and DIR, respectively. As a result, even if a mismatch occurs in the communication direction (communication operation) for some reason, the safety of the communication operation between the display control circuit 230 and the CGROM can be ensured. The communication direction switching control operation in the two-way balance transceiver 301 will be described in detail later. Also, the bi-directional balanced transceiver 301 used in this embodiment can be adapted to a system having two power supplies of 3.3V and 5V.

The display control circuit 230 is provided with four input/output terminals (terminals GMA31/GRB3 to terminal GMA28/GRB0 in FIG. 12). The input/output terminal GMA31/GRB3 to the input/output terminal GMA28/GRB0 act as output terminals of an address bus when the CGROM is the NOR type CGROM 206a, and act as input terminals of ready/busy signals when the CGROM is the NAND type CGROM 206b. In addition, the display control circuit 230 is provided with 26 output terminals (terminals GMA27 to GMA2 in FIG. 12) that act as output terminals for data (address designation data, etc.) relating to the addresses of the data storage areas in the CGROM.

The display control circuit 230 is also provided with two CG memory chip enable output terminals (terminal GCE_0 and terminal GCE_1 in FIG. 12). In this embodiment, the display control circuit 230 has two memory spaces corresponding to two CG memory chip enable output terminals (GCE_0, GCE_1: specific output terminals), and information such as memory type, bus width, and access timing is set in each memory space. However, in the present embodiment, the display control circuit 230 is configured so as not to support (use) a mixture of synchronous mode ROM and asynchronous mode ROM.

Further, the display control circuit 230 is provided with a plurality of data bus input terminals for acquiring image data (compressed moving/still image data) from the CGROM via a data bus.

The electrical connections of the components provided on the sub-board 202 are as follows.

The input/output terminals GMA31/GRB3 to the input/output terminals GMA28/GRB0 of the display control circuit 230 are connected to the input/output terminals B0 to B3 of the bidirectional balanced transceiver 301, respectively, as shown in FIGS. The input/output terminals A0 to A3 of the bidirectional balanced transceiver 301 are connected to the first to fourth connection terminals of the terminal group 303, respectively. That is, the input/output terminals GMA31/GRB3 to the input/output terminals GMA28/GRB0 of the display control circuit 230 are connected to the first to fourth connection terminals of the terminal group 303 via the bidirectional balance transceiver 301, respectively.

The output terminal GMA27 to output terminal GMA2 of the display control circuit 230 are connected to the 9th to 34th connection terminals of the terminal group 303, respectively, and the CG memory chip enable output terminal GCE_0 and the CG memory chip enable output terminal GCE_1 are connected to the 35th and 36th connection terminals of the terminal group 303, respectively. Furthermore, the plurality of data bus input terminals of the display control circuit 230 are connected to the corresponding connection terminals after the 37th connection terminal of the terminal group 303, respectively.

A control terminal DIR of the bidirectional balanced transceiver 301 is connected to the fifth connection terminal of the terminal group 303 , and a control terminal OE is connected to the output terminal of the AND circuit 302 . One input terminal of the AND circuit 302 is connected to the CG memory chip enable output terminal GCE_0, and the other input terminal of the AND circuit 302 is connected to the CG memory chip enable output terminal GCE_1. The sixth and seventh connection terminals of the terminal group 303 of the sub-board 202 are connected to the power supply voltage (+3.3V) terminal provided on the sub-board 202, and the eighth connection terminal is connected to the ground (GND) terminal provided on the sub-board 202.

(2) Configuration of CGROM Board (NOR Type) Next, the internal configuration of the CGROM board 204a on which the NOR type CGROM 206a is mounted will be described with reference to FIG.

When the NOR type CGROM 206a is mounted on the CGROM board 204a, the CGROM board 204a is provided with various signal wirings (buses) and a terminal group 311 including a plurality of connection terminals connected to the CGROM 206a via various buses together with the NOR type CGROM 206a.

The first to fourth connection terminals and the connection terminals after the ninth connection terminal in the terminal group 311 provided on the CGROM board 204a are connected to the CGROM 206a.

In the example shown in FIG. 12, the CGROM 206a is a NOR type flash memory (random access flash memory), so the first to fourth connection terminals and the ninth to 34th connection terminals in the terminal group 311 are connected to input terminals (not shown) of the address bus of the CGROM 206a. The 35th and 36th connection terminals in the terminal group 311 are connected to the CG memory chip enable input terminal (not shown) of the CGROM 206a, and the connection terminals after the 37th connection terminal are connected to the data output terminals of the CGROM 206a used when the display control circuit 230 acquires image data (compressed moving image/still image data) from the CGROM 206a.

The fifth connection terminal (predetermined connection terminal) in the terminal group 311 provided on the CGROM board 204a is connected to the eighth connection terminal through the signal wiring W2, and the eighth connection terminal is connected to the ground (GND) terminal provided on the CGROM board 204a. That is, when the CGROM 206a is a NOR flash memory, the fifth connection terminal is grounded via the signal wiring W2. Further, the sixth connection terminal and the seventh connection terminal in the terminal group 311 are connected to the power supply voltage (+3.3V) terminal provided on the CGROM board 204a.

The number of connection terminals included in the terminal group 311 is the same as the number of connection terminals in the terminal group 303 for connecting the CGROM board provided on the sub-board 202 . When the CGROM board 204a is connected (mounted) to the sub-board 202, both boards are connected such that the connection terminals of the CGROM board 204a are connected to the connection terminals of the sub-board 202 having the same terminal numbers. That is, as shown in FIG. 12, the first connection terminals, the second connection terminals, . . . , the 37th connection terminals, .

(3) Structure of CGROM Board (NAND Type) Next, the internal structure of the CGROM board 204b on which the NAND type CGROM 206b is mounted will be described with reference to FIG. In the configuration of the CGROM board 204b shown in FIG. 13, the same reference numerals are assigned to the same configurations as those of the CGROM board 204a on which the NOR-type CGROM 206a shown in FIG. 12 is mounted.

When the NAND-type CGROM 206b is mounted on the CGROM board 204b, the CGROM board 204b is provided with the NAND-type CGROM 206b and a transistor circuit 312 as its peripheral circuit. Also, the CGROM board 204b is provided with various signal wirings (buses) and a terminal group 311 including a plurality of connection terminals directly or indirectly connected to the CGROM 206b via various buses.

The first to fourth connection terminals in the terminal group 311 of the CGROM substrate 204 b are connected to the drain terminal of the transistor circuit 312 . The transistor circuit 312 has a gate terminal connected to the CGROM 206b and a source terminal connected to a ground (GND) terminal provided on the CGROM substrate 204b. That is, the first to fourth connection terminals are connected to the CGROM 206b via the transistor circuit 312. FIG.

In the example shown in FIG. 13, the CGROM 206b is a NAND flash memory (sequential access flash memory), so the gate terminal of the transistor circuit 312, that is, the first to fourth connection terminals in the terminal group 311 are connected to the ready/busy output terminal (not shown) provided in the CGROM 206b.

The fifth connection terminal (predetermined connection terminal) in the terminal group 311 of the CGROM board 204b is connected to the sixth and seventh connection terminals via the signal wiring W3, and the sixth and seventh connection terminals are connected to the power supply voltage (+3.3V) terminal provided on the CGROM board 204b. That is, when the CGROM 206b is a NAND flash memory, the fifth connection terminal is connected to the power supply voltage (+3.3V) terminal via the signal wiring W3.

An eighth connection terminal in the terminal group 311 of the CGROM board 204b is connected to a ground (GND) terminal provided on the CGROM board 204b.

Furthermore, the connection terminals after the ninth connection terminal in the terminal group 311 of the CGROM board 204b are connected to the CGROM 206b. At this time, the 9th to 34th connection terminals are connected to data input terminals (not shown) related to addresses provided in the CGROM 206b, and the 35th and 36th connection terminals are connected to the CG memory chip enable input terminals provided in the CGROM 206b. Connection terminals after the 37th connection terminal are connected to data output terminals (not shown) of the CGROM 206b used when the display control circuit 230 acquires image data (compressed moving/still image data) from the CGROM 206b.

Even when the NAND type CGROM 206b is mounted on the CGROM board 204b, the number of connection terminals included in the terminal group 311 of the CGROM board 204b is the same as the number of connection terminals of the terminal group 303 for connecting the CGROM board provided on the sub-board 202. When connecting (mounting) the CGROM board 204b to the sub-board 202, both boards are connected so that the connection terminals of the CGROM board 204b are connected to the connection terminals of the sub-board 202 having the same terminal number. That is, as shown in FIG. 13, the first connection terminals, the second connection terminals, . . . , the 37th connection terminals, .

[Communication operation between display control circuit and CGROM]
Next, the operation when the display control circuit 230 acquires image data (compressed moving/still image data) from the CGROM will be described with reference to FIGS. 12 to 15. FIG. 14 is a truth table showing the correspondence between the input signal and the output signal in the AND circuit 302 provided on the sub-board 202, and FIG. 15 is a truth table showing the correspondence between the signal level applied to the control terminal OE and the control terminal DIR and the communication direction in the two-way balanced transceiver 301 provided on the sub-board 202.

(1) Operation of AND Circuit and Bidirectional Balanced Transceiver As shown in FIG. 14, the AND circuit 302 outputs a HIGH level signal to the control terminal OE of the bidirectional balanced transceiver 301 only when HIGH level signals (voltage signals) are input to both input terminals, and outputs a LOW level signal to the control terminal OE under other input conditions.

As shown in FIG. 15, when a LOW level signal (voltage signal) is input to the control terminal OE and a LOW level signal is input to the control terminal DIR, the bidirectional balanced transceiver 301 causes the input/output terminals A0 to A3 of the bidirectional balanced transceiver 301 to act as output terminals and the input/output terminals B0 to B3 to act as input terminals. In this case, the communication direction between the display control circuit 230 and the CGROM is the direction from the display control circuit 230 to the CGROM.

When a LOW level signal is input to the control terminal OE and a HIGH level signal is input to the control terminal DIR, the bidirectional balanced transceiver 301 causes the input/output terminals A0 to A3 of the bidirectional balanced transceiver 301 to act as input terminals and the input/output terminals B0 to B3 to act as output terminals. In this case, the communication direction between the display control circuit 230 and the CGROM is the direction from the CGROM to the display control circuit 230 .

When the combination of the signal level input to the control terminal OE of the bidirectional balanced transceiver 301 and the signal level input to the control terminal DIR is a combination other than the above (when a HIGH level signal is input to the control terminal OE of the bidirectional balanced transceiver 301), the input/output terminals A0 to A3 and the input/output terminals B0 to B3 of the bidirectional balanced transceiver 301 enter a HIGH impedance state ("Z" in FIG. 15), that is, a state equivalent to an open state, thereby controlling the display. There is no communication between circuit 230 and CGROM.

(2) Communication Operation Between Display Control Circuit and CGROM (NOR Type) First, consider the case where the CGROM board 204a on which the NOR type CGROM 206a is mounted is connected (mounted) to the sub-board 202. FIG.

In this case, in this embodiment, at least one of the two CG memory chip enable output terminals GCE_0 and GCE_1 of the display control circuit 230 outputs a LOW level signal, so a LOW level signal is input to the control terminal OE of the bidirectional balanced transceiver 301. The signal levels of the CG memory chip enable output terminals GCE_0 and GCE_1 are set in hardware initialization processing (see FIG. 38 described later).

In this embodiment, the amplitude values of the signals output from the CG memory chip enable output terminals GCE_0 and GCE_1 (specific terminals) set in advance by the sub-control circuit 200 differ according to the type of CGROM. Therefore, the amplitude values of the signals output from the CG memory chip enable output terminals GCE_0 and GCE_1 provided in the display control circuit 230 change according to the type of storage means. However, the mode in which "the amplitude value of the output signal changes according to the type of CGROM" is not limited to this mode. As will be described later in modification 7, the display control circuit 230 may detect the type of connected storage means, and based on the detection result, set the amplitude value of the signal output from the CG memory chip enable output terminals GCE_0 and GCE_1 (specific terminals).

The fifth connection terminal of the sub-board 202 to which the control terminal DIR of the two-way balanced transceiver 301 is connected is grounded through the fifth connection terminal of the CGROM board 204a and the signal wiring W2, as shown in FIG.

Therefore, when the CGROM board 204a on which the NOR-type CGROM 206a is mounted is connected to the sub board 202, the input/output terminals A0 to A3 of the two-way balanced transceiver 301 act as output terminals, and the input/output terminals B0 to B3 act as input terminals, as shown in FIG. That is, the communication direction between the display control circuit 230 and the CGROM 206a in the bidirectional balance transceiver 301 is the direction from the display control circuit 230 to the CGROM 206a.

In this case, the signal wiring connected via the first to fourth connection terminals of the sub-board 202 and the first to fourth connection terminals of the CGROM board 204a can be used as an address bus, and the display control circuit 230 can normally perform the memory addressing operation for the NOR-type CGROM 206a. As a result, the display control circuit 230 can be directly addressed via the address bus to perform data read operations.

(3) Communication Operation Between Display Control Circuit and CGROM (NAND Type) Next, consider the case where the CGROM board 204b on which the NAND type CGROM 206b is mounted is connected (mounted) to the sub board 202. FIG.

Even in this case, in this embodiment, at least one of the two CG memory chip enable output terminals CGE_0 and CGE_1 of the display control circuit 230 outputs a LOW level signal, so a LOW level signal is input to the control terminal OE of the bidirectional balanced transceiver 301. That is, in this embodiment, a LOW level signal is input to the control terminal OE of the two-way balanced transceiver 301 regardless of whether the type of CGROM is NOR type or NAND type. The fifth connection terminal of the sub-board 202 to which the control terminal DIR of the two-way balanced transceiver 301 is connected is connected to the power supply voltage (+3.3 V) terminal via the fifth connection terminal of the CGROM board 204b and the signal wiring W3, as shown in FIG.

Therefore, when the CGROM board 204b mounting the NAND type CGROM 206b is connected to the sub-board 202, as shown in FIG. That is, the communication direction between the display control circuit 230 and the CGROM 206b in the two-way balance transceiver 301 is the direction from the CGROM 206b to the display control circuit 230. FIG.

In this case, the signal wiring connected through the first to fourth connection terminals of the sub-board 202 and the first to fourth connection terminals of the CGROM board 204b can be used as ready/busy signal communication wiring. That is, in this case, it is possible to transmit the ready/busy signal from the CGROM 206 to the display control circuit 230, which the display control circuit 230 refers to when data is read from the NAND type CGROM 206b by the sequential access method. As a result, the display control circuit 230 can normally acquire the memory state (ready/busy state) for the NAND type CGROM 206b.

As described above, in this embodiment, even if the type of CGROM is changed, the communication operation between the display control circuit 230 and the CGROM can be performed normally without changing the configuration of the sub-board 202 . Therefore, in this embodiment, for example, the data capacity, communication speed, price, etc. can be taken into account to select the optimum CGROM. Further, for example, when manufacturing a new pachinko game machine 1, it is possible to easily cope with the case where the sub-board 202 used in the pachinko game machine manufactured in the past is diverted from the conditions such as data capacity and communication speed, and only the type of CGROM is changed. That is, in the pachinko gaming machine 1 of this embodiment, it becomes possible to select a CGROM according to the embodiment, and the expandability of the pachinko gaming machine 1 can be ensured.

Furthermore, in this embodiment, by using the bidirectional balanced transceiver 301, the first to fourth connection terminals in the terminal group 303 of the sub board 202 and the first to fourth connection terminals in the terminal group 311 of the CGROM board 204 can be used as data input/output terminals. In this case, there is no need to separately provide data input terminals and data output terminals corresponding to the first to fourth connection terminals of the sub-board 202 and the CGROM board 204, and the space of the sub-board 202 and the CGROM board 204 can be saved.

As described above, in this embodiment, the two-way balance transceiver 301 can switch the "communication mode" between the display control circuit 230 and the CGROM according to the type of CGROM. However, the "form of communication" between the display control circuit 230 and the CGROM referred to in this specification means the general form of transmission and reception of various information between the display control circuit 230 and the CGROM.

For example, the “form of communication” between the display control circuit 230 and the CGROM referred to in this specification includes not only the form of transmission/reception between the display control circuit 230 and the CGROM of data (image data (compressed data of moving/still images)) necessary for displaying information related to the effect operation on the display device 13, but also the form of transmission/reception of information designating the address of the data stored in the CGROM between the display control circuit 230 and the CGROM, and This also includes the mode of transmission and reception when receiving a ready/busy signal. The present invention is not limited to this, and the "communication mode" referred to in this specification may mean only the communication mode in which the information transmission/reception mode changes according to the type of CGROM.

<Type of game state>
Next, the types of game states controlled and managed by the main CPU 71 will be described.

In the present embodiment, the types of game states controlled and managed by the main CPU 71 include a "big win game state" (special game state) and a "small win game state" (specific game state) in which the degree of expectation for prize balls differs from each other. The ``jackpot game state'' is a game state in which a round game occurs in which the opening period of the shutter of the first big prize hole 53 or the second big prize hole 54 (that is, the period of one round) is long (for example, 30 seconds), and the player can expect a large prize ball. That is, in the "jackpot game state", the state in which the shutter of the jackpot opening is repeatedly opened and closed is advantageous for the player.

On the other hand, the ``small win game state'' is a game state in which a round game occurs in which the period of one round is shorter (for example, 1.8 sec) compared to the ``big win game state,'' and the player cannot expect a large prize ball. That is, in the "small winning game state", the repeated state of the open state and closed state of the shutter of the big winning opening becomes a disadvantageous state for the player.

In addition, in the present embodiment, the types of gaming states controlled and managed by the main CPU 71 include a “probability variable gaming state” (high probability gaming state) and a “normal gaming state” (low probability gaming state) in which the odds of winning a “jackpot” are different from each other.

The "probability variable gaming state" is a gaming state in which the probability of winning a "jackpot" (1/131 in this embodiment) is high. On the other hand, the "normal gaming state" is a gaming state in which the "jackpot" winning probability (1/392 in this embodiment) is lower than that in the "probability variable gaming state".

Furthermore, in the present embodiment, the types of gaming states controlled and managed by the main CPU 71 include a “time-saving gaming state” (high winning game state) and a “non-time-saving gaming state” (low winning gaming state) in which the probability of winning a normal symbol (the probability that a normal symbol becomes a “win” mode) differs from each other.

The "time-saving gaming state" referred to in this specification is a gaming state in which the winning probability of normal symbols is high. That is, the ``time-saving game state'' is a game state in which the normal electric accessory 46 (blade member) provided in the second start port 45 is likely to be in an open state (a game state in which the second start port winning is likely to occur), and is an advantageous game state for the player. It should be noted that the "time saving game state" ends when a "jackpot" is determined, or when the variable display of special symbols for a predetermined number of times of time saving described later is executed. In addition, in the time-saving game state, control may be performed so that a variable time shorter than the variable time selected during the normal game state is easily selected as the variable time that is the time for performing variable display of the special symbols executed during the state. With such control, the variation time is shortened in the time-saving game state as compared to the normal game state, and the number of games played per unit time is increased, thereby providing a game state advantageous to the player.

On the other hand, the "non-time-saving (no time-saving) gaming state" is a gaming state in which the winning probability of normal symbols is lower than that of the "time-saving gaming state". Therefore, the "non-time-saving game state" is a game state in which the normal electric accessory 46 (wing member) is unlikely to be in an open state (a game state in which the second start opening prize is unlikely to occur), and is a game state disadvantageous to the player.

In addition, in the present embodiment, game states of various combinations of the above-described game states other than the "big win game state" and the "small win game state" are provided. Specifically, in the present embodiment, a gaming state in which a “probability variable gaming state” and a “time-saving gaming state” occur simultaneously (hereinafter referred to as a “high-probability time-saving state”), and a “probability-variing gaming state” and a “non-time-saving gaming state” occurring at the same time (hereinafter referred to as “no high-probability time-saving” state) are provided. In addition, in the state of "no high probability time saving", it is difficult for the player to determine whether the game state is "probability variable game state", so here, such a game state is also referred to as "latency game state". In addition, in the present embodiment, a game state in which a “normal game state” and a “non-time-saving game state” occur at the same time (hereinafter referred to as “no low-probability time-saving state”), and a “normal game state” and a “time-saving game state” are simultaneously generated (hereinafter referred to as “low-probability time-saving” state).

<Structure of Data Table Stored in Main ROM>
Next, configurations of various data tables stored in the main ROM 72 of the main control circuit 70 will be described with reference to FIGS. 16 to 25. FIG.

[Jackpot random number determination table (at the time of winning the first start)]
First, with reference to FIG. 16, the jackpot random number determination table (at the time of winning the first start opening) will be described. The big hit random number determination table (at the time of winning the first start hole) is a table referred to when determining any one of ``big win'', ``minor win'' and ``losing'' by lottery based on the random number value for big win decision acquired when the game ball enters (wins) the first start hole 44.例文帳に追加

The random number value for judging a big hit is a random number value for judging the result of the lottery performed in the wake of the starting prize, and more specifically, the random number value indicating the lottery result of the special symbols (the first special symbol and the second special symbol). In addition, in this embodiment, the random number for judging a big hit (random number for lottery of special symbols) is selected from 0 to 65535 (65536 types).

In this embodiment, when a game ball wins in the first starting port 44, one of "big win", "minor win" and "loss" is determined by lottery. Therefore, as shown in FIG. 16, the jackpot random number determination table (at the time of winning the first start opening) includes the range of jackpot determination random number values for determining the winning of "big hit", "minor hit" and "loss" for each value of the variable probability flag ("0 (= off)" or "1 (= on)"), and the determination value data corresponding to it ("big hit determination value data", "minor hit determination value data" and "losing determination value data") ”) is specified. The variable probability flag is one of the management flags stored in the main RAM 73, and is a flag for managing whether or not the gaming state is the "variable probability gaming state". When the game state is "probability variable game state", the fixed flag is "1".

In this embodiment, as shown in FIG. 16, when the first starting port 44 wins, if the variable probability flag is ``0'' and the random number for big hit determination is any one of '777' to '943', 'big win' is won and 'big hit determination value data' is determined. That is, the winning probability of the "jackpot" ("selection rate" in FIG. 16) in this case is 167/65536.

In addition, when the probability variable flag is ``0'' and the random number for big win determination is any one of ``1'' to ``300'' when winning the first start port 44, ``small win'' is won and ``small win determination value data'' is determined. That is, the winning probability of the "small hit" in this case is 300/65536.

Further, when the variable probability flag is ``0'' and the random number value for big hit judgment is neither ``1'' to ``300'' nor ``777'' to ``943'' at the time of winning the first starting port 44, ``losing'' is won and ``losing judgment value data'' is determined.

On the other hand, when the probability variable flag is ``1'' and the random number for big win determination is any one of ``777'' to ``1277'' at the time of winning the first starting port 44, ``big win'' is won and ``big win determination value data'' is determined as shown in FIG. That is, the winning probability of the "jackpot" ("selection rate" in FIG. 16) in this case is 500/65536, which is higher than that when the variable probability flag is "0".

In addition, when the probability variation flag is '1' and the random number for big win determination is any one of '1' to '300' when winning the first start port 44, 'small win' is won and 'small win determination value data' is determined. That is, the winning probability of the "small hit" in this case is 300/65536, which is the same as when the variable probability flag is "0".

Further, when the probability variable flag is ``1'' and the random number value for big hit judgment is neither ``1'' to ``300'' nor ``777'' to ``1277'' at the time of winning the first starting port 44, ``losing'' is won and ``losing judgment value data'' is determined.

As described above, in this embodiment, when a game ball wins in the first starting port 44, the selection rate (big hit probability) varies depending on whether the game state at the time of winning is the "probability variable game state". Specifically, when the game state is the ``probability variable game state'', the probability of a big hit when the game ball enters the first starting port 44 is about three times higher than when the game state is not the ``probability variable game state''.

[Jackpot random number determination table (at the time of winning the second start)]
Next, with reference to FIG. 17, the jackpot random number determination table (at the time of winning the second starting opening) will be described. The big hit random number determination table (at the time of winning a prize at the second start port) is a table referred to when performing a lottery as to whether or not there is a "big hit" based on the random number value for big hit determination acquired when the game ball enters (wins) the second start port 45.例文帳に追加

In this embodiment, when a game ball wins the second starting hole 45, either "big win" or "losing" is determined by lottery. In addition, when the game ball wins the second starting hole 45, the "small hit" is not won. Therefore, in the big hit random number determination table (at the time of winning the second start opening), as shown in FIG. 17, for each value of the variable probability flag (“0 (= OFF)” or “1 (= ON)”), the relationship between the range of the jackpot determination random number value for determining the winning of each “big hit” and “loss” and the corresponding determination value data (either “big hit determination value data” or “loss determination value data”) is defined.

In this embodiment, as shown in FIG. 17, when the second starting port 45 wins, if the variable probability flag is ``0'' and the random number value for big hit determination is any one of '777' to '943', 'big win' is won and 'big win determination value data' is determined. That is, the winning probability of the "jackpot" in this case ("selection rate" in FIG. 17) is 167/65536.

In addition, when the variable probability flag is ``0'' and the random number value for big hit judgment is neither ``777'' to ``943'' at the time of winning the second starting port 45, ``losing'' is won and ``losing judgment value data'' is determined.

On the other hand, when the second starting port 45 wins, if the variable probability flag is ``1'' and the random number value for big win determination is any one of ``777'' to ``1277'', as shown in FIG. That is, the winning probability of the "big win" (big win probability) in this case is 500/65536, which is higher than that when the variable probability flag is "0".

When the second start port 45 wins a prize, when the variable probability flag is ``1'' and the random number for big hit determination is neither ``777'' to ``1277'', it becomes ``losing'' and ``losing judgment value data'' is determined.

As described above, in the present embodiment, even when a game ball wins the second starting port 45, the selection rate (big hit probability) varies depending on whether the game state at the time of winning is the "probability variable game state". Specifically, in the same way as when winning the first starting hole 44, when the second starting hole 45 wins a prize, the jackpot probability when the game ball wins in the second starting hole 45 when the game state is the ``probability variable game state'' is about three times higher than that when the game state is not the ``probability variable game state''.

[Symbol Judgment Table (at the time of winning the first start)]
Next, referring to FIG. 18, the symbol determination table (at the time of winning the first start opening) will be described.

In this embodiment, a special symbol is selected based on the winning type (“big hit”, “minor win” or “losing”) of the lottery based on the big hit determination random number value performed when the game ball wins in the first start opening 44 and the symbol random number value (symbol determination random number value) acquired when the first start opening wins. The symbol determination table (at the time of winning the first start opening) is a table referred to when selecting the special symbol. The symbol random number is a random number for determining a special symbol, and is selected from 0 to 99 (100 types) regardless of the lottery winning type based on the big hit determination random number.

As shown in FIG. 18, the symbol determination table (at the time of winning the first start opening) defines the relationship between the symbol designation command ("zA1" to "zA3") for designating a special symbol and the symbol random number value for selecting the symbol designation command for each determination value data indicating the winning type of the lottery based on the random number value for judging the big hit.

When the winning type of the lottery based on the random number for judging the big win is "small win" (small win judging value data), there is one type of pattern designating command (zA2) to be selected, and the pattern designating command (zA2) is always determined. In addition, even when the lottery winning type based on the random number value for judging a big win is ``losing'' (losing judgment value data), only one type of pattern designating command (zA3) is selected, and the pattern designating command (zA3) is always determined.

On the other hand, when the winning type of lottery based on the random number for judging big hit is "big hit" (big hit judging value data), as shown in FIG. 18, there are a plurality of types of special symbols to be selected, and a plurality of kinds ("z0" to "z4") of pattern designation commands (selected pattern commands at the time of big hit in FIG. 18) at the time of "big hit" are prepared. Then, at the time of "big hit", the selected symbol command at the time of big hit determined also changes according to the symbol random number value to be acquired. For example, when the symbol random number obtained at the time of "big win" is any one of "40" to "59", the selection symbol command "z2" at the time of big win is selected, and the selection rate is 20/100.

[Symbol Judgment Table (at the time of winning the second starting gate)]
Next, referring to FIG. 19, the symbol determination table (at the time of winning the second start opening) will be described.

In this embodiment, a special symbol is selected based on the winning type (“big hit” or “losing”) of the lottery based on the random number value for judging the big hit performed when the game ball wins in the second start hole 45 and the random number value for determining the symbol acquired when the second start hole wins. The symbol determination table (at the time of winning the second starting opening) is a table referred to when selecting the special symbol.

As shown in FIG. 19, the symbol determination table (at the time of winning the second start opening) defines the relationship between symbol designation commands ("zA1" and "zA3") for designating a special symbol and the symbol random number value for selecting the symbol designation command for each determination value data indicating the winning type of the lottery based on the random number value for judging the big hit.

Even when the winning type of the lottery based on the random number value for judging the big win is ``losing'' (losing judgment value data), only one type of pattern designation command (zA3) is selected, and the pattern designation command (zA3) is always determined.

On the other hand, when the winning type of lottery based on the random number for judging big hit is "big hit" (big hit judging value data), as shown in FIG. 19, there are a plurality of types of special symbols to be selected, and a plurality of kinds ("z0" and "z4") of the symbol designating commands for "big winning" (selected symbol commands for big winning in FIG. 19) are prepared. Then, at the time of "big hit", the selected symbol command at the time of big hit determined also changes according to the symbol random number value to be acquired. For example, when the symbol random number obtained at the time of "big win" is any one of "29" to "99", the selection symbol command "z4" at the time of big win is selected, and the selection rate is 80/100.

[Jackpot type determination table]
Next, with reference to FIGS. 20 to 23, the jackpot type determination table will be described. In this embodiment, when a symbol selection command (one of 'z0' to 'z4') at the time of big win is determined with reference to a symbol determination table (see FIGS. 18 and 19), the type of 'big win' (contents of the big win game) is determined based on the selected symbol command at the time of big win. The big-hit type determination table is a table referred to when determining the type of "big-hit" (contents of the big-hit game) based on the big-hit selection symbol command.

In addition, in this embodiment, a jackpot type determination table is provided for each game state when a "jackpot" is won. FIG. 20 is a jackpot type determination table (part 1) referred to when a ``jackpot'' is won when the game state is ``no low probability of short working hours'', and FIG. FIG. 22 is a jackpot type determination table (part 3) to be referred to when a ``jackpot'' is won when the game state is ``no high probability of shortening working hours'', and FIG.

Each jackpot type determination table defines the relationship between jackpot selection symbol commands ("z0" to "z4") and various parameters for determining the type of "jackpot". As various parameters for determining the type of "jackpot" (contents of the jackpot game), the value of the time saving flag, the number of times of time saving, the value of the variable probability flag and the number of rounds in the jackpot game are defined.

For example, when a ``jackpot'' is won in the state of ``with high probability and short working hours'', and ``z1'' is determined as a selection pattern command at the time of a big hit, as shown in FIG.

The "number of rounds" defined in each jackpot type determination table is the number of rounds in which the opening time of the jackpot is relatively long in the jackpot game. Further, the "time saving flag" is one of the management flags stored in the main RAM 73, and is a flag for managing whether or not the game state is the "time saving game state". When the game state is the "time saving game state", the time saving flag is "1 (on)". In addition, the "time saving frequency" is the number of variable display of the special symbols given in the "time saving game state".

[Winning effect information determination table]
Next, with reference to FIG. 24, the winning effect information determination table will be described.

In this embodiment, the main control circuit 70 (main CPU 71) determines the information used when the sub-control circuit 200 determines the content of the performance based on the winning type (“big win”, “small win” or “losing”) determined at the time of winning (at the time of winning at the starting gate) and the symbol designation command or the selected symbol command at the time of the big win. For example, in the sub-control circuit 200, the information used when determining the content regarding the color change effect of the reserved symbol indicating the reserved ball of the special symbol, the content regarding the look-ahead effect, etc. is determined. The prize-winning performance information determination table is a table referred to when determining the outline of the performance contents executed by the sub-control circuit 200 based on the information acquired by the main control circuit 70 at the time of prize winning (at the time of starting prize winning).

The relation between the combination of various information determined at the time of winning (at the time of winning at the starting point) and 'performance information 1 at time of winning' and 'performance information 2 at time of winning' showing the outline of the content of performance executed by the sub-control circuit 200 is defined in the determination table of performance information at time of winning. In the present embodiment, as various information determined at the time of winning (at the time of starting winning), the type of starting port, the type of judgment value data, the type of selection symbol command at the time of big hit, and the type of symbol designation command are defined in the winning performance information determination table.

Prize-winning performance information 1 ("1A" to "1D") defined in the prize-winning performance information determination table is performance information mainly used in the sub-control circuit 200 to determine the content of the color change performance of the holding symbol indicating the holding ball of the special symbol. When the sub-control circuit 200 receives the prize-winning performance information 1 determined on the basis of the prize-winning performance information determination table, the sub-control circuit 200 selects one performance pattern from a plurality of types of performance patterns related to the color change performance of the reserved pattern included in the classification of the prize-winning performance information 1.例文帳に追加

Winning performance information 2 (“2A” to “2D”) specified in the winning performance information determination table is performance information mainly used in the sub-control circuit 200 to determine the content of the look-ahead performance (read-ahead continuous performance) based on the reserved ball of the special symbol. When the sub-control circuit 200 receives the prize-winning performance information 2 determined based on the prize-winning performance information determination table, the sub-control circuit 200 selects one performance pattern from a plurality of kinds of performance patterns of the look-ahead performance included in the classification of the prize-winning performance information 2.例文帳に追加

When the winning performance information determination table of the present embodiment is referred to, for example, when a ``jackpot'' is won at the time of winning a first starting opening, ``1A'' is determined as the winning performance information 1, and ``2A'' is determined as the winning performance information 2, regardless of the type of the jackpot selection symbol command.

[Variation production pattern decision table]
Next, with reference to FIG. 25, the variation effect pattern determination table will be described.

In the present embodiment, the main control circuit 70 (main CPU 71) determines the variation performance pattern of the special symbols based on information such as winning type ("big win", "small win" or "losing"), symbol designation command, selection symbol command at the time of big win, variation time, etc., when the variable display of special symbols is started. The variable performance pattern determination table is a table referred to when determining the variable performance pattern of this special symbol.

The variable effect pattern determined based on the variable effect pattern determination table (information included in a special symbol effect start command to be described later) is transmitted from the main control circuit 70 to the sub control circuit 200 (host control circuit 210). Then, when the sub-control circuit 200 receives the information of the variable performance pattern, it determines the type of performance based on the received information such as the variable performance pattern and the game state.

As shown in FIG. 25, the variable performance pattern determination table defines the relationship between the combination of the pattern designation command, the jackpot selection symbol command and the variable time of the special symbols determined at the time of winning (at the time of winning at the starting gate) and the type of performance (fluctuation performance pattern) executed by the sub-control circuit 200 during the variable display of the special symbols.

In this embodiment, the variable performance pattern is represented by two-digit numerical characters, and is represented by a combination of the “upper” (first digit) parameter and the “lower” (second digit) parameter described in the variable performance pattern column in FIG. For example, when the symbol designating command determined at the time of winning (at the time of starting winning) is ``zA1'', the jackpot selection symbol command is ``z0'', and the variation time of the special symbol is ``15000 msec'', the variation performance parameter is ``C1'' (combination of upper ``C'' and lower ``1'').

In addition, in this embodiment, the information of the variable effect parameter is included in the special symbol effect start command which will be described later. At this time, the “upper” parameters and the “lower” parameters defined in the variable effect pattern column are stored in different parameter areas. Therefore, in the variable effect pattern determination table, the "upper" parameter and the "lower" parameter of the variable effect pattern are defined separately.

<Structure of data table stored in sub-main ROM>
Next, configurations of various data tables stored in the sub-main ROM 205 of the sub-control circuit 200 will be described with reference to FIG.

[Variation production table]
First, referring to FIG. 26, the variation effect table will be described.

In the pachinko gaming machine 1 of the present embodiment, as described above, under the control of the sub-control circuit 200 (host control circuit 210), various effects are executed during the variable display of special symbols. The contents of the performance (performance pattern) performed at this time are determined based on the information of the variable performance pattern of the special symbols included in the special symbol performance start command, which will be described later, transmitted from the main control circuit 70 to the sub-control circuit 200 when the variable display of the special symbols is started. The variable effect table is referred to when determining the content of the effect (effect pattern) based on information such as the variable effect pattern and the game state.

As shown in FIG. 26, the variable performance table defines a correspondence relationship between a combination of various information (including variable performance pattern information) determined at the time of winning (at the time of starting prize winning), performance patterns ("EN00" to "EN44") and performance details determined by lottery, and random numbers and selection rates (winning probabilities) for selecting (determining) each performance pattern. In the present embodiment, as various information determined at the time of winning (at the time of winning at the starting point), the types of variable performance patterns of special symbols (“A0” to “A4”, “B1” to “B3” and “C1” to “CF”), the variation time of special symbols, the winning type (“big hit”, “small hit” or “losing”), the symbol designation command and the selection symbol command at the time of big hit are defined in the variation performance table.

In this embodiment, it is assumed that the fluctuation time of the special symbol specified in the fluctuation production table is substantially the same as the production time of the corresponding production pattern. Also, the random number specified in the variable effect table is a random number acquired in the sub lottery process, and is one of "0" to "999" (1000 types).

When the performance pattern is determined by referring to the variable performance table of the present embodiment, for example, when the variation pattern of the special symbols determined at the start of the variable display of the special symbols is 'C1' and the random number obtained when selecting the performance pattern is any value from '0' to '499', 'EN15' is selected as the performance pattern. In this case, an effect called "normal ready-to-win effect A" is performed during the variable display period (15000 msec) of the special symbols. Then, when the "normal ready-to-win effect A" ends, a "big hit" mode is displayed in the display area 13a of the display device 13, and the special symbols stop fluctuating.

<Overview of drawing control method>
Next, an outline of drawing processing executed by the display control circuit 230 when a drawing request is output from the host control circuit 210 to the display control circuit 230 will be described with reference to FIG. FIG. 27 is a diagram showing the flow of image data (moving image data and still image data) during drawing processing.

In this embodiment, data (compressed data) of images (moving and/or still images) to be displayed on the liquid crystal screen of the display device 13 is stored in the CGROM 206 in the CGROM board 204 . When a drawing request is input to the display control circuit 230, the display control circuit 230 first reads compressed image data from the CGROM 206 and decodes (decompresses) it. At this time, when the compressed moving image data is read out, the compressed moving image data is decoded by the moving image decoder 234 in the display control circuit 230, and when the compressed still image data is read out, the still image compressed data is decoded by the still image decoder 235 in the display control circuit 230.

Next, the display control circuit 230 writes the result of decoding the image data (decompressed image data) to a predetermined buffer designated as the texture source. In this embodiment, the movie buffer and texture buffer provided in the SDRAM 250 (external RAM) and the sprite buffer in the built-in VRAM 237 are specified as the texture source. For example, when displaying one moving image, the decompressed moving image data (decoding result) is written to the movie buffer in the SDRAM 250 . Further, for example, when displaying one still image, the decompressed still image data is written to the sprite buffer in the built-in VRAM 237 .

Next, the display control circuit 230 designates a rendering target for writing the rendering (drawing) result of the image data. As a rendering target, for example, a frame buffer provided within the SDRAM 250 (external RAM), a frame buffer provided within the built-in VRAM 237, or the like can be specified.

Next, the display control circuit 230 activates the rendering engine 241 to render the decoding result of the image data written to the texture source, and writes the rendering result to the rendering target. Note that in this processing, rendering processing is performed according to specification information (various types of information input from the 3D geometry engine 240) such as enlargement/reduction and rotation of the moving image.

Next, the display control circuit 230 displays the rendering result (display output data) written to the rendering target on the display screen of the display device 13 .

Note that in this embodiment, two frame buffers are prepared as rendering targets. When writing the rendering result from the rendering engine 241 to the frame buffer, the frame buffer to which the rendering result is written is switched for each frame. For example, when the rendering result is written to one frame buffer in a given frame, the rendering result is written to the other frame buffer in the next frame, and the rendering result is written to one frame buffer in the next frame. That is, in the present embodiment, the process of writing the rendering result to one frame buffer and the process of writing the rendering result to the other frame buffer are alternately switched for each frame.

In addition, in the flow of the rendering result writing process and display process described above, the rendering result written to one frame buffer in a predetermined frame is displayed on the display screen of the display device 13 in the next frame (the function of the one frame buffer is switched from the drawing function to the display function). Also, the rendering result written to the other frame buffer in the next frame is displayed on the display screen of the display device 13 in the next frame (the function of the other frame buffer is switched from the drawing function to the display function). That is, in the present embodiment, the rendering result display processing in one frame buffer and the rendering result display processing in the other frame buffer are alternately switched for each frame.

<Overview of audio playback control method>
Next, referring back to FIG. 8, the outline of the audio reproduction process executed by the audio/LED control circuit 220 when a sound request is output from the host control circuit 210 to the audio/LED control circuit 220 will be described.

In this embodiment, audio data to be output to the speaker 11 is stored in the CGROM 206 . The audio data stored in the CGROM 206 is compressed phrase data specified by a 13-bit long phrase number NUM (000H to 1FFFH), and a maximum of 8192 types (=213) of a series of background music (BGM), a group of dramatic sounds (announcement sounds), etc. are stored corresponding to the phrase numbers NUM. This phrase number NUM is specified by the setting value (operation parameter) of the voice command transmitted from the host control circuit 210 to the command register 225 of the voice/LED control circuit 220 .

The voice command is used for an Individual Write application in which a set value of 1 byte length is transmitted to any one of a large number of voice control registers built into the audio/LED control circuit 220, or in a Block Write application in which a group of N set values is transmitted to a continuous series of N voice control register groups.

In any case, the voice control register to be accessed is specified by a 1-byte long register address, and the storage capacity of each voice control register is 1 byte. In this embodiment, a large number of voice control registers are secured by dividing into seven register banks. That is, since the register bank is divided into 7 sections, the total number of voice control registers is, in principle, 7×256 at maximum.

In this embodiment, in all register banks, a specific register address is a voice control register for register bank setting. Therefore, in order to specify any one of the 7×256 voice control registers, the register bank is written in the voice control register for bank setting by the preceding voice command, and then the voice control register belonging to the register bank is specified by a 1-byte length register address.

By the way, the setting operation of the setting value to the voice control register does not necessarily have to directly specify the register address of the voice control register to be set, and it is also possible to specify the SAC data (Simple Access Code Data) stored in the CGROM 206 or the sequence code (Sequence Code) to complete a series of setting operations for a group of voice control registers. In order to realize such operations, the audio/LED control circuit 220 incorporates four simple access controllers 226a (simple access controllers) and 16 sequencers 226b (sequencers) shown in FIG.

Starting with SAC (Simple Access Code) data for making the simple access controller 226a function, the SAC data means a data group of up to 512 sets (=1024 bytes) in which the register address (1 byte) of the voice control register and the setting value (1 byte) of the voice control register are associated, and is a group terminated with the SAC end code (FFFFH) (see FIG. 8).

In the case of this embodiment, a maximum of 8192 types (=213) of such SAC data can be provided, and the host control circuit 210 can operate the simple access controller 226a by writing the 13-bit length SAC number to the voice control register for SAC control (see FIG. 8). The simple access controller 226a, which has started its function, sequentially reads a group of SAC data specified by the SAC number from the CGROM 206, and sets the set value indicated by the SAC data in the voice control register indicated by the SAC data.

Therefore, the host control circuit 210 only needs to write (register) the SAC number in the voice control register for SAC control, and can instruct a series of setting operations without individually designating the register address of the voice control register. In the voice control register for SAC control, it is possible to set a waiting time (waiting information as attached data) that defines the start timing of a series of setting operations, and it is also possible to delay the start timing of setting to the voice control register by the simple access controller 226a from the timing of writing the SAC number to the voice control register for SAC control.

Next, a sequence code for operating the sequencer 226b will be described. The sequence code, like the SAC data, is a plurality of sets of data in which the register address (1 byte) of the voice control register and the setting value (1 byte) for the voice control register are associated (see FIG. 8). However, unlike the SAC data, the sequence code can define a plurality of intermittently executable operation steps (a plurality of sequence steps) after a predetermined waiting time.

Also, the sequencer control voice control register can contain, for each of the sequencers SQ0 to SQ15, a waiting time (waiting information) that defines the start timing of the setting operation, the presence or absence of the repeating operation, and the number of repetitions (loop information). Therefore, the sequence code specifies a series of voice effects that take a predetermined amount of time to execute.

As shown in FIG. 8, a plurality of operation steps are separated by a step end code (FFFEH), and the end of the plurality of operation steps is terminated by a sequence end code (FFFFH). In the case of this embodiment, a maximum of 8192 types (=213) of sequence codes can be provided, and the host control circuit 210 can instruct the sequencer 226b to perform a series of setting operations by writing a 13-bit sequence code number and ancillary data defining the operation of the sequencer into a voice control register for sequencer control.

In this embodiment, only the necessary sets of such SAC data and sequence codes are stored in advance in the CGROM 206, and a group of SAC data and a group of sequence codes are identified by the SAC number and sequence code number. Therefore, in the case of the present embodiment, the voice commands for write use include not only direct setting operations to the voice control register, but also indirect setting operations via the simple access controller 226a and the sequencer 226b.

In order to realize the above operations, the host control circuit 210 and the audio/LED control circuit 220 are connected by a parallel signal line (data bus) capable of transmitting and receiving 1-byte data, a 2-bit long operation management data line (address bus) capable of transmitting operation management data, a 2-bit long control signal line capable of controlling read/write operations, and a chip select signal line for selecting the audio/LED control circuit 220.

The parallel signal lines are realized by the data bus of the host control circuit 210, and the operation management data lines are realized by the address bus of the host control circuit 210. FIG. The audio/LED control circuit 220 is assigned three port numbers PORT with the upper 6 bits being common and the lower 2 bits being 00, 01, and 10. When the host control circuit 210 executes an I/OREAD instruction or an I/OWRITE instruction for these port numbers PORT, the circuit is configured so that the chip select signal CS becomes active level in any case.

The data output to the lower 2 bits A0 to A1 of the address bus when the I/OREAD instruction or the I/OWRITE instruction is executed becomes the operation control data A0 to A1 for the audio/LED control circuit 220. Based on these 2 bits A0 to A1, it is specified whether the 1-byte data of the data bus at that time is a register address, write data, or read data.

That is, if the address data is [00], the data on the data bus at that timing is evaluated as a register address, and if the address data is [01], the data on the data bus at that timing becomes write data or read data. Note that read data is obtained when the I/OREAD instruction is executed, and write data is obtained when the I/OWRITE instruction is executed.

Therefore, the operation of transmitting a voice command to write a predetermined set value to a predetermined voice control register is realized by continuously executing the I/OWRITE instruction while changing the lower two bits A0 and A1 of the port number PORT of the voice/LED control circuit 220. Specifically, the lower two bits A0 to A1 of the address data are changed from [00] to [01], while the 1-byte data of the data bus is changed from [register address of voice control register] to [write data to voice control register], thereby realizing a predetermined voice command transmission operation.

When the write data is multiple bytes long and the register addresses of the control registers are consecutive, as in the case of transmitting the SAC number (13 bits), the sequence code number (13 bits), and the accompanying control data (standby information, loop information, etc.), the operation management data A0 to A1 of [01] are repeated in the order of [00]→[01]→[01]→[01], and multiple bytes of write data are transmitted.

The voice commands transmitted in this manner are subsequently executed within the voice/LED control circuit 220 as long as there is no communication error. However, if a communication error is recognized, such as data of multiple bytes not matching each other, the voice command will not be executed. Then, the error flag of the voice control register is set, and this error flag (status information STS) can be received by executing the I/OREAD instruction that changes the operation management data A0 to A1 of the address bus from [01] to [10].

Thus, in this embodiment, in the final cycle in which the operation management data A0 to A1 are transitioned from [00]→[01]→ . By retransmitting a voice command that could not be properly parallel-transmitted, the voice effect can be properly advanced. Therefore, according to the configuration of the present embodiment, it is possible to eliminate the unnaturalness of suddenly stopping the sound effect.

On the other hand, the data read operation by the I/OREAD operation is realized by continuously executing the I/OWRITE instruction and the I/OREAD instruction while changing the lower two bits A0 and A1 of the port number PORT of the audio/LED control circuit 220. FIG. If the read data has a length of multiple bytes, the I/OREAD instructions are continued for the required number of bytes.

Specifically, as an I/OWRITE operation, [register address (1 byte length) of voice control register storing operation status etc.] is output to port number PORT where the lower two bits A0 to A1 of the address data are [00]. Next, by executing the I/OREAD instruction for the port number PORT where the low-order two bits A0 to A1 of the address data are [01], necessary data such as operation status can be obtained from a predetermined voice control register.

The audio reproduced by the audio/LED control circuit 220 configured as described above is transmitted to the digital audio power amplifier 262 as a digital audio signal of the audio/LED control circuit 220 in the form of a 5-bit signal (SCLK, LRO, SD0, SD1, SD2), is amplified by the digital audio power amplifier 262, and is supplied to each speaker as an analog audio signal. Specifically, the amplified output (analog audio signal) of the digital audio power amplifier 262 is supplied to the lower speaker for low bass, and the amplified output (analog audio signal) of the digital audio power amplifier 262 is supplied to four normal speakers (for example, see FIG. 9 (L0, R0, L1, R1) and two deep bass (vibration) speakers (for example, see FIG. 9 (SUB0, SUB1)) which are arranged substantially aligned vertically and horizontally with respect to the player.

<Description of the operation of the main control circuit>
Next, contents of various processes executed by the main CPU 71 of the main control circuit 70 will be described with reference to FIGS. 28 to 35. FIG.

[Main control main processing]
First, with reference to FIG. 28, main control main processing controlled by the main CPU 71 will be described. Note that FIG. 28 is a flowchart showing the procedure of the main control main processing in this embodiment.

When the pachinko gaming machine 1 is powered on, first, the main CPU 71 performs initial setting processing (S1). In this processing, the main CPU 71 performs processing such as, for example, permitting access to the main RAM 73, returning from backup, and initializing the work area. Next, the main CPU 71 performs an initial value random number update process (S2). In this process, the main CPU 71 updates the initial random number counter value.

Next, the main CPU 71 performs special symbol control processing (S3). In this processing, the main CPU 71 performs predetermined control processing regarding the progress of the special symbol game and the special symbols (first special symbol and second special symbol) displayed on the special symbol display device 61 . Details of the special symbol control process will be described later with reference to FIG. 29 which will be described later.

Next, the main CPU 71 performs normal symbol control processing (S4). In this process, the main CPU 71 performs a predetermined control process regarding the progress of the normal symbol game and the normal symbols displayed on the normal symbol display device 62.

Next, the main CPU 71 performs control processing of the pattern display device (S5). In this process, the main CPU 71 controls the variable display of special symbols (first special symbol and second special symbol) and normal symbols based on the execution results of the special symbol control process (S3) and the normal symbol control process (S4).

Next, the main CPU 71 performs game information data generation processing (S6). In this process, the main CPU 71 generates game information data to be transmitted to the payout/launch control circuit 123 , the sub-control circuit 200 , the hall computer of the game parlor, etc., and stores the game information data in the main RAM 73 .

Next, the main CPU 71 performs storage/game state data generation processing (S7). In this process, the main CPU 71 generates memory/game state data to be transmitted to the sub-control circuit 200 based on the value of the variable probability flag and the value of the time saving flag, and stores the memory/game state data in the main RAM 73 .

After the process of S7, the main CPU 71 returns the process to the process of S2, and repeats the processes after S2 described above.

[Special symbol control process]
Next, with reference to FIG. 29, the special symbol control processing performed at S3 during the main control main processing (see FIG. 28) will be described. FIG. 29 is a flow chart showing the procedure of the special symbol control process in this embodiment. The numerical values in parentheses (“00” to “08”) written together with the reference numerals of the respective processing steps shown in FIG. The main CPU 71 advances the special symbol game by executing each processing step corresponding to the numerical value of the control state flag.

First, the main CPU 71 loads a control state flag (S11). In this process, the main CPU 71 reads the value of the control state flag stored in the main RAM 73 .

Based on the value of the control state flag loaded in S11, the main CPU 71 determines whether or not to execute various processes of S12 to S20, which will be described later. This control state flag indicates the game state of the special symbol game, and enables execution of any one of the processes of S12 to S20.

Further, the main CPU 71 executes the process of each step at a predetermined timing determined according to the waiting time set for each process of S12 to S20. In addition, during the period before reaching this predetermined timing, other subroutine processing is executed without executing the processing of each step. System timer interrupt processing (see FIG. 33, which will be described later) is also executed at predetermined intervals.

Then, when the process of S11 ends, the main CPU 71 performs a special symbol storage check process (S12).

In this processing, the main CPU 71 checks the reserved number of variable display of special symbols when the control state flag is a value (“00”) indicating special symbol storage check processing, and when the reserved number is not “0” (when there is a reserved ball), performs processing such as hit determination, determination of special symbols, and determination of variation pattern of special symbols. Also, in this process, the main CPU 71 sets the control state flag to a value ("01") indicating the special symbol variation time management process (S13) described later, and sets the special symbol variation time corresponding to the variation pattern determined in this process to the waiting time timer. That is, by this process, after the special symbol variation time corresponding to the variation pattern determined in the process of S12 has elapsed, the special symbol variation time management process, which will be described later, is set to be executed.

On the other hand, when the number of reserved balls is "0" (when there are no reserved balls), the main CPU 71 performs demonstration display processing for displaying a demonstration screen. The details of the special symbol storage check process will be described later with reference to FIG. 30 which will be described later.

Next, the main CPU 71 performs special symbol variation time management processing (S13). In this process, the main CPU 71 sets the control state flag to a value (“02”) indicating a special symbol display time management process (S14) described later when the control state flag is a value (“01”) indicating the special symbol variation time management process and the special symbol variation time has elapsed, and sets the waiting time after determination to the waiting time timer. That is, by this process, after the waiting time after confirmation set in the process of S13 has passed, the special symbol display time management process, which will be described later, is set to be executed.

Next, the main CPU 71 performs special symbol display time management processing (S14). In this process, the main CPU 71 determines whether the result of the hit determination is a ``big win'' or a ``minor win'' when the control state flag is a value ("02") indicating the special symbol display time management process and the waiting time set in the process of S13 has passed. Then, when the result of the hit determination is ``big win'' or ``minor win'', the main CPU 71 sets a control state flag to a value ("03") indicating a big win start interval management process (S15) described later, and sets a time corresponding to the big win start interval to a waiting time timer. That is, by this process, after the time corresponding to the big-hit start interval set in the process of S14 has passed, the later-described big-hit start interval management process is set to be executed.

On the other hand, if the result of the hit determination is neither a "big win" nor a "minor win", the main CPU 71 sets the control state flag to a value ("08") indicating a special symbol game ending process (S20), which will be described later. That is, in this case, it is set to execute a special symbol game ending process, which will be described later. The details of the special symbol display time management process will be described later with reference to FIG. 31 which will be described later.

Next, the main CPU 71 performs a big win start interval management process (S15) when the result of the win determination is determined to be a "big win" or a "minor win" in S14. In this process, the main CPU 71 updates the variables located in the main RAM 73 based on the data read out from the main ROM 72 in order to open the first big win opening 53 or the second big winning opening 54 when the control state flag is a value ("03") indicating the big win start interval management process and the time corresponding to the big win start interval set in the process of S14 has passed.

Further, in this process, the main CPU 71 sets a control state flag to a value (“04”) indicating a process during the opening of the big winning opening (S16) described later, and sets the opening upper limit time (for example, 30 seconds) of the big winning opening to the big winning opening opening time timer. That is, by this process, a setting is made so that the later-described process during the opening of the big winning opening is executed.

Next, the main CPU 71 performs processing during the opening of the big winning opening (S16). In this process, first, when the control state flag is a value (“04”) indicating the processing during the opening of the large winning opening, the main CPU 71 determines whether or not one of the condition that the large winning opening winning counter is equal to or greater than a predetermined number and the condition that the opening upper limit time has passed (the large winning opening opening time timer is “0”) is satisfied (predetermined closing condition is established).

In S16, when one of the conditions is satisfied, the main CPU 71 updates the variables positioned in the main RAM 73 in order to close the predetermined big winning opening (first big winning opening or second big winning opening). Then, the main CPU 71 sets the control state flag to a value (“05”) indicative of the remaining ball in the big winning opening monitoring process (S17) described later, and sets the waiting time timer to monitor the remaining balls in the big winning opening. That is, according to this process, after the time for monitoring the remaining balls in the big winning hole set in S17 has elapsed, the process for monitoring remaining balls in the big winning hole, which will be described later, is set to be executed.

In S16, the main CPU 71 also transmits an inter-round display command to the sub-control circuit 200 immediately before the end of the process during the opening of the big winning opening.

Next, the main CPU 71 carries out a process of monitoring remaining balls in the big winning opening (S17). In this process, the main CPU 71 determines whether or not the condition that the control state flag has a value ("05") indicating the remaining ball inside the big winning opening monitoring process and the value of the large winning opening opening frequency counter is equal to or greater than the maximum value of the number of opening times of the big winning opening when the monitoring time of the remaining balls inside the big winning opening has passed (it is the final round) is met.

In S17, when the main CPU 71 determines that the above condition is not satisfied, the main CPU 71 sets a value ("06") indicating the waiting time management process for reopening the big winning opening to the control state flag. Also, the main CPU 71 sets a waiting time timer to a time corresponding to the interval between rounds. That is, by this process, after the time corresponding to the interval between rounds has passed, the waiting time management process before reopening the big winning opening, which will be described later, is set to be executed.

On the other hand, in S17, when the main CPU 71 determines that the above conditions are satisfied, the main CPU 71 sets a control state flag to a value ("07") indicating a big win end interval process, and sets a time corresponding to the big win end interval (big win end interval time) to a waiting time timer. That is, by this process, after the time corresponding to the big-hit end interval set in S17 has passed, the later-described big-hit end interval process is set to be executed.

Next, in S17, when the main CPU 71 determines that the value of the large winning opening opening number counter is not equal to or greater than the maximum value of the large winning opening opening number, the main CPU 71 performs waiting time management processing before reopening the large winning opening (S18). In this process, the main CPU 71 stores and updates the value of the counter for the number of openings of the big winning opening to increase "1" when the control state flag is a value ("06") indicating the waiting time management process before reopening the big winning opening and the time corresponding to the interval between rounds has passed. In addition, the main CPU 71 sets a control state flag to a value (“04”) indicating processing during the opening of the big winning opening. Then, the main CPU 71 sets the opening upper limit time (for example, 30 sec) to the big winning opening opening time timer. That is, by this process, after the process of S18, the above-described process during opening of the big winning opening (S16) is set to be executed again.

Furthermore, in S18, the main CPU 71 transmits a command for displaying during opening of the big winning gate to the sub control circuit 200 immediately before the end of the waiting time management process before reopening the big winning gate.

Also, in S17, when the main CPU 71 determines that the value of the large winning opening opening number counter is equal to or greater than the maximum value of the large winning opening opening number, a jackpot ending interval process is performed (S19). In this process, the main CPU 71 sets the control state flag to a value ("08") indicating special symbol game end processing when the control state flag is a value ("07") indicating the big win end interval process and the time corresponding to the big win end interval has passed. That is, by this process, it is set so that the special symbol game end process, which will be described later, is executed after the process of S19. Details of the jackpot end interval processing will be described later with reference to FIG. 32 which will be described later.

Then, the main CPU 71 performs control to shift the game state to the probability variable game state when the big win pattern is the probability variable pattern, and performs control to shift the game state to the normal game state when the big win pattern is the non-probability variable pattern. When the big win pattern is a pattern corresponding to the "small win", the main CPU 71 controls the game state after the "small win" game is finished so as not to shift to a game state more advantageous than the game state controlled when the "small win" is won.

Next, when the big win game state or the small win game state ends, or when the "lost" is won, the main CPU 71 performs special symbol game end processing (S20).

In this process, when the control state flag is a value ("08") indicating the end of the special symbol game, the main CPU 71 stores and updates the data indicating the pending number (start memory information) so as to decrease it by "1". In addition, the main CPU 71 updates the special symbol storage area in order to display the next special symbol in a variable manner. Furthermore, the main CPU 71 sets a control state flag to a value (“00”) indicating special symbol storage check processing. That is, by this process, after the process of S20, the special symbol storage check process (S12) described above is set to be executed.

After the processing of S20, the main CPU 71 ends the special symbol control processing and shifts the processing to S4 of the main control main processing (see FIG. 28).

As described above, in the pachinko gaming machine 1 of the present embodiment, the special symbol game is advanced by sequentially setting various values to the control state flags. Specifically, when the game state is neither the big win game state nor the small win game state and the result of the win determination is ``losing'', the main CPU 71 sets the control state flag in order of ``00'', ``01'', ``02'' and ``08''. As a result, the main CPU 71 executes the special symbol storage check process (S12), the special symbol variation time management process (S13), the special symbol display time management process (S14), and the special symbol game end process (S20) in this order at a predetermined timing.

In addition, when the game state is neither the big winning game state nor the small winning game state and the result of judgment of winning is ``big winning'' or ``small winning'', the main CPU 71 sets the control status flags in order of ``00'', ``01'', ``02'' and ``03''. As a result, the main CPU 71 executes the above-described special symbol storage check process (S12), special symbol variation time management process (S13), special symbol display time management process (S14), and big win start interval management process (S15) in this order at predetermined timings, and executes transition control to the big win game state or the small win game state.

Furthermore, the main CPU 71 sets the control state flags to "04", "05" and "06" in this order when the transition control to the big win game state or the small win game state is executed. As a result, the main CPU 71 executes the processing during opening of the big winning prize (S16), the process of monitoring the remaining balls in the big winning prize (S17), and the waiting time management processing before reopening the big winning prize (S18) in this order at predetermined timings to execute the big winning game or the small winning game.

It should be noted that when the conditions for ending the jackpot game state are established during the jackpot game, the main CPU 71 sets the control state flags in the order of "04", "05", "07" and "08". As a result, the main CPU 71 executes the above-described process for opening the big winning opening (S16), the process for monitoring the remaining balls in the big winning opening (S17), the interval process for finishing the big winning game (S19) and the finishing process for the special symbol game (S20) in this order at predetermined timings, and ends the big winning game state.

As described above, in the special symbol control process, the process flow is branched according to the status. In addition, the normal symbol control process of S4 during the main control main process shown in FIG. 28 also branches the process flow according to the status, similar to the special symbol control process, as will be described later.

The processing program of this embodiment is programmed so that when the processing is branched according to the status, pure return processing from the small module to the parent module is possible with a call instruction. As a result, in this embodiment, the program capacity can be reduced compared to the case where a jump table is arranged for executing the above process.

[Special symbol memory check process]
Next, with reference to FIG. 30, the special symbol storage check process performed at S12 during the special symbol control process (see FIG. 29) will be described. Incidentally, FIG. 30 is a flow chart showing the procedure of the special symbol storage check process in this embodiment.

First, the main CPU 71 loads a control state flag (S31). In this process, the main CPU 71 reads the value of the control state flag stored in the main RAM 73 .

Next, the main CPU 71 determines whether or not the control state flag is a value (“00”) indicating special symbol storage check processing (S32). In S32, when the main CPU 71 determines that the control state flag is not "00" (NO determination in S32), the main CPU 71 ends the special symbol storage check process and returns the process to the special symbol control process (see FIG. 29).

On the other hand, when the main CPU 71 determines in S32 that the control state flag is "00" (when S32 determines YES), the main CPU 71 determines whether or not the number of pending second start winnings (variable display of the second special symbol) (second start memory number) is "0" (S33).

In S33, when the main CPU 71 determines that the number of reserved second starting opening prizes is not "0" (NO determination in S33), the main CPU 71 subtracts "1" from the value of the second start memory number corresponding to the number of reserved second starting opening prizes (S34).

In this embodiment, the main CPU 71 discriminates whether or not data is stored in the second special symbol start storage area (0) to the second special symbol start storage area (4) provided in the main RAM 73, and determines whether or not there is a start memory of the special symbol game corresponding to the variable display of the second special symbol being changed or held. In the second special symbol start memory area (0), data (information) of the special symbol game corresponding to the variable display of the second special symbol during variation is stored as start memory. In the second special symbol start storage area (1) to the second special symbol start storage area (4), the data (information) of the special symbol game corresponding to the variable display (reserved ball) of the second special symbol for four reserved times is stored as the start memory. The data included in the starting memory stored in each second special symbol starting memory area is, for example, data such as the big hit determination random number value and the big winning design random number value obtained when the second start opening 45 is won.

After the process of S34, the main CPU 71 performs a special symbol storage transfer process based on the second start opening winning (S35). In this process, the main CPU 71 transfers (stores) the data in the second special symbol start storage areas (1) to (4) to the second special symbol start storage areas (0) to (3) respectively. After the process of S35, the main CPU 71 performs the process of S40, which will be described later.

Here, returning to the processing of S33 again, when the main CPU 71 determines in S33 that the number of pending second starting opening prizes is "0" (if the determination is YES in S33), the main CPU 71 determines whether or not the number of pending first starting opening prizes (variable display of the first special symbol) (first start memory number) is "0" (S36).

In S36, when the main CPU 71 determines that the number of pending first starting opening prizes is "0" (YES in S36), the main CPU 71 performs a demonstration display process (S37). Then, after the process of S37, the main CPU 71 ends the special symbol storage check process, and returns the process to the special symbol control process (see FIG. 29).

It should be noted that the main CPU 71 sets a demonstration display permission value in the main RAM 73 in the demonstration display process of S<b>37 . That is, when the state in which the number of reserved first start winning prizes and second starting winning prizes has become "0" (the state in which the start memory of the special symbol game has become "0") is maintained for a predetermined time (for example, 30 sec), the main CPU 71 sets a predetermined value as a demonstration display permission value. Further, when the demonstration display permission value is the predetermined value in the demonstration display processing of S<b>37 , the main CPU 71 sets demonstration display command data in the main RAM 73 . The demonstration display command data is transmitted from the main CPU 71 of the main control circuit 70 to the host control circuit 210 within the sub control circuit 200 . Upon receiving the demonstration display command data, the sub-control circuit 200 causes the display area 13a of the display device 13 to display the demonstration screen.

On the other hand, when the main CPU 71 determines in S36 that the number of reserved first starting opening prizes is not "0" (NO determination in S36), the main CPU 71 subtracts "1" from the value of the first start memory number corresponding to the number of reserved first starting opening prizes (S38).

In this embodiment, the main CPU 71 discriminates whether or not data is stored in the first special symbol start storage area (0) to the first special symbol start storage area (4) provided in the main RAM 73, and determines whether or not there is a start memory of the special symbol game corresponding to the variable display of the first special symbol being changed or held. In the first special symbol start memory area (0), data (information) of the special symbol game corresponding to the variable display of the first special symbol during fluctuation is stored as start memory. In the first special symbol start storage area (1) to the first special symbol start storage area (4), the data (information) of the special symbol game corresponding to the variable display (retained ball) of the first special symbol for four reserved times is stored as the start memory. The data included in the starting memory stored in each first special symbol starting memory area is, for example, data such as the big hit determination random number value and the big winning symbol random number value obtained when the first starting port 44 is won.

After the process of S38, the main CPU 71 performs a special symbol storage transfer process based on the first start opening winning (S39). In this process, the main CPU 71 transfers (stores) the data in the first special symbol start storage areas (1) to (4) to the first special symbol start storage areas (0) to (3) respectively. After the process of S39, the main CPU 71 performs the process of S40, which will be described later.

After the process of S35 or S39, the main CPU 71 determines whether or not the value of the time saving state variation counter is "0" (S40).

In S40, when the main CPU 71 determines that the value of the time saving state variation counter is "0" (when S40 determines YES), the main CPU 71 performs the processing of S44, which will be described later. On the other hand, in S40, when the main CPU 71 determines that the value of the time saving state change counter is not "0" (NO determination in S40), the main CPU 71 subtracts "1" from the time saving state change counter (S41).

After the processing of S41, the main CPU 71 determines whether or not the value of the time saving state variation counter is "0" (S42).

In S42, when the main CPU 71 determines that the value of the time saving state variation counter is not "0" (NO determination in S42), the main CPU 71 performs the processing of S44, which will be described later. On the other hand, when the main CPU 71 determines in S42 that the value of the time saving state variation counter is "0" (when S42 determines YES), the main CPU 71 sets the time saving flag to "0" (S43).

After the process of S43, if the determination is YES in S40 or if the determination is NO in S42, the main CPU 71 sets the control state flag to a value ("01") indicating the special symbol variation time management process (S44). Also, in this process, the main CPU 71 transmits a pending subtraction command and a special symbol effect start command to the sub control circuit 200 .

Next, the main CPU 71 performs big hit determination processing (S45). In this processing, the main CPU 71 judges (determines) which of the "big win", "minor win" and "losing" is won by lottery based on the big win determination random number value acquired at the time of winning the starting prize.

Next, the main CPU 71 clears the information (data) in the storage area used for the previous variable display (S46). Next, the main CPU 71 sets the variation time corresponding to the determined special symbol variation pattern in the waiting time timer (S47). Then, after the process of S47, the main CPU 71 ends the special symbol storage check process and returns the process to the special symbol control process (see FIG. 29).

[Special symbol display time management process]
Next, with reference to FIG. 31, the special symbol display time management process performed at S14 during the special symbol control process (see FIG. 29) will be described. Incidentally, FIG. 31 is a flow chart showing the procedure of the special symbol display time management process in this embodiment.

First, the main CPU 71 determines whether or not the control state flag is a value (“02”) indicating special symbol display time management processing (S51). In S51, when the main CPU 71 determines that the control state flag is not the value (“02”) indicating the special symbol display time management process (when S51 determines NO), the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol display time management process (see FIG. 29).

On the other hand, when the main CPU 71 determines in S51 that the control state flag is the value (“02”) indicating the special symbol display time management process (when S51 determines YES), the main CPU 71 determines whether or not the value (waiting time) of the waiting time timer is “0” (S52). In this process, the main CPU 71 determines whether or not the waiting time (variation start waiting time) set in the waiting time timer after the change has been determined has expired.

In S52, when the main CPU 71 determines that the value of the waiting time timer is not "0" (NO determination in S52), the main CPU 71 terminates the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29). On the other hand, when the main CPU 71 determines in S52 that the value of the waiting time timer is "0" (YES in S52), the main CPU 71 determines whether or not the special symbol game is a "jackpot" (S53). Also, in this process, the main CPU 71 simultaneously transmits a special effect stop command to the sub control circuit 200 .

In S53, when the main CPU 71 determines that the special symbol game is not a "jackpot" (when S53 determines NO), the main CPU 71 sets the control state flag to a value ("08") indicating special symbol game end processing (S54). After the process of S54, the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29).

On the other hand, when the main CPU 71 determines in S53 that the special symbol game is a "jackpot" (if YES in S53), the main CPU 71 sets the jackpot flag to the ON state (S55). Incidentally, the jackpot flag is a flag indicating whether or not to play a jackpot game.

Next, the main CPU 71 clears the value of the time saving state variation count counter, the value of the time saving flag, and the value of the probability variation flag (S56). Next, the main CPU 71 sets the control state flag to a value (“03”) indicating the jackpot start interval management process (S57).

Next, the main CPU 71 sets the jackpot start interval time (for example, 5000 msec) corresponding to the special symbol (first special symbol or second special symbol) in the waiting time timer (S58). Next, the main CPU 71 sets a jackpot start command (special symbol winning start display command) corresponding to the special symbol in the main RAM 73 (S59). Also, in this process, the main CPU 71 simultaneously transmits a special symbol winning start display command to the sub-control circuit 200 .

Next, the main CPU 71 sets the round number display LED pattern flag to the ON state (S60). The number-of-rounds display LED pattern flag is a flag indicating whether to display the number of remaining rounds in a predetermined pattern. After the process of S60, the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29).

[Jackpot end interval processing]
Next, with reference to FIG. 32, the jackpot end interval processing performed at S19 during the special symbol control processing (see FIG. 29) will be described. In addition, FIG. 32 is a flowchart which shows the procedure of the jackpot end interval processing in this embodiment.

First, the main CPU 71 determines whether or not the control state flag is a value (“07”) indicating the jackpot end interval processing (S71).

In S71, when the main CPU 71 determines that the control state flag is not the value (“07”) indicating the jackpot end interval processing (when S71 determines NO), the main CPU 71 ends the jackpot end interval processing and returns the processing to the special symbol control processing (see FIG. 29). On the other hand, when the main CPU 71 determines in S71 that the control state flag is the value (“07”) indicating the jackpot end interval processing (when S71 determines YES), the main CPU 71 determines whether the value of the waiting time timer is “0” (S72). In this process, the main CPU 71 determines whether or not the jackpot end interval time set in the waiting time timer has expired.

In S72, when the main CPU 71 determines that the value of the waiting time timer is not "0" (NO determination in S72), the main CPU 71 ends the jackpot end interval processing and returns the processing to the special symbol control processing (see FIG. 29). On the other hand, when the main CPU 71 determines in S72 that the value of the waiting time timer is "0" (when the determination in S72 is YES), the main CPU 71 clears the large winning opening opening number display LED pattern flag (S73).

Next, the main CPU 71 clears the round number distribution flag (sets it to "0") (S74).

Next, the main CPU 71 sets a control state flag to a value (“08”) indicating special symbol game end processing (S75). Also, in this process, the main CPU 71 simultaneously transmits a special symbol per end display command to the sub-control circuit 200 . Next, the main CPU 71 clears the jackpot flag (S76).

Next, the main CPU 71 refers to the jackpot type determination table (see FIGS. 20 to 23), and sets the value of the probability variation flag based on the game state when the jackpot is won and the type of the jackpot selection symbol command (S77). Next, the main CPU 71 refers to the jackpot type determination table (see FIGS. 20 to 23), and sets the value of the time saving flag based on the game state when the jackpot is won and the type of the jackpot selection symbol command (S78).

Next, the main CPU 71 determines whether or not the value of the time saving flag is "1" (whether the time saving flag is on) (S79). In S79, when the main CPU 71 determines that the value of the time saving flag is not "1" (NO determination in S79), the main CPU 71 terminates the jackpot end interval process and returns the process to the special symbol control process (see FIG. 29).

On the other hand, in S79, when the main CPU 71 determines that the value of the time saving flag is "1" (when S79 determines YES), the main CPU 71 refers to the jackpot type determination table (see FIGS. 20 to 23), and sets the corresponding value of the number of times of time saving to the time saving state variation count counter based on the game state when the big win is won and the type of the selection symbol command when the big win is won (S80). After the processing of S80, the main CPU 71 ends the jackpot end interval processing and returns the processing to the special symbol control processing (see FIG. 29).

[System timer interrupt processing]
In the pachinko gaming machine 1 of the present embodiment, the main CPU 71 interrupts the main processing at predetermined intervals and executes system timer interrupt processing even during execution of the main processing. Specifically, the main CPU 71 executes system timer interrupt processing according to clock pulses generated from the clock generation circuit 74 at predetermined intervals (for example, 2 msec). Here, system timer interrupt processing executed by the main CPU 71 will be described with reference to FIG. FIG. 33 is a flow chart showing the procedure of system timer interrupt processing in this embodiment.

First, the main CPU 71 saves data (information) of each register (S121). Next, the main CPU 71 performs random number update processing (S122). In this process, the main CPU 71 updates various random numbers extracted from a big hit determination counter, a symbol determination counter, a hit determination counter, a fall determination counter, a variation pattern determination counter, an effect pattern determination counter, and the like. It should be noted that the big hit determination counter and the symbol determination counter lack fairness if the timing of updating the counter value is uncertain. Therefore, the big-hit determination counter and the pattern determination counter are updated at timing determined in a cycle of 2 msec in order to ensure fairness.

Next, the main CPU 71 performs switch input detection processing (S123). In this process, the main CPU 71 detects winning or passing through various starting ports, various winning ports, and the ball passage detector 43 . Details of the switch input detection process will be described later with reference to FIG. 34 described later.

Next, the main CPU 71 performs timer update processing (S124). Specifically, the main CPU 71 updates various timers such as a waiting time timer for synchronizing the main control circuit 70 and the sub-control circuit 200, and a large winning opening opening time timer for measuring the opening time of the large winning opening.

Next, the main CPU 71 performs command output processing (S125). In this process, the main CPU 71 outputs various commands such as winning commands and variation commands to the host control circuit 210 of the sub control circuit 200 .

Next, the main CPU 71 performs game information output processing (S126). In this process, the main CPU 71 outputs various information related to the game processed by the main control circuit 70, the sub-control circuit 200, the payout/shooting control circuit 123, etc. to the hall computer of the amusement arcade.

Next, the main CPU 71 restores the data of each register saved in S121 (S127). After the process of S127, the main CPU 71 terminates the system timer interrupt process.

[Switch input detection processing]
Next, with reference to FIG. 34, switch input detection processing performed at S123 in the system timer interrupt processing (see FIG. 33) will be described. FIG. 34 is a flow chart showing the procedure of switch input detection processing in this embodiment.

First, the main CPU 71 performs start-up winning detection processing (S131). In this process, the main CPU 71 determines whether or not a game ball has entered (passed through) the first starting hole 44 or the second starting hole 45 . That is, the main CPU 71 detects whether the winning of the game ball is detected by the first starting opening winning ball sensor 44a or the second starting opening winning ball sensor 45a. The details of the start opening winning detection process will be described later with reference to FIG. 35 which will be described later.

Next, the main CPU 71 performs general winning hole passage detection processing (S132). In this process, the main CPU 71 determines whether or not a game ball has entered the general winning hole 51 or 52 . That is, the main CPU 71 detects whether or not the general winning ball sensor 51a or 52a detects the winning of the game ball. When the winning of the game ball into the general winning opening 51 or 52 is detected, the main CPU 71 performs various predetermined processes corresponding to the winning.

Next, the main CPU 71 performs a special winning opening passage detection process (S133). In this process, the main CPU 71 determines whether or not a game ball has entered the first big winning hole 53 or the second big winning hole 54 . That is, the main CPU 71 detects whether or not the winning of the game ball is detected by the first big winning opening solenoid 53b or the second big winning opening solenoid 54b. When the winning of the game ball into the first big winning hole 53 or the second big winning hole 54 is detected, the main CPU 71 performs various predetermined processes corresponding to the winning.

Next, the main CPU 71 performs gate passage detection processing (S134). In this process, the main CPU 71 determines whether or not the game ball has passed through the ball passage detector 43 . That is, the main CPU 71 detects whether or not the passing of the game ball is detected by the passing ball sensor 43a. Next, when it is detected that the game ball has passed through the ball passage detector 43, the main CPU 71 performs various predetermined processes corresponding to the passage. After the process of S134, the main CPU 71 ends the switch input detection process, and shifts the process to S124 of the system timer interrupt process (see FIG. 33).

[Starting gate winning detection process]
Next, with reference to FIG. 35, the start opening winning detection process performed at S131 in the switch input detection process (see FIG. 34) will be described. Note that FIG. 34 is a flow chart showing the procedure of the start opening winning detection process in this embodiment.

First, the main CPU 71 determines whether or not winning of a game ball into the first starting hole 44 is detected based on the output signal of the first starting hole winning ball sensor 44a (S141).

When the main CPU 71 determines in S141 that the winning of the game ball into the first starting port 44 is not detected (NO determination in S141), the main CPU 71 performs the processing of S149 which will be described later. On the other hand, when the main CPU 71 determines in S141 that the game ball has entered the first start hole 44 and has detected the winning (S141 is YES), the main CPU 71 sets payout information corresponding to the first start hole win in the main RAM 73 (S142). In this embodiment, when a game ball wins the first starting hole 44, a predetermined number of game balls are paid out. Therefore, in the process of S142, payout information for a predetermined number of game balls is set.

After the processing of S142, the main CPU 71 determines whether or not the number of reserved balls (the number of reserved balls) for the first starting opening winning prize (variable display of the first special symbol) is less than "4" (S143).

In S143, when the main CPU 71 determines that the number of pending first start opening prizes is not less than "4" (NO determination in S143), the main CPU 71 performs the processing of S149, which will be described later. On the other hand, when the main CPU 71 determines in S143 that the number of reserved first starting opening prizes is less than "4" (if the determination is YES in S143), the main CPU 71 performs processing to add "1" to the number of reserved first starting opening prizes (S144).

After the processing of S144, the main CPU 71 acquires various random numbers used for the lottery, and stores the acquired various random numbers in a predetermined area of the main RAM 73 (S145). Specifically, the main CPU 71 acquires various random numbers such as a jackpot determination random number, a symbol random number, and a fall determination random number.

Next, the main CPU 71 performs a first special stop symbol determination process (S146). In this process, the main CPU 71 refers to the jackpot random number determination table (first start port) (see FIG. 16) and the symbol determination table (first start port) (see FIG. 18), and based on the jackpot determination random number value and the symbol random value acquired in S145, determines whether or not it is a "jackpot". judgment).

Next, the main CPU 71 performs a process of determining whether or not there is a fall (S147). In this process, the main CPU 71 performs a fall lottery based on the fall determination random number value acquired in S145, and determines whether or not a fall has occurred. Thereby, the main CPU 71 acquires drop lottery information (“0”: no drop, or “1”: drop).

Next, the main CPU 71 sets the pending addition command data at the time of winning the first starting opening in the main RAM 73 (S148).

In this process, the main CPU 71 refers to the jackpot random number determination table (first start port) (see FIG. 16), the symbol determination table (first start port) (see FIG. 18), the jackpot type determination table (see FIGS. 20 to 23), and the prize effect information determination table (see FIG. 24), which are obtained by referring to the game state (“normal”, “probability”, “short time”), winning type (“big win”, “minor win”, “losing”). ), the start memory number (the number of reserved first special patterns), the pattern designation command, the selection pattern command at the time of big win, the performance information at the time of winning, the result information of judgment of big win, the drop lottery information, etc., the information (transmission contents) to be included in the reserve addition command is determined.

At this time, the game state is obtained by referring to the values of the variable probability flag and the time saving flag, the winning type is obtained by referring to the big hit random number determination table (first start port) (see FIG. 16), the symbol designation command and the selection symbol command at the time of the big hit are obtained by referring to the symbol determination table (first start port) (see FIG. 18), and the winning effect information is obtained by referring to the winning effect information determination table (see FIG. 24). . Also, the big hit determination result information is acquired in the process of S146, and the falling lottery information is acquired in the process of S147.

Further, in the present embodiment, in the processing of S148, the pending addition command at the time of winning the first start opening is transmitted from the main CPU 71 to the sub control circuit 200 (host control circuit 210). Then, based on the pending addition command at the time of winning the first start opening, the sub-control circuit 200 selects the effect pattern of the pending effect and the look-ahead effect.

After the processing of S148, or when the determination in S141 or S143 is NO, the main CPU 71 determines whether or not the winning of the game ball into the second starting hole 45 is detected based on the output signal of the second starting hole winning ball sensor 45a (S149).

In S149, when the main CPU 71 determines that the winning of the game ball into the second starting hole 45 is not detected (NO determination in S149), the main CPU 71 ends the starting hole winning detection process, and shifts the process to S132 of the switch input detection process (see FIG. 34). On the other hand, when the main CPU 71 determines in S149 that the winning of the game ball into the second starting hole 45 has been detected (YES in S149), the main CPU 71 sets payout information corresponding to the winning of the second starting hole in the main RAM 73 (S150). In this embodiment, when a game ball wins the second starting hole 45, a predetermined number of game balls are paid out. Therefore, in the process of S150, payout information for a predetermined number of game balls is set.

After the processing of S150, the main CPU 71 determines whether or not the number of reserved balls (the number of reserved balls) of the second starting opening winning prize (variable display of the second special symbol) is less than "4" (S151).

In S151, when the main CPU 71 determines that the number of pending second starting opening prizes is not less than "4" (NO determination in S151), the main CPU 71 ends the starting opening winning detection processing, and shifts the processing to S132 of the switch input detection processing (see FIG. 34). On the other hand, when the main CPU 71 determines in S151 that the number of pending second starting opening prizes is less than "4" (if the determination is YES in S151), the main CPU 71 performs a process of adding "1" to the number of pending second starting opening prizes (S152). After the process of S152, the main CPU 71 acquires various random numbers used for the lottery, and stores the acquired various random numbers in a predetermined area of the main RAM 73 (S153). Specifically, the main CPU 71 acquires various random numbers such as a jackpot determination random number, a symbol random number, and a fall determination random number.

Next, the main CPU 71 performs a second special stop symbol determination process (S154). In this process, the main CPU 71 refers to the big-hit random number determination table (second starting port) (see FIG. 17) and the symbol determination table (second starting port) (see FIG. 19), and determines whether or not it is a "big win" based on the big-hit determination random number value and the symbol random number value acquired in S153. do

Next, the main CPU 71 performs a process of determining whether or not there is a fall (S155). In this process, the main CPU 71 performs a drop lottery based on the fall determination random number value acquired in S153, and determines whether or not a fall has occurred. Thereby, the main CPU 71 acquires drop lottery information (“0”: no drop, or “1”: drop).

Next, the main CPU 71 sets the pending addition command data at the time of winning the second starting opening in the main RAM 73 (S156).

In this process, the main CPU 71 obtains by referring to a jackpot random number determination table (second start port) (see FIG. 17), a pattern determination table (second start port) (see FIG. 19), a jackpot type determination table (see FIGS. 20 to 23), and a prize-winning effect information determination table (see FIG. 24). Information (transmission content) to be included in the reserved addition command is determined based on information such as the reserved number of second special patterns), pattern designation command, selection pattern command at the time of big win, presentation information at the time of prize winning, result information of judgment of big win, falling lottery information, etc.

At this time, the game state is obtained by referring to the values of the variable probability flag and the time saving flag, the winning type is obtained by referring to the jackpot random number determination table (second starting port) (see FIG. 17), the symbol designation command and the jackpot selection symbol command are obtained by referring to the symbol determination table (second starting port) (see FIG. 19), and the winning effect information is obtained by referring to the winning effect information determination table (see FIG. 24). . Also, the big hit determination result information is acquired in the process of S154, and the falling lottery information is acquired in the process of S155.

Further, in the present embodiment, in the processing of S156, the pending addition command at the time of winning the second start opening is transmitted from the main CPU 71 to the sub control circuit 200 (host control circuit 210). The sub-control circuit 200 selects the effect pattern of the pending effect and the look-ahead effect based on the pending addition command at the time of winning the second start opening. After the process of S156, the main CPU 71 ends the start opening winning detection process, and shifts the process to S132 of the switch input detection process (see FIG. 34).

<Description of the operation of the sub-control circuit>
Next, with reference to FIGS. 36 to 74, contents of various processes executed by various control circuits in the sub-board 202 of the sub-control circuit 200 (see FIG. 6, for example) will be described. The sub-control circuit 200 receives various commands transmitted from the main control circuit 70 (see FIG. 6, for example), and performs various processes based on these various commands.

[Sub-control main processing]
First, with reference to FIG. 36, the sub-control main processing executed by the host control circuit 210 (see FIG. 6, the same applies hereinafter) will be described. FIG. 36 is a flow chart showing an example of the sub-control main process in this embodiment. The sub-control main process is a process started when the power is turned on. In the sub-control main process described with reference to FIG. 36 and the sub-control main process described later (see FIGS. 47, 48, and 49), the same processes are given different reference numerals for convenience of explanation. For example, various initialization processes will be described as an example. Various initialization processes (step S201) in FIG. 36, various initialization processes (step S381) in FIG. 47, various initialization processes (step S391) in FIG. 48, and various initialization processes (step S401) in FIG.

First, the host control circuit 210 performs various initialization processes (step S201). In this processing, the host control circuit 210 performs various initial setting processing such as hardware initialization processing, device initialization processing, initialization processing for various applications, initialization processing for restoring backup data, and RTC acquisition processing. When game data has been erased by RAM clearing, random number initialization processing is also performed. Also, the host control circuit 210 clears the counter of the watchdog timer each time each initialization process ends. At startup, a reset time for the watchdog timer is set, and if no service pulse is written after that (during timeout), power-off processing is performed. The timing for clearing the watchdog timer is the start of each process in the main loop in the sub-control main process, the start of each initialization process, and the transition to power failure process.

Next, the host control circuit 210 enters the main loop and performs RTC acquisition processing based on the RTC time, that is, processing for acquiring the current time (step S202).

The host control circuit 210 performs random number initialization processing in step S203. This random number initialization process will be described later.

The host control circuit 210 acquires the control code of the character in step S204, and performs synchronization processing between the character and the solenoid (step S205). These processes will be described later in the "accessory solenoid control process".

The host control circuit 210 performs sub-device input processing in step S206. In this process, the host control circuit 210 performs information acquisition processing of operation details, etc., based on the input state of the operation means (determining whether or not the player has operated the operation means such as a button). This sub-device input process (step S206) includes brightness adjustment of LEDs and the like by the player's operation.

The host control circuit 210 performs various request control processes in step S207. In this process, the host control circuit 210 performs various request control processes such as sound request control process, LED request control process, and accessory request control process. Sound requests, LED requests, accessory requests, and the like are stored in a buffer and output to each device after a bank flip in step S213, which will be described later. As a result, synchronization with drawing can be achieved. Bank flipping is a process of switching the function of one frame buffer from the drawing function to the display function and switching the function of the other frame buffer from the display function to the drawing function.

Next, the host control circuit 210 enters a packet reception loop within the main loop, and performs main-sub command control processing (step S208). In this process, when the host control circuit 210 receives command data from the main CPU 71, it reads command data (command reception process) and stores the command data in the subwork RAM 210a (received data storage process).

The host control circuit 210 performs game data backup processing in step S209. In the pachinko machine 1 of the present embodiment, first data (magic code, program version and SUM value) and second data (magic code and SUM value, which are information set in the hall menu) are prepared as game data used for RAM clear determination. Then, in the game data backup process, after the first data is saved in the game data, it is backed up in the SRAM 210b (see FIG. 6). The game data is also backed up (mirrored) in another area of the SRAM 210b. After the power is turned on, the game data is restored from the data backed up in the SRAM 210b. At this time, the first data is used to check whether the backed up data is corrupted. If the backed up data is corrupted, check whether the second data is corrupted. At this time, all data stored in the SRAM 210b such as whole menu information are also initialized.

Next, the host control circuit 210 performs animation request construction processing (step S210). In this processing, the host control circuit 210 performs command analysis, state setting, and lottery processing, receives these, generates an animation request necessary when controlling the performance using the display device 13, and generates various requests (sound request, lamp request, and accessory request) for operating various performance devices in response to the performance control (display) in the display device 13 executed based on this animation request.

The host control circuit 210 executes the processes of steps S202 to S05 for the number of received commands, and exits the packet reception loop after executing the number of received commands. After that, the host control circuit 210 performs animation update processing (step S211), drawing processing (step S212), bank flip/waiting for bank flip end (step S213), and each processing in the main loop is repeated.

The host control circuit 210 repeatedly executes the example of the processing (main loop processing) of steps S202 to S213 described above at a predetermined FPS cycle. Note that the FPS cycle is set to, for example, approximately 16.7 msec (60 FPS), approximately 33.3 msec (30 FPS), or the like. The predetermined FPS period is time adjusted in step S213.

Timer interrupt processing, sub-device input processing, backlight control processing, backlight and various LED brightness adjustment, RTC acquisition processing, composition playback control, sound amplifier control processing, sound request control processing (when there are multiple sound requests for the same channel), sound request control processing (when volume is adjusted), LED brightness adjustment processing, accessory solenoid control processing, data load processing, and sub-random number processing will be described in this order. For convenience of explanation, the order of explanation of each process described above is different from the order of processing.

[Timer interrupt processing]
In the pachinko gaming machine 1 of the present embodiment, the host control circuit 210 performs interrupt processing in a cycle of 1 msec. Although the interrupt processing will be described in each processing to be described later, an example of typical interrupt processing will be briefly described here with reference to FIG. 37 . FIG. 37 is a flow chart showing an example of timer interrupt processing executed by the host control circuit (sub-control circuit). In the timer interrupt processing which will be briefly described with reference to FIG. 37 and the timer interrupt processing which will be described later (see FIGS. 44 and 46), the same processing is given different reference numerals for convenience of explanation. For example, referring to the accessory motor control as an example, the accessory motor control (step S251) in FIG. 37, the accessory motor control (step S352) in FIG. 44, and the accessory motor control (step S371) in FIG.

Referring to FIG. 37, in timer interrupt processing, host control circuit 210 first performs accessory motor control (step S251). Next, the host control circuit 210 performs input state determination processing based on the input information of the sub-device (step S252). Next, the host control circuit 210 performs control processing such as the backlight of the liquid crystal display device used as the display device 13, for example, based on the luminance value (step S253). Next, the host control circuit 210 performs sound amplifier check processing (step S254).

[Sub device input processing]
In this embodiment, the host control circuit 210 creates sub-device input determination information in the main process every 33.3 msec based on the input state of the sub-device detected by the timer interrupt every 1 msec, and controls the sub-device based on the created sub-device input determination information.

When the host control circuit 210 detects the input state of the sub-device by a timer interrupt every 1 msec, the host control circuit 210 creates sub-device input information, sub-device input ON edge information, sub-device input ON edge information (with repeat function), and sub-device input OFF edge information as the sub-device input determination information created in the main process based on the detection result.

The sub-device input processing shown in FIG. 36 will be described below with reference to FIGS. 38-41. Subdevices, such as push buttons, are controlled by the host control circuit 210 based on input (eg, manipulation) information. FIG. 38 is a diagram showing an example for explaining the generated sub-device input discrimination information, (a) a diagram showing the input state of the sub-device detected by the timer interrupt, (b) a diagram showing the sub-device input information produced in the main process, (c) a diagram showing the sub-device input ON edge information produced in the main process, (c) a diagram showing the sub-device input ON edge information (with repeat function) produced in the main process, and (d) a diagram showing the sub-device OFF edge information produced in the main process. FIG. 39 is a flowchart showing an example of sub-device input processing. FIG. 40 is a flowchart showing an example of sub-device input ON edge information (with repeat function) processing. FIG. 41 shows an example of sub-device input ON edge information (with repeat function) processing, and is a flowchart continued from FIG.

The sub-device input information created in the main process is created in accordance with the sub-device input state (see FIG. 38(a)) detected by the timer interrupt, as shown in FIG. 38(b). That is, 1 is set when the sub-device input state detected by the timer interrupt is ON. Also, 0 is set when the sub-device input state detected by the timer interrupt is OFF.

As shown in FIG. 38(c), the sub-device input ON edge information is set to 1 for only one frame in the main process when it is detected that the sub-device input state detected by timer interrupt has changed from OFF to ON.

The sub-device input ON edge information (with repeat function) is information that is used, for example, for debugging or control when an operation button is pressed long. As shown in FIG. When the ON state of the input state of the sub-device continues after that, 1 is set in one frame after elapse of 10 frames, for example, in the main processing as a fixed time until the start of key repeat, and after that, 1 is set in every four frames in the main processing, for example. The reason why only the first frame is lengthened by 10 frames in this way is that it is possible to determine whether or not the sub-device has been pressed for a long time.

As shown in FIG. 38(e), the sub-device input OFF edge information is set to 1 for only one frame in the main processing when it is detected that the sub-device input state has changed from ON to OFF by timer interrupt.

In this embodiment, assuming that there are a plurality of sub-devices, the host control circuit 210 manages the sub-device input discrimination information in units of bits. For example, bit0 is for the main button, bit1 is for the left button, and bit2 is for the right button.

Next, sub-device input processing (see step S206 in FIG. 36, for example) will be described with reference to FIG. This sub-device input process is a process for creating, for example, four types of information as sub-device input determination information: sub-device input information, sub-device input ON edge information, sub-device input ON edge information (with repeat function), and sub-device input OFF edge information.

The host control circuit 210 first creates current sub-device input information based on the current sub-device input state (step S301). Specifically, 1 is set if the sub-device is in the ON state, and 0 is set if the sub-device is in the OFF state.

Next, the host control circuit 210 updates the sub-device input information according to the current sub-device input information, that is, the sub-device input information created in step S301 (step S302).

Next, the host control circuit 210 determines whether the previous sub-device input information is 0 and the current sub-device input information is 1 (step S303). If the previous sub-device input information is 0 and the current sub-device input information is 1 (YES in step S303), the host control circuit 210 sets the sub-device input ON edge information to 1 (step S304), and proceeds to step S306. On the other hand, if the previous sub-device input information is 0 and the current sub-device input information is not 1 (that is, if the previous sub-device input information is 1 and/or the current sub-device input information is 0), the host control circuit 210 sets the sub-device input ON edge information to 0 (step S305), and proceeds to step S306.

The host control circuit 210 determines whether the previous sub-device input information is 1 and the current sub-device input information is 0 in step S306. If the previous sub-device input information is 1 and the current sub-device input information is 0 (YES in step S306), the host control circuit 210 sets the sub-device input OFF edge information to 1 (step S307), and proceeds to step S309. On the other hand, if the previous sub-device input information is 1 and the current sub-device input information is not 0 (that is, if the previous sub-device input information is 0 and/or the current sub-device input information is 1), the host control circuit 210 sets the sub-device input OFF edge information to 0 (step S308), and proceeds to step S309.

In step S309, the host control circuit 210 performs sub-device input ON edge information (with repeat function) processing. The details of this sub-device input ON edge information (with repeat function) processing will be described later.

When the sub-device input ON edge information (with repeat function) processing in step S309 ends, the host control circuit 210 sets the current sub-device input information to the previous sub-device input information (step S310), and ends the sub-device input processing.

Next, sub-device input ON edge information (with repeat function) processing will be described with reference to FIGS. 40 and 41. FIG.

As shown in FIG. 40, in the sub-device input ON edge information (with repeat function) processing, the host control circuit 210 first determines whether or not the previous sub-device input information is 0 (step S321). If the previous sub-device input information is 0 (YES in step S321), the process proceeds to step S322.

The host control circuit 210 determines whether or not the current sub-device input information is 1 in step S322. If the current sub-device input information is 1 (YES in step S322), that is, if the previous sub-device input information is 0 and the current sub-device input information is 1, the process proceeds to step S323. On the other hand, if the current sub-device input information is not 1 (NO in step S322), that is, if the previous sub-device input information is 0 and the current sub-device input information is 0, the sub-device input ON edge information (with repeat function) processing ends.

Next, the host control circuit 210 sets the sub-device input ON edge information (with repeat function) to 1 (step S323), sets 10 frames as the elapsed frame (step S324), and ends the sub-device input ON edge information (with repeat function) processing.

In step S321, if the previous sub-device input information is 1 (NO in step S321), the host control circuit 210 proceeds to step S325 in FIG.

Referring to FIG. 41, host control circuit 210 determines whether or not the current sub-device input information is 1 in step S325. If the current sub-device input information is 1 (YES in step S325), that is, if the previous sub-device input information is 1 and the current sub-device input information is 1, 1 is subtracted from the elapsed frame (step S326), and the process proceeds to step S327.

The host control circuit 210 determines whether or not the number of elapsed frames is 0 in step S327. If the elapsed frame is 0 (YES in step S327), the sub-device input ON edge information (with repeat function) is set to 1 (step S328), the elapsed frame is set to 4 (step S329), and the sub-device input ON edge information (with repeat function) processing ends.

In step S325, if the current sub-device input information is not 1 (NO in step S325), that is, if the previous sub-device input information is 1 and the current sub-device input information is 0, the host control circuit 210 sets the elapsed frame to 0 (step S330), and proceeds to step S331.

When the host control circuit 210 sets the sub-device input ON edge information (with repeat function) to 0 in step S331, the sub-device input ON edge information (with repeat function) processing ends.

In this way, the host control circuit 210 creates the above four types of sub-device input determination information in the main processing every 33.3 msec based on the input state of the sub-device detected by the timer interrupt every 1 msec. By controlling the sub-device based on these four types of sub-device input determination information, it becomes possible to easily control the sub-device's continuous hit effect, long press effect, time setting control, and other operations.

[Backlight control processing]
Next, backlight control processing (for example, backlight control processing for controlling the backlight of a liquid crystal display or the like) will be described with reference to FIGS. 42 and 43. FIG. FIG. 42 is a diagram showing an example for conceptually explaining the backlight control process. FIG. 43 is a flowchart illustrating an example of backlight control processing.

The backlight control process of the present embodiment uses the SPI asynchronous data write (SPI+DMA) function to continuously and continuously output a signal equivalent to pulse width modulation (hereinafter referred to as "PWM") from a serial output terminal of a serial peripheral interface (hereinafter referred to as "SPI") so that the duty (luminance) can be changed. This makes it possible to perform backlight control without using a driver for backlight control.

In this embodiment, for example, the frequency of the SPI clock is 100 kHz, the SPI1 clock is 0.01 msec, the time required to transmit 16-bit SPI data (1 data of luminance data is 16 bits) is 0.16 msec, the scheduled interrupt of the host control circuit 210 is 1 msec, and the number of luminance data transmitted from the SPI between scheduled interrupts of the host control circuit 210 is 100 bits. Therefore, the number of pieces of luminance data transmitted between scheduled interrupts of the host control circuit 210 is 6.25 (100/16) (see FIG. 42). Therefore, it is considered that the number of scheduled interrupts executed until 32 pieces of luminance data are replenished in a FIFO (First In First Out) data area capable of setting (storing) 64 pieces of 16-bit luminance data, for example, is 5 to 6 times. Note that this number of times differs depending on the period of the scheduled interrupt of the host control circuit 210 .

For example, when the number of luminance data set (stored) in a FIFO (First In First Out) data area capable of setting (storing) 64 pieces of 16-bit luminance data falls below 32, a callback function is called, so the FIFO data area is not always filled. Therefore, if other processing in the main processing executed at a cycle of 33.3 msec does not take time to set (store) luminance data in the FIFO data area, the FIFO data area may become empty (the backlight may become completely dark).

Therefore, in this embodiment, after the power is turned on, 64 pieces of 16-bit luminance data are first set to fill the FIFO data area. After that, when the number of luminance data set in the FIFO data area falls below 32, a callback function is called, and 32 pieces of data are set in the callback function so that the FIFO data area does not become empty.

As shown in FIG. 43, in the backlight control process, the host control circuit 210 first determines whether or not the process is for initial setting (step S341). When the host control circuit 210 determines that it is the initial setting process (that is, one of the processes in step 201 in FIG. 36) (YES in step S341), it sets 64 pieces of luminance data of 0 in the FIFO data area (step S342), and proceeds to step S343. On the other hand, if it is determined that the process is not the initial setting process (that is, the process of step S253 in FIG. 37) (NO in step S341), the process of step S342 is skipped and the process proceeds to step S343.

The host control circuit 210 determines in step S343 whether or not the luminance value has been changed. When the host control circuit 210 determines that the luminance value has been changed (YES in step S343), it changes the luminance data to be set in the FIFO data area (step S344), and proceeds to step S345. On the other hand, if it is determined that the brightness value has not been changed (NO in step S343), the process of step S344 is skipped and the process proceeds to step S345.

In step S345, the host control circuit 210 determines whether or not the number of luminance data set in the FIFO data area is less than 32. If the number of luminance data set in the FIFO data area is less than 32 (YES in step S345), 32 luminance data are set in the FIFO data area, that is, supplemented (step S346), and the backlight control process ends. On the other hand, if the number of luminance data set in the FIFO data area is greater than 32 (NO in step S345), host control circuit 210 terminates the backlight process.

In this way, by performing processing so that the luminance data set in the data area of the FIFO does not become empty, it is possible to continuously output a signal equivalent to PWM from the serial data output terminal of the SPI, and to perform backlight control without going through a driver for backlight control.

Note that the processing of steps S343 to S346 of the backlight control processing of this embodiment can be replaced as follows. That is, after 64 pieces of data of luminance 0 are set (see step S342), processing is performed to determine whether or not the number of pieces of luminance data set in the FIFO data area is less than 32 pieces. Thereafter, it is determined whether or not the luminance value is changed, and if it is determined that the luminance value is changed, 32 pieces of luminance data corresponding to the setting are set in the data area of the FIFO, and if it is determined that the luminance value is not changed, 32 pieces of the same luminance data as the previous time are set in the data area of the FIFO. The luminance data may be set in the data area of the FIFO in this way, and the backlight control process may be terminated.

In this embodiment, when the number of luminance data set in the FIFO data area falls below 32 (half the number of data that can be set in the FIFO), 32 luminance data are supplemented. However, the timing of supplementing the luminance data and the number of luminance data to be supplemented are not limited to this. Further, the number of luminance data to be replenished in the FIFO data area does not need to be the above-mentioned predetermined number. For example, when the number of luminance data set in the FIFO data area falls below the first number, a second number of luminance data may be replenished. However, from the viewpoint of preventing the brightness data from being set in the FIFO data area too frequently and the brightness data set in the FIFO data area not becoming empty, the predetermined number or the first number is preferably about half the number of data that can be set in the FIFO data area, but is not limited to this as described above. The above-mentioned "about half" is a range in which the frequency of setting luminance data in the FIFO data area does not become too high and the luminance data set in the FIFO data area does not become empty. For example, since the FIFO data area in this embodiment can set up to 64 pieces of 16-bit luminance data, when the number of luminance data set in the FIFO data area is 1 to 64, one or more new luminance data may be set. It is preferable to set more than one brightness data. Also, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient if at least two luminance data can be set. When the number of luminance data that can be set in the FIFO data area is, for example, two or more, and the number of luminance data set in the FIFO data area falls below a first number (for example, two), a second number (for example, one) of luminance data may be supplemented.

[Modified Example of Backlight Control Processing]
Next, a modification of the backlight control process will be described with reference to FIGS. 44 and 45. FIG. FIG. 44 is a flowchart showing an example of timer interrupt processing according to a modification of backlight control processing. FIG. 45 is a flow chart showing a modification of the backlight control process.

In the modification of the backlight control process, when there is a possibility that the 1 msec timer interrupt process may take time, it is determined whether or not a predetermined period of time or more has elapsed since the data was set in the FIFO data area in the backlight control process, and if the predetermined period of time or more has elapsed, the data is set in the FIFO data area.

In the timer interrupt processing of FIG. 44, the host control circuit 210 first performs backlight control processing (step S351). For convenience of explanation, the backlight control process in step S351 will be explained below with reference to FIG. 45 before explaining the processes after step S352.

As shown in FIG. 45, in the backlight control process, the host control circuit 210 first determines whether or not the process is for initial setting (step S361). When the host control circuit 210 determines that it is the initial setting process (that is, one of the processes in step 201 in FIG. 36) (YES in step S361), it sets 64 pieces of luminance data of 0 in the FIFO data area (step S362), and then proceeds to step S366. On the other hand, if it is determined that the process is not the initial setting process (that is, the process of step S351) (NO in step S361), the process proceeds to step S363.

In step S363, the host control circuit 210 determines whether or not the number of luminance data set in the FIFO data area is less than 32. If the number of luminance data set in the FIFO data area is less than 32 (YES in step S363), the FIFO data area is set or supplemented with 32 luminance data (step S364), and the process proceeds to step S365. On the other hand, if the number of luminance data set in the FIFO data area is greater than 32 (NO in step S363), the process proceeds to step S366. The above 32 are half the number of data that can be set in the FIFO, as described above.

In step S365, the host control circuit 210 resets the elapsed time (step S365) and starts counting the elapsed time (step S366). After starting the elapsed time measurement in step S366, the host control circuit 210 ends the backlight control process.

Returning to FIG. 44, the host control circuit 210 performs the accessory motor control after completing the backlight control process of step S351 (step S352).

In this modification, the host control circuit 210 performs a process that may take a long time, such as accessory motor control, and then determines whether or not the elapsed time from the start of timing in step S366 has exceeded a predetermined time (step S353). If the predetermined time or longer has elapsed (YES in step S353), 32 luminance data are set in the FIFO data area (step S354). On the other hand, if the predetermined time or more has not elapsed (NO in step S353), it is not necessary to replenish the data area of the FIFO with luminance data, so the process proceeds to step S357.

As described above, since it takes 0.16 msec to transmit 16 bits (1 data of luminance data is 16 bits) in SPI, it is considered that 5.12 msec is required to transmit 32 pieces of luminance data. Therefore, in this modification, in step S353, it is determined whether or not a predetermined time of 5.12 msec or more has elapsed.

After performing the process of step S354, the host control circuit 210 resets the elapsed time (step S355) and restarts counting the elapsed time (step S356). After starting to count the elapsed time in step S356, the host control circuit 210 performs input state determination processing (step S357), and ends the timer interrupt processing.

In this way, timing is started when luminance data is set in the data area of the FIFO, and luminance data in the data area of the FIFO can be prevented from becoming empty by replenishing the luminance data if the clocked time elapses for a predetermined time or longer after processing that may require time.

It should be noted that, in this modified example, an example in which the processing of steps S353 to S357 is performed after the accessory motor control (step S352) has been described, but this is merely an example. That is, from the viewpoint of preventing the brightness data set in the FIFO data area from becoming empty, the processing of steps S353 to S357 may be performed after processing that may take a long time, and such processing is not limited to a specific processing.

[Brightness adjustment of backlight and various LEDs]
Next, variations in brightness adjustment of the backlight and various LEDs will be described. The various LEDs correspond to board-side LEDs (for example, LEDs arranged on the game board 12), frame-side LEDs, etc. In this specification, lamp group 18 including LEDs (see, for example, FIG. 5) corresponds to this. Furthermore, in this specification, three variations of the first to third embodiments will be described as variations of brightness adjustment of the backlight and various LEDs with reference to FIGS. 46 to 49, respectively. FIG. 46 is a flowchart showing an example of timer interrupt processing showing backlight control processing. FIG. 47 is a sub-control main process (overall flow) executed by the host control circuit 210 for explaining the first embodiment of the brightness adjustment process of the backlight and various LEDs. FIG. 48 is a secondary control main process (overall flow) executed by the host control circuit 210 for explaining a second embodiment of the brightness adjustment process of the backlight and various LEDs. FIG. 49 is a sub-control main process (overall flow) executed by the host control circuit 210 for explaining the third embodiment of the brightness adjustment process of the backlight and various LEDs. However, in FIGS. 47 to 49, only the processes required for explanation are shown, and the other processes are omitted. Also in the first to third embodiments described below, as described above, the host control circuit 210 supplements the FIFO data area with luminance data when the luminance data set in the FIFO data area is about half.

The timing for replenishing the FIFO data area with luminance data is not limited to when the luminance data set in the FIFO data area is about half. The data area of the FIFO in this embodiment can set, for example, up to 64 pieces of 16-bit luminance data. Therefore, when the number of luminance data set in the FIFO data area is 1 to 64, one or more pieces of luminance data can be newly set. However, from the viewpoint of preventing the backlight from becoming dark (the brightness data set in the FIFO data area becomes 0), it is preferable to newly set one or more brightness data when the number of brightness data set in the FIFO data area is two or more. Also, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient if at least two luminance data can be set. When the number of luminance data that can be set in the FIFO data area is, for example, two or more, and the number of luminance data set in the FIFO data area falls below a first number (for example, two), a second number (for example, one) of luminance data may be supplemented.

(First embodiment)
For example, when the brightness of the backlight (for example, the backlight of a liquid crystal display) is adjusted by a player or the like, the brightness of the backlight is changed, but at this time, the control of the board-side LED and the frame-side LED may be affected. In such a case, the present embodiment sets the brightness of the backlight and the brightness of the board-side LED and the frame-side LED in common, and controls the backlight, the board-side LED, and the frame-side LED according to the setting. As a result, even if the update timing of the backlight control differs from the update timing of the control of the board-side LEDs and the frame-side LEDs, it is possible to facilitate the processing.

In the timer interrupt process of FIG. 46, the host control circuit 210 performs accessory motor control (step S371), input state determination process (step S372), and backlight control process (step S373) in this order.

As shown in FIG. 47, the host control circuit 210 performs initialization processing (step S381), and then shifts to the main loop to perform LED request control processing (step S382). The LED request made in step S382 was created in the animation building process (step S386 described later) one frame before.

After performing the process of step S382, the host control circuit 210 performs the sub-device (button) input determination information generation process (step S383) based on the input state of the sub-device, and proceeds to step S384.

In step S384, the host control circuit 210 sets the brightness of the backlight based on the input state of the sub-device (for example, the player or the like operates the brightness setting screen displayed on the liquid crystal display device used as the display device 13). The brightness of the backlight is set, for example, in three stages of strong, medium, and weak.

After performing the processing of step S384, the host control circuit 210 shifts to a packet reception loop, and first sets the brightness values of the board-side LED and the frame-side LED according to the effect mode to be executed and the brightness value setting (step S385). The brightness of the board-side LED and the frame-side LED is also set to three levels, for example, high, medium, and low, like the backlight.

Here, by setting the luminance of the board-side LED and the frame-side LED and the luminance of the backlight in common, it is possible to suppress an increase in the control load and change both the luminance setting of the board-side LED and the frame-side LED and the luminance of the backlight by the player's operation. For example, when the player or the like operates a brightness setting screen displayed on the liquid crystal display device used as the display device 13, the host control circuit 210 changes the brightness value of the backlight (step S384), and also changes the brightness values of the board-side LED and the frame-side LED (step S385). At this time, the level of the brightness value of the backlight and the level of the brightness value of the board-side LED and the frame-side LED are also common. For example, if the level of the brightness value of the backlight is medium, the levels of the brightness values of the board-side LED and the frame-side LED are also medium. As shown in FIG. 47, since the brightness update timing of the backlight differs from the brightness update timing of the board-side LEDs and the frame-side LEDs, the brightness of the board-side LEDs and the frame-side LEDs is updated after the backlight brightness is updated. However, control may be performed so that the brightness update timing of the backlight and the brightness update timing of the board-side LEDs and the frame-side LEDs are the same.

The brightness of the backlight, the brightness of the board-side LED and the frame-side LED are changed based on the player's operation of the brightness setting screen displayed on the liquid crystal display device used as the display device 13. However, the present invention is not limited to this. In this case, it is necessary to determine whether or not it is the period during which the push button functions as a presentation push button (push button valid period), so it is necessary to adjust the brightness of the board side LED and the frame side LED in the main flow and control the backlight according to the brightness of these LEDs.

The host control circuit 210 performs animation construction processing in step S386. An LED request is created in the animation building process of step S386. The created LED request is waited in the buffer and then output in the LED request control process (see step S382) of the next frame.

The host control circuit 210 repeats the processing of steps S385 and S386 according to the received packet.

After exiting the packet reception loop, the host control circuit 210 performs animation update processing (step S387), and then waits for bank flip/finish of bank flip (step S388).

The host control circuit 210 repeats each process of steps S382 to S388 in the main loop at a cycle of 33.3 msec.

(Second embodiment)
For example, when a player or the like performs a luminance adjustment operation, it may affect the control of the board-side LED and the frame-side LED, as described above. In such a case, for example, when the brightness adjustment operation is performed by a player or the like, the brightness value of the backlight is immediately changed, but the control of the board-side LED and the frame-side LED is executed after the fluctuation of the special symbols is completed or between bank flips.

As described above, in the timer interrupt process of FIG. 46, the host control circuit 210 performs the accessory motor control (step S371), the input state determination process (step S372), and the backlight control process (step S373) in this order.

As shown in FIG. 48, the host control circuit 210 performs initialization processing (step S391), and then shifts to the main loop to perform LED request control processing (step S392). The LED request made in step S392 was created in the animation building process (step S395 described later) one frame before.

After performing the process of step S392, the host control circuit 210 performs the above-described sub-device (button) input determination information generation process (step S393) based on the input state of the sub-device (for example, brightness adjustment operation by the player or the like), and proceeds to step S394.

In step S394, the host control circuit 210 sets the brightness of the backlight based on the input state of the sub-device (for example, brightness adjustment operation by the player or the like). The brightness of the backlight is set, for example, in three stages of strong, medium, and weak.

After performing the processing of step S394, the host control circuit 210 shifts to a packet reception loop and performs animation construction processing (step S395). An LED request is created in the animation building process in step S395. The created LED request is waited in the buffer and then output in the LED request control process (see step S392) of the next frame.

The host control circuit 210 repeats the process of step S395 according to the received packet.

After exiting the packet reception loop, the host control circuit 210 performs animation update processing (step S396), then performs bank flip/waiting for completion of bank flip (step S397), and proceeds to step S398.

In step S398, the host control circuit 210 determines whether or not the variation of the performance identification displayed on the liquid crystal display device as the display device 13 has ended, that is, whether or not the variation time of the performance identification pattern has elapsed (step S398). If the effect identification symbols have changed (YES in step S398), the host control circuit 210 changes the brightness of the board-side LED and the frame-side LED according to the set values at that time (step S399). On the other hand, if the variation of the special symbol has not ended (NO in step S398), the processing of steps S392 to S399 in the main loop with a period of 33.3 msec is repeated. It should be noted that the process of step S399 may be performed during the bank flip of step S397 instead of or in addition to when the variation of the special symbol is completed.

Thus, in the second embodiment, the host control circuit 210 controls the brightness of the backlight, which directly affects the eyes of the player, to be changed immediately based on the input state of the sub-device (for example, the brightness adjustment operation by the player or the like), but controls the brightness of the board-side LED and the frame-side LED so that it is changed after the brightness of the backlight is changed and after the fluctuation of the performance identification pattern is completed. In addition, when the brightness adjustment operation is performed by the player or the like during the variation of the performance identification pattern, the brightness of the board-side LED and the frame-side LED needs to be changed by the LED request control process, but the backlight can be changed immediately. Therefore, based on the input state of the sub-device, the brightness of the backlight is controlled so as to be changed immediately, but the brightness of the board-side LED and the frame-side LED is changed by the LED request control process, thereby making it possible to minimize the control load. That is, it is possible to change the brightness of the backlight and the brightness of the board-side LED and the frame-side LED while minimizing the control load, for example, by performing a single brightness adjustment operation by the player or the like.

When the brightness of the backlight is changed based on the input state of the sub-device (for example, a brightness adjustment operation by a player or the like), the host control circuit 210 sets the brightness data related to the brightness after the change in the data area of the FIFO.

(Third embodiment)
For example, when a player or the like performs a luminance adjustment operation, it may affect the control of the board-side LED and the frame-side LED, as described above. In such a case, the present embodiment changes the luminance value of the backlight when, for example, a player or the like performs a luminance adjustment operation, and also performs a limited performance of the board-side LED and the frame-side LED. Limited performance corresponds to, for example, limiting the number of LEDs that emit light in the effects of the board-side LEDs and the frame-side LEDs, or limiting the number of effects performed by the board-side LEDs and the frame-side LEDs. Limiting the number of effects corresponds to, for example, performing only effects 1 to 3 when effects 1 to 5 are originally performed, and omitting effects 4 and 5. As a result, the effect of the board-side LED and the frame-side LED is restricted without directly changing the luminance value, so that the intensity of the light received by the player from the board-side LED and the frame-side LED is suppressed. Further, even if the update timing of the backlight control and the update timing of the control of the board-side LED and the frame-side LED are different, the processing can be facilitated.

As described above, in the timer interrupt process of FIG. 46, the host control circuit 210 performs the accessory motor control (step S371), the input state determination process (step S372), and the backlight control process (step S373) in this order.

As shown in FIG. 49, the host control circuit 210 performs initialization processing (step S401), and then shifts to the main loop to perform LED request control processing (step S402). The LED request made in step S402 was created in the animation building process (step S407 described later) one frame before.

After performing the process of step S402, the host control circuit 210 performs the sub-device (button) input determination information generation process (step S403) based on the input state of the sub-device, and proceeds to step S404.

In step S404, the host control circuit 210 sets the brightness of the backlight based on the input state of the sub-device (for example, brightness adjustment operation by the player or the like). The brightness of the backlight is set, for example, in three stages of strong, medium, and weak.

After performing the process of step S404, the host control circuit 210 determines whether or not the brightness setting has been changed (step S405). If there is a change in brightness setting (YES in step S405), the host control circuit 210 limits the brightness of the board-side LED and the frame-side LED according to the setting at that time (step S406), and proceeds to the packet reception loop. On the other hand, if the luminance value setting has not been changed (NO in step S405), the host control circuit 210 proceeds to the packet reception loop without performing the processing of step S406.

After moving to the packet reception loop, the host control circuit 210 performs animation construction processing (step S407). An LED request is created in the animation building process in step S407. The created LED request is waited in a buffer and then output in the LED request control process (see step S402) for the next frame.

The host control circuit 210 repeats the process of step S407 according to the received packet.

After exiting the packet reception loop, the host control circuit 210 performs animation update processing (step S408), and then waits for bank flip/finish of bank flip (step S409).

The host control circuit 210 repeats the processing of steps S402 to S409 in the main loop with a period of 33.3 msec.

Regarding the brightness adjustment of the backlight and various LEDs (first to third embodiments) described above, the backlight control process of the present embodiment uses the SPI asynchronous data write (SPI+DMA) function, for example, to continuously output a signal equivalent to PWM from the SPI serial output terminal. On the other hand, the board-side LED and the frame-side LED are controlled based on the LED request created one frame before the main loop, as shown in step S382 of FIG. 47, for example. Therefore, even if the brightness of the backlight and various LEDs is adjusted, the timing of changing the brightness of the backlight differs from the timing of changing the brightness of the board-side LEDs and the frame-side LEDs.

[RTC Acquisition Processing]
Next, RTC acquisition processing will be described with reference to FIG. As described above, the RTC acquisition process is performed both within various initialization processes (see step S201 in FIG. 36) and in the main loop (see step S201 in FIG. 36). Note that FIG. 50 is a flowchart showing an example of the RTC acquisition process.

For example, when the correct time cannot be obtained due to an RTC abnormality such as when communication with the RTC cannot be performed or when an abnormality occurs in the RTC itself, the time is not updated and remains the previous time. Therefore, when an RTC performance (for example, a performance related to Christmas at Christmas time) is executed based on the RTC time, if an RTC abnormality occurs, there is a possibility that the RTC performance cannot be executed. Furthermore, since the RTC time is not updated when the RTC or above occurs, there is a risk that the RTC effect will continue to be executed or that the RTC effect will be executed at an unexpected time.

Therefore, in the RTC acquisition process of the present embodiment, when the RTC is abnormal, that is, when the previous RTC time differs from the current RTC time, the RTC effect is executed based on the current time. Note that the RTC is provided with a secondary battery so that the time can be managed even when the host control circuit 210 is powered off. Also, the host control circuit 210 acquires the time from the RTC and manages the error occurrence time and the like.

As shown in FIG. 50, in the RTC acquisition process, the host control circuit 210 first acquires the RTC time (step S412), and then proceeds to step S413.

The host control circuit 210 updates the previous time in step S413. In updating the previous time, the current time updated in step S416, which will be described later, is used as the previous time. After that, the host control circuit 210 determines whether or not the RTC is abnormal (step S414). If the RTC is abnormal (YES in step S414), the current time is maintained (step S415) and the process proceeds to step S417. On the other hand, if the RTC is not abnormal (NO in step S414), the current time is updated (step S416), and the process proceeds to step S417.

In the RTC acquisition process of the present embodiment, it is determined whether or not the RTC is abnormal (step S414) after updating the previous time (step S413). Alternatively, it may be determined whether or not the RTC is abnormal before updating the previous time, and if the RTC is not abnormal, the previous time may be updated so that the current time is not maintained.

In step S417, the host control circuit 210 determines whether or not the current time is the designated time (for example, the time to execute the RTC effect). If the current time is the designated time (YES in step S417), the process proceeds to step S418, and if the current time is not the designated time (NO in step S417), the process proceeds to step S420.

The host control circuit 210 determines in step S418 whether or not the previous time and the current time do not match. If the RTC is abnormal, the previous time and the current time do not match (YES in step S418). If the previous time and the current time do not match (YES in step S418), the RTC effect execution flag is set to 1 (step S419). That is, when the RTC is abnormal, the RTC effect is executed when the current time reaches the designated time. After performing the process of step S419, the host control circuit 210 terminates the RTC acquisition process. On the other hand, if the previous time and the current time do not match (NO in step S418), the process proceeds to step S420.

Host control circuit 210 sets the RTC effect execution flag to 0 in step S420. After performing the process of step S420, the host control circuit 210 ends the RTC acquisition process.

Thus, in this embodiment, even if there is an RTC abnormality, it is possible to avoid a situation in which the RTC presentation is not performed by executing the RTC presentation when the current time reaches the specified time.

[Composition playback control]
Next, composition reproduction control will be described with reference to FIGS. 51 and 52. FIG.

A composition is scene data combining material data for forming an image (movie) to be displayed on a liquid crystal display device used as the display device 13, and generally consists of a plurality of layers. Layers include animations, vector graphics, still images, lights, and more.

FIG. 51 is a flow chart showing an example of animation control main processing executed by the display control circuit 230 . As shown in FIG. 51, the display control circuit 230 first clears the composition playback information (step S431). Then, the display control circuit 230 executes composition reproduction control processing (step S432). This composition reproduction control process will be described later. After that, the display control circuit 230 executes the top-level direct drawing function (step S433), and ends the animation control main processing.

FIG. 52 is a flowchart showing an example of composition reproduction control processing executed by the display control circuit 230. As shown in FIG. As shown in FIG. 52, the display control circuit 230 first determines whether the determined priority number is less than the upper limit of the priority number (or equal to or less than the upper limit) (step S441). If the determined priority number is less than the upper limit of the priority number (or equal to or less than the upper limit) (YES in step S441), the process proceeds to step S442. The priority number is the number of layers of the composition to be played simultaneously, and the upper limit of the priority number is predetermined based on the composition to be played. Therefore, as long as the processing by the host control circuit 210 is normal, the determined priority number does not exceed the upper limit of the priority number. Therefore, when the determined priority number exceeds the upper limit of the priority number (NO in step S441), the display control circuit 230 ends the composition reproduction control process.

In step S442, display control circuit 230 determines whether the determined number of displays is less than (or less than) the number of usable displays, that is, determines whether the determined number of displays is less than (or less than) the number of displays that can be used (for example, installed) in the system (step S442). If the determined number of displays is less than (or less than) the number of usable displays (YES in step S442), the process proceeds to step S443.

In step S443, display control circuit 230 determines whether or not the used display number is 0, that is, whether or not there is a usable display number. If the used display number is not 0 (YES in step S443), that is, if there is a usable display number, display control circuit 230 proceeds to step S444. On the other hand, if the used display number is 0 (NO in step S443), that is, if there is no usable display number, display control circuit 230 proceeds to step S459.

By the way, the pachinko gaming machine 1 of the present embodiment is provided with two frame buffers as frame buffers in which compositions are registered. These two frame buffers are used by switching the function of one frame buffer from the drawing function to the display function and switching the function of the other frame buffer from the display function to the drawing function by bank flipping. Hereinafter, in this specification, a frame buffer having a display function will be simply referred to as a "frame buffer", and a frame buffer having a drawing function will be referred to as a "drawing result output destination buffer".

In step S444, the display control circuit 230 determines whether or not a composition is registered in the drawing result output destination buffer. It should be noted that in the determination processing of step S444, it is determined whether or not all compositions have been registered (that is, whether or not there are any unregistered compositions). If all compositions are registered in the drawing result output destination buffer (YES in step S444), the display control circuit 230 sets a drawing target (step S445). Setting a drawing target is a process of setting a display on which drawing is to be performed. If no composition is registered in the drawing result output destination buffer (NO in step S444), that is, if there is an unregistered composition, display control circuit 230 proceeds to step S450.

In step S446, the display control circuit 230 sets the drawing result output destination buffer to the frame buffer. That is, the process of step S446 is a process of switching the drawing result output destination buffer to the frame buffer by bank flipping. At this time, the composition registered in the drawing result output destination buffer switched from the frame buffer is cleared. After that, the display control circuit 230 determines whether or not there is a pause flag in the composition registered in the frame buffer switched from the drawing output destination buffer by the bank flip in step S446 (step S447). The pause flag is a debug function flag for pausing the image, and if the pause flag is present (YES in step S447), the display control circuit 230 registers composition reproduction information in the drawing output destination buffer switched from the frame buffer by the bank flip in step S446 (step S448) and reproduces the composition (step S449). On the other hand, if there is no pause flag (NO in step S447), the process moves to step S459. The composition playback information includes, for example, the size of the frame buffer, the size of the composition, the coordinates of the four vertices of the image to be played back, the composition registration information, the loop composition to be played back, the length of the composition, the start frame setting, the loop playback flag, and the like. Registration of composition reproduction information means collecting composition reproduction information, and composition reproduction means registering the collected composition reproduction information. When the composition playback information is registered, the previous playback information is cleared.

In step S450, the display control circuit 230 determines whether or not the number of frames reproduced in the drawing result output destination buffer is equal to or greater than the upper limit (that is, whether or not the number of reproduced frames exceeds the number of frames held by the composition). If the number of frames reproduced in the drawing result output destination buffer is not equal to or greater than the upper limit (NO in step S450), the display control circuit 230 proceeds to step S457, registers composition reproduction information in the drawing result output destination buffer (step S457), and reproduces the composition (step S458).

When the display control circuit 230 determines in step S450 that the number of frames reproduced in the drawing result output destination buffer is equal to or greater than the upper limit (YES in step S450), the process proceeds to step S451.

In step S451, the display control circuit 230 determines whether or not the playback mode of the composition registered in the frame buffer is loop playback. If the playback mode of the composition registered in the frame buffer is loop playback (YES in step S451), display control circuit 230 performs playback from the beginning during loop playback (step S452), and then proceeds to step S457. If the playback mode of the composition registered in the frame buffer is not loop playback (NO in step S451), the display control circuit 230 proceeds to step S453.

In step S453, the display control circuit 230 determines whether or not the playback mode of the composition registered in the frame buffer is frame continuation display. If the reproduction mode of the composition registered in the frame buffer is continuous frame display (YES in step S453), display control circuit 230 reproduces the last frame during continuous frame display (step S454), and then proceeds to step S457. If the playback mode of the composition registered in the frame buffer is not continuous frame display (NO in step S453), display control circuit 230 proceeds to step S455.

In step S455, the display control circuit 230 determines whether or not the playback mode of the composition registered in the frame buffer is shot playback. If the playback mode is shot playback (YES in step S455), display control circuit 230 clears the composition during shot playback (step S456), and then proceeds to step S459. If the playback mode of the composition registered in the frame buffer is not shot playback (NO in step S455), display control circuit 230 proceeds to step S457.

Note that the composition playback information registration in step S457 is, in principle, performed when no composition is registered in the drawing result output destination buffer (when NO is determined in step S444). However, as described above, even if the frame buffer switched from the drawing output destination buffer by the bank flip in step S446 has a pause flag (YES in step S447), the display control circuit 230 registers the composition reproduction information in the drawing output destination buffer switched from the frame buffer by the bank flip in step S446 (step S448) and reproduces the composition (step S449). In this way, when the frame buffer switched from the rendering output destination buffer by the bank flip in step S446 has a pause flag (YES in step S447), the composition playback information is immediately registered in the rendering output destination buffer (step S448) and the composition is played back (step S449), so that rapid processing can be performed.

In step S459, display control circuit 230 adds 1 to the determined number of displays, and returns to step S442.

When display control circuit 230 determines in step S442 that the determined number of displays exceeds the upper limit of the number of usable displays (NO in step S442), if there is data to be directly drawn, the display control circuit 230 executes the direct drawing function (step S460). After that, the display control circuit 230 adds 1 to the determined priority number (step S461), and returns to step S441.

As described above, in the composition reproduction control of the present embodiment, in principle, reproduction information of a new composition is not registered while a composition is registered in the drawing output destination buffer. However, only when a specific condition is satisfied (when YES is determined in step S447, i.e., when the composition registered in the drawing output destination buffer has a pause flag), it is possible to perform the processing (composition reproduction information registration) when the composition is not registered. That is, in a state in which the composition is registered in the drawing output destination buffer, the composition can be registered again at an arbitrary timing, so depending on the content of the re-registered composition (newly), it is possible to overwrite the effect, skip the effect, or stop the effect.

In addition, the process of step S441 (the process of determining whether the determined priority number is less than (or equal to or less than) the upper limit of the priority number (the process of determining whether the determined number of displays is less than (or less than) the number of usable displays) is a higher order process than the process of step S442. Therefore, by returning from the process of step S459 to step S442 and performing the process, the priority number determined in step S441 can be shared among a plurality of displays. This makes it possible to reduce the processing load.

[Sound amplifier check process]
Next, the sound amplifier check processing shown in FIG. 37 will be described with reference to FIGS. 53 to 55. FIG. In this sound amplifier check process, it is determined whether or not the digital audio power amplifier 262 (hereinafter referred to as "sound amplifier") is in an abnormal state (for example, an overcurrent abnormality, a high temperature abnormality, a DC detection abnormality in which the audio signal does not change, etc.), and confirmation of the setting information of the sound amplifier is performed. FIG. 53 is a flowchart showing an example of sound amplifier check processing. FIG. 54 is a flowchart showing an example of normal amplifier check processing. FIG. 55 is a flowchart showing an example of a deep bass amplifier check process.

The pachinko game machine 1 of this embodiment includes, as sound amplifiers, a normal amplifier for amplifying normal sound data and a deep bass amplifier for amplifying heavy bass sound data.

As shown in FIG. 53, the host control circuit 210 performs normal amplifier check processing (step S471) and deep bass amplifier check processing (step S472).

As shown in FIG. 54, in the normal amp check process, the host control circuit 210 first determines whether or not settings have been made from the binary file (step S481). If there is a binary file at initialization, settings are made from the binary file. The initialization process is executed not only when the power is turned on, but also when a problem is found in the amplifier check and resetting is performed. Also, in the present embodiment, settings are made from a binary file, but the present invention is not limited to this, and any storage area that is different from the read settings, such as a binary file, may be used.

When the host control circuit 210 determines that the settings have been made from the binary file (YES in step S481), it determines whether or not the register serving as the reference of the register value to be checked is normal (step S482), and then proceeds to step S483. In the determination process of step S482, since the register values are checked in order of address, it is determined whether or not there is a register value to start checking, and whether or not the value is normal.

The host control circuit 210 rearranges the received data from the binary file in step S483. After that, the host control circuit 210 compares the value of the RAM of the register with the received data (step S484), and determines whether or not the value of the normal amplifier is normal (step S485). The host control circuit 210 ends the normal amplifier check process after performing the determination process of step S485.

On the other hand, if the settings have not been made from the binary file in step S481 (NO in step S481), the host control circuit 210 performs a process of comparing the default value and the set value (step S486), and ends the normal amplifier check process. After completing the normal amplifier check process, the host control circuit 210 performs a deep bass amplifier check process.

As shown in FIG. 55, in the deep bass amp check process, the host control circuit 210 first determines whether or not the settings have been made from the binary file (step S491).

When the host control circuit 210 determines that the settings have been made from the binary file (YES in step S491), the host control circuit 210 performs processing to determine whether or not the register to be checked is normal (step S492), and then proceeds to step S493.

In step S493, the host control circuit 210 clears the registers 0x17-0x25 with appropriate values (binary file information) in consideration of the case where the values cannot be read due to a hardware failure.

The host control circuit 210 rearranges the received data from the binary file in step S494. Thereafter, the host control circuit 210 compares the RAM value of the register with the received data (step S495), and updates the RAM address (step S496). The host control circuit 210 ends the deep bass amplifier check process after performing the update process in step S496.

On the other hand, if the settings have not been made from the binary file in step S491 (NO in step S491), the host control circuit 210 performs a process of comparing the default value and the set value (step S497), and ends the deep bass amplifier check process.

As described above, in this embodiment, the host control circuit 210 performs the sound amplifier check process in the 1 msec interrupt process. By the way, such sound amplifier check processing can also be performed in the main loop. However, when the sound amplifier check process is performed in the main loop, if the sound amplifier check process takes time, there is a risk that other processes will be pressed. Therefore, by performing the sound amplifier check process in the interrupt process as in the present embodiment, it becomes possible to perform the sound amplifier check process without putting pressure on other processes in the main loop.

Further, the sound amplifier check process shown in the timer interrupt process (see FIG. 37) may be performed in the interrupt process of 1 msec, for example, as shown in FIG. This normal amplifier/heavy bass amplifier (batch) check process (step S497) is a process of collectively performing the normal amplifier check process (see FIG. 54) and the heavy bass amplifier check process (see FIG. 55).

However, if the sound amplifier check process is performed in the interrupt process of 1 msec, there may be a case where the sound amplifier check process cannot be executed in its entirety. Therefore, a more preferred embodiment of the sound amplifier check process will be described with reference to FIGS. 57 to 59. FIG. FIG. 57 is a flow chart showing an example of a more preferable form of sound amplifier check processing. FIG. 58 is a flow chart showing an example of a more preferable form of the normal amplifier/heavy bass amplifier check process. FIG. 59 is a flowchart continued from FIG. 58 showing an example of a more preferable form of the normal amplifier/heavy bass amplifier check process.

In a more preferred embodiment of the sound amplifier check process, as shown in FIG. 57, the host control circuit 210 performs normal amplifier/heavy bass amplifier (division) check process (step S498). This normal amplifier/heavy bass amplifier (divided) check process will be described in detail later, but each check process for the normal amplifier and each check process for the heavy bass amplifier are divided, the check process is performed within the range that can be performed within the interrupt process of 1 msec, and the continuation process is performed in the next and subsequent frames. That is, among all check processing of the normal amplifier and all check processing of the heavy bass amplifier, only a part of check processing is performed in one interrupt processing, but all checks are performed over a plurality of interrupt processings. By doing so, in the interrupt processing, it is possible to execute all of the check processing of the normal amplifier and the check processing of the deep bass amplifier without ending in the middle.

As shown in FIG. 58, in the normal amplifier/heavy bass amplifier (division) check process, the host control circuit 210 first determines whether or not settings have been made from the binary file (step S501).

When the host control circuit 210 determines that the settings have been made from the binary file (YES in step S501), it determines whether the check status is 0 (step S502). If the check status is 0 (YES in step S502), the host control circuit 210 determines whether or not the register value checked by the normal amplifier is normal (step S503). After performing the process of step S503, the host control circuit 210 sets the check status to 1 (step S504), and ends the normal amplifier/heavy bass amplifier (division) check process. When the host control circuit 210 determines that the check status is not 0 in step S502 (NO in step S502), the process proceeds to step S505. In the process of step S503, the determination of whether each register value of a plurality of registers is normal may be further divided for each register.

The host control circuit 210 determines whether the check status is 1 in step S505. If the check status is 1 (YES in step S505), the host control circuit 210 rearranges the received data from the binary file (step S506). After that, the host control circuit 210 compares the value of the RAM of the register of the normal amplifier with the received data (step S507), and determines whether or not the number of divisions of the normal amplifier has been executed (step S508). If the processes for the number of divisions of the normal amplifier have been executed (YES in step S508), the host control circuit 210 sets the check status to 2 (step S509), and ends the normal amplifier/heavy bass amplifier (division) check process. On the other hand, if the processes for the number of divided normal amplifiers have not been executed (NO in step S508), the host control circuit 210 ends the normal amplifier/heavy bass amplifier (division) check process without updating the check status. That is, since the check status is not updated and is maintained at 1, the host control circuit 210 repeats the process when the check status is 1 in the next and subsequent frames. When the host control circuit 210 determines that the check status is not 1 in step S505 (NO in step S505), the process proceeds to step S510. In the process of step S508, the process of comparing the RAM value of each register out of a plurality of registers with the received data may be further divided for each register.

The host control circuit 210 determines whether the check status is 2 in step S510. If the check status is 2 (YES in step S510), the host control circuit 210 determines whether or not the value of the normal amplifier is normal (step S511). After that, the host control circuit 210 determines whether or not the processes for the division number of the normal amplifiers have been executed (step S512). If the number of normal amplifier divisions has been processed (YES in step S512), the host control circuit 210 sets the check status to 3 (step S513), and ends the normal amplifier/heavy bass amplifier (division) check process. On the other hand, if the processes for the division number of the normal amplifier have not been executed (NO in step S512), the host control circuit 210 ends the normal amplifier/heavy bass amplifier (division) check process without updating the check status. That is, since the check status is not updated and is maintained at 2, the host control circuit 210 repeats the processing when the check status is 2 in the next and subsequent frames. When the host control circuit 210 determines that the check status is not 2 in step S510 (NO in step S510), the process proceeds to step S514 (see FIG. 59).

Referring to FIG. 59, host control circuit 210 determines whether or not the check status is 3 in step S514. If the check status is 3 (YES in step S514), the host control circuit 210 determines whether or not the register value checked by the deep bass amplifier is normal (step S515). After that, the host control circuit 210 determines whether or not the processing for the division number of the deep bass amplifier has been executed (step S516). If the processes for the number of divisions of the deep bass amplifier have been executed (YES in step S516), the host control circuit 210 sets the check status to 4 (step S517), and ends the normal amplifier/heavy bass amplifier (division) check process. On the other hand, if the processes for the number of divisions of the deep bass amplifier have not been executed (NO in step S516), the host control circuit 210 ends the normal amplifier/heavy bass amplifier (division) check process without updating the check status. That is, since the check status is not updated and is maintained at 3, the host control circuit 210 repeats the process for the check status of 3 in the next and subsequent frames. If the host control circuit 210 determines in step S514 that the check status is not 3 (NO in step S514), the process proceeds to step S518.

The host control circuit 210 determines whether the check status is 4 in step S518. If the check status is 4 (YES in step S518), the host control circuit 210 clears the register value of the deep bass amplifier with an appropriate value (step S519). Thereafter, the host control circuit 210 sets the check status to 5 (step S520), and ends the normal amplifier/heavy bass amplifier (division) check process. When the host control circuit 210 determines in step S518 that the check status is not 4 (NO in step S518), the process proceeds to step S521.

The host control circuit 210 determines whether the check status is 5 in step S521. If the check status is 5 (YES in step S521), the host control circuit 210 rearranges the received data from the binary file (step S522). After that, the host control circuit 210 compares the RAM value of the register of the heavy bass amplifier with the received data (step S523), and updates the RAM address (step S524). After that, the host control circuit 210 determines whether or not the processing for the division number of the deep bass amplifier has been executed (step S525). If the processing for the number of divisions of the deep bass amplifier has been executed (YES in step S525), the host control circuit 210 determines whether or not the update of the RAM address is completed (step S526), sets the check status to 0 (step S527), and ends the normal amplifier/heavy bass amplifier (division) check process. In step S525, when the processing for the number of divisions of the heavy bass amplifier has not been executed (NO in step S525), and when it is determined in step S526 that the RAM address update has not been completed (NO in step S526), the host control circuit 210 ends the normal amplifier/heavy bass amplifier (division) check process without updating the check status. That is, since the check status is not updated and is maintained at 5, the host control circuit 210 repeats the process for the check status of 5 in the next and subsequent frames. When the host control circuit 210 determines that the check status is not 5 in step S521 (NO in step S521), it ends the normal amplifier/heavy bass amplifier (division) check process.

In this way, in a more preferred embodiment of the sound amplifier check process, each check process for the normal amplifier and each check process for the deep bass amplifier are divided, and the check process is performed within a range that can be performed within a 1 msec interrupt process (that is, within one frame), and the subsequent process is performed in the next and subsequent frames. In this way, since part of the check processing of the normal amplifier and part of the check processing of the deep bass amplifier are performed over a plurality of frames in one frame, it is possible to perform all of the check processing of each amplifier over a plurality of frames.

When the check status is 4, the host control circuit 210 does not determine whether or not the processes for the number of divisions have been executed (for example, if the check status is 3, the process of step S516 corresponds). This is because the process of step S519, which is performed when the check status is 4, can be performed in such a short time as not to affect the 1 msec interrupt process. In other words, the process performed when the check status is 4 (step S519) includes the process performed when the check status is 0 (step S503), the process performed when the check status is 1 (steps S506 and S507), the process performed when the check status is 2 (step S511), the process performed when the check status is 3 (step S515), and the process performed when the check status is 5 (steps S522 to S52). This is because the time required for processing is shorter than in 4) and does not affect the 1 msec interrupt processing. Thus, in the pachinko gaming machine 1 of the present embodiment, it is decided whether or not to determine whether or not the processing for the number of divisions has been executed in consideration of the time required for processing (whether or not the interrupt processing of 1 msec is affected). However, even for processing that does not affect the 1 msec interrupt processing (for example, processing such as step S519 that is performed when the check status is 4), it may be determined whether or not the processing for the number of divisions has been executed.

It should be noted that the processes of steps S503, S511, and S515 may be performed by further dividing the determination of whether or not each register value out of a plurality of registers is normal for each register. In this case, the progress of further divided judgments may be managed by the second check status. That is, the progress of the processing can be managed by the check status (first check status) related to the large category processing shown in FIGS. 58 and 59 and the check status (second check status) related to the small category processing that is further divided from the large category processing. Similarly, in each of the processes of steps S506-S507 and steps S522-S523, the process of comparing the RAM value of each register out of a plurality of registers with the received data may be further divided for each register. In this case, the progress of further divided processing may be managed by the second check status. That is, the progress of the processing can be managed by the check status (first check status) related to the large category processing shown in FIGS. 58 and 59 and the check status (second check status) related to the small category processing that is further divided from the large category processing. For example, even if a power failure occurs in the middle of small classification processing or judgment, the progress of small classification processing or judgment may be checked by the first check status and the second check status after the power is restored, and control may be performed to restart each processing or judgment.

Also, the check status can be set to 0 when the power is turned on, and when the power is interrupted during processing, the check status can be set to the previous power interruption after the power is restored. Of course, if power failure occurs, power is turned on, or backup clear (RAM clear) processing is performed, the check status may be set to 0 after power is restored, and all processing and determination may be performed again (or all processing and determination or part of processing and determination may be performed again as one of initialization processing).

[Sound request control processing (when there are multiple sound requests for the same channel)]
Next, regarding the sound request control processing shown in FIG. 36, the sound request control processing when there are a plurality of sound requests (also called SAC requests) for the same channel will be described with reference to FIG. FIG. 60 is a flow chart showing an example of sound request control processing when there are multiple sound requests for the same channel.

In the pachinko machine 1 of the present embodiment, when a plurality of SAC requests are made to the same playback channel in the same frame of the main loop performed at a cycle of 33.3 msec, a mute command of, for example, 2 msec is added between SAC requests for registration. As a result, it is possible to prevent the game sound output based on the SAC request from being overlaid with other game sounds, and it is possible to output the game sound with high precision. However, in this case, although there is an advantage that the game sound is not overwritten, there is a possibility that the processing may take time. Therefore, in the pachinko game machine 1 of the present embodiment, when a plurality of SAC numbers are specified (registered) in the same virtual track in the same frame of the main loop, a case of making a later-arriving SAC request with an interval from the first-arriving SAC request and a case of making a later-arriving SAC request without an interval from the first-arriving SAC number are provided. Specifically, it will be described below.

As shown in FIG. 60, in the sound request control process (when there are multiple sound requests for the same channel), the host control circuit 210 first confirms the SAC number and playback channel (step S541), and then proceeds to step S542.

In step S542, host control circuit 210 determines whether there are multiple SAC requests for the same playback channel. For example, since the SAC numbers are different for SHOT reproduction and LOOP reproduction, there are cases where a plurality of SAC numbers are specified for the same reproduction channel without intervals. If there are multiple SAC requests for the same playback channel (YES in step S542), host control circuit 210 proceeds to step S543. On the other hand, if there are not a plurality of SAC requests for the same playback channel (NO in step S542), the sound request control process is terminated. In this embodiment, one virtual track corresponds to one playback channel, so the determination processing in step S542 is synonymous with determining whether or not there is a SAC request for the same virtual track. That is, the 'track' is an interface for decoding and playing back the 'phrase', and the 'playback channel' is the concept for playing back the 'phrase'. That is, when a "playback channel" is specified and a "phrase" is requested to be played back, the phrase is assigned to the corresponding "track" and played back. A "virtual track" is an "interface for phrase playback control". There are 128 channels of virtual tracks, which can be automatically distributed to 32 channels of phrase playback channels. However, since this function is not used in this embodiment, "virtual tracks" = "playback channels."

In step S543, host control circuit 210 determines whether or not SHOT reproduction and LOOP reproduction are chained. If SHOT playback and LOOP playback are chained (YES in step S543), host control circuit 210 executes the SAC request for LOOP playback after one frame (33.3 msec) (step S544), and ends the sound request control process. In the case of chain reproduction of SHOT reproduction and LOOP reproduction, by executing the SAC request of LOOP reproduction with a delay of one frame, it is possible to prevent the sound of SHOT reproduction from being overwritten and to prevent the sound of SHOT reproduction from being difficult to hear. On the other hand, if it is not a chain reproduction of SHOT reproduction and LOOP reproduction (NO in step S543), host control circuit 210 proceeds to step S545.

The host control circuit 210 determines in step S545 whether or not the mute command between SACs is a mute setting for all reproduction channels. For example, when the variable display of special symbols and decorative symbols ends, etc., a mute command is uniformly set between SACs for all reproduction channels. Then, if the mute command between SACs is a mute setting for all reproduction channels (YES in step S545), the host control circuit 210 sets the SAC data corresponding to the later-arriving SAC request without overwriting the mute command on the SAC data corresponding to the first-arriving SAC request so that the mute is executed (step S546), and ends the sound request control process. On the other hand, if the mute command between SACs is not mute setting for all reproduction channels (NO in step S545), the mute command for each reproduction channel is overwritten with SAC data corresponding to the SAC request that arrives later and set (step S547), and the sound request control processing is terminated.

As described above, in the pachinko machine 1 of the present embodiment, when a plurality of SAC requests are made to the same reproduction channel in the same frame of the main loop, and the plurality of SAC requests are chain reproduction of SHOT reproduction and LOOP reproduction, the SAC number of LOOP reproduction is delayed by one frame (for example, 33.3 msec) so as not to overlap the sound of LOOP reproduction with respect to SHOT reproduction. SHOT reproduction is, for example, reproduction of a phrase once, and LOOP reproduction is, for example, LOOP reproduction (reproduction of a plurality of times) of a phrase.

When the mute command between SACs is mute setting for all reproduction channels, the SAC data corresponding to the SAC number is registered without overwriting the later arriving SAC data with the mute command so that the mute is executed. Thereby, for example, when the variable display of the special symbol ends, it is possible to secure the time until the variable display of the next special symbol is started. Furthermore, when the mute command between SACs is not mute setting for all reproduction channels, the mute command for each reproduction channel is overwritten with the SAC data corresponding to the later arriving SAC request so that mute is not executed. In this way, by executing or not muting the sound depending on the situation, the promptness of the processing (promptness by overwriting the muting) can be ensured while making use of the game sound effect of the muting.

[Sound request control processing (when volume is adjusted)]
Next, with respect to the sound request control processing shown in FIG. 36, variations of the sound request control processing when volume adjustment is performed will be described. In this specification, as variations of sound request control processing when volume adjustment is performed, five variations of first to fifth embodiments will be described with reference to FIGS. 61 to 65, respectively. FIG. 61 is a flowchart showing a first embodiment of sound request control processing when volume adjustment is performed. FIG. 62 is a flow chart showing a second embodiment of sound request control processing when volume adjustment is performed. FIG. 63 is a flow chart showing a third embodiment of sound request control processing when volume adjustment is performed. FIG. 64 is a flow chart showing a fourth embodiment of sound request control processing when volume adjustment is performed. FIG. 65 is a flowchart showing a fifth embodiment of sound request control processing when volume adjustment is performed.

(First embodiment)
As shown in FIG. 61, in the first embodiment of the sound request control process (when the volume is adjusted), the host control circuit 210 first performs the input process of the audio data specified by the SAC number (step S551). After that, the process moves to step S552. The SAC number is registered for each channel by the host control circuit 210. FIG.

In step S552, host control circuit 210 designates a speaker as an output destination based on the audio data designated by the SAC number, and proceeds to step S553. In this first embodiment, the audio data specified by the SAC number incorporates information about which speaker is to be used for output. Speakers include, for example, a general-purpose speaker (used for outputting normal sounds other than specific sounds) and a dedicated speaker (for example, a deep bass speaker) used for outputting specific sounds (such as error sounds and warning sounds). Note that the host control circuit 210 sets which of the plurality of speakers is to be the dedicated speaker in various initialization processes (see, for example, various initialization processes (step S201) in FIG. 36).

In step S553, the host control circuit 210 determines whether volume control is performed by a hardware switch. If it is volume control by the hardware switch (YES in step S553), volume control by the hardware switch (see reference numeral 281 in FIG. 9) is performed (step S554), and the process proceeds to step S556. On the other hand, if the volume is not controlled by the hardware switch (NO in step S553), user volume control (see reference numeral 282 in FIG. 9) is performed (step S555), and the process proceeds to step S556.

In step S556, the host control circuit 210 performs debug volume control during debugging (see reference numeral 283 in FIG. 9), and then proceeds to step S557.

In step S557, the host control circuit 210 determines whether or not the volume control is for a specific sound. The specific sound corresponds to a sound that should not be affected by volume adjustment, such as an error sound. Further, the audio data instructed by the SAC number incorporates information indicating that the output destination of the normal sound is the shared speaker and information indicating that the output destination of the specific sound is the dedicated speaker.

If it is determined in step S558 that the volume control is not for the specific sound (NO in step S557), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for the normal sound set for the channel (step S558), and proceeds to step S560. In the volume control in step S558, control is performed to change the volume according to the volume adjustment.

On the other hand, if it is determined in step S557 that the volume control is for the specific sound (YES in step S557), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set in the channel (step S559), and proceeds to step S560. In the volume control in step S559, regardless of whether or not volume adjustment has been performed, control is performed to output a constant volume without being affected by the volume adjustment (that is, even if a volume change operation is performed, control is performed to output a constant volume before and after the operation is performed).

In step S560, the host control circuit 210 determines whether volume control has been performed for the number of channels (32 channels from 1CH to 32CH in this embodiment).

If volume settings for the number of channels have been performed in step S560 (YES in step S560), volume control incorporated in the audio data specified by the SAC number is performed (step S561), and the sound request control process ends.

If volume control for the number of channels has not been performed in step S560 (NO in step S560), the host control circuit 210 returns to step S557, and the processing of steps S557 to S560 is performed until volume control for the number of channels is performed (until YES is determined in step S560). Although not shown in FIG. 61, considering that the SAC number is specified for each channel, it is preferable to perform volume control for the number of channels in step S561 as well.

(Second embodiment)
As shown in FIG. 62, in the second embodiment of the sound request control process (when the volume is adjusted), the host control circuit 210 first performs the input process of the audio data designated by the SAC number (step S571). After that, the process moves to step S572. The SAC number is registered for each channel by the host control circuit 210. FIG.

In the second embodiment, for example, a shared channel for general use (used for outputting normal sounds other than specific sounds) and a dedicated channel used for outputting specific sounds (error sounds, warning sounds, etc.) are prepared. The host control circuit 210 sets dedicated channels (CH31, CH32) used for outputting specific sounds among a plurality of channels (1 to 32CH) and shared channels (CH1 to CH30) used for sounds other than specific sounds in various initialization processes (see, for example, various initialization processes (step S201) in FIG. 36).

In step S572, the host control circuit 210 determines whether volume control is performed by a hardware switch. If it is volume control by the hardware switch (YES in step S572), volume control by the hardware switch (see reference numeral 281 in FIG. 9) is performed (step S573), and the process proceeds to step S575. On the other hand, if the volume is not controlled by a hardware switch (NO in step S572), user volume control (see reference numeral 282 in FIG. 9) is performed (step S574), and the process proceeds to step S575.

In step S576, the host control circuit 210 performs debug volume control during debugging (see reference numeral 283 in FIG. 9), and then proceeds to step S576.

The host control circuit 210 determines in step S576 whether or not the volume control is for a specific sound. Also in the second embodiment, the specific sound corresponds to a sound that should not be affected by volume adjustment, such as an error sound.

If it is determined in step S576 that the volume control is not for the specific sound (NO in step S576), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for the normal sound set for the channel (step S577), and proceeds to step S578. In the volume control in step S577, control is performed to change the volume according to the volume adjustment.

On the other hand, if it is determined in step S576 that the volume control is for the specific sound (YES in step S576), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set for the channel (step S579), and proceeds to step S582. In the volume control in step S579, regardless of whether or not volume adjustment has been performed, control is performed such that a constant volume is output without being affected by the volume adjustment (that is, even if a volume change operation is performed, a constant volume is output before and after the operation is performed).

The host control circuit 210 determines in step S578 whether or not the playback is on a playback channel that is not affected by volume adjustment. If the playback is on a playback channel (eg, CH31, CH32) that is not affected by volume adjustment (YES in step S578), a constant volume is specified (step S580). If playback is performed on a playback channel (eg, CH1 to CH30) subject to volume adjustment (NO in step S578), the volume is set according to the user volume (step S581). When the process of step S580 ends or the process of step S581 ends, the host control circuit 210 proceeds to step S582.

In step S582, the host control circuit 210 determines whether volume control has been performed for the number of channels (32 channels from 1CH to 32CH in this embodiment).

If volume settings for the number of channels have been performed in step S632 (YES in step S582), volume control incorporated in the audio data specified by the SAC number is performed (step S583), and the sound request control process ends.

If the volume control for the number of channels has not been performed in step S582 (NO in step S582), the host control circuit 210 returns to step S576, and the processing of steps S576 to S582 is performed until the volume control for the number of channels is performed (until YES is determined in step S582). Although not shown in FIG. 62, it is preferable to perform volume control for the number of channels in the process of step S583 as well.

(Third embodiment)
As shown in FIG. 63, in the third embodiment of the sound request control process (when the volume is adjusted), the host control circuit 210 first performs the input process of the audio data specified by the SAC number (step S591). After that, the process moves to step S592.

In step S592, the host control circuit 210 determines whether volume control is performed by a hardware switch. If it is volume control by the hardware switch (YES in step S592), volume control by the hardware switch (see reference numeral 281 in FIG. 9) is performed (step S593), and the process proceeds to step S595. On the other hand, if the volume is not controlled by a hardware switch (NO in step S592), user volume control (see reference numeral 282 in FIG. 9) is performed (step S594), and the process proceeds to step S595.

In step S595, the host control circuit 210 performs debug volume control during debugging (see reference numeral 283 in FIG. 9), and then proceeds to step S596.

In step S596, the host control circuit 210 determines whether or not the volume control is for a specific sound. Also in the third embodiment, the specific sound corresponds to a sound that should not be affected by volume adjustment, such as an error sound.

If it is determined in step S596 that the volume control is not for the specific sound (NO in step S596), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for the normal sound set for the channel (step S597), and proceeds to step S599. In the volume control in step S597, control is performed to change the volume according to the volume adjustment.

On the other hand, if it is determined in step S596 that the volume control is for the specific sound (YES in step S596), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set in the channel (step S598), and proceeds to step S599. In the volume control in step S598, regardless of whether or not volume adjustment has been performed, control is performed such that a constant volume is output without being affected by the volume adjustment (that is, even if a volume change operation is performed, a constant volume is output before and after the operation is performed).

In step S599, the host control circuit 210 determines whether the data currently in the playback channel (the data being played back) is data that will not be affected by volume adjustment. If the data in the playback channel is data that is not affected by volume adjustment (YES in step S599), a constant volume is specified for the next playback channel (step S600). If the data in the reproduction channel is data subject to volume adjustment (NO in step S599), the next time, the volume corresponding to the volume adjustment is set in the reproduction channel (step S601). When the process of step S600 ends or the process of step S601 ends, the host control circuit 210 proceeds to step S602.

In step S602, the host control circuit 210 determines whether volume control has been performed for the number of channels (32 channels from 1CH to 32CH in this embodiment).

If volume settings for the number of channels have been performed in step S602 (YES in step S602), volume control incorporated in the audio data specified by the SAC number is performed (step S603), and the sound request control process ends.

If the volume control for the number of channels has not been performed in step S602 (NO in step S602), the host control circuit 210 returns to step S599, and the processing of steps S599 to S602 is performed until the volume control for the number of channels is performed (until YES is determined in step S602). Although not shown in FIG. 63, it is preferable to perform volume control for the number of channels in the process of step S603 as well.

In the third embodiment, in step S599, it is determined whether or not the data currently in the reproduction channel (the data being reproduced) is data that is not affected by the volume adjustment. If the determination result in step S599 is YES, the next reproduction channel is set to a constant volume (step S600), and if the determination result in step S599 is NO, the next reproduction channel is set to a volume corresponding to the volume adjustment. That is, in this modification, as the processing in the next step after steps S597 and S598, after confirming whether or not the audio data set this time and the audio data already being reproduced on the reproduction channel to which the audio data is set are data that will not be affected by the volume adjustment, processing is performed to determine whether or not the volume adjustment setting of the current audio data is the same as the previous volume adjustment setting of the audio data. When the volume adjustment setting of the current audio data is the same as the setting of the volume adjustment of the previous audio data, a process of determining whether or not the data is unaffected by the volume adjustment is performed. When the setting of the volume adjustment of the current audio data is not the same as the setting of the previous volume adjustment of the audio data, the setting of the volume adjustment of the audio data set this time is performed, and then the processing is shifted to discriminate whether or not the data are not affected by the volume adjustment. The process proceeds to determine whether the data is unaffected by volume adjustment. Then, when the data are not affected by the volume adjustment, a process of setting a constant volume to the reproduction channel is performed, and when the data are the data affected by the volume adjustment, a process of setting the volume corresponding to the volume adjustment to the reproduction channel is performed. After that, as in step S602, it is preferable to move to the process of determining whether or not the number of channels has been set. In this modified example, the only processing that differs from the third embodiment is the processing described above, and other processing is the same as the processing of the third embodiment (the processing of steps S592 to S598, the processing of steps S602, and the processing of steps S603 shown in FIG. 63).

(Fourth embodiment)
As shown in FIG. 64, in the fourth embodiment of the sound request control process (when volume adjustment is performed), host control circuit 210 first checks whether the SAC number is affected by volume adjustment (step S611). After that, the process moves to step S612.

In step S612, the host control circuit 210 updates the flag indicating whether or not the SAC number is affected by the volume adjustment, and inputs the audio data specified by the SAC number (step S613). Specifically, if the SAC number is affected by volume adjustment, the flag is set to ON (if the SAC number is not affected by volume adjustment, the flag is OFF).

In step S614, the host control circuit 210 determines whether volume control is performed by a hardware switch. If it is volume control by the hardware switch (YES in step S614), volume control by the hardware switch (see reference numeral 281 in FIG. 9) is performed (step S615), and the process proceeds to step S617. On the other hand, if the hardware switch is not used for volume control (NO in step S614), user volume control (see reference numeral 282 in FIG. 9) is performed (step S610), and the process proceeds to step S617.

In step S617, the host control circuit 210 performs debug volume control during debugging (see reference numeral 283 in FIG. 9), and then proceeds to step S618.

In step S618, the host control circuit 210 determines whether or not volume control is performed for a specific sound. Also in the fourth embodiment, the specific sound corresponds to a sound that should not be affected by volume adjustment, such as an error sound.

If it is determined in step S618 that the volume control is not for the specific sound (NO in step S618), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for the normal sound set for the channel (step S619), and proceeds to step S620. In the volume control in step S619, control is performed to change the volume according to the volume adjustment.

On the other hand, if it is determined in step S618 that the volume control is for the specific sound (YES in step S618), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set for the channel (step S622), and proceeds to step S624. In the volume control in step S622, regardless of whether or not volume adjustment is performed, control is performed to output a constant volume without being affected by the volume adjustment (that is, even if a volume change operation is performed, control is performed to output a constant volume before and after the operation is performed).

In step S620, the host control circuit 210 determines whether or not the playback is on a playback channel that is not affected by volume adjustment. That is, it is determined whether or not the flag is set to ON in step S612. If the playback is on a playback channel that is not affected by volume adjustment (YES in step S620), a constant volume is specified for the playback channel (step S621), and the process moves to step S624. If the reproduction is not on the reproduction channel that is not affected by the volume adjustment (NO in step S620), the volume corresponding to the volume adjustment is set for the reproduction channel (step S623), and the process proceeds to step S624.

In step S624, the host control circuit 210 determines whether volume control has been performed for the number of channels (32 channels from 1CH to 32CH in this embodiment).

If volume settings for the number of channels have been performed in step S624 (YES in step S624), volume control incorporated in the audio data specified by the SAC number is performed (step S625), and the sound request control process ends.

If volume control for the number of channels has not been performed in step S624 (NO in step S624), the host control circuit 210 returns to step S618, and the processing of steps S618 to S624 is performed until volume control for the number of channels is performed (until YES is determined in step S624). Although not shown in FIG. 64, it is preferable to perform volume control for the number of channels in the process of step S625 as well.

(Fifth embodiment)
As shown in FIG. 65, in the fifth embodiment of the sound request control process (when the volume is adjusted), the host control circuit 210 first performs the input process of the audio data specified by the SAC number (step S631). After that, the process moves to step S632.

The host control circuit 210 confirms whether the audio data is audio data whose volume is adjusted for each channel (step S633). Specifically, if the audio data specified by the SAC number is audio data that is affected by volume adjustment, the flag is set to ON (if the audio data specified by the SAC number is audio data that is not affected by volume adjustment, the flag is OFF).

In step S633, the host control circuit 210 determines whether volume control is performed by a hardware switch. If it is volume control by the hardware switch (YES in step S633), volume control by the hardware switch (see reference numeral 281 in FIG. 9) is performed (step S634), and the process proceeds to step S636. On the other hand, if the volume is not controlled by a hardware switch (NO in step S633), user volume control (see reference numeral 282 in FIG. 9) is performed (step S635), and the process proceeds to step S636.

In step S636, the host control circuit 210 performs debug volume control during debugging (see reference numeral 283 in FIG. 9), and then proceeds to step S637.

In step S637, the host control circuit 210 determines whether or not the volume control is for a specific sound. Also in the fifth embodiment, the specific sound corresponds to a sound that should not be affected by volume adjustment, such as an error sound.

If it is determined in step S637 that the volume control is not for the specific sound (NO in step S637), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for the normal sound set in the channel (step S638), and proceeds to step S639. In the volume control in step S638, control is performed to change the volume according to the volume adjustment.

On the other hand, if it is determined in step S637 that the volume control is for the specific sound (YES in step S637), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set in the channel (step S641), and proceeds to step S643. In the volume control in step S641, regardless of whether or not volume adjustment has been performed, control is performed such that a constant volume is output without being affected by the volume adjustment (that is, even if a volume change operation is performed, a constant volume is output before and after the operation is performed).

The host control circuit 210 determines in step S639 whether or not the channel is not affected by volume adjustment. That is, it is determined whether or not the flag is set to ON in step S632. If the channel is not affected by volume adjustment (YES in step S639), a constant volume is set for the playback channel (step S641). If the channel is affected by the volume adjustment (NO in step S639), the volume corresponding to the volume adjustment is set for the reproduction channel (step S642). When the process of step S641 ends or when the process of step S642 ends, the host control circuit 210 proceeds to step S643.

In step S643, the host control circuit 210 determines whether volume control has been performed for the number of channels (32 channels from 1CH to 32CH in this embodiment).

If volume settings for the number of channels have been performed in step S643 (YES in step S643), volume control incorporated in the audio data specified by the SAC number is performed (step S644), and the sound request control process ends.

If volume control for the number of channels has not been performed in step S643 (NO in step S643), the host control circuit 210 returns to step S637, and the processing of steps S637 to S643 is performed until volume control for the number of channels is performed (until YES is determined in step S643). Although not shown in FIG. 65, it is preferable to perform volume control for the number of channels in the process of step S644 as well.

According to the sound request control process (first embodiment to fifth embodiment) when the volume is adjusted as described above, when the volume is adjusted, it is possible to easily perform voice control such that when the volume is adjusted, the volume corresponding to the volume adjustment is output for normal sounds, and for example, for serious specific sounds such as error sounds, a constant volume is output from the speaker even if the volume is adjusted.

[LED luminance adjustment processing]
Next, brightness adjustment of the LED will be described with reference to FIGS. 36 and 66. FIG. FIG. 66 is an attenuation table showing an example of the luminance attenuation value of each color (red, green, blue) according to the luminescence intensity of the strong, medium, and weak LEDs. This attenuation table is stored in the sub-main ROM 205 (see FIG. 6, for example).

The pachinko gaming machine 1 of the present embodiment is configured such that the brightness of the LED can be adjusted in three steps by, for example, a player's operation. Specifically, when the luminance adjustment operation is performed on the luminance setting screen displayed on the liquid crystal display device used as the display device 13, the host control circuit 210 performs switching processing of the attenuation table shown in FIG. For example, when an operation is performed to change from high to medium among the three levels of luminance, the host control circuit 210 performs processing for switching the reference table from high to medium in the attenuation table of FIG.

The LED whose brightness can be adjusted by the player's operation may be, for example, an LED provided on the glass door 4 (see, for example, FIG. 3), or may be, for example, a backlight of a liquid crystal display device used as the display device 13. Note that the brightness adjustment of the LED is not limited to three steps, and may be configured to be adjustable in more steps, for example.

The output value of the LED is represented by Equation (1) below.
Output value of LED=Luminance value based on LED data×(100−Luminance attenuation value)/100 Expression (1)
The output value of the LED in the above formula (1) can also be set for each reproduction channel of the LED. It should be noted that the parameter changed by the player's operation is the brightness attenuation value. For example, when the luminance attenuation value is 0, the luminance is the strongest, and when the luminance attenuation value is 100, the luminance is the weakest and is turned off. Also, the calculation of the output value of the LED is performed inside the sequencer 226b (see FIG. 7).

The LED data table, which defines the LED data and playback patterns, is created by creating a BLD file (LED animation) using tools such as ActiveLED (UE) and LEDMaker (UE), adding information to the created BLD file, and converting the LED list (Excel macro) (UE).

By the way, in the case of a three-primary full-color LED, if the luminance attenuation values of red, green, and blue are uniformly set to be the same, the white balance may be disturbed, and, for example, white may become yellow. For example, when the brightness of the LED is lowered, the brightness attenuation value of blue needs to be maximized among red, green, and blue, and it is preferable that the brightness attenuation value of red is minimized.

Therefore, in the pachinko gaming machine 1 of the present embodiment, even if the brightness of the LED is changed by the player's operation, for example, the brightness attenuation value is set for each of the 1024 ports, so that the white balance can be maintained as much as possible.

Specifically, when the brightness of the LED is adjusted to one of high, medium, and low by the operation of the player or the like, the sound/LED control circuit 220 refers to the attenuation table in FIG. 66 and controls the brightness of the LED based on the brightness attenuation values set for each of red, green, and blue. Since the attenuation table is prepared for, for example, 1024 ports (each LED), an attenuation value can be set for each port.

For example, when the brightness of the LED is set high by the operation of the player or the like, the sequencer 226b of the audio/LED control circuit 220 substitutes the red brightness attenuation value of 0, the green brightness attenuation value of 5, and the blue brightness attenuation value of 25 into the above equation (1) to calculate the output value of the LED. Similarly, the sequencer 226b of the audio/LED control circuit 220 substitutes the red luminance attenuation value 50, the green luminance attenuation value 53, and the blue luminance attenuation value 63 into the above equation (1) when the LED luminance is set to medium by the player's operation, and substitutes the red luminance attenuation value 80, the green luminance attenuation value 81, and the blue luminance attenuation value 85 into the above equation (1) when the LED luminance is set to low by the player's operation. and calculate the output value of the LED. Then, the audio/LED control circuit 220 controls light emission of the LED based on the output value of the LED thus calculated.

In this way, the audio/LED control circuit 220 calculates the output value of the LED based on the luminance attenuation value set corresponding to each of red, green, and blue, and controls the light emission of the LED based on the calculated output value of the LED, thereby making it possible to maintain the white balance as much as possible even if the luminance of the LED is changed by the operation of the player or the like.

[Accessory solenoid control process]
Next, the accessory solenoid control process will be described with reference to FIGS. 36, 37 and 67. FIG. FIG. 67 is a block diagram showing an example of a connection state between an LED port, an LED, and a solenoid.

In the pachinko game machine 1 of the present embodiment, for example, the movements of movable bodies (accessories) provided in the game area are diversified, and control of the movable bodies is complicated accordingly. Therefore, for simple movements among the wide variety of movements of the movable body, the control load of the movable body is suppressed by operating the members that make up the accessory with a solenoid or providing a locking mechanism on the accessory. Upon receiving a request for motor operation, the accessory driver sequentially outputs the contents of the motor operation data. The output of the motor driver and the determination of the end of motor operation are performed by timer interrupt processing of 1 msec as shown in FIG. In the timer interrupt process, output determination and end determination of the accessory motor (that is, determination of start and end) are performed, and synchronous control of a plurality of motors is also performed.

In addition, as shown in FIG. 67, the sound/LED control circuit 220 of the pachinko game machine 1 of the present embodiment controls the emission of the frame-side LEDs and the board-side LEDs (for example, the LEDs arranged on the game board 12 and the backlight of the liquid crystal display device used as the display device 13) connected to each LED port, via LED drivers, based on commands from the host control circuit 210. Of the LED ports (Port0 to Port23) controlled by the LED driver, the solenoid is connected to Port6, and the LEDs are connected to the other ports.

The audio/LED control circuit 220 receives a command from the host control circuit 210 and causes the LEDs connected to the ports of the frame-side LED and the board-side LED to emit light via the LED driver. As a result, even if the number of solenoids increases due to the diversification of the movement of the character, it is possible to suppress the control load for operating the character while maintaining the diversity of the movement of the character.

By the way, when the operation of the solenoid is executed via the LED driver as shown in FIG. 67, it is necessary to synchronously control the motor that operates the accessory and the operation of the solenoid. It should be noted that the operation of the accessory, including synchronous control of a plurality of motors, is performed by interrupt processing of 1 msec.

Therefore, in the pachinko game machine 1 of the present embodiment, a control code is added to the role product sequence table, and a value larger than 0 is set to the control code when synchronous control of the solenoid and a plurality of motors for operating the role product is desired. Then, in the processing of the main loop, the host control circuit 210 acquires the control code of the character being reproduced by the character-thing device (see step S204 in FIG. 36), and when the acquired control code has a value greater than 0, controls the LED port corresponding to the control code (for example, Port 6 to which the solenoid is connected) (see step S205 in FIG. 36). This makes it possible to perform synchronous control of the solenoid and a plurality of motors that operate accessories.

The reason why the control of the LED port corresponding to the control code is executed in the main loop is to avoid affecting the normal LED control executed by 1 msec interrupt processing.

In addition, in the pachinko machine 1 of the present embodiment, solenoids are connected to some of the LED ports (Port0 to Port23). For example, when the brightness of the LEDs is adjusted by the player or the like, the voltage to the solenoid is also reset. Further, when executing a synchronous effect for synchronizing the light emission of the LED and the operation of the solenoid, it is also possible to easily execute such a synchronous effect.

[Data load process]
In the pachinko gaming machine 1 of this embodiment, data load processing is performed as one of various initialization processing (see step S201 in FIG. 36) executed when the power is turned on. Also, data load processing may be performed during the game. These data load processes are data transfers from ROM to RAM or buffers (for example, data transfer from sub-main ROM 205 to SRAM 210b, data transfer from CGROM 206 to built-in VRAM 237 (for example, see FIG. 6)), that is, the process of loading data stored in ROM into RAM or buffers (data load process).

In the above data load processing, if the amount of data to be transferred is large, it takes time to load, and there is a risk that the watchdog will be reset and the data load processing will end. When the watchdog is reset, it is difficult to determine whether the cause of the reset is simply because the amount of data is large and it takes time, or because an error occurred during data loading. In addition, when the data loading process ends, the host control circuit 210 cannot determine whether the loading is completed or the loading is unsuccessful, and continues to wait for the completion of loading, which may result in a state in which automatic recovery is not possible.

Therefore, in this embodiment, when the time required for the data load process exceeds a predetermined upper limit, the data load process is terminated as an error and the data is loaded again. The data loading process will be described below with reference to FIG. FIG. 68 is a flow chart showing an example of data load processing executed by the host control circuit 210 as one of various initialization processing.

As shown in FIG. 68, the host control circuit 210 first sets the upper limit of the transfer time (step S651). Transfer time is the time required to load data from ROM to RAM. Although the upper limit of the transfer time varies depending on the amount of data to be transferred, it is determined by the following formula (2) in this embodiment.
Upper limit of transfer time = (Amount of data transferred per unit time) x (Guideline for transfer time + α) Equation (2)
The amount of data to be transferred per unit time and the estimated transfer time in the above formula (2) may be set in advance based on the amount of data to be transferred, or may be calculated, for example, by the host control circuit 210 based on the amount of data to be transferred. It should be noted that α is the time for allowing a margin for data loading.

When the process of step S651 ends, the host control circuit 210 proceeds to step S652 and starts loading data from ROM to RAM.

After starting data loading (step S652), the host control circuit 210 determines whether or not data loading is completed (step S653). If data loading has not been completed (NO in step S653), the host control circuit 210 proceeds to step S654. On the other hand, if data loading has been completed (YES in step S653), host control circuit 210 ends the data loading process.

In step S654, host control circuit 210 determines whether or not the data transfer time exceeds the upper limit. If the data transfer time does not exceed the upper limit (YES in step S654), the watchdog timer is cleared at regular time intervals (step S655). On the other hand, if the data transfer time exceeds the upper limit (NO in step S654), host control circuit 210 determines that an error has occurred, and executes error processing. The error processing executed here is the processing of resetting the load data by the watchdog reset without clearing the watchdog timer (step S656) and reloading. After that, the host control circuit 210 returns to step S654. That is, when the data transfer time exceeds the upper limit (NO in step S654), reloading is performed as error processing.

In this way, when data load processing is performed, the host control circuit 210 keeps clearing the watchdog timer at regular time intervals while waiting for the completion of loading so that a watchdog reset is not applied during normal loading. However, when the data load processing exceeds a predetermined upper limit, the host control circuit 210 resets the load data and reloads it. As a result, even if the data loading process takes a long time, it is automatically restored by reloading.

[Sub random number processing]
Next, sub-random number processing executed in the main loop by the host control circuit 210 will be described.

The sub-random number processing includes random number initialization processing executed as one of various initialization processing (see step S201 in FIG. 36) when power is turned on, random number periodic update processing executed periodically, and random number acquisition processing executed when random numbers are used. The sub-random number process is different from the lottery of special symbols by the main CPU 71 (see FIG. 5, for example), which is related to the payout of balls. However, the sub-random number processing described below may be applied to the random number processing executed by the main CPU 71 . These sub-random number processes described above will be described with reference to FIGS. 69 to 72. FIG. FIG. 69 is a flowchart showing an example of random number initialization processing executed by the host control circuit 210 as one of various initialization processing. FIG. 70 is a flowchart illustrating an example of random number periodic update processing. 71 is (a) a flowchart showing an example of random number 1 acquisition processing, (b) a flowchart showing an example of random number 2 acquisition processing, (c) a flowchart showing an example of random number 3 acquisition processing, and (d) a flowchart showing an example of random number 4 acquisition processing. FIG. 72 is a flowchart showing an example of random number acquisition processing executed when random numbers are used.

In the pachinko gaming machine 1 of the present embodiment, four random numbers are used (random number 1 to random number 4), and the initialization process for these four random numbers is executed at the same timing as the game data RAM clear, as shown in FIG.

As shown in FIG. 69, in the random number initialization process, the host control circuit 210 first acquires the RTC time (minutes and seconds) (step S671), and then enters a loop for the number of random numbers.

In the random number loop, the host control circuit 210 first creates a random number SEED (step S672). Random number SEED creation in the random number initialization process is executed based on the following equation (3).
SEED (random numbers 1 to 4) = (RTC time (seconds) + (RTC time (minutes) x 60) + random number (random numbers 1 to 4)) x initial prime number Expression (3)

After creating the random number SEED in step S672, the host control circuit 210 stores the random number SEED created in step S672 in the random number backup, ie, the SRAM 210b (see FIG. 6, for example) (step S673). The random number SEED backed up here is the random number SEED created this time, but the information backed up up to the last time may be erased or may be stored continuously.

When the host control circuit 210 executes the processes of steps S672 and S673 for the number of random numbers (four random numbers 1 to 4 in this embodiment), the host control circuit 210 exits the loop for the number of random numbers and terminates the random number initialization process.

Thus, the minutes and seconds of the RTC time are used in the random number initialization process. Therefore, the time when the power is turned on is involved in the random number SEED at the time of initialization to the minute/second unit.

Next, with reference to FIG. 70, random number periodic update processing will be described. The random number periodic update process is a process of periodically updating the random numbers 1 to 4 even if none of the random numbers 1 to 4 are used while waiting for the end of the bank flip shown in FIG.

As shown in FIG. 70, in the random number periodic update process, the host control circuit 210 performs random number 1 acquisition process (step S681), random number 2 acquisition process (step S682), random number 3 acquisition process (step S683), and random number 4 acquisition process (step S684) in this order. The random number periodic update process is always executed while waiting for the end of the bank flip. Also, even if the bank flip end waiting does not occur due to any processing failure in the main loop, the host control circuit 210 performs the random number periodical updating process once in one frame.

As shown in FIG. 71( a ), the random number 1 acquisition process updates the random number 1 (step S 685 ), that is, updates the random number 1 after acquiring the random number 1 . After that, the random number 1 is backed up, that is, the obtained random number 1 is stored in the SRAM 210b (see FIG. 6, for example) (step S686). Similarly, as shown in FIG. 71(b), the random number 2 acquisition process updates the random number 2 (step S687) and backs up the random number 2 (step S688). Similarly, as shown in FIG. 71(c), the random number 3 acquisition process updates the random number 3 (step S689) and backs up the random number 3 (step S690). Similarly, as shown in FIG. 71(d), the random number 4 acquisition process updates the random number 4 (step S691) and backs up the random number 4 (step S692). The random numbers backed up in steps S686, S688, S690, and S692 are the random numbers acquired this time, but the information backed up up to the last time may be erased or stored continuously.

Random numbers 1 to 4 are obtained from random numbers generated within the range of 0 to 32767, but the range of generated random numbers is not limited to this.

As shown in FIG. 72, in the random number acquisition process executed when a random number is used, the host control circuit 210 first performs the random number 3 acquisition process (step S693). This random number 3 acquisition process is a process of acquiring a random number for determining the random number to be used among random number 1, random number 2, and random number 4. FIG. After executing the random number 3 acquisition process in step S693, the host control circuit 210 proceeds to step S694.

In step S694, the host control circuit 210 determines whether the remainder obtained by dividing the random number obtained in the random number 3 obtaining process in step S693 by 4 (hereinafter simply referred to as the "remainder") is 0 or 1. If the remainder is 0 or 1 (YES in step S694), random number 1 acquisition processing is performed (step S695). On the other hand, if the remainder is neither 0 nor 1 (NO in step S694), the process proceeds to step S696.

The host control circuit 210 determines whether or not the remainder is 2 in step S696. If the remainder is 2 (YES in step S696), random number 2 acquisition processing is performed (step S697). On the other hand, if the remainder is not 2 (NO in step S696), the process proceeds to step S698.

Host control circuit 210 determines whether the remainder is 3 in step S698. If the remainder is 3 (YES in step S698), random number 4 acquisition processing is performed (step S699). On the other hand, if the remainder is not 3 (NO in step S698), this means that there are no remainders from 0 to 3, so the process is restarted from step S693.

Random number 1 acquisition processing (step S695), random number 2 acquisition processing (step S697), random number 3 acquisition processing (step S693), and random number 4 acquisition processing (step S699) are all as shown in FIG.

In this way, in the random number acquisition process executed when random numbers are used, although the random numbers selected from random number 1, random number 2, and random number 4 are updated, the random numbers that are not selected are not updated.

In addition, in the Pachinko game machine 1 of the present embodiment, random number initialization processing is performed when the power is turned on, random number acquisition processing is performed for the selected random number when the random number is used, and random number periodical update processing is performed even when bank flip end wait or bank flip end wait does not occur.

The calculation formula for updating random numbers is as shown in formula (4) below.
Current update value = (Previous update value x Prime number of each random number) + 1 Expression (4)
Here, the return value of the random number acquisition process is a value of 0 to 32767 obtained by shifting right from 32 bits to 16 bits. That is, the current update value calculated based on the above equation (4) is represented by 32 bits, and the 32-bit current update value is shifted right from 32 bits and returned to 16 bits. Then, the 16th bit is masked, and the value indicated by the 1st to 15th bits (any one of 0 to 32767) is determined as the update value this time.

By performing the above-described sub-random number processing, it is possible to randomize the acquired random numbers and suppress the occurrence of bias in the acquired random numbers. In particular, the random number SEED at the time of initialization is related to the time when the power is turned on up to the minute/second unit, so the initial value can be changed each time.

[Modified example of sub-random number processing]
Although the sub-random number processing in the present embodiment has been described above, the sub-random number processing (modification) described below may be performed in place of or in combination with the above-described sub-random number processing. Also, the sub-random number processing (modification) described below may be applied to the random number processing executed by the main CPU 71 . A modification of this sub-random number processing will be described with reference to FIGS. 73 and 74. FIG. Note that FIG. 73 is a sub-control main process (overall flow) executed by the host control circuit 210 for explaining a modification of the sub-random number process. However, FIG. 73 shows only the processing necessary for explanation, and omits the other processing. FIG. 74 is a flow chart showing an example of reception interrupt processing executed by the host control circuit 210. FIG.

The host control circuit 210 first performs a random number initialization process (step S701) which is executed as one of various initialization processes (see step S201 in FIG. 36). In this random number initialization process, for example, a power of 2 random number seed and a current random number seed number are prepared, and a predetermined initial value is set in the stack pointer.

After performing the random number initialization process in step S701, the host control circuit 210 enters the main loop, performs sub-device input processing (step S702), and then performs various request control processes (step S703). In this various request control processing (step S703), output is made to various devices based on the request created in step S705 (described later) one frame before.

After performing sub-device input processing (step S702) and various request control processing (step S703), the host control circuit 210 performs random number table creation processing (step S704). In the random number table creation process in step S704, a new random number table is created by updating the random numbers registered in the random number table having a power-of-two size at the drawing timing. For acquisition of the random number registered in the random number table, for example, among power-of-two random number seeds, a random number seed determined based on the current random number seed number is used. For example, if 2 ³ (8) random number seeds a to h are provided, and the current random number seed number is 4, then the random number seed of d is used.

The host control circuit 210 can create a random number table having a size of 2 ⁵ (32), for example, in step S704, and 32 random numbers are registered in this random number table. When the random number is registered in the random number table, the host control circuit 210 updates the value of the random number seed. The random number seed is updated by multiplying the previous update value by a prime number and then adding 1, as in the above equation (4). In this modified example, the size of the random number table may be a power of 2 (number), and 2 ⁵ (32) is used, but any power of 2 (number) may be used.

As shown in FIG. 74, the random number seed used to generate the random number table in step S704 is updated using the value of the CPU counter by the CPU processor of the host control circuit 210 (step S802) when a serial command is received (step S801). In the random number seed update process in step S802, the random number seed number is incremented and the incremented random number seed number is used as the current random number seed number, thereby updating the random number seed used to create the random number table.

Returning to FIG. 73, after performing the random number table creation processing in step S704, the host control circuit 210 enters a packet reception loop.

In the packet reception loop, the host control circuit 210 performs animation construction processing (step S705) for creating a request for animation for moving image effects, and performs random number acquisition processing when random numbers are used (step S706). Note that the request created in step S705 is output in the next frame after waiting in the buffer.

The host control circuit 210 acquires a random number from the random number table created in step S704 in the random number acquisition process of step S706. The random number obtained here is used for a lottery (for example, a lottery for determining an animation for a moving picture effect) related to the effect executed by the host control circuit 210 . When the host control circuit 210 obtains the random number from the random number table in step S706, it updates (increments) the reference position of the random number table. Note that the reference position of the random number table is only performed when a random number is obtained from the random number table, and is not performed in the random number table creation processing in step S704.

The host control circuit 210 repeats the processing of steps S705 and S706 as many packets as received. The host control circuit 210 exits the packet reception loop after performing the processing of steps S705 and S706 for the number of packets received.

After exiting the packet reception loop, the host control circuit 210 performs animation update processing (step S707), and then performs bank flip/waiting for completion of bank flip (step S708).

The host control circuit 210 repeats the processing of steps S702 to S708 in the main loop with a period of 33.3 msec.

According to the modified example of the sub-random number processing described above, even if there are multiple chances to obtain random numbers within the packet reception loop, the same random number table that has already been created is used to obtain random numbers by changing the reference position.

[Other expansion examples]
The pachinko gaming machine 1 of the present embodiment can apply the present invention to all gaming machines in which a game is played using game media and a privilege is given based on the result of the game. In other words, the main control circuit 100 itself may electromagnetically manage the game media held by the player and allow the game to be played by circulating enclosed game balls or the game to be played without medals. Further, the game media owned by the player may be electromagnetically managed by a game media management device that is mounted (connected) to the main control circuit 100 and that manages the game media.

When managed by a game media management device connected to the main control circuit 100, the game media management device has ROM and RWM (or RAM) and is provided in the gaming machine, and is connected to an external game media handling device (not shown) with a two-way communication function via a predetermined interface. When a prize is won (the winning combination is established), the action of paying out game media (that is, the action of paying out game media to the player to acquire the required game media) or the action of electromagnetically recording the game media to be used in the game may be performed. Further, the game medium management device not only manages the actual number of game media, but also may manage the number of game media displayed on the owned game medium number display device (not shown) for displaying the number of game media held in front of the pachinko gaming machine 1, for example, based on the management result of the number of game media. In other words, the game media management device may record and display the total number of game media that a player can use for games by an electromagnetic method.

Further, in this case, the game medium management device has the performance that allows the player to freely transmit a signal indicating the number of recorded game media to the external game medium handling device, and has the performance that the number of recorded game media cannot be reduced except when the player directly operates the device. It is desirable to have the ability to not transmit a signal indicating the number of media.

In addition to the above, the game machine may be provided with lending operation means, return (settlement) operation means, and an external connection terminal board that can be operated by the player, and the game medium handling device may be provided with an insertion slot for valuables such as banknotes, an insertion slot for recording media (e.g., IC cards), a non-contact communication antenna for depositing electronic money, etc. from a mobile terminal, other various operation means such as lending operation means, return operation means, and an external connection terminal plate on the game medium handling device side (all not shown).

As a flow of the game at that time, for example, the player deposits valuable value into the game medium handling device by any method, subtracts a predetermined number of valuable value based on the operation of any of the lending operation means, and increases the game media corresponding to the subtracted value from the game medium handling device to the game medium management device. Then, the player plays the game, and repeats the above operation when the game medium is required. After that, a predetermined number of game media are acquired as a result of the game, and when the game is finished, the game medium management device transmits the number of game media to the game medium handling device by operating any return operation means, and the game medium handling device discharges the recording medium recording the number of game media. The game medium management device clears the number of game media stored by itself when transmitting the number of game media. The player takes the ejected recording medium to a prize counter or the like to exchange for prizes, or moves the game machine to play a game based on the game medium recorded on another machine.

In the above example, all game media are sent to the game medium handling device, but only the number of game media desired by the player may be sent from the gaming machine or the game medium handling device, and the game media possessed by the player may be divided and processed. In addition, it is also possible to eject cash or a cash equivalent instead of just ejecting the recording medium, or to store the information in a portable terminal or the like. Further, the game medium handling device may be configured so that the member recording medium of the game hall can be inserted, and the member recording medium is stored so that the game can be played again at a later date.

Further, in the game machine or the game medium handling device, by operating a predetermined operation means (not shown), a lock operation for locking the game medium or valuable value data communication to the game medium handling device or the game medium management device may be executed. In this case, information that only the player can know, such as a one-time password, may be set, or the player may be recorded by imaging means provided in the game medium handling device.

In the above description, the case where the game medium management device is applied to a pachinko game machine is explained, but the game medium management device can be similarly provided in a pachislot machine, a slot machine using game balls, or a sealed type game machine so that the game media of the players can be managed.

Thus, by providing the above-described game medium management device, the number of parts inside the game machine can be reduced compared to the case where the game medium is physically provided for the game. Not only can the production cost and manufacturing cost of the game machine be reduced, but also the player can be prevented from directly contacting the game medium, the game environment can be improved, noise can be reduced, and the reduction of the parts also reduces the power consumption of the game machine. In addition, it is possible to prevent fraudulent acts through game media or through the slot for inserting or paying out game media. That is, it is possible to provide a gaming machine capable of improving various environments surrounding the gaming machine.

Further, when the present invention is applied to a game system having an enclosed type game machine configured so that the game medium can be played without being ejected to the outside, and a game medium management device connected to the game machine so as to be able to transmit and receive data regarding the increase or decrease in the game medium associated with consumption, lending, and payout of the game medium via a communication cable, the game system may be configured as follows.

The outline of the enclosed game machine will be described below. In the enclosed type game machine, the shooting device is positioned above the game area and shoots game balls as game media from above to the game area. When the player operates the handle, the ball feed solenoid is driven by the payout control circuit, and the ball feed pestle pushes the game ball in the waiting state toward the launch pad. As a result, the game ball moves to the launch pad. A subtraction sensor is provided on the route from the standby position to the launch pad, and detects a game ball moving to the launch pad. When a game ball is detected by the subtraction sensor, 1 is subtracted from the number of possessed balls. In this way, since game balls as game media are shot from above into the game area, so-called return balls (foul balls) can be avoided in enclosed type game machines. The game ball discharged from the game area after rolling in the game area is polished by the ball polishing device. The game ball polished by the ball polishing device is conveyed upward by the lifting device and guided to the shooting device. Game balls are not discharged to the outside of the enclosed type game machine, and a fixed number (for example, 50) of game balls circulate through a series of paths in the game machine.

Since game balls are not ejected to the outside of the game machine, enclosed type game machines are not provided with an upper tray or a lower tray for temporarily holding game balls. Since the game balls are not discharged to the outside in the closed-type game machine, the game balls are not actually in the hands of the player, and the number of game balls does not actually increase or decrease as the game is played. In an enclosed type game machine, a player starts a game after obtaining a ball by lending it from a game medium management device. Here, obtaining a ball means that a player obtains a game medium in terms of data management. As game balls are shot from the shooting device, the balls in the player's possession are consumed, and the number of balls in the player's possession decreases. In addition, when the game balls pass through the respective prize winning openings provided in the game area, the number of payouts according to the conditions set according to the winning openings is performed, and the number of possessed balls is increased. Furthermore, the number of balls in possession is increased by lending out from the game medium management device. It should be noted that "consumption, lending, and payout of game media" indicates consumption, lending, and payout of held balls. Also, "increase or decrease in game media" means that the number of balls held increases or decreases due to consumption, lending, or payout. Also, "data related to increase/decrease in game media associated with consumption, lending, and payout of game media" is data relating to decrease in owned balls due to shooting game balls and increase in owned balls due to lending and paying out.

The enclosed game machine has a payout control circuit and a touch panel type liquid crystal display device. The payout control circuit is connected to various sensors for detecting the passage of game balls through the winning openings. The payout control circuit manages the number of balls held. For example, when a game ball passes through each winning hole, the number of game balls to be paid out is added to the number of balls. Also, when a game ball is shot, the number of possessed balls is subtracted. The payout control circuit transmits data regarding the number of balls held by the player to the game medium management device. The liquid crystal display device is positioned above the gaming machine and receives requests for conversion of game value managed by the game medium management device to possession balls (ball lending) and counting (return) of possession balls. These requests are transmitted to the payout control circuit via the game medium management device, and the payout control circuit instructs the game medium management device to transmit data regarding the current number of balls in possession. Here, the "game value" includes money/banknotes, prepaid media, tokens, electronic money, tickets, and the like, which can be converted into holding balls by the game media management device. In this embodiment, the game media management device is a so-called CR unit, and is configured to be able to accept bills, prepaid media, and the like. In addition, the counted number of balls in hand can be used for prize exchange, etc. at a game arcade or the like where the game system is installed.

In addition, the enclosed game machine has a backup power supply. As a result, even if the power is turned off at night or the like, the data immediately before the power is turned off can be retained. In addition, this backup power supply may be used to continuously detect opening of the door frame by the door opening sensor, for example. As a result, it is possible to prevent fraudulent acts at night. In this case, information such as the number of times the door frame has been opened may be stored. Furthermore, information such as the number of times the door frame has been opened may be output to a liquid crystal display device or the like of the game machine when the power is turned on.

The game medium management device has a game machine connection board. The game medium management device is configured to transmit and receive data (transmission signal) to and from the game machine via the game machine connection board. The transmitted and received data includes information such as the unique ID of the CPU provided in the main control circuit, the unique ID of the CPU provided in the payout control circuit, the game machine manufacturer code stored in the game machine, the security chip manufacturer code, and the game machine model code. When one of the game machine and the game medium management device is a transmission source and the other is a transmission destination, when the transmission source transmits a transmission signal, the transmission destination that received the transmission signal transmits a confirmation signal that is the same signal as the transmission signal to the transmission source, and the transmission source compares the transmission signal and the confirmation signal to determine whether they are the same.

In this manner, the transmission source compares the confirmation signal transmitted from the transmission destination with the transmission signal and determines whether or not they are the same, thereby confirming that the signal transmitted from the transmission source has been transmitted to the transmission source without being tampered with. As a result, it is possible to suppress cheating such as falsification of transmission/reception signals between the game machine and the game medium management device.

Further, in the gaming system, the transmission source may have a modulation section for modulating a signal, the signal modulated by the modulation section may be transmitted as the transmission signal, and the transmission destination may have a demodulation section for demodulating the signal modulated by the modulation section.

As a result, even if the transmission/reception signal between the game machine and the game medium management device is read, it is difficult to decipher the signal, and fraud such as falsification of the transmission/reception signal between the game machine and the game medium management device can be suppressed.

Further, in the gaming system, when the transmission signal is received from the transmission source, the transmission destination may transmit an acknowledgment signal, which is a signal indicating that the transmission signal has been received, to the transmission source separately from the confirmation signal.

Thus, by comparing the transmission signal and the confirmation signal, it is possible not only to confirm that the normal signal has been transmitted and received, but also to confirm that the normal signal has been transmitted and received based on the approval signal.

[Appendix]
[First gaming machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball enters a starting hole, and a big win game is played when the result of the lottery is a big win.

As this type of game machine, a long press effect that changes the execution mode of a specific game effect is performed on the condition that the player performs a predetermined long press operation on the operation means, and a short press operation that is shorter than the long press operation is performed multiple times. In the gaming machine disclosed in Japanese Patent Application Laid-Open No. 2015-065977, when a long-press operation is performed within a long-press operation acceptance valid period for determining whether or not a long-press operation has been performed, a long-press effect is executed.

(First issue)
As in the game machine described in Japanese Patent Application Laid-Open No. 2015-065977, if control is performed by determining whether a long-pressing operation has been performed on the operating means or a repeated hit effect has been performed, the control load will increase, which is not preferable.

However, in recent years, there has been a demand for a game machine capable of increasing interest by performing effects that can give a further visual impact.

In order to solve the above first problem, a first gaming machine having the following configuration is provided.

The first game machine is
A gaming machine capable of executing main processing (eg, main loop processing) in which various processing (eg, various request control processing) is performed every predetermined time (eg, 33.3 msec),
a predetermined operating means (for example, a main button);
a control means (e.g., host control circuit 210) capable of performing interrupt processing every time (e.g., 1 msec) shorter than the predetermined time and generating input information in the main processing based on the input state of the operating means detected by the interrupt processing;
with
The control means is
After the input state of the operating means changes from OFF to ON as the input information, as the input information, after it is determined that the ON state continues for a certain time (for example, 10 frames) after the input state of the operating means changes from OFF to ON, as long as the ON state continues for a time shorter than the certain time (for example, 4 frames), it is possible to periodically determine that the ON state has occurred (for example, ON edge information with a repeat function). (For example, the host control circuit 210 that executes the process of step S309);
device control means (e.g., host control circuit 210) capable of executing control of a predetermined device based on the information (e.g., the ON edge information with repeat function) generated by the input information generation means.

According to the first game machine, based on the input state of the operation means (for example, the input information of the sub-device), after it is determined that the ON state has continued for a certain period of time after the input state of the operation means has changed from the OFF state to the ON state, as long as the ON state of the operation means continues for a period of time shorter than the certain period, by generating information that can be used to periodically determine that the ON state has occurred, it is possible to easily perform controls such as control of continuous hitting effects of the sub-devices, control of long-press effects, and the like.

Further, according to the first game machine, it is possible to reduce the control load and execute the control according to the mode of the operating means.

[Second gaming machine, third gaming machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed, for example, on a liquid crystal display based on the result of the lottery.

As this type of game machine, a game machine equipped with a display device that emits light with a backlight has been disclosed (see, for example, Japanese Patent Application Laid-Open No. 2016-159026).

(Second issue)
However, for example, if the luminance of the light emitting means of the backlight is unstable, the display of the effect image on the display device may become unstable, which is not preferable.

In order to solve the above second problem, a second game machine and a third game machine having the following configurations are provided.

The second game machine is
a light-emitting means (e.g., backlight) capable of emitting light in a predetermined manner;
Data storage means (for example, FIFO data area) for storing drive data (for example, luminance data) corresponding to the light emission mode of light emission by the light emitting means in a predetermined area;
light emission drive means (for example, LSI) for outputting a control signal based on the drive data stored in the data storage means to the light emission means;
data setting means for setting the drive data in a predetermined area of the data storage means (for example, the host control circuit 210 for executing the process of step S346);
with
The data setting means
The drive data set in the predetermined area of the data storage means is configured to set new drive data when the number of drive data that can be set in the predetermined area reaches a reference number of data.

According to the second gaming machine, when the number of drive data that can be stored in the predetermined area of the drive data set in the predetermined data area reaches the reference data number, new drive data is set. Therefore, the control signal output by the light emission drive means (for example, a signal equivalent to PWM continuously output from the serial data output terminal of the SPI) can be output, and the light emission means can stably emit light without going through the driver.

The above-mentioned "reference number of data" corresponds to 1 to 64 if the number of data that can be set in a predetermined area of the data storage means (for example, the data area of the FIFO) is up to 64, for example. Also, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient if at least two luminance data can be set. When the number of luminance data that can be set in the FIFO data area is, for example, two or more, and the number of luminance data set in the FIFO data area falls below a first number (for example, two), a second number (for example, one) of luminance data may be supplemented.

The third game machine is
a light-emitting means (e.g., backlight) capable of emitting light in a predetermined manner;
Data storage means (for example, FIFO data area) for storing drive data (for example, luminance data) corresponding to the light emission mode of light emitted by the light emitting means in a predetermined area (for example, FIFO data area);
light emission drive means (for example, LSI) for outputting a control signal based on the drive data stored in a predetermined area of the data storage means to the light emission means;
data setting means for setting the drive data in a predetermined area of the data storage means (for example, the host control circuit 210 for executing the process of step S346);
timer means (for example, the host control circuit 210 that executes the process of step S356) capable of measuring the elapsed time since the drive data was set in a predetermined area of the data storage means;
with
The data setting means
The driving data can be set in a predetermined area of the data storage means (the process of step S354 can be executed) based on the passage of a predetermined time or longer measured by the time measuring means.

According to the third game machine, the drive data is set in the predetermined area of the data storage means when the time elapsed since the drive data was set in the predetermined area of the data storage means exceeds the predetermined time. For example, if some processing takes a long time, the drive data set in the predetermined area of the data storage means may disappear before the timing of setting the drive data in the predetermined area of the data storage means. In this regard, according to this game machine, even if it is not the timing to set the drive data in the predetermined area of the data storage means, the drive data is set in the predetermined area of the data storage means based on the lapse of the predetermined time or more, so that the drive data set in the predetermined data area can be prevented from becoming empty. Therefore, it is possible to output a control signal (for example, a PWM-equivalent signal continuously output from the serial data output terminal of the SPI) output by the light emission drive means, so that the light emission means can stably emit light without a driver.

Further, according to the second gaming machine and the third gaming machine, it is possible to suppress unstable light emission of the light emitting means.

[Fourth Gaming Machine, Fifth Gaming Machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed on a liquid crystal display or the like based on the result of the lottery.

As this type of game machine, there is known a game machine that is used for presentation and decoration by causing a light emitting device, which is provided on the front side and which is made up of a plurality of light emitters such as LEDs, to emit light in a predetermined manner. Also disclosed is a gaming machine in which a player or the like can adjust the brightness of these light emitting devices within a preset range (see, for example, Japanese Patent Application Laid-Open No. 2008-295551).

(Third issue)
By the way, in recent years, the production has become flashy, including a light-emitting device including a plurality of light-emitting bodies such as LEDs provided on the front side. Therefore, when the brightness of the light emitting device is high, some players may feel stressed by it. If a player or the like can operate the brightness of the light-emitting device, the player can adjust the brightness to a desired level, but this alone may not be enough.

In order to solve the third problem, a fourth game machine and a fifth game machine having the following configurations are provided.

(1) The fourth gaming machine is
a first light emitting means (e.g., backlight) capable of emitting light in a predetermined manner;
an operation means (for example, a luminance setting screen displayed on a liquid crystal display device used as the display device 13) capable of changing the luminance of the first light emitting means to any one of a plurality of steps;
a first light emission control means (for example, a host control circuit 210 that executes the process of step S384) capable of changing the luminance of the first light emission means to any one of a plurality of levels based on the operation of the operation means;
a second light-emitting means (for example, a board-side LED or a frame-side LED) provided separately from the first light-emitting means;
a second light emission control means (for example, a host control circuit 210 that executes the process of step S385) capable of changing the luminance of the second light emission means;
with
The second light emission control means is
The brightness of the second light emitting means can be changed to any one of the plurality of levels at a timing different from the timing at which the brightness of the first light emitting means is changed based on the operation of the operating means.

According to the fourth gaming machine of (1) above, when the operation means capable of changing the luminance of the first light emitting means is operated, the luminance of the second light emitting means is also changed at a timing different from the timing at which the luminance of the first light emitting means is changed, and the luminance of the second light emitting means is also changed to one of a plurality of levels, so that the degree of freedom in changing the luminance by the player can be further enhanced.

(2) In the fourth gaming machine described in (1) above,
Data storage means (for example, FIFO data area) for storing driving data corresponding to the light emission mode of light emission by the first light emitting means in a predetermined area;
light emission drive means (for example, LSI) for outputting a control signal based on the drive data stored in the data storage means to the first light emission means;
data setting means for setting the drive data in a predetermined area of the data storage means (for example, the host control circuit 210 for executing the process of step S346);
with
The data setting means
When the number of drive data that can be stored in the predetermined area of the data storage means reaches a reference number of data, new drive data is set, and
It is characterized in that, when the operation means is operated, drive data after luminance is changed is set as the new drive data.

According to the fourth game machine of (2) above, when the number of drive data that can be stored in the predetermined data area reaches the number of reference data, new drive data is set, so that the control signal output by the light emission drive means (for example, a signal equivalent to PWM continuously output from the serial data output terminal of the SPI) can be output, and the light emission means can stably emit light without going through the driver. Moreover, when the luminance is changed, the drive data after the change is set as new drive data, so that the first light emitting means can stably emit light according to the set luminance.

The above-mentioned "reference number of data" corresponds to 1 to 64 if the number of data that can be set in a predetermined area of the data storage means (for example, the data area of the FIFO) is up to 64, for example. Also, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient if at least two luminance data can be set. When the number of luminance data that can be set in the FIFO data area is, for example, two or more, and the number of luminance data set in the FIFO data area falls below a first number (for example, two), a second number (for example, one) of luminance data may be supplemented.

(1) The fifth game machine is
a lottery means (for example, the main CPU 71 that executes the process of step S45) for performing a lottery based on the establishment of a predetermined condition;
display means for displaying a predetermined effect image (for example, a liquid crystal display device used as the display device 13);
variable display control means (eg, a display control circuit 230) for performing variable display of symbols (eg, identification symbols for performance) on the display means based on the result of the lottery;
a first light emitting means (e.g., backlight) capable of emitting light in a predetermined manner;
an operation means (for example, a luminance setting screen displayed on a liquid crystal display device used as the display device 13) capable of changing the luminance of the first light emitting means to any one of a plurality of steps;
a first light emission control means (for example, a host control circuit 210 that executes the process of step S394) capable of changing the luminance of the first light emission means to any one of a plurality of levels based on the operation of the operation means;
a second light-emitting means (for example, a board-side LED or a frame-side LED) provided separately from the first light-emitting means;
second light emission control means (host control circuit 210 for executing the process of step S392) for controlling the light emission mode of the second light emission means based on a predetermined request;
with
The second light emission control means is
Based on the operation of the operating means, the brightness of the second light emitting means can be changed (for example, the process of step S399 can be executed) after the brightness of the first light emitting means is changed and after the variable display of the pattern is finished.

According to the fifth game machine of (1) above, the brightness of the first light emitting means can be changed when the operation means is operated. Further, the luminance of the second light emitting means is changed after the luminance of the first light emitting means is changed and after the variable display of the pattern is finished. Here, since the light emitting mode of the second light emitting means is controlled based on a predetermined request, it is possible to change the brightness of the first light emitting means and the second light emitting means while minimizing the control load by changing the luminance of the second light emitting means after the completion of the variable display of the pattern.

(2) In the fifth gaming machine described in (1) above,
Data storage means (for example, FIFO data area) for storing driving data corresponding to the light emission mode of light emission by the first light emitting means in a predetermined area;
light emission drive means (for example, LSI) for outputting a control signal based on the drive data stored in the data storage means to the first light emission means;
data setting means for setting the drive data in a predetermined area of the data storage means (for example, the host control circuit 210 for executing the process of step S346);
with
The data setting means
When the number of drive data that can be stored in the predetermined area of the data storage means reaches a reference number of data, new drive data is set, and
It is characterized in that, when the operation means is operated, drive data after luminance is changed is set as the new drive data.

According to the fourth game machine of (2) above, when the number of drive data that can be stored in the predetermined data area reaches the number of reference data, new drive data is set, so that the control signal output by the light emission drive means (for example, a signal equivalent to PWM continuously output from the serial data output terminal of the SPI) can be output, and the light emission means can stably emit light without going through the driver. Moreover, when the luminance is changed, the drive data after the change is set as new drive data, so that the first light emitting means can stably emit light according to the set luminance.

The above-mentioned "reference number of data" corresponds to 1 to 64 if the number of data that can be set in a predetermined area of the data storage means (for example, the data area of the FIFO) is up to 64, for example. Also, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient if at least two luminance data can be set. When the number of luminance data that can be set in the FIFO data area is, for example, two or more, and the number of luminance data set in the FIFO data area falls below a first number (for example, two), a second number (for example, one) of luminance data may be supplemented.

Further, according to the fourth game machine and the fifth game machine, it is possible to provide a game machine that allows a player or the like to more preferably adjust the brightness of the light emitting device.

[Sixth gaming machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed on a liquid crystal display or the like based on the result of the lottery.

As this type of game machine, there is known a game machine that is used for presentation and decoration by causing a light emitting device, which is provided on the front side and which is made up of a plurality of light emitters such as LEDs, to emit light in a predetermined manner. Also disclosed is a gaming machine in which a player or the like can adjust the brightness of these light emitting devices within a preset range (see, for example, Japanese Patent Application Laid-Open No. 2008-295551).

(Fourth issue)
By the way, in recent years, the production has become flashy, including a light-emitting device including a plurality of light-emitting bodies such as LEDs provided on the front side. Therefore, when the intensity of the light received from the light emitting device is high, some players may feel stress.

In order to solve the above fourth problem, a sixth gaming machine having the following configuration is provided.

(1) The sixth gaming machine is
The game machine according to the present invention is
a first light emitting means (e.g., backlight) capable of emitting light in a predetermined manner;
an operation means (for example, a luminance setting screen displayed on a liquid crystal display device used as the display device 13) capable of changing the luminance of the first light emitting means to any one of a plurality of steps;
a first light emission control means (for example, a host control circuit 210 that executes the process of step S394) capable of changing the luminance of the first light emission means to any one of a plurality of levels based on the operation of the operation means;
a second light-emitting means (for example, a board-side LED or a frame-side LED) provided separately from the first light-emitting means;
a second light emission control means (for example, a host control circuit 210 that executes the process of step S406) capable of changing the light emission mode of the second light emission means;
with
The second light emission control means is
Based on the operation of the operating means, the mode of the light emitting effect executed by the second light emitting means can be restricted and executed at a timing different from the timing at which the luminance of the first light emitting means is changed.

According to the sixth game machine of (1) above, when the operation means capable of changing the luminance of the first light emitting means is operated, the mode of the light emitting effect executed by the second light emitting means is restricted. Therefore, it is possible to suppress the intensity of the light received from the second light emitting means with a simple process.

(2) In the sixth gaming machine described in (1) above,
Data storage means (for example, FIFO data area) for storing driving data corresponding to the light emission mode of light emission by the first light emitting means in a predetermined area;
light emission drive means (for example, LSI) for outputting a control signal based on the drive data stored in the data storage means to the first light emission means;
data setting means for setting the drive data in a predetermined area of the data storage means (for example, the host control circuit 210 for executing the process of step S346);
with
The data setting means
When the number of drive data that can be stored in the predetermined area of the data storage means reaches a reference number of data, new drive data is set, and
It is characterized in that, when the operation means is operated, drive data after luminance is changed is set as the new drive data.

According to the fifth game machine of (2) above, when the number of drive data that can be stored in the predetermined data area reaches the number of reference data, new drive data is set. Therefore, the control signal output by the light emission drive means (for example, a signal equivalent to PWM continuously output from the serial data output terminal of the SPI) can be output, and the light emission means can stably emit light without going through the driver. Moreover, when the luminance is changed, the drive data after the change is set as new drive data, so that the first light emitting means can stably emit light according to the set luminance.

The above-mentioned "reference number of data" corresponds to 1 to 64 if the number of data that can be set in a predetermined area of the data storage means (for example, the data area of the FIFO) is up to 64, for example. Also, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient if at least two luminance data can be set. When the number of luminance data that can be set in the FIFO data area is, for example, two or more, and the number of luminance data set in the FIFO data area falls below a first number (for example, two), a second number (for example, one) of luminance data may be supplemented.

Thus, according to the sixth gaming machine, it is possible to provide a gaming machine that allows a player or the like to preferably adjust the intensity of the light received from the light emitting device.

[Seventh gaming machine]
2. Description of the Related Art Conventionally, among gaming machines such as pachinko machines, there are known gaming machines that perform effects that depend on, for example, an RTC (real time clock).

In this type of gaming machine, there is a well-known gaming machine that determines an abnormality of the RTC when the power is turned on, notifies the date and time if there is an abnormality, and can quickly deal with the abnormality when the RTC is recognized (for example, see Japanese Patent Application Laid-Open No. 2017-51853 (for example, paragraph [0094])).

(Fifth issue)
According to the gaming machine disclosed in Japanese Patent Application Laid-Open No. 2017-51853, if there is an abnormality in the RTC, the date and time are notified, so there is a possibility that it can be dealt with quickly.

In order to solve the fifth problem, a seventh gaming machine having the following configuration is provided.

The seventh game machine is
a real-time clock (for example, an RTC) capable of outputting time information;
time information management means (for example, the host control circuit 210 that executes the process of step S413) capable of acquiring time information from the real-time clock and updating the acquired time to current time information;
Effect execution means (eg, host control circuit 210) capable of executing a specific effect (eg, RTC effect) based on the fact that the current time information is specific time information (eg, specified time);
Abnormality determination means (for example, the host control circuit 210 that executes the process of step S414) for determining an abnormality of the real-time clock;
with
The time information management means is
When the real-time clock is determined to be abnormal, the previous time information obtained last time by the time information management means is maintained as the current time information (for example, step S415), and when the real-time clock is determined to be normal, the previous time information can be updated to the current time information (for example, the process of step S416).
The production executing means is
The specific effect is executed (step S419) on condition that the current time information is the specific time information (YES in step S417) and the previous time information and the current time information do not match (YES in step S418).

According to the seventh gaming machine, even if the RTC is abnormal, it is possible to suitably perform an effect dependent on the RTC.

[8th gaming machine, 9th gaming machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed on a display device or the like based on the result of the lottery. If the result of the lottery is a big win, a big win game is started.

As this type of gaming machine, there is known a gaming machine that decodes compressed image data, appropriately converts the decoded image data, stores it in a frame buffer, and outputs it to a display device (for example, JP-A-2014-87402 (see, for example, paragraph [0100])).

(Sixth issue)
2. Description of the Related Art In recent years, the variety of effect images displayed on a display device has increased, and the control of the effect images tends to be complicated. In such a case, it is desirable to efficiently control the effect image.

In order to solve the sixth problem, the following eighth and ninth gaming machines are provided.

The eighth game machine is
A gaming machine capable of executing processing (e.g., bank flip) to switch functions between a drawing output destination buffer having a drawing function and a frame buffer having a display function,
a registration means (for example, a display control circuit 230 capable of executing steps S449 and S458) capable of registering image information (for example, a composition) relating to an effect image to be displayed on a predetermined display means in the drawing output destination buffer;
After switching from the drawing output destination buffer to the frame buffer (for example, after the processing of step S446 is performed), based on the image information registered by the registration means, effect image display control means (for example, display control circuit 230) for controlling display of the effect image on the predetermined display means;
with
The registration means
when the image information registered in the frame buffer switched from the drawing output destination buffer includes image information for pausing the image (for example, when it is determined as YES in step S447), a first registering means (for example, a display control circuit 230 executing the processing of step S449) for registering the image information in the drawing output destination buffer;
Even if there is no image information registered in the drawing output buffer (for example, even if it is identified as NO in Step S444), the production image displayed in the specified display means (for example, the image information registered in the frame buffer is reached (for example, in Step S450) When it is identified as YES, it is characterized by having a second registration means (for example, a display control circuit 230 that can execute step S458) to register the image information in the drawing output buffer.

According to the eighth game machine, while image information is registered under the condition that the image information is not registered, even if the image information is registered, the image information is registered when the registered image information includes specific image information, so that the effect image can be controlled efficiently.

The ninth game machine is
a plurality of display means (for example, a display) capable of reproducing a predetermined effect image;
display control means (for example, a display control circuit 230) capable of controlling image information related to the effect images reproduced on the plurality of display means;
with
The display control means is
a layer number determination means (for example, a display control circuit 230 that executes the process of step S441) for determining the adequacy of the number of layers of image information simultaneously reproduced on the display means;
display means number determination means (for example, a display control circuit 230 that executes the process of step S442) for determining the appropriateness of the number of display means used for reproducing the effect image when the number of layers is appropriate (for example, when it is determined as YES in step S441);
When the number of display means used for reproducing the effect image is appropriate (for example, when YES is determined in step S442), display means presence determination means (for example, a display control circuit 230 that executes the process of step S443) for determining the presence of the display means to be registered for the image information;
an image information registration means (for example, a display control circuit 230 for executing the processes of steps S449 and S458) for registering image information reproduced on the display means when there is a display means for which the image information is to be registered (for example, when YES is determined in step S443);
After the image information to be played back on one of the plurality of display means is registered by the image information registration means, the determination by the number of display means determination means and the determination by the display means existence determination means are performed (the process of step S459 is executed and then the process of returning to step S442 is performed) so that the image information is registered in another display means other than the one display means.

According to the ninth game machine, when there are a plurality of display means and the number of layers of the image information is appropriate, the image information related to the effect image displayed on one display means is registered, and then the image information related to the effect image displayed on another display means different from the one display means is registered.

Thus, according to the eighth gaming machine and the ninth gaming machine, it is possible to provide gaming machines capable of efficiently performing control related to effect images.

[Tenth gaming machine, Eleventh gaming machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed, for example, on a liquid crystal display based on the result of the lottery. In addition to such an effect image, an audio effect is also output.

As this type of gaming machine, there is known a gaming machine that determines whether or not the timing for determining an abnormality of the digital amplifier has arrived, and, for example, when the operation determination timing determined at intervals of about several seconds has arrived, acquires an abnormality notification signal ERR from the input port Pi2, and determines whether the digital amplifier is at an abnormal level or not (see Japanese Patent Application Laid-Open No. 2016-209723 (for example, paragraphs [0178] and [0179])).

(Seventh subject)
2. Description of the Related Art In recent years, due to an increase in the variety of effects images displayed on liquid crystal displays and the like, the contents of effects have become more sophisticated, and interest has been enhanced. However, along with the sophistication of the performance contents, the performance contents of the game sound tend to be sophisticated, and in order to output the normal game sound, it is necessary to properly perform the determination processing of the amplifying device for amplifying the game sound.

In order to solve the seventh problem, the tenth and eleventh gaming machines having the following configurations are provided.

(1) The tenth gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing, interrupt processing, etc.) each time a predetermined time elapses,
Output means (for example, speaker 11) capable of outputting game sound;
Amplifying means (for example, digital audio power amplifier 262) capable of amplifying the game sound output from the output means;
Abnormality determination means (for example, the host control circuit 210 that executes the processes of steps S503, S511, S515, etc.) that performs abnormality determination processing to determine whether the amplifier is normal;
with
The abnormality determination means is
The abnormality determination process can be executed by dividing it into a plurality of abnormality determination processes (for example, steps S503, S511, S515, etc.),
A part of the abnormality determination process (e.g., step S503, step S511, step S515) divided into a plurality of times is executed in one time of the predetermined process (for example, one frame) executed within the predetermined time, and part or all of the remaining abnormality determination process can be executed in the predetermined process after the next time.

According to the tenth game machine of (1) above, part of the abnormality determination processing of the amplifying means (for example, a normal amplifier or a deep bass amplifier) is performed over a plurality of frames in a predetermined process (for example, one frame). Therefore, it is possible to execute the entire abnormality determination process of each amplifying means over a plurality of frames.

(2) Another example of the tenth gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing, interrupt processing, etc.) each time a predetermined time elapses,
Output means (for example, speaker 11) capable of outputting game sound;
Amplifying means (for example, digital audio power amplifier 262) capable of amplifying the game sound output from the output means;
Setting information confirmation means (for example, host control circuit 210 for executing processes such as steps S506 to S507 and steps S522 to S523) for confirming setting information about the amplification means;
with
The setting information confirmation means is
The confirmation process can be executed by dividing it into a plurality of confirmation processes,
A part of the confirmation process (for example, the host control circuit 210 that executes the processes of steps S506 to S507, steps S522 to S523, etc.) is executed in one time of the predetermined process executed within the predetermined time, and part or all of the remaining confirmation process can be executed in the predetermined process after the next time.

According to another example of the tenth game machine of (2) above, since a part of the confirmation processing of the setting information of the amplification means (for example, a normal amplifier or a deep bass amplifier) in a predetermined process (for example, one frame) is performed over a plurality of frames, it is possible to execute all the confirmation processing of the setting information of each amplification means over a plurality of frames.

(1) The eleventh gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing, interrupt processing, etc.) each time a predetermined time elapses,
Output means (for example, speaker 11) capable of outputting game sound;
Amplifying means (for example, digital audio power amplifier 262) capable of amplifying the game sound output from the output means;
Abnormality determination means (e.g., host control circuit 210 that executes processes such as steps S503, S511, and S515) that can divide the abnormality determination process for determining whether the amplifying means is normal into a plurality of abnormality determination processes (e.g., processes with check status = 0, 2, and 3) and perform the plurality of abnormality determination processes over a plurality of times of the predetermined process;
progress management means (for example, a host control circuit 210 that manages check status) that manages the progress of the abnormality determination process;
with
The progress management means
It is possible to determine whether or not one of the plurality of abnormality determination processes (for example, processes with check status = 0, 2, 3) has been completed in one predetermined process,
The abnormality determination means is
When the one abnormality determination process (e.g., check status 0 process) is completed in the one predetermined process, another abnormality determination process (e.g., check status 2 process) different from the one abnormality determination process (e.g., check status 2 process) is executed in the next and subsequent predetermined processes (e.g., the next frame and thereafter), and when the one abnormality determination process (e.g., check status 0 process) is not completed in the one predetermined process, the one abnormality determination process (e.g., check status 0 process) can be executed again in the next and subsequent predetermined processes. characterized by

According to the eleventh gaming machine described in (1) above, part of the abnormality determination processing of the amplifying means (for example, a normal amplifier or a heavy bass amplifier) is performed over a plurality of frames in a predetermined process (for example, one frame). Moreover, when one abnormality determination process is not completed in one predetermined process (for example, the main process or interrupt process of one frame), the one abnormality determination process is executed again in the next predetermined process (for example, the next frame or later), so all the abnormality determination processes are executed until they are completed.

(2) Another example of the eleventh gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing, interrupt processing, etc.) each time a predetermined time elapses,
Output means (for example, speaker 11) capable of outputting game sound;
Amplifying means (for example, digital audio power amplifier 262) capable of amplifying the game sound output from the output means;
A setting information confirmation means (for example, a host control circuit 210 that executes the processes of steps S506 to S507, steps S522 to S523, etc.), which can execute confirmation processing of setting information about the amplification means by dividing it into a plurality of confirmation processes (for example, processes with check status = 1 and 5), and performs the confirmation processes a plurality of times over a plurality of the predetermined processes;
a progress management unit (for example, a host control circuit 210 that manages check status) that manages the progress of the confirmation process of the setting information;
with
The progress management means
It is possible to determine whether or not one of the plurality of confirmation processes (for example, processes with check status = 1, 5) has been completed in one predetermined process,
The setting information confirmation means is
When the one confirmation process (e.g., check status=1) is completed in the one predetermined process, another confirmation process (e.g., check status=5) is executed in the next and subsequent predetermined processes, and when the one confirmation process is not completed in the one predetermined process, the one confirmation process can be executed again in the next and subsequent predetermined processes.

According to another example of the eleventh game machine of (2) above, part of the confirmation processing of the setting information of the amplifying means (for example, a normal amplifier or a deep bass amplifier) in a predetermined process (for example, one frame) is performed over a plurality of frames. Therefore, it is possible to execute the entire confirmation process of the setting information of each amplifying means over a plurality of frames. Moreover, when one confirmation process is not completed in one predetermined process (for example, the main process or interrupt process of one frame), the one confirmation process is executed again in the next predetermined process (for example, the next frame or later), so all the confirmation processes are executed until they are completed.

As described above, according to the tenth and eleventh gaming machines, it is possible to provide gaming machines capable of appropriately performing the determination process of the amplifying device.

[12th gaming machine, 13th gaming machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed, for example, on a liquid crystal display based on the result of the lottery. In addition to such effect images, game sounds are also output from the speaker.

As a game machine of this type, a game machine is disclosed that outputs audio data such as game sounds from an audio memory by writing a SAC number to an audio control register to cause a simple access controller to function (see, for example, Japanese Unexamined Patent Application Publication No. 2017-79971).

(Eighth problem)
In recent years, the variation of game sounds has increased along with the increase in variations of effect images.

In order to solve the eighth problem, a twelfth game machine and a thirteenth game machine having the following configurations are provided.

(1) The twelfth gaming machine is
setting means (for example, host control circuit 210) capable of assigning and setting sound information (for example, SAC number) related to game sound data to a channel;
sound output means (for example, a sound/LED control circuit) capable of outputting a game sound based on the sound information assigned to the channel;
with
The setting means
In assigning sound information to one channel, when a plurality of sound information is set to the one channel (for example, when it is determined as YES in the processing of step S542),
when the plurality of sound information are specific sound information (for example, chain reproduction of SHOT reproduction and loop reproduction), any one of the plurality of sound information (for example, loop reproduction) is set by delaying at least a predetermined time (for example, one frame) or more; and
second setting means (for example, the host control circuit 210 that executes the processing of steps S546 and S547) for setting the plurality of sound information without delaying the predetermined time or more (for example, in the frame) on condition that the plurality of sound information is non-specific sound information different from the specific sound information (for example, determination of NO in the processing of step S543).

According to the twelfth game machine of (1) above, when a plurality of sound information are set in one channel, when the plurality of sound information are specific sound information, one of the sound information is set with a delay, so that the sound effect by delaying (for example, the sound effect by muting) can be enjoyed. On the other hand, if the plurality of sound information are non-specific sound information, the plurality of sound information are set without delay, so that the processing can be performed quickly. In other words, by delaying or not delaying according to the situation, it is possible to secure the promptness of the processing while making the most of the game sound effect due to the delay.

(2) In the twelfth gaming machine described in (1) above,
The specific sound information is
includes at least first sound information that is reproduced only once (for example, SHOT reproduction) and second sound information that is reproduced multiple times (LOOP reproduction),
The first setting means
It is characterized in that the second sound information can be set after setting the first sound information with a delay of a predetermined time or more.

According to the twelfth game machine of (2) above, since the second sound information is set to be reproduced a plurality of times by delaying the setting of the first sound information to be reproduced only once for a predetermined time or more, it is possible to prevent the first sound information to be reproduced only once from becoming difficult to hear.

The thirteenth game machine is
setting means (for example, sound/LED control circuit) capable of assigning and setting sound information (for example, SAC number) related to game sound data to a channel;
sound output means capable of outputting a game sound based on the sound information assigned to the channel;
with
The setting means
In assigning sound information to one channel, when a plurality of sound information is set to the one channel (for example, when it is determined as YES in the processing of step S542),
a first setting means (for example, the host control circuit 210 that executes the process of step S544) for setting one of the plurality of sound information (for example, loop reproduction) with a delay of at least a predetermined time (for example, one frame) when the plurality of sound information is specific sound information (for example, SHOT+loop chain reproduction);
a second setting unit (for example, the host control circuit 210 that executes the processing of steps S546 and S547) that sets the plurality of sound information without delaying the predetermined time or more (for example, in the frame) on condition that the plurality of sound information is non-specific sound information different from the specific sound information (for example, determination as NO in the processing of step S543);
has
The second setting means
When the mute setting is set for all channels (for example, when YES is determined in the processing of step S545), the sound information is set without overwriting the mute setting (for example, the processing of step S546 is performed). .

According to the thirteenth game machine, when a plurality of sound information are set in one channel, when the plurality of sound information are specific sound information, one of the sound information is set with a delay, so that a sound effect (for example, a sound effect due to muting) by delaying can be enjoyed. On the other hand, if the plurality of sound information are non-specific sound information, the plurality of sound information are set without delay, so that the processing can be performed quickly. In other words, by delaying or not delaying according to the situation, it is possible to secure the promptness of the processing while making the most of the game sound effect due to the delay. Furthermore, when a plurality of sound information is non-specific sound information, when mute setting is made for all channels, the sound information is set without overwriting the mute setting, and when mute setting is made for one channel instead of mute setting for all channels, the sound information is set by overwriting the mute setting, so that it is possible to secure a necessary period (for example, a period from the end of the variable display of the special pattern to the start of the variable display of the next special pattern).

Thus, according to the 12th game machine and the 13th game machine, it is possible to provide a game machine capable of suitably outputting game sounds.

[14th game machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed, for example, on a liquid crystal display based on the result of the lottery. In addition to such effect images, game sounds are also output from the speaker.

As this type of gaming machine, there is disclosed a gaming machine that outputs a sound that makes the game lively in conjunction with an effect image displayed on a liquid crystal display or the like (see, for example, Japanese Patent Application Laid-Open No. 2014-144066).

(9th problem)
However, in the gaming machine described in Japanese Patent Application Laid-Open No. 2014-144066, the secondary volume is maintained at a fixed value, and the volume of the effect sound is controlled by the primary volume.

In order to solve the ninth problem, a fourteenth gaming machine having the following configuration is provided.

(1) The 14th gaming machine is
Output means (for example, speaker 11) capable of outputting a predetermined game sound;
sound data setting means (for example, host control circuit 210) capable of setting sound data (for example, sound data) relating to game sounds output from the output means;
Volume control means (eg, host control circuit 210 for executing sound requests) having a plurality of playback channels (eg, CH1 to CH31) and capable of controlling the volume output from the output means;
with
The volume control means is
a first volume control means (for example, a hardware switch volume control 281, a volume setting screen user volume control 282, and a debug volume control 283 during debugging) that can change information related to volume for all of the plurality of playback channels based on a predetermined operation (for example, a hardware switch operation or a screen operation by a user);
a second volume control means (for example, a first reproduction channel primary control 284, a second reproduction channel primary control 285, and a host control circuit 210 that executes volume controls 286, 287, 288 incorporated in audio data) capable of changing information related to volume for each reproduction channel among the plurality of reproduction channels;
and configured to be able to change the volume output from the output means by multiplying the information related to the volume by the first volume control means and the information related to the volume by the second volume control means,
The second volume control means
volume control (first playback channel primary control 284) for controlling the information related to the volume to be changed when the predetermined operation is performed for each playback channel;
volume control (second playback channel primary control 285) for controlling output of information (for example, error sound or alarm sound for illegal activity) related to a constant volume before and after the operation is performed even if the predetermined operation is performed for each playback channel.

According to the fourteenth game machine of (1) above, since the game sound output from the output means is defined by combining the information related to the volume by the first volume control means and the information related to the volume by the second volume control means, the volume of the game sound can be diversified. Moreover, the second volume control means performs control so that, even if a predetermined operation is performed for each reproduction channel, information relating to a constant volume is output before and after the operation is performed. Thus, even if a predetermined operation is performed, it is possible to perform control for outputting information relating to a constant sound volume before and after the operation, not for all channels but for a specific reproduction channel.

(2) In the fourteenth gaming machine described in (1) above,
The first volume control means
It is characterized by being able to control information related to sound volume by debugging volume control during debugging.

According to the 14th game machine of (2) above, the game sound data used in the game can be used as it is during debugging, and the work efficiency during debugging can be improved.

Further, according to the fourteenth gaming machine, it is possible to provide a gaming machine capable of diversifying the volume variations of the effect sounds.

[15th to 19th game machines]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed, for example, on a liquid crystal display based on the result of the lottery. In addition to such effect images, game sounds are also output from the speaker.

As this type of gaming machine, a gaming machine is disclosed in which the volume of game sounds output from a speaker can be adjusted by a player's operation (see, for example, Japanese Patent Application Laid-Open No. 2011-229766).

(Tenth problem)
However, if the volume of the game sound output from the speaker can be adjusted by manipulating the game sound, there is a possibility that even sounds whose volume should not be changed, such as error sounds and warning sounds, may be affected, which is not preferable.

In order to solve the tenth problem, the following fifteenth to nineteenth gaming machines are provided.

(1) The fifteenth gaming machine is
a plurality of output means (for example, speaker 11) capable of outputting a predetermined game sound;
an operation means (for example, a volume setting screen) capable of operating the volume output from the output means;
sound control means (for example, a host control circuit 210 that executes sound request control processing) capable of controlling the volume based on the operation of the operation means;
with
The volume output from the output means is at least defined by first information (for example, an audio signal output by the second reproduction channel primary control 285) having information of a constant volume before and after the operation is performed even if the operation means is operated, and second information (for example, an audio signal output by the first reproduction channel primary control 284) having information on a volume that is changed based on the operation of the operation means.
The plurality of output means includes at least a dedicated output means (e.g., a dedicated speaker) used to output a specific sound and a shared output means (e.g., a shared speaker) used to output a sound other than the specific sound,
The sound control means is
With respect to the dedicated output means, a specific sound control means (for example, a host control circuit 210 that executes step S559) capable of executing control to output the first information so that a constant volume is output before and after the operation is performed even if the operation means is operated;
The common output means includes non-specific sound control means (for example, the host control circuit 210 that executes step S558) capable of executing control to output the second information so that the volume is changed based on the operation of the operation means.

According to the fifteenth game machine of (1) above, the dedicated output means used for outputting a specific sound is controlled to output a constant volume before and after the operation even if the operating hand capable of operating the volume is operated. That is, although the volume can be operated, a constant volume is output without changing the volume before and after the operation of the operating means. Further, the shared output means used for outputting sounds other than the specific sound outputs the second information in which the volume information is changed based on the operation of the operating hand capable of operating the volume, so that the volume can be suitably adjusted.

(2) In the fifteenth gaming machine described in (1) above,
The dedicated output means is a speaker for vibration.

According to the fifteenth game machine of (2) above, it is possible to output a specific sound (for example, an error sound, a warning sound, etc.) from the vibration speaker at a constant volume.

(3) In the gaming machine of (1) or (2) above,
Dedicated output setting means (e.g., host control circuit 210 for executing the process of step S201) for setting which one of the plurality of output means is to be the dedicated output means when power is turned on (e.g., during various initialization processes in step S201),
The data relating to the specific sound (for example, the audio data relating to the specific sound designated by the SAC number) is characterized in that the output destination of the specific sound is defined as the dedicated output means.

According to the game machine of (3) above, when the power is turned on, the output destination of the data related to the specific sound is specified to the dedicated output means, so it is possible to set which output means to be the dedicated output means.

(1) The 16th game machine is
Output means (for example, speaker 11) capable of outputting a predetermined game sound;
an operation means (for example, a volume setting screen) capable of operating the volume output from the output means;
sound control means (for example, a host control circuit 210 that executes sound request control processing) having a plurality of playback channels and capable of controlling the volume based on the operation of the operation means;
with
The volume output from the output means is at least defined by first information (for example, an audio signal output by the second reproduction channel primary control 285) having information of a constant volume before and after the operation is performed even if the operation means is operated, and second information (for example, an audio signal output by the first reproduction channel primary control 284) having information on a volume that is changed based on the operation of the operation means.
The plurality of reproduction channels include at least a dedicated channel used for outputting a specific sound and a shared channel used for outputting a sound other than the specific sound,
The sound control means is
For the dedicated channel, a specific sound control means (for example, a host control circuit 210 that executes step S580) capable of executing control to output the first information so that a constant volume is output before and after the operation is performed even if the operation means is operated;
For the shared channel, non-specific sound control means (for example, the host control circuit 210 that executes step S581) that can execute control to output the second information so that the volume is changed based on the operation of the operation means.

According to the 16th game machine of (1) above, even if the operation means is operated for the exclusive channel used for outputting the specific sound, it is controlled to output a constant sound volume before and after the operation is performed. That is, although the volume can be operated, constant volume information is output without changing the volume before and after the operation of the operating means. Further, since the shared channel used for outputting sounds other than the specific sound is controlled to change the volume based on the operation of the operating hand capable of operating the volume, the volume can be suitably adjusted.

(2) In the sixteenth gaming machine described in (1) above,
Channel setting means (for example, a host control circuit 210 that executes the process of step S201) for setting dedicated channels (for example, CH31, CH32) used for outputting the specific sound and common channels (for example, CH1 to CH30) used for outputting the sound other than the specific sound when the power is turned on;
sound information registering means (for example, a host control circuit 210 for registering SAC numbers) for registering sound information (for example, SAC numbers) for the data of the specific sounds and sounds other than the specific sounds in the dedicated channel or the shared channel;
is further provided.

According to the 16th game machine of (2) above, when the power is turned on, a dedicated channel used for outputting a specific sound and a shared channel used for outputting a sound other than the specific sound are set, and sound information concerning each data of the specific sound and the sound other than the specific sound is registered in each channel, so that versatility can be improved.

The seventeenth gaming machine is
Output means (for example, speaker 11) capable of outputting a predetermined game sound;
an operation means (for example, a volume setting screen) capable of operating the volume output from the output means;
sound control means (for example, a host control circuit 210 for executing sound request control processing) having a reproduction channel and capable of controlling the volume based on the operation of the operation means;
with
The volume output from the output means is at least defined by first information (for example, an audio signal output by the second reproduction channel primary control 285) having information of a constant volume before and after the operation is performed even if the operation means is operated, and second information (for example, an audio signal output by the first reproduction channel primary control 284) having information on a volume that is changed based on the operation of the operation means.
The sound control means is
data discriminating means (for example, the host control circuit 210 for executing step S599) for discriminating whether or not the game sound data being reproduced on the reproduction channel is specific data for a specific sound;
a specific sound control means (for example, a host control circuit 210 that executes step S600) capable of executing control to output the first information so that a constant volume is output before and after the operation is performed even if the operation means is operated when the data determination means determines that the game sound data being reproduced on the reproduction channel is the specific data;
non-specific sound control means (e.g., host control circuit 210 for executing step S601) capable of executing control to output the second information so that the volume is changed based on the operation of the operation means when the data discrimination means determines that the game sound data being reproduced on the reproduction channel is non-specific data.

According to the seventeenth game machine, when it is determined that the data of the game sound being reproduced is the specific data, even if the operating means is operated, the control is performed so that a constant volume is output before and after the operation is performed, and when the data of the game sound being reproduced is determined to be non-specific data, the volume is controlled to be changed based on the operation of the operating means, so that the volume can be adjusted appropriately.

The 18th game machine is
Output means (for example, speaker 11) capable of outputting a predetermined game sound;
an operation means (for example, a volume setting screen) capable of operating the volume output from the output means;
sound control means (for example, a host control circuit 210 for executing sound request control processing) having a reproduction channel and capable of controlling the volume based on the operation of the operation means;
with
The volume output from the output means is at least defined by first information (for example, an audio signal output by the second reproduction channel primary control 285) having information of a constant volume before and after the operation is performed even if the operation means is operated, and second information (for example, an audio signal output by the first reproduction channel primary control 284) having information on a volume that is changed based on the operation of the operation means.
The sound control means is
a specific sound control means (for example, a host control circuit 210 that executes step S621) capable of setting the first information to the reproduction channel so that, when the sound information (for example, a SAC number) corresponding to the sound output reproduced on the reproduction channel is specific sound information, a constant volume is output before and after the operation is performed even if the operation means is operated;
and non-specific sound control means (for example, host control circuit 210 for executing step S623) capable of setting the second information in the reproduction channel so that the volume is changed based on the operation of the operation means when sound information (for example, SAC number) corresponding to the game sound reproduced in the reproduction channel is non-specific sound information.

According to the eighteenth game machine, when the sound information (for example, SAC number) corresponding to the sound output reproduced on the reproduction channel is specific sound information, the control is performed so that a constant volume is output even if the operation means is operated.

The 19th game machine is
Output means (for example, speaker 11) capable of outputting a predetermined game sound;
an operation means (for example, a volume setting screen) capable of operating the volume output from the output means;
sound control means (for example, a host control circuit 210 for executing sound request control processing) having a reproduction channel and capable of controlling the volume based on the operation of the operation means;
with
The volume output from the output means includes at least first information (e.g., an audio signal output by the second reproduction channel primary control 285) having constant volume information before and after the operation even if the operation means is operated, second information (e.g., an audio signal output by the first reproduction channel primary control 284) having volume information that is changed based on the operation of the operation means, and volume information incorporated in the sound data specified from the sound information registered in the reproduction channel. and third information (e.g., audio signals output by volume controls 286, 287, 288 embedded in the audio data) and
The sound control means is
Identification information setting means (e.g., the host control circuit 210 that executes the process of step S632) that presets identification information (e.g., a flag indicating whether each channel is affected by volume adjustment) that can identify the sound data specified from the sound information (e.g., SAC number) registered in the reproduction channel is specific sound data (e.g., sound data that is not affected by volume adjustment);
a first volume setting means (for example, a host control circuit 210 capable of executing the process of step S641) capable of setting the first information to the reproduction channel so that a constant volume is output before and after the operation is performed even if the operation means is operated when the identification information can identify that the sound data specified by the sound information (for example, the SAC number) is the specific sound data in setting the volume to the reproduction channel;
a second volume setting means (for example, a host control circuit 210 capable of executing the processing of step S638) capable of setting the second information to the reproduction channel so that the volume is changed based on the operation of the operation means when the identification information can identify that the sound data specified by the sound information is not the specific sound data in setting the volume to the reproduction channel (for example, when NO is determined in step S637);
and third volume setting means (for example, the host control circuit 210 capable of executing the process of step S644) for setting third information to the reproduction channel when setting the volume to the reproduction channel.

According to the nineteenth game machine, the identification information is set in advance so that the sound data specified from the sound information registered in the reproduction channel can be identified as the specific sound data, and when the sound information specified from the sound information can be identified as the specific sound data by the identification information, the fixed volume is set to be output even if the operation means is operated. Also, the volume is set to be changed based on the sound data specified from the sound information registered in the reproduction channel. Further, the third information having volume information included in the sound data specified from the sound information registered in the reproduction channel is set in the reproduction channel. In this way, it is possible to suitably adjust the volume.

In the gaming machine described above, when the sound data specified by the sound information (for example, the SAC number) registered in the reproduction channel can be identified as the specific sound data by the identification information (for example, when it is determined as YES in step S637), even if the operation means is operated, a constant volume is output before and after the operation is performed. However, even if the sound data specified from the sound information registered in the reproduction channel is specific sound data (first information related to constant volume), the sound information registered in the reproduction channel (for example, the SAC number) is multiplied with the volume incorporated in the sound data specified, so the output volume may not be constant.

Thus, according to the 15th to 19th gaming machines, it is possible to provide a gaming machine capable of suitably adjusting the sound volume.

[20th game machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a game is known in which a light-emitting means composed of a light-emitting body such as an LED is provided on the front side of the game machine, and the light-emitting means is lighted or blinked in a predetermined manner to perform a light-emitting effect.

As this type of game machine, there is known a game machine in which the luminance of a light emitting means can be adjusted by a player or the like (see, for example, Japanese Patent Application Laid-Open No. 2008-295551).

(11th problem)
According to the gaming machine described in Japanese Patent Application Laid-Open No. 2008-295551, although the brightness of the light emitting means can be challenged by the operation of the player or the like, if the light emitting means can emit light in full color, changing the brightness may significantly change the color of the emitted light.

In order to solve the eleventh problem, a twentieth gaming machine having the following configuration is provided.

The 20th gaming machine is
predetermined light emitting means (for example, lamp (LED) group 18);
Operation means (for example, a luminance setting screen displayed on a liquid crystal display device used as the display device 13) that can be operated to select the luminance of the light emitting means;
storage means (e.g., sub-main ROM 205) for storing a luminance information table (e.g., attenuation table) in which luminance information is set for each of a plurality of colors (e.g., RGB) as luminance information (e.g., luminance attenuation rate) relating to the luminance of the light emitting means;
luminance control means (for example, a host control circuit 210) capable of controlling the luminance of the light emitting means based on the luminance information table when the luminance is selected by the operation means;
with
The storage means
storing a luminance information table in which the luminance information is set for each of the plurality of colors in correspondence with the luminance selectable by the operation means;
The brightness control means is
Based on the luminance information table corresponding to the luminance selected by the operation means, the luminance of the light emitting means can be controlled so that the attenuation rate of blue is the largest and the attenuation rate of red is the smallest among the plurality of colors.

According to the twentieth game machine, the light emission of the light emitting means is controlled based on the luminance information set for each of the plurality of colors so that the attenuation rate of blue is the largest among the plurality of colors and the attenuation rate of red is the smallest. Therefore, even if the luminance of the light emitting means is changed by the operation of a player or the like, for example, it is possible to suppress the change in the emitted color, that is, to maintain the white balance.

As described above, according to the twentieth game machine, it is possible to provide a game machine capable of changing the luminance while suppressing the change in the emission color.

[21st game machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed, for example, on a liquid crystal display based on the result of the lottery.

As this type of game machine, there has been proposed a game machine in which a movable body is arranged on a game board, and by actuating the movable body, an impact is given to the player, thereby increasing motivation for the game. (See, for example, Japanese Unexamined Patent Publication No. 2006-288694).

(12th problem)
For example, in a game machine that operates a movable body as disclosed in Japanese Patent Application Laid-Open No. 2006-288694, movements of the movable body have become more diverse in recent years, and along with this, control for actuating the movable body has become more complicated. Therefore, in recent years, there is a demand for a gaming machine that can suppress the control load while providing a variety of movements of the movable bodies.

In order to solve the twenty-first problem, a twenty-first gaming machine having the following configuration is provided.

The 21st game machine is
prescribed role and
a control means (for example, a host control circuit 210) capable of controlling the operation of the predetermined role;
an actuating member (for example, a solenoid) capable of actuating a member constituting the accessory;
a plurality of light emitting means (e.g., LEDs);
a plurality of connection units (for example, Port0 to Port23) capable of transmitting signals to the connected light emitting means by being connected to any one of the plurality of light emitting means;
a light emission control means (for example, an audio/LED control circuit 220) capable of controlling the light emission means by transmitting a signal to the light emission means through the connection section;
with
The actuating member is
connected to one of the plurality of connection portions, and configured to be able to operate a member constituting the accessory by a signal from the light emission control means;
The control means is
The operation member connected to any one of the plurality of connection portions can be operated in synchronization with the predetermined accessory.

According to the twenty-first game machine, even if the number of operating members increases due to the diversification of the movements of the role, it is possible to maintain the diversity of the movements of the role, suppress the control load for operating the role, and synchronize the role and the operating members.

Thus, according to the twenty-first gaming machine, it is possible to provide a gaming machine capable of suppressing the control load.

[22nd game machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is conducted when a game ball wins a prize in a starting hole, and an effect image is displayed, for example, on a liquid crystal display based on the result of the lottery.

As this type of game machine, there is known a game machine that reads compressed data from a CGROM that stores compressed data of still images and moving images displayed on a liquid crystal display device, decompresses the read compressed data, and generates image data to be output to the liquid crystal display device (see, for example, Japanese Unexamined Patent Application Publication No. 2016-159026).

(13th problem)
However, as described in Japanese Unexamined Patent Application Publication No. 2016-159026, for example, when reading compressed data from a CGROM to generate image data to be output, if the amount of data is large, loading processing takes time. In this case, a watchdog reset may occur even though the loading process is progressing normally, which is not preferable.

In order to solve the thirteenth problem, a twenty-second gaming machine having the following configuration is provided.

(1) The 22nd gaming machine is
a read-only storage area (for example, sub-main 205 or CGROM 206) in which game data related to a game is stored;
A volatile storage area (for example, SRAM 210b or built-in VRAM 237) in which game data related to games can be read and written,
transfer executing means (for example, a host control circuit 210 for executing the data loading process of FIG. 68) for executing a load process for reading the game data stored in the read-only memory area and writing the data to the volatile memory area;
a watchdog timer and
clearing means (for example, a host control circuit 210 having a CPU processor) for clearing the clocking of the watchdog timer after a predetermined period of time has elapsed;
with
The transfer executing means is
It is characterized by having load reprocessing means (host control circuit 210 that executes the processing of step S656) that resets the watchdog timer and executes the load processing again when the load processing exceeds a predetermined time.

According to the twenty-second game machine of (1) above, when the time required for the load processing by the transfer execution means exceeds the predetermined upper limit, the load processing is terminated and the load processing is executed again. Therefore, even when the load processing takes time, it is possible to automatically return.

As described above, according to the twenty-second gaming machine, even if the loading process takes time, it is possible to proceed with the loading process favorably.

(2) In the twenty-second gaming machine described in (1) above,
The clearing means is
When the load process does not exceed the predetermined time, the watchdog timer is cleared (for example, the process of step S655), and only when the load process exceeds the predetermined time, error processing (for example, the process of step S656) is executed without clearing the clocking of the watchdog timer,
The transfer executing means is
The load processing is executed again as the error processing.

According to the 22nd game machine of (2) above, the watchdog timer is cleared when the load processing does not exceed the predetermined time, and the error processing is executed without clearing the watchdog timer only when the load processing exceeds the predetermined time.

[23rd gaming machine, 24th gaming machine]
2. Description of the Related Art Conventionally, in a game machine such as a pachinko machine, a lottery is performed when a game ball enters a starting hole, and a big win game is performed when the result of the lottery is a big win. In addition, for example, a liquid crystal display on which the effect image is displayed is provided, and the effect image determined by lottery is displayed on the liquid crystal display.

In this type of gaming machine, lotteries are performed in various situations, and such lotteries are performed by generating and obtaining random numbers. For example, Japanese Patent Application Laid-Open No. 2017-023629 describes a method of determining the number of digits of a newly obtained random number value, calculating a one-digit numerical value from the reference random number value by the determined number of digits, and arranging the calculated value in each digit to obtain a new numerical value.

(14th problem)
In the random number acquisition process for acquiring random numbers, it is required that the acquired random numbers are less likely to have regularity. However, complicating the process undesirably increases the control load. Therefore, it is preferable to perform a random number acquisition process in which regularity is less likely to occur while suppressing an increase in control load.

In order to solve the 14th problem, a 23rd game machine and a 24th game machine having the following configurations are provided.

The 23rd gaming machine is
A gaming machine that performs a lottery using a predetermined random number,
a real-time clock (for example, an RTC) capable of outputting time information;
Random number generation means (for example, host control circuit 210 that executes the processes in FIGS. 70 and 71) for generating random numbers used in a predetermined lottery;
with
The random number generation means is
initialization means (for example, host control circuit 210 for executing random number initialization processing) that acquires time information from the real-time clock and generates an initial value of random numbers using the acquired time information;
Unsteady update means (host control circuit 210 that executes the process of FIG. 71) for updating the random number when the generated random number is used in the lottery;
steady update means (host control circuit 210 for executing the process of FIG. 70) for periodically updating the random numbers even if the generated random numbers are not used in the lottery;
It is characterized by

According to the 23rd game machine, since the initial value of the random number is generated using the time information obtained from the real-time clock, the obtained random number can be made random, and the occurrence of bias in the obtained random number can be suppressed. In particular, the initial value of the random number is related to the time when the power is turned on, down to minutes and seconds, so it is possible to change the initial value each time.

The 24th game machine is
A gaming machine that performs a lottery using a predetermined random number,
Random number table creation means (for example, the host control circuit 210 that executes the process of step S704) for creating a random number table in which a plurality of random numbers are registered using one of a plurality of random number seeds (for example, random number seeds a to h);
random number acquisition means for acquiring a random number to be used in a predetermined lottery by referring to the random number table created by the random number table creation means (for example, the host control circuit 210 for acquiring a random number from the random number table created in step S704 in the random number acquisition process in step S706);
Reference position updating means for updating the reference position of the random number table at a timing different from the timing at which the random number table is created (host control circuit 210 for updating the reference position of the random number table when a random number is obtained from the random number table in step S706);
with
The random number obtaining means is
After referring to the random number table to obtain a random number, the same random number table in which the reference position is updated can be referenced to obtain the random number to be used in the predetermined lottery without creating the random number table (for example, the packet reception loop in FIG. 73 can be performed to execute the random number obtaining process in step S706).

According to the twenty-fourth game machine, even if there are a plurality of opportunities to acquire random numbers, the same random number table that has already been created is used to update the reference position and acquire the random numbers, so that the random numbers to be acquired can be made irregular and the control load can be reduced.

Thus, according to the 12th game machine and the 13th game machine, it is possible to provide a game machine capable of suitably outputting game sounds.

As described above, according to the twenty-third and twenty-fourth gaming machines, it is possible to provide gaming machines capable of executing processing in which regularity is unlikely to occur while suppressing an increase in the control load.

Further, according to the first to twenty-fourth gaming machines, it is possible to preferably provide a gaming machine capable of suppressing a decline in interest.

1 Pachinko machine (game machine)
2 main body 3 base door 4 glass door 11 speaker 11a speaker box 11b connection terminal group 12 game board 13 display device 15 launching device 16 payout device 18 lamp (LED) group 20 accessory 43 ball passage detector 44 first starting port 45 second starting port 46 normal electric accessories 51, 52 general winning port 53 first big winning port 54 2nd big prize winning port 55 out port 56 game nail 61 special design display device 62 normal design display device 63 normal design reservation display device 64 first special design reservation display device 65 second special design reservation display device 70 main control circuit 71 main CPU
72 Main ROM
73 Main RAM
77 one-chip microcomputer 123 payout/launch control circuit 200 sub-control circuit 201 relay board 202 sub-board 203 control ROM board 204, 204a, 204b CGROM board 205 sub-main ROM
206, 206a, 206b CG ROMs
210 host control circuit 210a sub-work RAM
210b SRAM
220 audio/LED control circuit 230 display control circuit 262 digital audio power amplifier

Claims (1)

A gaming machine capable of executing a process of switching functions between a drawing output destination buffer having a drawing function and a frame buffer having a display function,
a registering means capable of registering image information relating to an effect image to be displayed on a predetermined display means in the drawing output destination buffer;
effect image display control means for controlling display of the effect image on the predetermined display means based on the image information registered by the registration means after switching from the rendering output destination buffer to the frame buffer;
a first light emitting means capable of emitting light in a predetermined manner;
an operation means capable of changing the luminance of the first light emitting means;
first light emission control means capable of changing the luminance of the first light emission means based on the operation of the operation means;
a second light emitting means provided separately from the first light emitting means;
a second light emission control means capable of changing the luminance of the second light emission means;
with
The registration means
When the image information is registered in the drawing output destination buffer, it is possible not to register the new image information,
When the image information registered in the frame buffer switched from the drawing output destination buffer is pause image information for pausing an image, the pause image information can be registered in the drawing output destination buffer switched from the frame buffer,
The second light emission control means is
The gaming machine is characterized in that, when the brightness of the first light emitting means is changed based on the operation of the operating means, the brightness of the second light emitting means can be changed at a timing different from the timing at which the brightness of the first light emitting means is changed.

Images