JP2023097072A - Display device - Google Patents

Abstract

To provide a display device that can suppress a change in luminance by an off-leak of a switching transistor.SOLUTION: A display device 1 comprises a plurality of pixels, and each of the plurality of pixels comprises: a light emitting element EL; a holding capacitor Cs; a drive transistor TD; and a writing transistor T3. The holding capacitor Cs is formed of: a lower part electrode 310 that is connected to a gate electrode of the drive transistor TD, and connected to the writing transistor T3; a first insulation layer 140; a first top part electrode 220 that is connected to a source electrode of the drive transistor TD, and has a first facing part to be arranged facing the lower part electrode 310; a second insulation layer 150; and a second top part electrode 320 that is connected to the source electrode of the drive transistor TD, and has a second facing part to be arranged facing the lower part electrode 310, in which the first facing part and second facing part are formed in a part where the first and second facing parts are not overlapped, and the lower part electrode 310 is formed so as to overlap each of the first facing part and second facing part.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to display devices.

Organic EL elements are known as electro-optical elements used in self-luminous display devices. An organic EL element is an electro-optical element that utilizes the phenomenon that an organic thin film emits light when an electric field is applied thereto, and color gradation is obtained by controlling the current value flowing through the organic EL element. Therefore, an organic EL display device using an organic EL element includes a drive transistor for controlling the current amount of the organic EL element, a storage capacitor for holding the control voltage of the drive transistor, and a control voltage written in the storage capacitor. A pixel circuit including a sampling transistor (writing transistor) is provided for each pixel (see Patent Document 1).

JP 2013-057947 A

By the way, off-leakage of a switching transistor such as a writing transistor reduces the electric charge held in the storage capacitor, thereby reducing light emission current flowing through a light-emitting element such as an organic EL element. It can happen that the brightness changes. Japanese Patent Laid-Open No. 2002-200003 does not disclose suppression of luminance change due to off-leakage of the write transistor.

Accordingly, the present disclosure provides a display device capable of suppressing luminance changes due to off-leakage of switching transistors.

A display device according to an aspect of the present disclosure is a display device including a plurality of pixels arranged two-dimensionally, wherein each of the plurality of pixels includes a light-emitting element and a data signal line. A holding capacitor for holding a data signal, a drive transistor for supplying a current corresponding to the data signal to the light emitting element, and a write transistor connected between the data signal line and a gate electrode of the drive transistor, , a write transistor having one of a source electrode and a drain electrode connected to the data signal line, wherein the storage capacitor includes a gate electrode of the drive transistor and a first electrode layer connected to the write transistor; a first insulating layer covering a first electrode layer; and a second electrode connected to the source electrode of the drive transistor and having a first facing portion arranged on the first insulating layer so as to face the first electrode layer. a second insulating layer covering the first insulating layer and the second electrode layer; and a third electrode connected to the source electrode of the driving transistor and at least partially formed on the second insulating layer. and a third electrode layer having a second facing portion arranged to face the first electrode layer, and the first facing portion and the second facing portion are formed of the display device. The first electrode layers are formed at positions that do not overlap each other in plan view, and the first electrode layers are formed so as to overlap each of the first facing portion and the second facing portion in plan view.

According to the display device according to one embodiment of the present disclosure, change in luminance due to off-leakage of the switching transistor can be suppressed.

FIG. 1 is a plan view schematically showing the configuration of a pixel circuit of a display device according to a comparative example. FIG. 2 is a cross-sectional view schematically showing the configuration of a pixel circuit of a display device according to a comparative example cut along the II-II cutting line in FIG. 3 is a block diagram showing a functional configuration of the display device according to Embodiment 1. FIG. 4 is a circuit diagram showing a configuration of a pixel circuit of the display device according to Embodiment 1. FIG. 5 is a plan view schematically showing the configuration of the pixel circuit of the display device according to Embodiment 1. FIG. 6 is a cross-sectional view schematically showing the configuration of the pixel circuit of the display device according to Embodiment 1, cut along the VI-VI cutting line in FIG. FIG. 7 is a cross-sectional view schematically showing the configuration of the pixel circuit of the display device according to Embodiment 1, cut along the VII-VII cutting line in FIG. FIG. 8 is a diagram for explaining the effect of the display device according to Embodiment 1. FIG. 9 is a timing chart of various gate control signals of the display device according to Embodiment 1. FIG. 10 is a cross-sectional view schematically showing a first example of the configuration of the pixel circuit of the display device according to Embodiment 2, cut along a cutting line corresponding to the VI-VI cutting line in FIG. FIG. 11 is a cross-sectional view schematically showing a second example of the configuration of the pixel circuit of the display device according to Embodiment 2, cut along a cutting line corresponding to the VI-VI cutting line in FIG. FIG. 12 is a cross-sectional view schematically showing the configuration of the pixel circuit of the display device according to Embodiment 2, taken along the cutting line corresponding to the VII-VII cutting line in FIG. 13A and 13B are diagrams for explaining the manufacturing method of the display device according to the second embodiment. 14 is a plan view schematically showing the configuration of the pixel circuit of the display device according to Embodiment 3. FIG. 15 is a cross-sectional view schematically showing the configuration of the pixel circuit of the display device according to Embodiment 3, cut along the XV-XV cutting line of FIG. 14. FIG.

(Circumstances leading to this disclosure)
Prior to the description of the present disclosure, the background to the present disclosure will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a plan view schematically showing the configuration of a pixel circuit 1011 of a display device according to a comparative example. FIG. 2 is a cross-sectional view schematically showing the configuration of a pixel circuit 1011 of a display device according to a comparative example, cut along the II-II cutting line in FIG. Note that hereinafter, a circuit and a region where the circuit is formed may be referred to with the same reference numerals.

As shown in FIG. 1, the sub-pixel circuits 1011R, 1011G and 1011B are formed in three sub-pixel regions 1011R, 1011G and 1011B obtained by dividing the pixel region 1011, respectively. The sub-pixel circuits 1011R, 1011G, and 1011B have the same configuration.

The pixel circuit 1011 is formed of, for example, a first wiring layer, a semiconductor layer, and a second wiring layer arranged in this order on the substrate 110 . The first wiring layer mainly includes control signal lines INI, REF, and WS, reference voltage lines VINI and VREF, one electrodes of storage capacitors Cs _R , Cs _G , and Cs _B (for example, the lower electrode 210 shown in FIG. 2), And it is used as a gate electrode of each transistor. The semiconductor layer is used as the channel region of each transistor. The second wiring layer mainly includes the data signal lines Vdat _R , Vdat _G , Vdat _B , the positive power supply line VCC, the other electrodes of the storage capacitors Cs _R , Cs _G , Cs _B (for example, the first upper electrode shown in FIG. 2). 220), and the source and drain electrodes of each transistor. Different layers are connected by vias. The positive power line VCC is an example of a power line.

The light emitting elements EL _R , E _{G ,} and EL _B included in the pixel circuit ₁₀₁₁ generate data signals ( _data Voltage) Light is emitted with luminance corresponding to Vdat _R , Vdat _G , and Vdat _B. Each of the storage capacitors Cs _R , Cs _G , and Cs _B carries charges on the data signal lines Vdat _R , Vdat for determining the potential difference Vgs between the gate and source of each of the drive transistors _TDR , _TDG , and TD _B , which will be described later. _G , accumulated through Vdat _B ;

Although not shown, a planarization layer is provided to cover the substrate, the first wiring layer, the _{semiconductor layer} , and the _second wiring layer. Formed on top.

In the above description, "R", "G", and "B" are assigned to the symbols of the respective components according to the sub-pixel circuits. , “G” and “B” may be omitted. Taking the holding capacitors Cs _R , Cs _G , and Cs _B as an example, they may also be referred to as holding capacitors Cs.

As shown in FIG. 2, the pixel circuit 1011 has a cross-sectional configuration including a substrate 110, a first undercoat layer 120, a second undercoat layer 130, a first insulating layer 140, a second insulating layer 150, It has metal layers 160 and 180, a light emitting layer 170, a fourth insulating layer 200, a lower electrode 210, a first upper electrode 220, a positive power supply line VCC and a data signal line _VdatG . In the example of FIG. 2, the display device is a top emission display device. That is, the light emitted from the light-emitting elements EL _R , _ELG , and EL _B is emitted in the surface direction of the substrate 110 (Z-axis positive direction).

Substrate 110 is, for example, a glass substrate or a glass film. A plurality of pixels (pixel circuits 1011 ) are formed on the substrate 110 .

The first undercoat layer 120 is provided to cover the surface of the substrate 110 . The first undercoat layer 120 is, for example, an insulating layer (silicon nitride layer) made of a silicon nitride film.

The second undercoat layer 130 is provided so as to cover the surface of the first undercoat layer 120 . The second undercoat layer 130 is, for example, an insulating layer (silicon oxide layer) made of, for example, a silicon oxide film. The electrode formed on the second undercoat layer 130 forms the first wiring layer.

Note that the undercoat layer is not limited to SiO or SiN, and may be a thin film having a barrier property. Also, its thickness can be changed as appropriate.

The lower electrode 210 is part of the electrode formed on the second undercoat layer 130 and functions as one electrode for forming the storage capacitor Cs_conv. The lower electrode 210 is connected to each of the gate electrodes of the write transistor T3 and the drive transistor TD.

The first insulating layer 140 is provided so as to cover the second undercoat layer 130 on which one or more electrodes (first wiring layer) including the lower electrode 210 are formed. A first insulating layer 140 is filled between the lower electrode 210 and the first upper electrode 220 . The first insulating layer 140 is, for example, a silicon oxide film, but may be made of an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film. The electrodes formed on the first insulating layer 140 form a second wiring layer. Note that the holding capacitance Cs_conv shown in FIG. 2 corresponds to the holding capacitance Cs shown in FIG.

The first upper electrode 220 , the positive power line VCC and the data signal line Vdat are part of the electrodes formed on the first insulating layer 140 . In the present embodiment, first upper electrode 220 has a portion (first facing portion) that faces lower electrode 210 and functions as the other electrode for forming storage capacitor Cs_conv. The first facing portion is a portion of the first upper electrode 220 that overlaps the lower electrode 210 in plan view. Note that "A" and "B" are provided facing each other means that another metal layer is not formed at least partly between "A" and "B".

The positive power supply line VCC is connected to the drain electrode of the drive transistor TD and the power supply 30 (see FIG. 3), and is elongated in the X-axis direction in plan view.

A data signal line Vdat _G is a data signal line of the sub-pixel circuit 1011G adjacent to the sub-pixel circuit 1011B. The positive power supply line VCC and the data signal line Vdat _G are provided at positions that do not overlap the lower electrode 210 (the lower electrode 210 of the pixel circuit 1011R) in plan view.

The second insulating layer 150 is provided so as to cover the first insulating layer 140 in which a plurality of electrodes (second wiring layer) including the first upper electrode 220, the data signal line Vdat _G , etc. are formed. The second insulating layer 150 is, for example, thicker (length in the Z-axis direction) than the first insulating layer 140 . The second insulating layer 150 is, for example, a silicon oxide film, but may be composed of an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film. Also, the second insulating layer 150 may be composed of an inorganic insulating film and an organic insulating film. The organic insulating film functions, for example, as a planarization layer for planarizing the surface of the substrate 110 .

The metal layer 160 is an electrode for forming an EL layer, such as an anode. A metal layer 160 is formed for each sub-pixel.

The light-emitting layer 170 is provided for each region partitioned by the third insulating layer 190, and emits light by a light-emitting current corresponding to the amount of charge accumulated in the storage capacitor Cs.

The metal layer 180 is an electrode for forming an EL layer, such as a cathode. Metal layer 180 is connected to negative power supply line VCATH. The metal layer 180 is formed to collectively cover a plurality of pixels. Metal layer 180 is an example of a fourth electrode layer.

The third insulating layer 190 is a bank (partition wall) that partitions the substrate 110 for forming the light emitting layer 170 . The third insulating layer 190 is made of photosensitive thermosetting resin.

The light emitting layer 170, the third insulating layer 190, and the metal layers 160 and 180 form an EL layer.

Note that a protective film, a sealing resin, and a sealing substrate may be laminated in this order on the EL layer (not shown).

Note that the lower electrode 210, the first upper electrode 220, the positive power supply line VCC, and the data signal line Vdat are, for example, molybdenum (Mo), tungsten (W), aluminum (Al), copper (Cu), silver (Ag), and It is made of a metal such as titanium (Ti) or an alloy.

As described above, in the pixel circuit according to the comparative example, the storage capacitor Cs_conv is formed by the lower electrode 210, the first upper electrode 220, and the first insulating layer 140 between the lower electrode 210 and the first upper electrode 220. be done.

Polysilicon semiconductor TFTs (Thin Film Transistors) are generally used for switching transistors such as the compensation transistor T2 and the write transistor T3 shown in FIG. 1 from the viewpoint of emphasizing high-speed operation. However, the polysilicon semiconductor TFT has a relatively large off-leakage current due to leakage caused by crystal defects and the like, and the electric charge held in the storage capacitor Cs_conv escapes. The light emission current flowing through the element EL is reduced, and the desired luminance (desired gradation value) cannot be displayed, or the desired luminance cannot be maintained.

The off-leakage current of a polysilicon semiconductor TFT tends to depend on process control (control of Si crystallinity) at the time of manufacturing, and there is a limit to how much the existing technology can reduce it. Factors that cause off-leakage current include sub-threshold leakage current (drain-source leakage), gate leakage current (gate insulating film leakage), GIDL (gate-induced-drain-leakage current) current, and junction leakage current ( crystalline defect leakage current) is exemplified.

Accordingly, the inventors of the present application conducted extensive research on a display device capable of suppressing a change in luminance due to off-leakage of a switching transistor, and created the display device described below.

Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings. It should be noted that each embodiment described below is a specific example of the present disclosure. Therefore, numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of constituent elements, and the like shown in the following embodiments are examples and are not intended to limit the present disclosure. Therefore, among the constituent elements in each of the following embodiments, the constituent elements not described in the independent claims of the present disclosure will be described as optional constituent elements.

Each figure is a schematic diagram and is not necessarily strictly illustrated. Moreover, in each figure, the same code|symbol is attached|subjected to the substantially same structure, and the overlapping description is abbreviate|omitted or simplified.

In the present specification and drawings, the X-axis, Y-axis and Z-axis indicate the three axes of a right-handed three-dimensional orthogonal coordinate system. In each embodiment, the Z-axis direction is defined as the stacking direction of each layer. In this specification, “planar view” means the case where the pixel circuit is viewed along the thickness direction of the pixel circuit.

In addition, in this specification, terms that indicate the relationship between elements such as identical and parallel, terms that indicate the shape of elements such as rectangular and long, and numerical values and numerical ranges are strictly meaning only is not an expression that represents a substantially equivalent range, for example, a difference of about several percent (for example, about 10%).

(Embodiment 1)
[1-1. Configuration of display device]
First, a schematic configuration of the display device 1 according to the present embodiment will be described with reference to FIGS. 3 to 5. FIG. FIG. 3 is a block diagram showing the functional configuration of the display device 1 according to this embodiment. In the following description, for the sake of brevity, the same reference numerals may be used to refer to a signal and a wiring that transmits the signal.

As shown in FIG. 3, the display device 1 includes a display module 10, a control section 20, and a power supply 30. The display module 10 has a display panel 12 (display unit), a gate driver 13 and a data driver 14 .

The display panel 12 is configured by arranging a plurality of pixel circuits 11 (pixels) two-dimensionally (in a matrix). That is, the display panel 12 has a plurality of pixel rows L. FIG. Each pixel circuit 11 has sub-pixel circuits 11R, 11G, and 11B (sub-pixels) corresponding to R, G, and B emission colors, respectively. In the present embodiment, an example in which each of a plurality of pixels forming a plurality of pixel rows L has an organic EL element as a light emitting element will be described, but the present invention is not limited to this. The display panel 12 may have a QLED (Quantum-dot Light Emitting Diode) element as a light emitting element.

Each row of the matrix is provided with three control signal lines INI, REF and WS connected to the plurality of pixel circuits 11 arranged in the same row. Control signal lines INI, REF and WS transmit control signals INI, REF and WS supplied from the gate driver 13 to the pixel circuit 11 . Note that the number of control signal lines and the control signals are just an example, and the present invention is not limited to this example. Also, the control signal lines INI, REF, and WS are examples of scanning lines.

A scanning line is arranged for each of a plurality of pixel rows L, and provided for selecting a pixel row L for writing a data signal corresponding to a video signal.

Each column in matrix is provided with three data signal lines Vdat _R , Vdat _G , and Vdat _B connected to a plurality of pixel circuits 11 arranged in the same column. The data signal lines Vdat _R , Vdat _G , and Vdat _B transmit data signals Vdat _R , Vdat _G , and Vdat _B related to the emission luminance of R, G, and B supplied from the data driver 14 to the pixel circuit 11 , respectively. do.

Although the gate driver 13 is arranged on one side of the display panel 12 in FIG. 3, it may be arranged on both sides. In addition, the data driver 14 may be implemented in the display panel 12 as a COG (Chip on Glass) or as a COF (Chip On Film).

The control unit 20 controls each component of the display module 10 . The control unit 20 receives a video signal from the outside and supplies control signals for displaying an image of each frame of the video signal on the display panel 12 to the gate driver 13 and the data driver 14 .

The power supply 30 supplies operating power to the display panel 12 , the gate driver 13 , the data driver 14 , and the control section 20 . The power supply 30 supplies the display panel 12 with, for example, reference voltages VINI, VREF, a positive power supply voltage VCC, and a negative power supply voltage VCATH.

Here, the detailed configuration of the pixel circuit 11 will be described with reference to FIGS. 4 to 7. FIG. FIG. 4 is a circuit diagram showing the configuration of the pixel circuit 11 of the display device 1 according to this embodiment.

As shown in FIG. 4, the sub-pixel circuits 11R, 11G, and 11B forming the pixel circuit 11 have the same configuration. The configuration of the pixel circuit 11 will be described below, focusing on the sub-pixel circuit 11R.

The sub-pixel circuit 11R has an initialization transistor T1- _R , a compensation transistor T2- _R , a write transistor T3- _R , a storage capacitor Cs- _R , a drive transistor TD _-R , and a light-emitting element EL _-R . Also, the sub-pixel circuit 11R has control signal lines INI, REF, WS, reference voltage lines VINI, VREF, data signal lines Vdat _R , positive power line VCC, and negative power line VCATH. Note that the initialization transistor _T1R and the compensation transistor _T2R are not essential components.

The initialization transistor _T1R is turned on according to the control signal INI, and sets the source node of the driving transistor _TDR to the reference voltage (reference voltage) VINI.

The compensation transistor _T2R is turned on according to the control signal REF, and supplies the reference voltage VREF to the gate electrode (gate node) of the driving transistor _TDR . This corresponds to initializing the potential of the electrode (eg, anode) of the light emitting element _ELR .

The write transistor T3- _R is turned on according to the control signal WS, and causes the voltage of the data signal Vdat- _R to be held in the holding capacitor Cs- _R . The write transistor T3- _R is connected between the data signal line Vdat- _R and the gate electrode of the drive transistor TD- _R . Specifically, one of the source electrode and the drain electrode of the write transistor _T3R is connected to the data signal line _VdatR , and the other of the source electrode and the drain electrode is connected to one of the source electrode and the drain electrode of the compensation transistor _T2R . , is connected to the gate electrode of the drive transistor _TDR .

One of the source and drain electrodes of the drive transistor TD _R is connected to the positive power supply line VCC, and the other of the source and drain electrodes is connected to the anode of the light emitting element EL _R. The data signal stored in the storage capacitor Cs _R is A light emitting current corresponding to Vdat _R is supplied to the light emitting element EL _R. As a result, the light emitting element EL _R emits light with luminance corresponding to the data signal Vdat _R.

The holding capacitor _CsR holds the data signal _VdatR supplied via the data signal line _VdatR . Although the details will be described later, the holding capacitor _CsR according to the present disclosure has a larger capacity than the holding capacitor _CsR according to the comparative example. The holding capacitance _CsR according to the present disclosure is realized by a combined capacitance of the holding capacitance Cs_conv shown in the comparative example and the holding capacitance Cs_add (see FIG. 6).

The light-emitting element EL _R is a self-luminous light-emitting element, and is an organic EL (Electro Luminescence) element in this embodiment. An anode electrode of the light emitting element EL _R is connected to one of a source electrode and a drain electrode of the driving transistor _TDR . A cathode voltage (negative power supply voltage VCATH) is applied to the cathode electrode of the light emitting element EL _R through a cathode power supply line (negative power supply line VCATH).

Note that the gate potential _VgR shown in FIG. 4 indicates the potential of the gate electrode of the drive transistor _TDR , and the source potential _VsR indicates the potential of the source electrode of the drive transistor _TDR .

Each transistor described above is configured by, for example, an n-type thin film transistor (n-type TFT), but may be configured by a p-type thin film transistor (p-type TFT). Also, for each transistor described above, for example, a polysilicon semiconductor TFT is used, but the present invention is not limited to this.

Here, the cross-sectional configuration of the pixel circuit 11 will be described with reference to FIGS. 5 to 7. FIG. FIG. 5 is a plan view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to this embodiment. FIG. 6 is a cross-sectional view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, taken along the line VI-VI in FIG. FIG. 7 is a cross-sectional view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment taken along line VII-VII in FIG.

As shown in FIGS. 5 to 7, the pixel circuit 11 according to the present embodiment has a lower electrode 310 instead of the lower electrode 210 of the pixel circuit 1011 according to the comparative example, and furthermore has a second upper electrode 320 and a second upper electrode 320 . It has 4 insulating layers 200 .

The lower electrode 310 is connected to the gate electrode of the drive transistor TD _R and the write transistor T3 _R , and functions as one electrode for forming the storage capacitors Cs_conv and Cs_add. The lower electrode 310 is an electrode having a larger area in plan view than the lower electrode 210 according to the comparative example. The lower electrode 310 is formed, for example, so as to partially cover the first upper electrode 220 and the second upper electrode 320 in plan view. For example, the lower electrode 310 is provided so as to overlap the first opposing portion of the first upper electrode 220 and the second opposing portion of the second upper electrode 320 in plan view. For example, the lower electrode 310 is formed across the positive power supply line VCC. Note that the lower electrode 310 does not overlap the data signal line (the data signal line Vdat _G in the example of FIG. 6) of the adjacent sub-pixel circuit in plan view.

In a plan view, the lower electrode 310 has a first electrode portion 310a that faces the first upper electrode 220, a second electrode portion 310b that faces the first electrode portion 320a, and a second electrode portion 320b that faces the second electrode portion 320b. It has a third electrode portion 310c and a fourth electrode portion 310d connected to the gate electrode of the drive transistor _TDR . The lower electrode 310 covers the first upper electrode 220 (for example, the first facing portion described later), the first electrode portion 320a and the second electrode portion 320b.

The first electrode portion 310a is, for example, rectangular, and the second electrode portion 310b and the third electrode portion 310c are elongated. For example, the second electrode portion 310b and the third electrode portion 310c are elongated along the positive power line VCC. The lower electrode 310 has a configuration in which the positive power supply line VCC is sandwiched between the second electrode portion 310b and the third electrode portion 310c in plan view. The first electrode portion 310a corresponds to the lower electrode 210 shown in the comparative example. The fourth electrode portion 310d is an example of a first wiring portion.

A portion of the lower electrode 310 that overlaps the first upper electrode 220 and the second upper electrode 320 in a plan view, that is, a portion of the lower electrode 310 that covers the first upper electrode 220 and the second upper electrode 320 is a third facing portion. is an example. Also, in plan view, the portion of the first upper electrode 220 that overlaps with the lower electrode 310 is an example of the first facing portion. It can also be said that the first upper electrode 220 has a first facing portion arranged to face the lower electrode 310 on the first insulating layer 140 . The first upper electrode 220 is an example of a second electrode layer.

As shown in FIGS. 6 and 7 , the pixel circuit 11 has a second upper electrode 320 and a third insulating layer 190 between the second insulating layer 150 and the metal layer 160 .

The first insulating layer 140 is formed to cover the second undercoat layer 130 on which one or more electrodes (first wiring layer) including the lower electrode 310 are formed. It can also be said that the first insulating layer 140 is formed to cover the lower electrode 310 .

The second insulating layer 150 is formed to cover the first insulating layer 140 on which one or more electrodes (second wiring layer) including the first upper electrode 220 are formed. It can also be said that the second insulating layer 150 covers the first upper electrode 220 and the first insulating layer 140 .

The second upper electrode 320 is at least partially formed on the second insulating layer 150 and functions as the other electrode for forming the storage capacitor Cs_add. The second upper electrode 320 is connected to one of the source electrode and the drain electrode of the driving transistor _TDR through the connecting portion 330 . That is, the second upper electrode 320 is electrically connected to the first upper electrode 220 and has the same potential. In addition, in the present embodiment, the second upper electrode 320 is connected to one of the source electrode and the drain electrode of the initialization transistor _T1R through the connection portion 330 . The second upper electrode 320 is an example of a third electrode layer.

Note that the connecting portion 330 connects the first upper electrode 220 to one of the source electrode and the drain electrode of the driving transistor _TDR . The connecting portion 330 is an example of a second wiring portion.

Note that the connection between the connection portion 330 and the second upper electrode 320 is realized at the contact portion C, as shown in FIG. A through-hole 151 is formed in the second insulating layer 150 at a position where the connecting portion 330 and the second upper electrode 320 (for example, the third electrode portion 320c) overlap. 330 and the second upper electrode 320 are connected. For example, the connection portion 330 directly formed on the first insulating layer 140 and the second upper electrode 320 are connected in the through hole 151 . It can also be said that the second upper electrode 320 is electrically connected to the source electrode of the driving transistor TD through the connection portion 330 .

The second upper electrode 320 has a first electrode portion 320a, a second electrode portion 320b and a third electrode portion 320c. In this embodiment, the second upper electrode 320 is directly formed on the second insulating layer 150 .

The first electrode portion 320a has a portion facing the second electrode portion 310b, and is provided closer to the data signal line Vdat _R than the positive power supply line VCC. The first electrode portion 320a is elongated in the X-axis direction along the positive power supply line VCC. The first electrode portion 320a is a portion that overlaps with the lower electrode 310 (for example, the second electrode portion 310b) in plan view.

The second electrode portion 320b has a portion facing the third electrode portion 310c, and is between the positive power supply line VCC and the data signal line (data signal line Vdat _G in the example of FIG. 5) of the adjacent sub-pixel. provided in The first electrode portion 320a is elongated in the X-axis direction along the positive power supply line VCC. The second electrode portion 320b is a portion that overlaps with the lower electrode 310 (for example, the third electrode portion 310c) in plan view.

The first electrode portion 320a and the second electrode portion 320b are provided at positions that do not overlap with the first facing portion in plan view. The first electrode portion 320a and the second electrode portion 320b are formed so as to sandwich the positive power supply line VCC in plan view. The first electrode portion 320a and the second electrode portion 320b may be provided in parallel in plan view. Also, the length in the X-axis direction of the second electrode portion 320b may be the same as the length in the X-axis direction of the first electrode portion 320a. The first electrode portion 320a and the second electrode portion 320b are examples of the second facing portion.

The third electrode portion 320c is long in a direction intersecting (for example, a direction orthogonal to) the longitudinal direction (X-axis direction) of the first electrode portion 320a and the second electrode portion 320b in plan view, and is the first electrode portion 320c. It is provided to electrically connect the electrode portion 320 a and the second electrode portion 320 b to the connection portion 330 . The third electrode portion 320c is formed to cover the inner surface of the through hole 151, for example. Further, the third electrode portion 320c intersects the fourth electrode portion 310d in plan view, and overlaps with a part of the fourth electrode portion 310d.

From the viewpoint of suppressing an increase in parasitic capacitance of the existing wiring, the second upper electrode 320 is preferably formed in a region where there is no signal line or the like in the lower layer.

The fourth insulating layer 200 is provided so as to cover the second insulating layer 150 on which one or more electrodes (third wiring layer) including the second upper electrode 320 are formed. The fourth insulating layer 200 is, for example, a silicon oxide film, but may be made of an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film.

Note that the constituent materials of each electrode layer described above are, for example, titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), molybdenum (Mo), silver (Ag), and neodymium (Nd). and copper (Cu). Alternatively, it may be a compound containing at least one of them or a laminated film containing two or more of them. Also, for example, a transparent conductive film such as ITO may be used.

As described above, in the pixel circuit 11 according to the present embodiment, in addition to the storage capacitor Cs_conv shown in the pixel circuit 1011 according to the comparative example, the lower electrode 310, the second upper electrode 320, and the lower electrode 310 and the second upper electrode A storage capacitor Cs_add is formed by the first insulating layer 140 and the second insulating layer 150 between 320 . Specifically, a first auxiliary holding capacitance between the second electrode portion 310b and the first electrode portion 320a, a second auxiliary holding capacitance between the third electrode portion 310c and the second electrode portion 320b, and a A holding capacity Cs_add is formed by a combined capacity of the third auxiliary holding capacity between the four-electrode portion 310d and the third electrode portion 320c.

The holding capacitance Cs_add is expressed by the following (equation 1 ).

Cs_add=ε0×εx×S/d1 (Formula 1)

Note that ε0 indicates the permittivity of vacuum, and εx indicates the relative permittivity. Also, the total holding capacitance Cs of the pixel circuit 11 can be calculated by the following (Equation 2).

Cs=Cs_conv+Cs_add (Formula 2)

The holding capacitor Cs has a value larger than the holding capacitor Cs_conv.

Thus, the display device 1 according to the present embodiment can make the holding capacitor Cs larger than the holding capacitor Cs_conv described in the comparative example.

Also, in plan view, the overlapping area of the second electrode portion 310b and the first electrode portion 310a and the overlapping area of the third electrode portion 310c and the second electrode portion 310b may be equal, for example. That is, the holding capacitance Cs_add formed by the second electrode portion 310b and the first electrode portion 310a may be equal to the holding capacitance Cs_add formed by the third electrode portion 310c and the second electrode portion 310b. Note that the two holding capacitors Cs_add are not limited to being equal, and may be different from each other.

[1-2. Effect of increasing the retention capacity]
The effect of increasing the holding capacitance Cs will be described with reference to FIG. FIG. 8 is a diagram for explaining the effects of the display device 1 according to this embodiment. The vertical axis of FIG. 8 indicates the degree of decrease in pixel current (luminescence current), and the horizontal axis indicates time. FIG. 8 shows a comparison of the degree of reduction in pixel current during one frame between the display device 1 and the display device of the prior art, based on the value of the pixel current at the start of one frame. Note that the conventional technology means a display device in which the storage capacitor of the pixel circuit is formed only by the storage capacitor Cs_conv of the storage capacitors Cs_conv and Cs_add.

As shown in FIG. 8, in the display device 1 according to the present embodiment, a decrease in pixel current during one frame is suppressed ("-ΔIpix improved). Since the display device 1 has a larger holding capacitance Cs than the conventional one, the amount of accumulated charge is also larger than the conventional one. On the other hand, the amount of pixel current that leaks due to off-leakage is constant regardless of the storage capacitor Cs. In other words, in the display device 1, the ratio of the amount of charge reduction due to off-leakage to the amount of accumulated charge is small. Therefore, in the display device 1 according to the present embodiment, as shown in FIG. 8, the degree of decrease in the pixel current is moderated, so the decrease in the emission current is suppressed, and the change in luminance due to off-leakage can be suppressed. .

For example, when the combined holding capacitance of the holding capacitance Cs_conv and the holding capacitance Cs_add is 1.5 times the holding capacitance of the single holding capacitance Cs_conv, the potential difference Vgs between the gate and source of the drive transistors _TDR , _TDG , and _TDB decreases. can be suppressed to about 0.67 times, the corresponding decrease in the pixel current Ipix can be suppressed.

Note that the display device 1 according to the present embodiment has a configuration in which a combined storage capacitor Cs of the storage capacitor Cs_conv and the storage capacitor Cs_add is formed, so the pixel current increases as the storage capacitor increases. Therefore, in the display device 1, the pixel current flowing through the light-emitting element EL when the pixel value is the same is the same as when the display device 1 has a configuration in which the storage capacitor Cs is formed only by the storage capacitor Cs_conv (for example, a configuration according to the comparative example). so that the data signal may be conditioned.

[1-3. Operation of Pixel Circuit]
Operation of the pixel circuit 11 will be described with reference to FIG. FIG. 9 is a diagram showing a timing chart of various gate control signals (control signals INI, REF, WS) of the display device 1 according to this embodiment.

As shown in FIG. 9, the period from time t1 to time t4 is the extinguishing period. At time t1, the control signal REF changes from low level to high level to turn on the compensation transistors T2 _R , T2 _G , and T2 _B , thereby starting the extinguishing period. A period from time t2 to time t3 is an initialization period during which the control signal REF is at low level, the control signal INI is at high level, and the initialization operation is performed. Time t3 to time t4 is a threshold compensation period (Vth compensation period) during which the control signal REF is at high level, the control signal INI is at low level, and the threshold compensation operation is performed.

From time t4 to time t5, since the control signal WS is at high level, the write transistors T3 _R , T3 _G and T3 _B are turned on, and the data signal lines Vdat _R are applied to the storage capacitors Cs _R , Cs _G and Cs _B , respectively. , Vdat _G and Vdat _B are written. A period from time t4 to time t5 is a data write period. From time t4 to time t5, for example, charges are accumulated simultaneously in the holding capacitors Cs_conv and Cs_add.

Then, at time t5, the control signal WS becomes low level, so that the light emitting elements EL _R , EL _G , and EL _B emit light.

Note that the light-off period is a period for initial setting, specifically a period in which the sub-pixel circuit is not lit (that is, black display). Assuming that there are n pixel rows and one horizontal period is 1H, the off period is a period defined by n×H, for example. Note that "black display" is not limited to being completely black (non-light emitting), but includes being substantially black, and may also include, for example, having a predetermined luminance or less.

[1-4. effects, etc.]
_{In the} following, _the effects _{of the} display device 1 will be described _. line and data signal Vdat, storage capacitors Cs _R , Cs _G , Cs _B are described as storage capacitors Cs, drive transistors TD _R , TD _G , TD _B are described as drive transistors TD, write transistors T3 _R , T3 _G and T3 _B are referred to as write transistor T3.

As described above, the display device 1 according to the present embodiment is a display device including a plurality of pixels (pixel circuits 11) arranged two-dimensionally. Each of the plurality of pixels includes a light emitting element EL, a storage capacitor Cs that holds a data signal supplied through a data signal line Vdat, and a driving transistor TD that supplies a current corresponding to the data signal Vdat to the light emitting element EL. , a write transistor T3 connected between the data signal line Vdat and the gate electrode of the drive transistor TD, wherein one of the source electrode and the drain electrode is connected to the data signal line Vdat. The storage capacitor Cs is composed of a lower electrode 310 (an example of a first electrode layer) connected to the gate electrode of the drive transistor TD and the write transistor T3, a first insulating layer 140 covering the lower electrode 310, and the drive transistor TD. A first upper electrode 220 connected to the source electrode and having a first facing portion disposed on the first insulating layer 140 to face the lower electrode 310; and a second upper electrode 320 (an example of a third electrode layer) connected to the source electrode of the driving transistor TD and at least partially formed on the second insulating layer 150 and facing the lower electrode 310 . and a second upper electrode 320 having a second opposing portion (for example, a first electrode portion 320a and a second electrode portion 320b) that are arranged in parallel with each other. The lower electrodes 310 are formed so as not to overlap each other in plan view, and the lower electrode 310 is formed so as to overlap each of the first facing portion and the second facing portion in plan view.

Accordingly, in addition to the storage capacitor Cs_conv formed by the lower electrode 310, the first upper electrode 220 (first facing portion), and the first insulating layer 140, the lower electrode 310, the second upper electrode 320 (second facing portion), and A storage capacitor Cs_add formed of the first insulating layer 140 (or the first insulating layer 140 and the second insulating layer 150) is formed. That is, in the display device 1, each of the plurality of pixels has a larger storage capacitance Cs than in the conventional case. As described with reference to FIG. 8, such a display device 1 is less susceptible to off-leakage because the amount of accumulated charge is larger than that of the conventional device. Therefore, the display device 1 according to the present embodiment can suppress changes in brightness due to off-leakage of the write transistor T3 (switching transistor).

Also, the second facing portion is formed directly on the second insulating layer 150 .

As a result, the holding capacitor Cs_add is formed by the second opposing portion (for example, the first electrode portion 320a and the second electrode portion 320b) directly formed on the second insulating layer 150 and the lower electrode 310, so that each pixel can be increased.

The lower electrode 310 has a third facing portion covering the first facing portion and the second facing portion, and a fourth electrode portion 310d connecting the third facing portion and the gate electrode of the driving transistor TD. The upper electrode 320 overlaps a part of the fourth electrode portion 310d (an example of the first wiring portion) in plan view.

As a result, capacitance is formed even in the portion where the second upper electrode 320 and the fourth electrode portion 310d overlap, so that the storage capacitance Cs_add can be further increased.

In addition, the first facing portion has a rectangular shape in plan view, and the second facing portion has an elongated shape in plan view.

As a result, the first facing portion and the second facing portion are formed with different shapes, so even if there is a limit to the layout area in which the first facing portion and the second facing portion can be provided, the holding capacitor Cs_add can be effectively increased.

In addition, the second insulating layer 150 is located at a position where the second upper electrode 320 overlaps the connection portion 330 (an example of the second wiring portion) that connects the first upper electrode 220 and the source electrode of the driving transistor TD in plan view. A through hole 151 is formed, and the second upper electrode 320 is electrically connected to the source electrode of the drive transistor TD through the through hole 151 .

As a result, the second upper electrode 320 can be formed wider, so that the storage capacitance Cs_add can be further increased.

Further, a positive power supply line VCC (an example of a power supply line) is provided which is connected to the drain electrode of the drive transistor TD and formed in a long shape in plan view. They are formed so as to sandwich the line VCC.

This makes it possible to effectively increase the storage capacitance Cs_add by utilizing the space around the positive power supply line VCC in plan view.

(Embodiment 2)
The display device according to the present embodiment will be described below with reference to FIGS. 10 to 13. FIG. In the following, differences from the first embodiment will be mainly described, and descriptions of the same or similar contents as those of the first embodiment will be omitted or simplified. In this embodiment, an example in which the other electrode forming the storage capacitor Cs_add is formed below the upper surface of the second insulating layer 150 will be described. A configuration in which the other electrode is formed in the through hole of the second insulating layer 150 will be described with reference to FIG. will be explained.

[2-1. Configuration of display device]
FIG. 10 is a cross-sectional view schematically showing a first example of the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, taken along a cutting line corresponding to the VI-VI cutting line in FIG.

As shown in FIG. 10, the first electrode portion 320a and the second electrode portion 320b of the second upper electrode 320 are not on the second insulating layer 150, but on the through holes 152 and 153 formed in the second insulating layer 150. formed. In the example of FIG. 10, the through holes 152 and 153 are recesses penetrating the second insulating layer 150 in the Z-axis direction. In the second insulating layer 150, recesses (through holes 152 and 153) penetrating to the first insulating layer 140 side (the negative side of the Z axis) at positions overlapping with the first electrode portion 320a and the second electrode portion 320b in plan view. can be said to be formed.

In this case, the first electrode part 320 a and the second electrode part 320 b are formed on the first insulating layer 140 . That is, the first electrode portion 320a, the second electrode portion 320b, and the first upper electrode 220 are formed in the same layer (second wiring layer), and the distance d2 to the lower electrode 310 is the same. The distance d2 is a distance smaller than the distance d1.

The first electrode portion 320a is arranged between the first upper electrode 220 and the positive power supply line VCC so as not to contact each other in a cross-sectional view, and the second electrode portion 320b is arranged between the positive power supply line VCC and the data signal. and the line Vdat _G so as not to contact each other. That is, the first electrode portion 320a and the second electrode portion 320b are electrically isolated from the first upper electrode 220, the positive power line VCC and the data signal line _VdatG , respectively. The first electrode portion 320 a and the second electrode portion 320 b have a portion (first portion) facing the lower electrode 310 .

The storage capacitor Cs_add is calculated as follows, where S is the overlapping area of the lower electrode 310 and the second upper electrode 320 in plan view, and d2 is the distance between the lower electrode 310 and the second upper electrode 320. It can be calculated by (Equation 3).

Cs_add=ε0×εx×S/d2 (Formula 3)

The first electrode portion 320a is formed to cover the inner surface 152a of the through hole 152, and the second electrode portion 320b is formed to cover the inner surface 153a of the through hole 153. As shown in FIG. The through holes 152 and 153 are formed at positions that do not overlap each electrode (the first upper electrode 220, the positive power supply line VCC and the data signal line Vdat _G ) of the second wiring layer in plan view. The through-hole 152 is formed between the first upper electrode 220 and the positive power supply line VCC in plan view and is elongated along the positive power supply line VCC. It is formed in an elongated shape along the positive power supply line VCC between the line VCC and the data signal line _VdatG . For example, the through holes 152 and 153 are parallel through grooves in plan view.

A portion of the first electrode portion 320a formed on the inner surface 152a of the through hole 152 (an example of the second portion), and a portion of the second electrode portion 320b formed on the inner surface 153a of the through hole 153 (second portion). ) extends along the positive power supply line VCC in plan view. By forming electrodes on the inner surfaces 152 a and 153 a , capacitance is formed between the electrodes and the lower electrode 310 . In other words, by forming the electrodes on the inner surfaces 152a and 153a, an effect of further increasing the holding capacitance Cs_add is expected. Note that the second portion is connected to the first portion.

The number of through holes 152 and 153 formed in the second insulating layer 150 is not limited to two. There may be one, or three or more. Moreover, the through holes 152 and 153 are not limited to being through grooves, and may be realized by a plurality of cylindrical through holes.

FIG. 11 is a cross-sectional view schematically showing a second example of the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, cut along a cutting line corresponding to the VI-VI cutting line in FIG.

As shown in FIG. 11 , the first electrode portion 320 a and the second electrode portion 320 b of the second upper electrode 320 are formed in recesses 154 and 155 formed in the second insulating layer 150 . In the example of FIG. 11, the recesses 154 and 155 are bottomed (non-penetrating) grooves that do not penetrate the second insulating layer 150 in the Z-axis direction. In the second insulating layer 150, bottomed recesses 154 and 155 recessed toward the first insulating layer 140 side (Z-axis negative side) are formed at positions overlapping with the first electrode portion 320a and the second electrode portion 320b in plan view. It can be said that it is.

Since the concave portions 154 and 154 are bottomed grooves, the first electrode portion 320 a and the second electrode portion 320 b are formed on the bottom surfaces of the concave portions 154 and 155 . That is, the first electrode portion 320a and the second electrode portion 320b are formed between the second wiring layer and the third wiring layer, and the distance to the lower electrode 310 is the distance d3. The distance d3 is smaller than the distance d1 and larger than the distance d2 (see FIG. 10).

The positions in plan view where the recesses 154 and 155 are formed are the same as the through holes 152 and 153 .

The holding capacitance Cs_add is expressed by the following (Equation 4 ).

Cs_add=ε0×εx×S/d3 (Formula 4)

The first electrode portion 320 a is formed to cover the inner surface of the recess 154 , and the second electrode portion 320 b is formed to cover the inner surface of the recess 155 .

FIG. 12 is a cross-sectional view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, taken along the cutting line corresponding to the VII-VII cutting line in FIG.

As shown in FIG. 12, since the second upper electrode 320 overlaps the third electrode portion 310c in a plan view, a holding capacitance Cs_add is also formed between the second upper electrode 320 and the third electrode portion 310c. Thereby, the holding capacitance Cs can be further increased. Further, in the example of FIG. 12, no recess is formed above the third electrode portion 310c. Above the third electrode portion 310c is a region where the third electrode portion 310c and the fourth electrode portion 310d overlap in plan view. Since the region is physically close to the drive transistor TD, no recess is formed in the region in consideration of the influence on the operation of the drive transistor TD.

In this case, the overlapping area of the second electrode portion 310b and the first electrode portion 320a in a plan view is S1, and the storage capacitor formed by the second electrode portion 310b and the first electrode portion 320a is Cs_add_1 (in FIG. 12). Cs_add) between the second electrode portion 310b and the first electrode portion 320a; The holding capacitance Cs_add_2 (holding capacitance Cs_add between the fourth electrode portion 310d and the third electrode portion 320c in FIG. 12) formed with the first electrode portion 320a and the following (Equation 5) holds: .

Cs_add_2/S2<Cs_add_1/S1 (Formula 5)

The second insulating layer 150 has a bottomed concave portion formed above the third electrode portion 310c to such an extent that it does not affect the operation of the driving transistor TD. may be formed. The depth of such recesses can be obtained by, for example, experiments.

The number of recesses 154 and 155 formed in the second insulating layer 150 is not limited to two. It may be three or more. Further, the recesses 154 and 155 are not limited to groove-shaped recesses, and may be realized by a plurality of cylindrical recesses.

[2-2. Display device manufacturing method]
Next, a method for manufacturing the through holes 151, the recesses 154 and the recesses 155 shown in FIGS. 11 and 12 will be described with reference to FIG. 13A and 13B are diagrams for explaining the manufacturing method of the display device 1 according to the present embodiment. FIG. 13 schematically shows an exposure process for forming through-holes 151, recesses 154 and recesses 155. As shown in FIG. Note that the amount of light (eg, UV light) incident on the photomask 500 is, for example, uniform in plan view. Also, although the resin that is the material of the second insulating layer 150 is assumed to be a positive photosensitive resin, it is not limited to this.

After the first wiring layer including the lower electrode 310 is formed on the first insulating layer 140, the second insulating layer 150 is formed by applying a positive photosensitive resin for forming the second insulating layer 150 and pre-baking. is cured (provisionally cured) with , exposed with a photomask 500 shown in FIG.

As shown in FIG. 13, through holes 151, recesses 154 and recesses 155 are formed by an exposure process using a photomask 500. As shown in FIG. The photomask 500 has a light blocking portion 510 , a transmission portion 520 and a halftone portion 530 . The photomask 500 is a multi-tone mask configured to have two or more transmissive portions having different light transmittances in addition to the light shielding portion 510 .

The light shielding portion 510 is provided in a region where the through hole 151, the concave portion 154 and the concave portion 155 are not formed (for example, the region including the third electrode portion 310c is formed), and is a portion that blocks light incident on the photomask 500. .

The transmission portion 520 is provided in a region where the through hole 151 is formed, and is a portion that transmits light incident on the photomask 500 .

The halftone portion 530 is provided in a region where a groove with a bottom is formed (for example, a region where the first electrode portion 310a and the second electrode portion 310b are formed), and partially transmits light incident on the photomask 500. This is the part to do. The halftone portion 530 has a lower transmittance than the transmissive portion 520 and a higher transmittance than the light shielding portion 510 . The halftone portion 530 is elongated in the X-axis direction.

By using such a photomask 500, grooves having different depths (for example, through grooves and non-through grooves) can be formed by one exposure. When forming the through holes 152 and 153 shown in FIG. 10, a photomask in which the halftone portion 530 is replaced with the transmission portion 520 may be used.

[2-3. effects, etc.]
As described above, in the second insulating layer 150 of the display device 1 according to the present embodiment, the first insulating layer 140 side (Z Bottomed recesses 154 and 155 are formed on the bottom surface of the recesses 154 and 155 (for example, the first electrode portion 320a and the second electrode portion 320b). may be

As a result, the distances between the first electrode portion 320a and the second electrode portion 320b and the lower electrode 310 can be shortened, so that the storage capacitance Cs_add can be further increased. A second insulating layer 150 exists between the first electrode portion 320a and the second electrode portion 320b and the underlying signal line. Therefore, the display device 1 can increase the storage capacitance Cs while suppressing short-circuiting of the first electrode portion 320a and the second electrode portion 320b with other signal lines.

Further, in the second insulating layer 150, through holes 152 and 153 (an example of recessed portions) are formed through the first insulating layer 140 side at positions overlapping with the lower electrode 310 in plan view. are formed directly on the first insulating layer 140 .

As a result, the distance between the first electrode portion 320a and the second electrode portion 320b and the lower electrode 310 can be reduced to the distance d2 between the first upper electrode 220 and the lower electrode 310, so that the storage capacitance Cs_add can be further increased. can be done. Therefore, the display device 1 can further increase the storage capacitance Cs.

The second facing portion is composed of a first portion facing the lower electrode 310 and a second portion formed on the inner surface of the recess (for example, the inner surfaces 152a and 153a of the through holes 152 and 153).

Thereby, a capacitance is formed by the second portion and the lower electrode 310, so that the storage capacitance Cs_add can be further increased.

(Embodiment 3)
The display device according to this embodiment will be described below with reference to FIGS. 14 and 15. FIG. In the following, differences from the first embodiment will be mainly described, and descriptions of the same or similar contents as those of the first embodiment will be omitted or simplified. In this embodiment, the case where the VCC auxiliary line 410 and the VCATH auxiliary line 420 are formed in the pixel circuit 11 will be described. Although FIG. 14 shows an example in which both the VCC auxiliary line 410 and the VCATH auxiliary line 420 are formed in the pixel circuit 11, at least one of the VCC auxiliary line 410 and the VCATH auxiliary line 420 is formed. All you have to do is

[3-1. Configuration of display device]
FIG. 14 is a plan view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to this embodiment. FIG. 15 is a cross-sectional view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, taken along line XV-XV in FIG.

As shown in FIGS. 14 and 15, the pixel circuit 11 of the display device 1 according to the present embodiment includes a VCC auxiliary line 410 and a VCATH auxiliary line 420 in addition to the pixel circuit 11 according to the first embodiment. The VCC auxiliary line 410 is an example of a first auxiliary line, and the VCATH auxiliary line 420 is an example of a second auxiliary line.

The VCC auxiliary line 410 is a wiring that is electrically connected to the positive power supply line VCC and provided in the pixel circuit 11 to suppress the voltage drop of the positive power supply voltage VCC within the display area. The VCC auxiliary line 410 is, for example, a metal wiring having a lower resistance than the positive power supply line VCC. For example, the VCC auxiliary line 410 is metal wiring. Further, the VCC auxiliary line 410 is elongated along the data signal line Vdat so as to at least partially overlap the data signal line Vdat (in the example of FIG. 14, the data signal line Vdat _R ) in a plan view, for example. Although formed, it does not have to overlap with the data signal line Vdat. The VCC auxiliary line 410 is provided for each pixel, for example.

The VCATH auxiliary line 420 is a wiring that is electrically connected to the metal layer 180 and provided within the pixel circuit 11 to suppress voltage drop of the negative power supply voltage VCATH within the display area. The VCATH auxiliary line 420 is, for example, metal wiring having a lower resistance than the metal layer 180 . For example, the VCATH auxiliary line 420 is a metal wiring. Further, the VCATH auxiliary line 420 is elongated along the data signal line Vdat so as to at least partially overlap the data signal line Vdat (data signal line Vdat _B in the example of FIG. 14) in plan view, for example. However, it does not have to overlap with the data signal line Vdat. The VCATH auxiliary line 420 is provided for each pixel, for example.

The VCC auxiliary line 410 and the VCATH auxiliary line 420 are formed on the second insulating layer 150, and the pixel circuit 11 having the VCC auxiliary line 410 and the VCATH auxiliary line 420 is formed on the fourth insulating layer 200. FIG. The VCC auxiliary line 410 and the VCATH auxiliary line 420 are provided at positions that do not overlap the lower electrode 310 and the connecting portion 330 in plan view.

Therefore, in the pixel circuit 11 having the VCC auxiliary line 410 and the VCATH auxiliary line 420, without forming an additional layer, the VCC auxiliary line 410 and the VCATH auxiliary line 420 are not formed in the area other than the area where the VCC auxiliary line 410 and the VCATH auxiliary line 420 are formed in plan view. A second top electrode 320 may be formed.

Assuming that the distance between the data signal line Vdat _R and the VCC auxiliary line 410 is d4, and the distance between the data signal line Vdat _R and the first electrode portion 320a and the second electrode portion 320b is d5, the following (Equation 6) holds.

d4>d5 (Formula 6)

Since the insulating layer (second insulating layer 150) below the VCC auxiliary line 410 is thick, short-circuiting between the data signal line Vdat _R and the VCC auxiliary line 410 can be suppressed. That is, the insulation between the data signal line Vdat _R and the VCC auxiliary line 410 can be maintained.

Although the VCATH auxiliary line 420 is not shown in FIG. 15, the distance between the data signal line Vdat _R and the VCATH auxiliary line 420 is also the distance d4.

At least a part of the second electrode portion 320b and the third electrode portion 320c is provided on the lower electrode 310 side (Z-axis minus side) with respect to the VCC auxiliary line 410 and the VCATH auxiliary line 420 in a cross-sectional view.

[3-2. effects, etc.]
As described above, the display device 1 according to the present embodiment is connected to the drain electrode of the driving transistor TD, and is connected to the positive power supply line VCC formed in a long shape in a plan view and the positive power supply line VCC. , and a VCC auxiliary line 410 (an example of a first auxiliary line) having a resistance lower than that of the positive power supply line VCC. Also, the VCC auxiliary line 410 may be formed on the second insulating layer 150 . Further, the display device 1 according to the present embodiment includes a metal layer 180 (an example of a fourth electrode layer) that is connected to the cathode electrode of the light emitting element EL and covers a plurality of pixels, and a metal layer 180 that is connected to the metal layer A VCATH auxiliary line 420 (an example of a second auxiliary line) having a resistance lower than 180, and the VCATH auxiliary line 420 may be formed on the second insulating layer 150 .

Accordingly, in the display device 1 in which at least one of the VCC auxiliary line 410 and the VCATH auxiliary line 420 is provided, the second upper insulating layer 150 is provided on the second insulating layer 150 for forming at least one of the auxiliary lines. An electrode 320 can be formed. In other words, the display device 1 does not need to include a dedicated insulating layer for forming the second upper electrode 320 . Therefore, the display device 1 capable of suppressing a change in luminance due to off-leakage can be realized at low cost.

(Other embodiments)
Although the display device according to the present disclosure has been described above based on each embodiment, the display device according to the present disclosure is not limited to the above embodiments. Another embodiment realized by combining arbitrary components in each embodiment, and a modification obtained by applying various modifications that a person skilled in the art can think of without departing from the scope of the present disclosure for each embodiment For example, the present disclosure also includes various devices incorporating the display device according to the present embodiment.

For example, one of the trenches formed in the second insulating layer (the trench for forming the storage capacitor) may be a through trench and the other may be a bottomed trench.

Further, the present disclosure described above may be implemented as a single display panel. The present disclosure may be implemented in a configuration that does not include a power supply and controller. Such a display panel includes a plurality of pixels arranged two-dimensionally, and each of the plurality of pixels holds a light-emitting element and a data signal supplied via a data signal line. a storage capacitor, a driving transistor for supplying a current corresponding to a data signal to the light emitting element, and a writing transistor connected between the data signal line and the gate electrode of the driving transistor, wherein one of the source electrode and the drain electrode is and a write transistor connected to the data signal line. The storage capacitor includes a first electrode layer connected to the gate electrode of the driving transistor and the writing transistor, a first insulating layer formed on the first electrode layer, and a source electrode of the driving transistor. A second electrode layer having a first electrode part arranged on the insulating layer so as to face the first electrode layer, a second insulating layer formed on the first insulating layer, and a source electrode of the driving transistor are connected. and a third electrode layer at least partially formed on the second insulating layer, the third electrode layer having a second electrode portion disposed facing the first electrode layer. The first electrode portion and the second electrode portion are provided at positions that do not overlap each other in plan view of the display panel, and the first electrode layer covers the first electrode portion and the second electrode portion. Note that the ICs forming the control unit may be mounted on the display panel.

Also, the present disclosure described above may be implemented as a single active matrix substrate. The present disclosure may be implemented in a configuration that does not include a power source, a control unit, and an EL layer (eg, a light-emitting layer and electrode layers sandwiching the light-emitting layer). Such an active matrix substrate is used in a display device having a plurality of pixels arranged two-dimensionally, and pixel circuits for forming each of the plurality of pixels include light emitting elements, A holding capacitor for holding a data signal supplied through a data signal line, a drive transistor for supplying a current corresponding to the data signal to a light emitting element, and a gate electrode of the data signal line and the drive transistor. A write transistor having one of a source electrode and a drain electrode connected to a data signal line, wherein the storage capacitor includes a gate electrode of the drive transistor and a first electrode layer connected to the write transistor. a first insulating layer formed on the first electrode layer; and a first electrode portion connected to the source electrode of the drive transistor and arranged on the first insulating layer to face the first electrode layer. an electrode layer, a second insulating layer formed on the first insulating layer, and a third electrode layer connected to the source electrode of the driving transistor and at least partially formed on the second insulating layer, It is formed by one electrode layer and a third electrode layer having a second electrode portion arranged to face each other. The first electrode portion and the second electrode portion are provided at positions that do not overlap each other in plan view of the active matrix substrate, and the first electrode layer covers the first electrode portion and the second electrode portion.

Further, in each of the above-described embodiments, an example in which the display panel is a top-emission display panel has been described, but the display panel may be a bottom-emission display panel.

Also, the control section and the data driver in each of the above embodiments may be realized by one IC, or may be realized by different ICs.

The functions and configurations of the initialization transistors _T1G and _T1B in each of the above embodiments are, for example, the same as those of the initialization transistors _T1R , and the functions and configurations of the compensation transistors _T2G and _T2B are, for example, compensation The function and configuration of the write transistors _T3G and T3B are the same as the transistor _T2R , the function and configuration of the write transistors T3G and _T3B are the same as the write transistor _T3R , and the function and configuration of the drive transistors _TDG and _TDB are the same as the drive transistor TD It may be the same as _R.

Further, the functions and configurations of the light emitting elements EL _G and EL _B in each of the above embodiments may be the same as those of the light emitting element EL _R , for example.

Also, the functions and configurations of the holding capacitors _CsG and _CsB in each of the above embodiments may be the same as those of the holding capacitor _CsR , for example.

Moreover, although the display device in each of the above embodiments has been described as an example of displaying a color image, it is not limited to this, and may display a monochrome image, for example.

The present disclosure is useful, for example, for display devices using organic EL elements and the like.

Reference Signs List 1 display device 10 display module 11 pixel circuit 11B, 11G, 11R sub-pixel circuit 12 display panel 13 gate driver 14 data driver 20 control section 30 power supply 110 substrate 120 first undercoat layer 130 second undercoat layer 140 first insulating layer 150 second insulating layer 151 through hole 152, 153 through hole (recess)
152a, 153a inner surface 154, 155 recess 160 metal layer 180 metal layer (fourth electrode layer)
170 Light Emitting Layer 190 Third Insulating Layer 200 Fourth Insulating Layer 220 First Upper Electrode (Second Electrode Layer)
310 lower electrode (first electrode layer)
310a first electrode portion 310b second electrode portion 310c, 320c third electrode portion 310d fourth electrode portion (first wiring portion)
320 second upper electrode (third electrode layer)
320a first electrode portion (second facing portion)
320b second electrode portion (second facing portion)
330 connection part (second wiring part)
410 VCC auxiliary line (first auxiliary line)
420 VCATH auxiliary line (second auxiliary line)
500 photomask 510 light shielding portion 520 transmission portion 530 halftone portion C contact portion Cs, Cs _B , Cs _G , Cs _R , Cs_add, Cs_conv Storage capacitors d1, d2, d3, d4, d5 Distances EL _B , _ELG , EL _R light emitting element INI initialization signal line, control signal L pixel row REF reference signal line, control signal t1, t2, t3, t4, t5 time T1 _B , T1 _G , T1 _R initialization transistor T2 _B , T2 _G , T2 _R compensation Transistors T3 _B , T3 _G , T3 _R Write transistors TD _B , TD _G , TD _R drive transistors VCATH Negative power supply line, negative power supply voltage VCC Positive power supply line (power supply line), positive power supply voltage Vdat _B , Vdat _G , Vdat _R data Signal line, data signal WS Write signal line, control signal

Claims (11)

A display device comprising a plurality of pixels arranged two-dimensionally,
each of the plurality of pixels,
a light emitting element;
a holding capacitor for holding a data signal supplied via a data signal line;
a driving transistor that supplies a current corresponding to the data signal to the light emitting element;
a write transistor connected between the data signal line and a gate electrode of the drive transistor, wherein one of a source electrode and a drain electrode is connected to the data signal line;
The holding capacity is
a gate electrode of the drive transistor and a first electrode layer connected to the write transistor;
a first insulating layer covering the first electrode layer;
a second electrode layer connected to the source electrode of the drive transistor and having a first facing portion arranged on the first insulating layer so as to face the first electrode layer;
a second insulating layer covering the first insulating layer and the second electrode layer;
a third electrode layer connected to the source electrode of the drive transistor and at least partially formed on the second insulating layer, the second opposing portion being arranged to face the first electrode layer; and a third electrode layer having
The first facing portion and the second facing portion are formed at positions that do not overlap each other in a plan view of the display device,
The display device, wherein the first electrode layer is formed so as to overlap with each of the first facing portion and the second facing portion in plan view. The display device according to claim 1, wherein the second facing portion is directly formed on the second insulating layer. In the second insulating layer, a bottomed recess recessed toward the first insulating layer is formed at a position overlapping the first electrode layer in plan view,
The display device according to claim 1, wherein the second facing portion is formed on the bottom surface of the recess. The second insulating layer has a recess penetrating toward the first insulating layer at a position overlapping with the first electrode layer in plan view,
The display device according to claim 1, wherein the second facing portion is formed on the first insulating layer. 5. The display device according to claim 3, wherein the second facing portion is composed of a first portion facing the first electrode layer and a second portion formed on an inner surface of the recess. moreover,
a power supply line connected to the drain electrode of the drive transistor and formed in an elongated shape in the plan view;
a first auxiliary line connected to the power line and having a resistance lower than that of the power line;
The display device according to any one of claims 1 to 5, wherein the first auxiliary line is formed on the second insulating layer. moreover,
a fourth electrode layer connected to the cathode electrode of the light emitting element and covering the plurality of pixels;
a second auxiliary line connected to the fourth electrode layer and having a resistance lower than that of the fourth electrode layer;
The display device according to any one of claims 1 to 6, wherein the second auxiliary line is formed on the second insulating layer. The first electrode layer is
a third facing portion covering the first facing portion and the second facing portion;
a first wiring portion connected to the gate electrode of the drive transistor;
The display device according to any one of claims 1 to 7, wherein the third electrode layer overlaps with a part of the first wiring portion in the plan view. The first facing portion has a rectangular shape in the plan view,
The display device according to claim 8, wherein the second facing portion has an elongated shape in the plan view. A through hole is formed in the second insulating layer at a position where the third electrode layer overlaps with the second wiring portion connecting the second electrode layer and the source electrode of the driving transistor in the plan view. cage,
The display device according to any one of claims 1 to 9, wherein the third electrode layer is electrically connected to the source electrode of the drive transistor through the through hole. further comprising a power supply line connected to the drain electrode of the drive transistor and formed in an elongated shape in the plan view;
The display device according to any one of claims 1 to 5, wherein the second facing portion is formed so as to sandwich the power line in the plan view.

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