JP2023087028A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of reducing an on-resistance while suppressing a decrease in a breakdown voltage.SOLUTION: A semiconductor device 1 includes: a semiconductor layer 2 having a first principal surface 3; an n-type drift region 54 formed in a surface layer part of the first principal surface 3; a trench gate structure 61 formed on the first principal surface 3 and including a gate trench 65 including a first side wall 62, a second side wall 63, and a bottom wall 64 in the drift region 54, an insulation layer 66 formed in an inner wall of the gate trench 65, and an embedded electrode 67 embedded in the gate trench 65 across the insulation layer 66, and applied with a gate voltage; and an n+-type high concentration drift region 91 formed in a region along an outer wall of the trench gate structure 61 in the drift region 54 and having an n-type impurity concentration exceeding an n-type impurity concentration of the drift region 54.SELECTED DRAWING: Figure 7

Description

The present invention relates to semiconductor devices.

Patent Document 1 discloses a trench gate power semiconductor device. This semiconductor device includes a drift layer formed with a groove, a gate insulating film formed on the inner surface of the groove, and a gate electrode film embedded in the groove with the gate insulating film interposed therebetween.

Patent Document 2 discloses a semiconductor device having a power transistor with a trench gate structure. This semiconductor device includes an epitaxial layer (drift layer) having a main surface in which a groove is formed, a gate insulating layer formed on the inner surface of the groove, a dummy gate electrode and a gate buried in the groove with the gate insulating layer interposed therebetween. an electrode and an insulating layer interposed between the dummy gate electrode and the gate electrode.

WO2012/165319A1 Japanese Patent Application Laid-Open No. 2006-202931

In the field of semiconductor devices having a trench gate structure, one of the challenges is to reduce the on-resistance. One possible way to reduce the on-resistance is to increase the concentration of the drift layer. In this case, the on-resistance can be reduced by increasing the carrier density. However, if the concentration of the entire drift layer is increased collectively, electric field concentration tends to occur in the semiconductor layer, resulting in a decrease in breakdown voltage.

An embodiment of the present invention provides a semiconductor device capable of reducing on-resistance while suppressing a decrease in breakdown voltage.

One embodiment of the present invention includes a semiconductor layer having a main surface, a drift region of a first conductivity type formed in a surface layer portion of the main surface, sidewalls and a bottom wall formed in the main surface, the drift region having sidewalls and a bottom wall. an insulating layer formed on an inner wall of the trench; and a buried electrode buried in the trench with the insulating layer interposed therebetween and to which a gate voltage is applied; and the trench in the drift region a first conductivity type high concentration drift region formed in a region along an outer wall of a gate structure and having a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the drift region; .

According to this semiconductor device, a region serving as a main current path in the drift region is highly doped by the high-concentration drift region. As a result, it is possible to avoid increasing the concentration in the entire drift region, thereby reducing the on-resistance while suppressing a decrease in the breakdown voltage.

FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention, viewed from one direction. FIG. 2 is a block circuit diagram showing the electrical structure of the semiconductor device shown in FIG. FIG. 3 is a cross-sectional perspective view of region III shown in FIG. 1, and is a cross-sectional perspective view showing a configuration including a high-concentration drift region according to the first configuration example. FIG. 4 is a cross-sectional perspective view with the electrodes removed from FIG. FIG. 5 is a cross-sectional perspective view of FIG. 4 with an interlayer insulating layer removed. 6 is a plan view of FIG. 5. FIG. FIG. 7 is an enlarged cross-sectional view of the area containing the two trench gate structures shown in FIG. FIG. 8 is an enlarged cross-sectional view of one trench gate structure shown in FIG. FIG. 9 is a plan view of the region IX shown in FIG. 1, showing the structure of part of the input region of the semiconductor layer. 10 is a cross-sectional view taken along line X-X shown in FIG. 9. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 9. FIG. 12A is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view for explaining an example of a method for manufacturing the semiconductor device shown in FIG. 1. FIG. FIG. 12B is a cross-sectional view for explaining the process after FIG. 12A. FIG. 12C is a cross-sectional view for explaining the process after FIG. 12B. FIG. 12D is a cross-sectional view for explaining the process after FIG. 12C. FIG. 12E is a cross-sectional view for explaining the process after FIG. 12D. FIG. 12F is a cross-sectional view for explaining the process after FIG. 12E. FIG. 12G is a cross-sectional view for explaining the process after FIG. 12F. FIG. 12H is a cross-sectional view for explaining the process after FIG. 12G. FIG. 12I is a cross-sectional view for explaining the process after FIG. 12H. FIG. 12J is a cross-sectional view for explaining the process after FIG. 12I. FIG. 12K is a cross-sectional view for explaining the process after FIG. 12J. FIG. 12L is a cross-sectional view for explaining the process after FIG. 12K. FIG. 12M is a cross-sectional view for explaining the process after FIG. 12L. FIG. 12N is a cross-sectional view for explaining the process after FIG. 12M. FIG. 12O is a cross-sectional view for explaining the process after FIG. 12N. FIG. 12P is a cross-sectional view for explaining the process after FIG. 12O. FIG. 12Q is a cross-sectional view for explaining the process after FIG. 12P. FIG. 12R is a cross-sectional view for explaining the process after FIG. 12Q. FIG. 12S is a cross-sectional view for explaining the process after FIG. 12R. FIG. 12T is a cross-sectional view for explaining the process after FIG. 12S. FIG. 12U is a cross-sectional view for explaining the process after FIG. 12T. FIG. 12V is a cross-sectional view for explaining the process after FIG. 12U. 13A is a cross-sectional view of a region corresponding to FIG. 7, showing a form in which a high-concentration drift region according to a second form example is formed. FIG. FIG. 13B is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which a high-concentration drift region according to the third embodiment is formed. FIG. 13C is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which a high-concentration drift region according to a fourth form example is formed. FIG. 13D is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which a high-concentration drift region according to the fifth embodiment is formed. FIG. 13E is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which a high-concentration drift region according to the sixth embodiment is formed. FIG. 13F is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which a high-concentration drift region according to the seventh embodiment is formed. FIG. 13G is a cross-sectional perspective view of the region corresponding to FIG. 5, and is a cross-sectional perspective view showing a form in which a high-concentration drift region according to the eighth embodiment is formed. FIG. 14 is a cross-sectional view of a region corresponding to FIG. 7, showing a semiconductor device according to a second embodiment of the present invention. FIG. 15 is a perspective view showing a semiconductor package in which the semiconductor device shown in FIG. 1 is incorporated, through a sealing resin. 16 is a plan view of FIG. 15. FIG.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a perspective view of a semiconductor device 1 according to a first embodiment of the present invention, viewed from one direction.

Referring to FIG. 1, semiconductor device 1 includes a semiconductor layer 2 . The semiconductor layer 2 contains silicon. The semiconductor layer 2 is formed in a chip shape having a rectangular parallelepiped shape. The semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4. ing.

The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in plan view (hereinafter simply referred to as "plan view") as seen from the normal direction Z thereof. The side surface 5A and the side surface 5C extend along the first direction X and face each other in a second direction Y intersecting the first direction X. As shown in FIG. The side surface 5B and the side surface 5D extend along the second direction Y and face each other in the first direction X. The second direction Y is, more specifically, orthogonal to the first direction X. As shown in FIG.

An output region 6 and an input region 7 are set in the semiconductor layer 2 . The output region 6 is set in a region on the side surface 5</b>D of the first main surface 3 of the semiconductor layer 2 . The input region 7 is set in a region on the side surface 5B side of the first main surface 3 of the semiconductor layer 2 .

In plan view, the area S1 of the output region 6 is equal to or larger than the area S2 of the input region 7 (S2≦S1). A ratio S1/S2 of the area S1 to the area S2 may exceed 1 and be 10 or less (1<S1/S2≦10). The ratio S1/S2 may be greater than 1 and 5 or less, or 5 or more and 10 or less. The planar shape of the input area 7 and the planar shape of the output area 6 are arbitrary and are not limited to specific shapes.

The output region 6 includes a power MISFET (Metal Insulator Semiconductor Field Effect Transistor) 9 having a gate, drain and source as an example of an insulated gate transistor.

The input area 7 includes a control IC (Integrated Circuit) 10 as an example of a control circuit. The control IC 10 includes multiple types of functional circuits that implement various functions. The plurality of types of functional circuits include circuits that generate gate control signals for driving and controlling the power MISFET 9 based on electrical signals from the outside. The control IC 10 forms a so-called IPD (Intelligent Power Device) together with the power MISFET 9 . The IPD is also called an IPM (Intelligent Power Module).

Input region 7 is electrically isolated from output region 6 by region isolation structure 8 . In FIG. 1, the region isolation structures 8 are indicated by hatching. Although a detailed description is omitted, the region isolation structure 8 may have a trench isolation structure in which a trench is filled with an insulator.

A plurality of (six in this embodiment) electrodes 11 , 12 , 13 , 14 , 15 , 16 and a gate control wiring 17 are formed on the semiconductor layer 2 . In FIG. 1, a plurality of electrodes 11 to 16 and gate control wiring 17 are indicated by hatching. The plurality of electrodes 11-16 includes a power supply electrode 11 (drain electrode), an output electrode 12 (source electrode), an input electrode 13, a reference potential electrode 14, an ENABLE electrode 15 and a SENSE electrode 16 in this embodiment.

The number, arrangement and planar shape of the plurality of electrodes 11 to 16 are arbitrary, and are not limited to the form shown in FIG. The number, arrangement and planar shape of the plurality of electrodes 11 to 16 are adjusted according to the specifications of the power MISFET 9 and the specifications of the control IC 10 .

A power electrode 11 is formed on the second main surface 4 of the semiconductor layer 2 . The power electrode 11 is electrically connected to the second main surface 4 of the semiconductor layer 2 . The power supply electrode 11 transmits the power supply voltage to the drain of the power MISFET 9 and various circuits of the control IC 10 .

The power electrode 11 may include at least one of a Ti layer, Ni layer, Au layer, Ag layer, and Al layer. The power electrode 11 may have a single layer structure including a Ti layer, Ni layer, Au layer, Ag layer, or Al layer. The power supply electrode 11 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer and an Al layer are laminated in an arbitrary manner.

An output electrode 12 is formed on the output region 6 . The output electrode 12 is electrically connected to the source of the power MISFET9. The output electrode 12 transmits an electric signal generated by the power MISFET 9 to the outside.

An input electrode 13, a reference potential electrode 14, an ENABLE electrode 15 and a SENSE electrode 16 are formed on the input region 7 respectively. Input electrode 13 transmits an input voltage for driving control IC 10 .

Reference potential electrode 14 transmits a reference potential (for example, ground potential) to control IC 10 . ENABLE electrode 15 transmits an electrical signal for enabling or disabling some or all of the functions of control IC 10 . SENSE electrode 16 transmits an electrical signal for detecting an abnormality in control IC 10 .

The gate control wiring 17 is selectively routed to the output region 6 and the input region 7 . The gate control wiring 17 includes a first gate control wiring 17A and a second gate control wiring 17B in this form. The number of gate control wirings 17 is arbitrary, and is adjusted according to the transmission distance of gate control signals and the number of gate control signals to be transmitted.

The gate control wiring 17 is electrically connected to the gate of the power MISFET 9 in the output region 6 and electrically connected to the control IC 10 in the input region 7 . Gate control wiring 17 transmits a gate control signal generated by control IC 10 to the gate of power MISFET 9 . A gate control signal includes a gate voltage and a reference potential. On/off of the power MISFET 9 is controlled by a gate control signal.

Output electrode 12, input electrode 13, reference potential electrode 14, ENABLE electrode 15, SENSE electrode 16, and gate control wiring 17 each contain at least one of nickel, palladium, aluminum, copper, an aluminum alloy, or a copper alloy. You can

The output electrode 12, the input electrode 13, the reference potential electrode 14, the ENABLE electrode 15, the SENSE electrode 16 and the gate control wiring 17 are made of Al--Si--Cu (aluminum--silicon--copper) alloy, Al--Si (aluminum--silicon) alloy. , or at least one of Al—Cu (aluminum-copper) alloys.

The output electrode 12, the input electrode 13, the reference potential electrode 14, the ENABLE electrode 15, the SENSE electrode 16, and the gate control wiring 17 may contain the same type of electrode material, or may contain mutually different electrode materials. .

FIG. 2 is a block circuit diagram showing the electrical structure of semiconductor device 1 shown in FIG. A case where the semiconductor device 1 is mounted in a vehicle will be described below as an example.

Semiconductor device 1 includes power supply electrode 11 , output electrode 12 , input electrode 13 , reference potential electrode 14 , ENABLE electrode 15 , SENSE electrode 16 , gate control wiring 17 , power MISFET 9 and control IC 10 .

The power electrode 11 is connected to a power source. Power supply electrode 11 provides power supply voltage to power MISFET 9 and control IC 10 . The power supply voltage may be 10V or more and 20V or less. The output electrode 12 is connected to a load.

The input electrode 13 may be connected to an MCU (Micro Controller Unit), a DC/DC converter, an LDO (Low Drop Out), or the like. Input electrode 13 provides an input voltage to control IC 10 . The input voltage may be between 1V and 10V. The reference potential electrode 14 is connected to the reference potential wiring. Reference potential electrode 14 provides a reference potential to power MISFET 9 and control IC 10 .

The ENABLE electrode 15 may be connected to the MCU. An electric signal for enabling or disabling some or all of the functions of the control IC 10 is input to the ENABLE electrode 15 . The SENSE electrode 16 may be connected to a resistor.

A gate of the power MISFET 9 is connected to a control IC 10 (a gate control circuit 25 to be described later) via a gate control wiring 17 . A drain of the power MISFET 9 is connected to the power supply electrode 11 . A source of the power MISFET 9 is connected to a control IC 10 (a current detection circuit 27 to be described later) and an output electrode 12 .

Control IC 10 includes sensor MISFET 21 , input circuit 22 , voltage control circuit 23 , protection circuit 24 , gate control circuit 25 , active clamp circuit 26 , current detection circuit 27 , reverse connection protection circuit 28 and abnormality detection circuit 29 .

A gate of the sensor MISFET 21 is connected to the gate control circuit 25 . A drain of the sensor MISFET 21 is connected to the power electrode 11 . A source of the sensor MISFET 21 is connected to the current detection circuit 27 .

Input circuit 22 is connected to input electrode 13 and voltage control circuit 23 . Input circuit 22 may include a Schmitt trigger circuit. The input circuit 22 shapes the waveform of the electrical signal applied to the input electrode 13 . A signal generated by the input circuit 22 is input to the voltage control circuit 23 .

The voltage control circuit 23 is connected to a protection circuit 24 , a gate control circuit 25 , a power supply reverse connection protection circuit 28 and an abnormality detection circuit 29 . Voltage control circuit 23 generates various voltages according to the electrical signal from input circuit 22 and the electrical signal from protection circuit 24 . The voltage control circuit 23 includes a drive voltage generation circuit 30 , a first constant voltage generation circuit 31 , a second constant voltage generation circuit 32 and a reference potential/reference current generation circuit 33 in this embodiment.

The drive voltage generation circuit 30 generates a drive voltage for driving the gate control circuit 25 . The drive voltage may be set to a value obtained by subtracting a predetermined value from the power supply voltage. The drive voltage generation circuit 30 may generate a drive voltage of 5 V or more and 15 V or less by subtracting 5 V from the power supply voltage. A drive voltage is input to the gate control circuit 25 .

A first constant voltage generation circuit 31 generates a first constant voltage for driving the protection circuit 24 . The first constant voltage generation circuit 31 may include a Zener diode. The first constant voltage may be 1 V or more and 5 V or less. The first constant voltage is input to the protection circuit 24 (more specifically, an open load detection circuit 35 and the like, which will be described later).

A second constant voltage generation circuit 32 generates a second constant voltage for driving the protection circuit 24 . The second constant voltage generation circuit 32 may include a regulator circuit. The second constant voltage may be 1 V or more and 5 V or less. The second constant voltage is input to the protection circuit 24 (more specifically, an overheat protection circuit 36 and a low-voltage malfunction suppression circuit 37, which will be described later).

The reference potential/reference current generation circuit 33 generates reference potentials and reference currents for various circuits. The reference potential may be 1 V or more and 5 V or less. The reference current may be 1 mA or more and 1 A or less. A reference potential and a reference current are input to various circuits. When various circuits include comparators, the reference potential and reference current may be input to the comparators.

The protection circuit 24 is connected to the voltage control circuit 23 , the gate control circuit 25 , the abnormality detection circuit 29 , the source of the power MISFET 9 and the source of the sensor MISFET 21 . Protection circuit 24 includes an overcurrent protection circuit 34 , an open load detection circuit 35 , an overheat protection circuit 36 and a low voltage malfunction suppression circuit 37 .

The overcurrent protection circuit 34 is connected to the source of the gate control circuit 25 and the sensor MISFET21. An overcurrent protection circuit 34 protects the power MISFET 9 from overcurrent. Overcurrent protection circuit 34 may include a current monitor circuit. A signal generated by the overcurrent protection circuit 34 is input to the gate control circuit 25 (more specifically, a drive signal output circuit 40 described later).

The open load detection circuit 35 is connected to the voltage control circuit 23 and the source of the power MISFET 9 . A load open detection circuit 35 detects a short-circuited state or an open state of the power MISFET 9 . A signal generated by the open load detection circuit 35 is input to the voltage control circuit 23 .

The overheat protection circuit 36 is connected to the voltage control circuit 23 . Overheat protection circuit 36 monitors the temperature of semiconductor device 1 . The overheat protection circuit 36 may include temperature sensitive devices such as temperature sensitive diodes and thermistors. An overheat protection circuit 36 protects the power MISFET 9 from excessive temperature rise. A signal generated by the overheat protection circuit 36 is input to the voltage control circuit 23 .

The low voltage malfunction suppression circuit 37 is connected to the voltage control circuit 23 . The low-voltage malfunction suppression circuit 37 suppresses malfunction of the power MISFET 9 when the power supply voltage is less than a predetermined value. A signal generated by the low-voltage malfunction suppression circuit 37 is input to the voltage control circuit 23 .

The gate control circuit 25 is connected to the voltage control circuit 23 , the protection circuit 24 , the gate of the power MISFET 9 and the gate of the sensor MISFET 21 . The gate control circuit 25 controls on/off of the power MISFET 9 and on/off of the sensor MISFET 21 .

Gate control circuit 25 generates a plurality of types of gate control signals according to the electrical signal from voltage control circuit 23 and the electrical signal from protection circuit 24 . A plurality of types of gate control signals are input to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 through the gate control wiring 17, respectively. Gate control circuit 25 more specifically includes an oscillation circuit 38 , a charge pump circuit 39 and a drive signal output circuit 40 .

The oscillator circuit 38 oscillates according to the electrical signal from the voltage control circuit 23 and generates a predetermined electrical signal. An electrical signal generated by the oscillator circuit 38 is input to the charge pump circuit 39 . The charge pump circuit 39 boosts the electric signal from the oscillation circuit 38 . The electric signal boosted by the charge pump circuit 39 is input to the drive signal output circuit 40 .

The drive signal output circuit 40 generates a plurality of types of gate control signals according to the electrical signal from the charge pump circuit 39 and the electrical signal from the protection circuit 24 (more specifically, the overcurrent protection circuit 34). A plurality of types of gate control signals are inputted to the gate of the power MISFET 9 and the gate of the sensor MISFET 21 via the gate control wiring 17 . The sensor MISFET 21 and the power MISFET 9 are simultaneously driven and controlled by the drive signal output circuit 40 .

Active clamp circuit 26 protects power MISFET 9 from back electromotive force. The active clamp circuit 26 is connected to the power electrode 11 , the gate of the power MISFET 9 and the gate of the sensor MISFET 21 . Active clamp circuit 26 may include two diodes that are reverse biased together. The two diodes may include a Zener diode and a pn junction diode.

The current detection circuit 27 is connected to the protection circuit 24 , the abnormality detection circuit 29 , the source of the power MISFET 9 and the source of the sensor MISFET 21 . Current detection circuit 27 generates a current detection signal according to the electrical signal generated by power MISFET 9 and the electrical signal generated by sensor MISFET 21 . The current detection signal is input to the abnormality detection circuit 29 .

A reverse power connection protection circuit 28 is connected to the reference potential electrode 14 and the voltage control circuit 23 . The power supply reverse connection protection circuit 28 protects the voltage control circuit 23, the power MISFET 9, etc. from a reverse voltage when the power supply is reversely connected.

Abnormality detection circuit 29 is connected to voltage control circuit 23 , protection circuit 24 and current detection circuit 27 . The abnormality detection circuit 29 monitors the voltage of the protection circuit 24 . In the protection circuit 24, if any of the overcurrent protection circuit 34, load open detection circuit 35, overheat protection circuit 36, and low voltage malfunction suppression circuit 37 malfunctions (such as voltage fluctuation), the voltage of the protection circuit 24 Generates an abnormality detection signal corresponding to the output and outputs it to the outside.

Abnormality detection circuit 29 more specifically includes a first multiplexer circuit 41 and a second multiplexer circuit 42 . The first multiplexer circuit 41 includes two inputs, one output and one selection control input. The input portion of the first multiplexer circuit 41 is connected to the protection circuit 24 and the current detection circuit 27, respectively. A second multiplexer circuit 42 is connected to the output of the first multiplexer circuit 41 . A voltage control circuit 23 is connected to the selection control input section of the first multiplexer circuit 41 .

The first multiplexer circuit 41 generates an abnormality detection signal according to the electric signal from the voltage control circuit 23, the voltage detection signal from the protection circuit 24, and the current detection signal from the current detection circuit 27. FIG. The abnormality detection signal generated by the first multiplexer circuit 41 is input to the second multiplexer circuit 42 .

The second multiplexer circuit 42 includes two inputs and one output. The input section of the second multiplexer circuit 42 is connected to the output section of the second multiplexer circuit 42 and the ENABLE electrode 15, respectively. The SENSE electrode 16 is connected to the output of the second multiplexer circuit 42 .

When an MCU is connected to the ENABLE electrode 15 and a resistor is connected to the SENSE electrode 16 , an ON signal is input from the MCU to the ENABLE electrode 15 and an abnormality detection signal is taken out from the SENSE electrode 16 . The abnormality detection signal is converted into an electrical signal by a resistor connected to the SENSE electrode 16 . An abnormal state of the semiconductor device 1 is detected based on this electrical signal.

FIG. 3 is a cross-sectional perspective view of the region III shown in FIG. 1, and is a cross-sectional perspective view showing a form including the high-concentration drift region 91 according to the first form example. FIG. 4 is a cross-sectional perspective view of FIG. 3 with reference potential electrode 14 and gate control wiring 17 removed. FIG. 5 is a cross-sectional perspective view with the interlayer insulating layer 122 removed from FIG.

6 is a plan view of FIG. 5. FIG. FIG. 7 is an enlarged cross-sectional view of the area containing the two trench gate structures 61 shown in FIG. FIG. 8 is an enlarged cross-sectional view of one trench gate structure 61 shown in FIG.

3 to 8, semiconductor layer 2 in this embodiment has a laminated structure including an n ⁺ -type semiconductor substrate 51 and an n-type epitaxial layer 52 . A second main surface 4 of the semiconductor layer 2 is formed by the semiconductor substrate 51 . The epitaxial layer 52 forms the first main surface 3 of the semiconductor layer 2 . Semiconductor substrate 51 and epitaxial layer 52 form side surfaces 5A to 5D of semiconductor layer 2 .

The epitaxial layer 52 has an n-type impurity concentration lower than that of the semiconductor substrate 51 . The n-type impurity concentration of the semiconductor substrate 51 may be 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ^{−3 or} less. The n-type impurity concentration of the epitaxial layer 52 may be 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less.

The epitaxial layer 52 has a thickness Tepi less than the thickness Tsub of the semiconductor substrate 51 (Tepi<Tsub). The thickness Tsub of the semiconductor substrate 51 may be 50 μm or more and 450 μm or less. The thickness Tsub may be 50 μm to 150 μm, 150 μm to 250 μm, 250 μm to 350 μm, or 350 μm to 450 μm.

By reducing the thickness Tsub of the semiconductor substrate 51, the resistance value can be reduced. The thickness Tsub of the semiconductor substrate 51 can be adjusted by grinding. In this case, the second main surface 4 of the semiconductor layer 2 may be a ground surface having grinding marks.

The thickness Tepi of the epitaxial layer 52 may be 5 μm or more and 20 μm or less. The thickness Tepi of the epitaxial layer 52 may be 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less. The thickness Tepi is preferably 5 μm or more and 15 μm or less.

The semiconductor substrate 51 is formed as a drain region 53 on the second main surface 4 side of the semiconductor layer 2 . The epitaxial layer 52 is formed as a drift region 54 (drain drift region) in the surface layer portion of the first main surface 3 of the semiconductor layer 2 . The bottom of drift region 54 is formed by the boundary of semiconductor substrate 51 and epitaxial layer 52 . The epitaxial layer 52 is hereinafter referred to as a drift region 54 .

A p-type body region 55 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 in the output region 6 . The body region 55 may have a p-type impurity concentration of 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ^{−3 or} less.

Body region 55 is formed in the surface layer of drift region 54 . The bottom of body region 55 is formed in a region on the first main surface 3 side with respect to the bottom of drift region 54 . The thickness of the body region 55 may be 0.5 μm or more and 2 μm or less. The thickness of the body region 55 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

A plurality of trench gate structures 61 are formed on the first main surface 3 of the semiconductor layer 2 in the output region 6 . The plurality of trench gate structures 61 each extend in a strip shape along the first direction X in plan view and are spaced apart along the second direction Y. As shown in FIG.

A plurality of trench gate structures 61 are formed in a striped shape as a whole in a plan view. The multiple trench gate structures 61 each have a first end on one side and a second end on the other side in the first direction X. As shown in FIG.

3 to 6 show the region on the one end side of each trench gate structure 61 and omit the illustration of the region on the other end side. The structure of the region on the other end side of each trench gate structure 61 is substantially the same as the structure of the region on the one end side of each trench gate structure 61 .

The width WT of each trench gate structure 61 may be between 0.5 μm and 2 μm. The width WT is the width in the direction (second direction Y) orthogonal to the direction (first direction X) in which each trench gate structure 61 extends. Width WT may be between 0.5 μm and 1 μm, between 1 μm and 1.5 μm, or between 1.5 μm and 2 μm. The width WT is preferably 0.8 μm or more and 1.2 μm or less.

A plurality of trench gate structures 61 pass through body region 55 and reach drift region 54 . The depth DT of each trench gate structure 61 may be 1 μm or more and 10 μm or less. The depth DT may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The depth DT is preferably 2 μm or more and 6 μm or less.

Each trench gate structure 61 includes a first sidewall 62 on one side, a second sidewall 63 on the other side, and a bottom wall 64 connecting the first sidewall 62 and the second sidewall 63 . Below, the 1st side wall 62, the 2nd side wall 63, and the bottom wall 64 may be collectively called an "inner wall" or an "outer wall."

A first sidewall 62 , a second sidewall 63 and a bottom wall 64 of each trench gate structure 61 are located within the drift region 54 . A first sidewall 62 and a second sidewall 63 of each trench gate structure 61 extend along the normal direction Z. As shown in FIG. A first sidewall 62 and a second sidewall 63 of each trench gate structure 61 may be formed perpendicular to the first major surface 3 .

The absolute value of the angle (taper angle) formed between first side wall 62 and first main surface 3 in semiconductor layer 2 may be more than 90° and 95° or less (for example, about 91°). The absolute value of the angle (taper angle) formed between second side wall 63 and first main surface 3 in semiconductor layer 2 may be more than 90° and 95° or less (for example, about 91°). Each trench gate structure 61 may be formed in a tapered shape (tapered shape) in which the width WT narrows from the first main surface 3 side toward the bottom wall 64 side in a cross-sectional view.

A bottom wall 64 of each trench gate structure 61 is located in a region on the first main surface 3 side with respect to the bottom of the drift region 54 . A bottom wall 64 of each trench gate structure 61 is formed in a convex curved shape (U-shape) toward the bottom of the drift region 54 .

A bottom wall 64 of each trench gate structure 61 is located in a region on the first main surface 3 side with an interval IT of 1 μm or more and 10 μm or less from the bottom of the drift region 54 . The interval IT may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The interval IT is preferably 1 μm or more and 5 μm or less.

The plurality of trench gate structures 61 includes first trench gate structures 61A and second trench gate structures 61B alternately arranged along the second direction Y. As shown in FIG. A first depletion layer extends into the drift region 54 from the outer wall of the first trench gate structure 61A. A second depletion layer extends into the drift region 54 from the outer wall of the second trench gate structure 61B.

A plurality of trench gate structures 61 are arranged such that the first depletion layer overlaps the second depletion layer. More specifically, the first depletion layer is located on the first main surface 3 side with respect to the bottom wall 64 of each trench gate structure 61 in the region between the first trench gate structure 61A and the second trench gate structure 61B. It overlaps the second depletion layer in the region.

The first depletion layer is the second depletion layer in the region between the first trench gate structure 61A and the second trench gate structure 61B, in the region on the bottom side of the drift region 54 with respect to the bottom wall 64 of each trench gate structure 61. preferably overlap. According to such a structure, concentration of an electric field on the bottom wall 64 of each trench gate structure 61 can be suppressed, so reduction in breakdown voltage can be suppressed.

A pitch PS between sidewalls of trench gate structures 61 adjacent to each other may be 0.2 μm or more and 2 μm or less. The pitch PS is 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, 0.8 μm or more and 1.0 μm or less, 1.0 μm or more and 1.2 μm or less, 1 .2 μm or more and 1.4 μm or less, 1.4 μm or more and 1.6 μm or less, 1.6 μm or more and 1.8 μm or less, or 1.8 μm or more and 2.0 μm or less. The pitch PS is preferably 0.3 μm or more and 1.5 μm or less.

The pitch PS is orthogonal to the extending direction (first direction X) of each trench gate structure 61 between the first sidewall 62 of the trench gate structure 61 on one side and the second sidewall 63 of the trench gate structure 61 on the other side. It is the distance in the direction (second direction Y).

A pitch PC between central portions of trench gate structures 61 adjacent to each other may be 1 μm or more and 3 μm or less. The pitch PC may be 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The pitch PC is preferably 1.2 μm or more and 1.8 μm or less.

Pitch PC is a direction (second is the distance in the direction Y).

Since the channel area per unit area can be increased by narrowing the pitch PC, the channel resistance can be reduced. Also, it is possible to improve the breakdown voltage. However, in this case, there is a trade-off that the on-resistance of the drift region 54 increases due to the reduction of the current path in the drift region 54 . Countermeasures against this contradiction will be described later.

6-8, each trench gate structure 61 includes a gate trench 65, an insulating layer 66 and a buried electrode 67 (electrode). The gate trench 65 is formed by digging the first main surface 3 of the semiconductor layer 2 toward the second main surface 4 side.

Gate trench 65 defines first sidewall 62 , second sidewall 63 and bottom wall 64 of trench gate structure 61 . The first sidewall 62 , the second sidewall 63 and the bottom wall 64 of the trench gate structure 61 are hereinafter also referred to as the first sidewall 62 , the second sidewall 63 and the bottom wall 64 of the gate trench 65 .

The insulating layer 66 is formed like a film along the inner wall of the gate trench 65 . The insulating layer 66 defines a recessed space within the gate trench 65 . A portion of the insulating layer 66 covering the bottom wall 64 of the gate trench 65 is formed along the bottom wall 64 of the gate trench 65 . As a result, the insulating layer 66 defines a U-shaped recessed space in the gate trench 65 .

The insulating layer 66 contains at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). .

The insulating layer 66 may have a laminated structure including a SiN layer and a SiO ₂ layer laminated in this order from the semiconductor layer 2 side. The insulating layer 66 may have a laminated structure including a SiO ₂ layer and a SiN layer laminated in this order from the semiconductor layer 2 side. The insulating layer 66 may have a single layer structure consisting of a _SiO2 layer or a SiN layer. The insulating layer 66 has a single layer structure consisting of a SiO ₂ layer in this embodiment.

Referring to FIG. 8, insulating layer 66 includes bottom-side insulating layer 68 and opening-side insulating layer 69 formed in this order from bottom wall 64 side of gate trench 65 toward first main surface 3 side of semiconductor layer 2 . including.

The bottom insulating layer 68 covers the inner wall of the gate trench 65 on the bottom wall 64 side. More specifically, the bottom-side insulating layer 68 covers the inner wall of the gate trench 65 on the bottom wall 64 side with respect to the bottom of the body region 55 . The bottom insulating layer 68 defines a U-shaped space on the bottom wall 64 side of the gate trench 65 . The bottom insulating layer 68 has a smooth inner wall surface defining a U-shaped space. The bottom-side insulating layer 68 is in contact with the drift region 54 (more specifically, the high-concentration drift region 91 described later). A portion of the bottom insulating layer 68 may contact the body region 55 .

The opening-side insulating layer 69 covers the inner wall of the gate trench 65 on the opening side. More specifically, opening-side insulating layer 69 covers first sidewall 62 and second sidewall 63 of gate trench 65 in a region on the opening side of gate trench 65 with respect to the bottom of body region 55 . The opening side insulating layer 69 is in contact with the body region 55 . A portion of the opening-side insulating layer 69 may be in contact with the drift region 54 .

Bottom insulating layer 68 has a first thickness T1. The opening-side insulating layer 69 has a second thickness T2 (T2<T1) less than the first thickness T1. The first thickness T1 is the thickness along the normal direction of the inner wall of the gate trench 65 in the bottom insulating layer 68 . The second thickness T2 is the thickness along the normal direction of the inner wall of the gate trench 65 in the opening side insulating layer 69 .

A ratio T1/WT of the first thickness T1 to the width WT of the gate trench 65 may be 0.1 or more and 0.4 or less. The ratio T1/WT is 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, 0.25 or more and 0.3 or less, 0.3 or more and 0.35 or less. , or 0.35 or more and 0.4 or less. The ratio T1/WT is preferably 0.25 or more and 0.35 or less.

The first thickness T1 of the bottom insulating layer 68 may be between 1500 Å and 4000 Å. The first thickness T1 may be 1500 Å to 2000 Å, 2000 Å to 2500 Å, 2500 Å to 3000 Å, 3000 Å to 3500 Å, or 3500 Å to 4000 Å. The first thickness T1 is preferably 1800 Å or more and 3500 Å or less.

The second thickness T2 of the opening-side insulating layer 69 may be 1/100 or more and 1/10 or less of the first thickness T1 of the bottom-side insulating layer 68 . The second thickness T2 may range from 100 Å to 500 Å. The second thickness T2 may be 100 Å to 200 Å, 200 Å to 300 Å, 300 Å to 400 Å, or 400 Å to 500 Å. The second thickness T2 is preferably 200 Å or more and 400 Å or less.

The bottom insulating layer 68 is formed such that the first thickness T1 decreases from the portion covering the first sidewall 62 and the second sidewall 63 of the gate trench 65 toward the portion covering the bottom wall 64 of the gate trench 65 . It is

The thickness of the portion of the bottom insulating layer 68 covering the bottom wall 64 of the gate trench 65 is smaller than the thickness of the portion of the bottom insulating layer 68 covering the first sidewall 62 and the second sidewall 63 of the gate trench 65 . . The width of the opening on the bottom wall side of the U-shaped space defined by the bottom insulating layer 68 is expanded by the reduction of the first thickness T1. This suppresses the tapering of the U-shaped space.

Bottom insulating layer 68 more specifically includes sidewall covering 70 and bottom wall covering 71 . The sidewall covering portion 70 covers the first sidewall 62 and the second sidewall 63 of the gate trench 65 to form the sidewall of the U-shaped space. The bottom wall covering portion 71 covers the bottom wall 64 of the gate trench 65 and forms the bottom wall of the U-shaped space.

The bottom wall covering portion 71 has a thickness TB different from the thickness TS of the side wall covering portion 70 within the range of the first thickness T1. More specifically, the thickness TB of the bottom wall covering portion 71 is less than the thickness TS of the side wall covering portion 70 (TB<TS).

A ratio TB/TS of thickness TB of bottom wall covering portion 71 to thickness TS of side wall covering portion 70 may be 0.5 or more and 0.8 or less. The ratio TB/TS is 0.5 or more and 0.55 or less, 0.55 or more and 0.6 or less, 0.6 or more and 0.65 or less, 0.65 or more and 0.7 or less, 0.7 or more and 0.75 or less. , or 0.75 or more and 0.8 or less. The ratio TB/TS is preferably 0.65 or more and 0.75 or less.

The bottom wall covering portion 71 includes a corner portion 71A and a deepest portion 71B. The corner portion 71</b>A defines a boundary portion with the side wall covering portion 70 . The deepest part 71B defines the bottom of the U-shaped space. The deepest portion 71B may have a thickness TD (TD≠TC) different from the thickness TC of the corner portion 71A. The thickness TD of the deepest portion 71B may exceed the thickness TC of the corner portion 71A (TD>TC).

A difference TD-TC between the thickness TD and the thickness TC may be 10 Å or more and 200 Å or less. The difference TD-TC may be 10 Å to 50 Å, 50 Å to 100 Å, 100 Å to 150 Å, or 150 Å to 200 Å. The difference TD-TC is preferably 10 Å or more and 80 Å or less.

The U-shaped space defined by the bottom insulating layer 68 is formed by removing the surface portion of the bottom insulating layer 68 by an etching method during the manufacturing process. The etching method may be a wet etching method.

The inner wall surface of the bottom insulating layer 68 is an etched surface formed by an etching method. The first thickness T1 of the bottom insulating layer 68 decreases toward the bottom wall 64 of the gate trench 65 because the bottom wall covering portion 71 is removed more than the side wall covering portion 70 is removed. .

The embedded electrode 67 is embedded in the gate trench 65 with the insulating layer 66 interposed therebetween. A predetermined gate control signal including a gate voltage is applied to the embedded electrode 67 . The embedded electrode 67 has an insulation isolation type electrode structure including a bottom side electrode 72 , an opening side electrode 73 and an intermediate insulating layer 74 in this embodiment.

The bottom electrode 72 is buried on the bottom wall 64 side of the gate trench 65 with the insulating layer 66 interposed therebetween. More specifically, the bottom electrode 72 is buried on the bottom wall 64 side of the gate trench 65 with the bottom insulating layer 68 interposed therebetween. The bottom-side electrode 72 faces the drift region 54 (more specifically, the high-concentration drift region 91 described later) with the bottom-side insulating layer 68 interposed therebetween. A portion of the bottom electrode 72 may face the body region 55 with the bottom insulating layer 68 interposed therebetween.

The bottom electrode 72 includes a first end 72A, a second end 72B and a wall 72C. The first end portion 72A is located on the opening side of the gate trench 65 . The second end portion 72B is positioned on the bottom wall 64 side of the gate trench 65 . The wall portion 72C connects the first end portion 72A and the second end portion 72B and extends like a wall along the inner wall of the gate trench 65 .

The first end 72A is exposed from the bottom insulating layer 68 . The first end portion 72A protrudes toward the first main surface 3 of the semiconductor layer 2 with respect to the bottom insulating layer 68 . As a result, the bottom electrode 72 defines a recess having an inverted concave shape in a cross-sectional view between the bottom side insulating layer 68 and the opening side insulating layer 69 on the opening side of the gate trench 65 . The width of the first end portion 72A is less than the width of the wall portion 72C.

The second end portion 72</b>B is formed in a convex curve toward the bottom wall 64 of the gate trench 65 . More specifically, the second end portion 72B is formed along the bottom wall (etching surface) of the U-shaped space partitioned by the bottom insulating layer 68 (bottom wall covering portion 71). It is formed in a smooth convex curve toward the bottom wall 64 of the.

With such a structure, local electric field concentration on the bottom electrode 72 can be suppressed, so that a decrease in breakdown voltage can be suppressed. In particular, by embedding the bottom electrode 72 in the U-shaped space of the bottom insulating layer 68 that has been expanded by etching, the bottom electrode 72 tapers from the first end 72A to the second end 72B. can be appropriately suppressed. Thereby, local electric field concentration on the second end portion 72B of the bottom electrode 72 can be appropriately suppressed.

Such a structure is particularly effective when the film-like insulating layer 66 is formed on the inner wall of the tapered gate trench 65 extending from the first main surface 3 to the second main surface 4 . The tapered gate trench 65 has a convexly curved bottom wall 64 directed toward the second main surface 4 , or has an opening width extending from the first main surface 3 toward the second main surface 4 in cross-sectional view. It includes a narrowing tapered gate trench 65 or a gate trench 65 with both features.

That is, when the film-like insulating layer 66 is formed on the inner wall of the gate trench 65 having the convex curved bottom wall 64 toward the second main surface 4 as one form of the tapered shape, the inner wall of the gate trench 65 has a gate. A tapered recessed (U-shaped) space whose opening width narrows toward the bottom wall 64 of the trench 65 is defined.

In this case, the embedded electrode 67 (bottom side electrode 72) embedded in the concave space is also tapered along the inner wall of the concave space. When the tapered embedded electrode 67 (bottom side electrode 72 ) is formed, the electric field is locally concentrated on the bottom wall 64 of the gate trench 65 . As a result, the breakdown voltage is lowered due to electric field concentration.

Therefore, when the gate trench 65 having the convexly curved bottom wall 64 directed toward the second main surface 4 is formed, the thickness TB of the bottom wall covering portion 71 of the insulating layer 66 (bottom side insulating layer 68) is covered by the side wall. By setting the thickness of the portion 70 to be less than TS (TB<TS), it is possible to appropriately prevent the recessed space defined by the insulating layer 66 from becoming tapered. As a result, electric field concentration on the bottom wall 64 of the gate trench 65 can be suppressed, so that a decrease in breakdown voltage can be suppressed.

In addition, when the film-like insulating layer 66 is formed on the inner wall of the tapered gate trench 65 as one form of the tapered shape, the gate trench 65 has a tapered shape in which the opening width narrows toward the bottom wall 64 of the gate trench 65 . A concave space in the shape is defined.

In this case, the embedded electrode 67 (bottom side electrode 72) embedded in the concave space is also tapered along the inner wall of the concave space. When the tapered embedded electrode 67 (bottom side electrode 72 ) is formed, the electric field is locally concentrated on the bottom wall 64 of the gate trench 65 . As a result, the breakdown voltage is lowered due to electric field concentration.

Therefore, when the tapered gate trench 65 is formed, the thickness TB of the bottom wall covering portion 71 of the insulating layer 66 (bottom side insulating layer 68) is set to be less than the thickness TS of the side wall covering portion 70 (TB<TS). By doing so, it is possible to appropriately prevent the recessed space defined by the insulating layer 66 from becoming tapered. As a result, electric field concentration on the bottom wall 64 of the gate trench 65 can be suppressed, so that a decrease in breakdown voltage can be suppressed.

Bottom electrode 72 may comprise at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, or a copper alloy. Bottom electrode 72 comprises conductive polysilicon in this form. The conductive polysilicon may contain n-type impurities or p-type impurities. The conductive polysilicon preferably contains n-type impurities.

The opening side electrode 73 is embedded in the opening side of the gate trench 65 with the insulating layer 66 interposed therebetween. More specifically, the opening-side electrode 73 is embedded in an inverted recess defined on the opening side of the gate trench 65 with the opening-side insulating layer 69 interposed therebetween. The opening-side electrode 73 faces the body region 55 with the opening-side insulating layer 69 interposed therebetween. A part of the opening-side electrode 73 may face the drift region 54 (more specifically, the high-concentration drift region 91 described later) with the opening-side insulating layer 69 interposed therebetween.

The opening-side electrode 73 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, or a copper alloy. The opening-side electrode 73 contains conductive polysilicon in this form. The conductive polysilicon may contain n-type impurities or p-type impurities. The conductive polysilicon preferably contains n-type impurities.

The exposed portion of the opening-side electrode 73 exposed from the gate trench 65 is covered with a film-shaped cap insulating layer 75 . The cap insulating layer 75 continues to the opening side insulating layer 69 in the gate trench 65 . The cap insulating layer 75 may contain silicon oxide (SiO ₂ ).

The intermediate insulating layer 74 is interposed between the bottom-side electrode 72 and the opening-side electrode 73 to electrically insulate the bottom-side electrode 72 and the opening-side electrode 73 . More specifically, the intermediate insulating layer 74 covers the outer surface (more specifically, the protrusion) of the bottom-side electrode 72 exposed from the bottom-side insulating layer 68 in the region between the bottom-side electrode 72 and the opening-side electrode 73 . covered. An intermediate insulating layer 74 covers the first end 72A of the bottom electrode 72 . The intermediate insulating layer 74 is continuous with the insulating layer 66 (bottom side insulating layer 68).

Intermediate insulating layer 74 has a third thickness T3. The third thickness T3 is less than the first thickness T1 of the bottom electrode 72 (T3<T1). The third thickness T3 may be 1/100 or more and 1/10 or less of the first thickness T1. The third thickness T3 may range from 100 Å to 500 Å. The third thickness T3 may be 100 Å to 200 Å, 200 Å to 300 Å, 300 Å to 400 Å, or 400 Å to 500 Å. The third thickness T3 is preferably 200 Å or more and 400 Å or less.

The intermediate insulating layer 74 contains at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). include. The intermediate insulating layer 74 has a single layer structure consisting of a SiO ₂ layer in this embodiment.

When driving the power MISFET 9 (that is, during gate ON control), a gate voltage may be applied to the bottom electrode 72 and a gate voltage may be applied to the opening electrode 73 . In this case, the bottom-side electrode 72 and the opening-side electrode 73 function as gate electrodes. As a result, the voltage drop between the bottom electrode 72 and the aperture electrode 73 can be suppressed, so that the electric field concentration between the bottom electrode 72 and the aperture electrode 73 can be suppressed. Moreover, since the on-resistance of the semiconductor layer 2 can be lowered, power consumption can be reduced.

When driving the power MISFET 9 (that is, during gate ON control), a reference potential may be applied to the bottom electrode 72 and a gate voltage may be applied to the opening electrode 73 . In this case, the bottom electrode 72 functions as a field electrode, while the aperture electrode 73 functions as a gate electrode. As a result, the parasitic capacitance can be reduced, so that the switching speed can be improved.

3 to 6, a plurality of (two in this embodiment) trench contact structures 81 are formed on the first main surface 3 of the semiconductor layer 2. As shown in FIG. The plurality of trench contact structures 81 includes one trench contact structure 81 located on one end side of each trench gate structure 61 and the other trench contact structure 81 located on the other end side of each trench gate structure 61 (not shown). abbreviated).

The trench contact structure 81 on one side extends like a strip along the second direction Y and is connected to one ends of the plurality of trench gate structures 61 . The trench contact structure 81 on the other side, like the trench contact structure 81 on the one side, extends in a strip shape along the second direction Y and is connected to the other ends of the plurality of trench gate structures 61 .

The trench contact structure 81 on the other side has substantially the same structure as the trench contact structure 81 on the one side. A detailed description of the trench contact structure 81 on the other side is omitted.

The width WTC of each trench contact structure 81 may be 0.5 μm or more and 3 μm or less. The width WTC is the width in the direction (first direction X) orthogonal to the direction (second direction Y) in which each trench contact structure 81 extends. The width WTC may be 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, or 2.5 μm to 3.0 μm. The width WTC is preferably 0.8 μm or more and 2 μm or less. The width WTC of each trench contact structure 81 is preferably equal to the width WT of each trench gate structure 61 (WTC=WT).

Each trench contact structure 81 penetrates body region 55 and reaches drift region 54 . The depth DTC of each trench contact structure 81 may be 1 μm or more and 10 μm or less. The depth DTC may be 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm. The depth DTC is preferably 2 μm or more and 6 μm or less. The depth DTC of each trench contact structure 81 is preferably equal to the depth DT of each trench gate structure 61 (DTC=DT).

Each trench contact structure 81 includes a first sidewall 82 on one side, a second sidewall 83 on the other side, and a bottom wall 84 connecting the first sidewall 82 and the second sidewall 83 . A first sidewall 82 of each trench contact structure 81 is a connection surface connected to the trench gate structure 61 . Below, the 1st side wall 82, the 2nd side wall 83, and the bottom wall 84 may be collectively called an "inner wall" or an "outer wall."

A first sidewall 82 , a second sidewall 83 and a bottom wall 84 of each trench contact structure 81 are located within the drift region 54 . A first sidewall 82 and a second sidewall 83 of each trench contact structure 81 extend along the normal direction Z. As shown in FIG. A first sidewall 82 and a second sidewall 83 of each trench contact structure 81 may be formed perpendicular to the first main surface 3 .

The absolute value of the angle (taper angle) formed between first side wall 82 and first main surface 3 in semiconductor layer 2 may be more than 90° and 95° or less (for example, about 91°). The absolute value of the angle (taper angle) formed between second side wall 83 and first main surface 3 in semiconductor layer 2 may be more than 90° and 95° or less (for example, about 91°). Each trench contact structure 81 may be formed in a tapered shape (tapered shape) in which the width WTC narrows from the first main surface 3 side of the semiconductor layer 2 toward the bottom wall 84 side in a cross-sectional view.

A bottom wall 84 of each trench contact structure 81 is located in a region on the first main surface 3 side with respect to the bottom of the drift region 54 . A bottom wall 84 of each trench contact structure 81 is formed in a convex curve toward the bottom of the drift region 54 .

A bottom wall 84 of each trench contact structure 81 is located in a region on the first main surface 3 side with an interval ITC of 1 μm or more and 10 μm or less from the bottom of the drift region 54 . The interval ITC may be 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm. The interval ITC is preferably 1 μm or more and 5 μm or less. The spacing ITC is preferably equal to the spacing IT of the trench gate structure 61 (ITC=IT).

Each trench contact structure 81 includes contact trenches 85 , contact insulating layers 86 and contact electrodes 87 . The contact trench 85 is formed by digging the first main surface 3 of the semiconductor layer 2 toward the second main surface 4 side.

Contact trench 85 defines first sidewall 82 , second sidewall 83 and bottom wall 84 of trench contact structure 81 . The first sidewall 82 , the second sidewall 83 and the bottom wall 84 of the trench contact structure 81 are hereinafter also referred to as the first sidewall 82 , the second sidewall 83 and the bottom wall 84 of the contact trench 85 .

First sidewall 82 of contact trench 85 communicates with first sidewall 62 and second sidewall 63 of gate trench 65 . Contact trench 85 forms one trench with gate trench 65 .

The contact insulating layer 86 is formed like a film along the inner wall of the contact trench 85 . The contact insulating layer 86 defines a recessed space within the contact trench 85 . A portion of the contact insulating layer 86 covering the bottom wall 84 of the contact trench 85 is formed along the bottom wall 84 of the contact trench 85 .

The contact insulating layer 86 defines a recessed U-shaped space in the contact trench 85 in the same manner as the bottom insulating layer 68 of the trench gate structure 61 . In other words, although a detailed description is omitted, the portion of the contact insulating layer 86 covering the bottom wall 84 of the contact trench 85 is similar to the bottom side insulating layer 68 of the trench gate structure 61 , the sidewall covering portion 70 and the bottom. It has a wall covering portion 71 (a corner portion 71A and a deepest portion 71B).

The contact insulating layer 86 has a fourth thickness T4. The fourth thickness T4 may range from 1500 Å to 4000 Å. The fourth thickness T4 may be 1500 Å to 2000 Å, 2000 Å to 2500 Å, 2500 Å to 3000 Å, 3000 Å to 3500 Å, or 3500 Å to 4000 Å. The fourth thickness T4 is preferably 1800 Å or more and 3500 Å or less. The fourth thickness T4 is preferably equal to the first thickness T1 of the bottom insulating layer 68 (T4=T1).

The contact insulating layer 86 contains at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). include.

The contact insulating layer 86 may have a laminated structure including a SiN layer and a SiO ₂ layer laminated in this order from the semiconductor layer 2 side. The contact insulating layer 86 may have a laminated structure including a SiO ₂ layer and a SiN layer laminated in this order from the semiconductor layer 2 side. The contact insulating layer 86 may have a single layer structure consisting of a _SiO2 layer or a SiN layer. In this embodiment, the contact insulating layer 86 has a single layer structure consisting of a SiO ₂ layer. Contact insulating layer 86 is preferably made of the same insulating material as insulating layer 66 .

Contact insulating layer 86 is integrated with insulating layer 66 at the communicating portion between gate trench 65 and contact trench 85 . The contact insulating layer 86 formed on the inner wall of the contact trench 85 on one side has an insulating lead-out portion 86A led out to one end portion side of the gate trench 65 in this embodiment. The insulating lead-out portion 86A crosses the communicating portion between the gate trench 65 and the contact trench 85 and covers the inner wall of the gate trench 65 on the one end side.

The insulating lead-out portion 86A is integrated with the bottom-side insulating layer 68 and the opening-side insulating layer 69 in the gate trench 65 . The insulating lead-out portion 86A defines a U-shaped space along with the bottom-side insulating layer 68 on the inner wall of the gate trench 65 on one end side.

Although not shown, the contact insulating layer 86 formed on the inner wall of the contact trench 85 on the other side has an insulating extension portion 86A drawn out to the inner wall of the gate trench 65 in this embodiment. The insulating lead-out portion 86A crosses the communicating portion between the gate trench 65 and the contact trench 85 and covers the inner wall of the gate trench 65 on the other end side.

The insulating lead-out portion 86A is integrated with the bottom-side insulating layer 68 and the opening-side insulating layer 69 in the gate trench 65 . The insulating lead-out portion 86A defines a U-shaped space along with the bottom-side insulating layer 68 on the inner wall of the gate trench 65 on the other end side.

The contact electrode 87 is embedded in the contact trench 85 with the contact insulating layer 86 interposed therebetween. Unlike the embedded electrode 67, the contact electrode 87 is embedded in the contact trench 85 as an integrated body. The contact electrode 87 has one end exposed from the contact trench 85 and the other end in contact with the contact insulating layer 86 .

The other end of the contact electrode 87 is formed in a convex curve toward the bottom wall 84 of the contact trench 85 in the same manner as the bottom electrode 72 of the trench gate structure 61 . More specifically, the other end of the contact electrode 87 is formed along the bottom wall (etching surface) of the U-shaped space partitioned by the contact insulating layer 86 and faces the bottom wall 84 of the contact trench 85. It is formed in a smooth convex curve.

With such a structure, the same effects as those described for the trench gate structure 61 can be obtained. That is, since local electric field concentration on the contact electrode 87 can be suppressed, a decrease in breakdown voltage can be suppressed.

The contact electrode 87 is electrically connected to the bottom electrode 72 of the embedded electrode 67 at the junction between the gate trench 65 and the contact trench 85 . More specifically, the contact electrode 87 formed in the contact trench 85 on one side has an electrode lead-out portion 87A led out to one end portion side of the gate trench 65 . Electrode lead-out portion 87A is located in gate trench 65 across the communicating portion between gate trench 65 and contact trench 85 .

The electrode lead-out portion 87A is embedded in a U-shaped space partitioned by the contact insulating layer 86 within the gate trench 65 . The electrode lead-out portion 87A is integrated with the bottom electrode 72 inside the gate trench 65 . Thereby, the contact electrode 87 is electrically connected to the bottom electrode 72 . The contact electrode 87 is also a lead-out portion of the bottom-side electrode 72 lead out into the contact trench 85 from the gate trench 65 .

An intermediate insulating layer 74 is interposed between the electrode lead-out portion 87A and the opening side electrode 73 in the gate trench 65 . Thereby, the contact electrode 87 is electrically insulated from the opening side electrode 73 in the gate trench 65 .

Although not shown, the contact electrode 87 formed in the contact trench 85 on the other side has, more specifically, an electrode lead-out portion 87A led out to the other end side of the gate trench 65. . Electrode lead-out portion 87A is located in gate trench 65 across the communicating portion between gate trench 65 and contact trench 85 .

The electrode lead-out portion 87A is embedded in a U-shaped space partitioned by the contact insulating layer 86 within the gate trench 65 . The electrode lead-out portion 87A is integrated with the bottom electrode 72 inside the gate trench 65 . Thereby, the contact electrode 87 is electrically connected to the bottom electrode 72 . The contact electrode 87 is also a lead-out portion of the bottom-side electrode 72 lead out into the contact trench 85 from the gate trench 65 .

Contact electrode 87 may contain at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, or a copper alloy. Contact electrode 87 includes conductive polysilicon in this form. The conductive polysilicon may contain n-type impurities or p-type impurities. The conductive polysilicon preferably contains n-type impurities. Contact electrode 87 preferably comprises the same conductive material as bottom electrode 72 .

An exposed portion of the contact electrode 87 exposed from the contact trench 85 is covered with a film-shaped cap insulating layer 88 . The cap insulating layer 88 continues to the contact insulating layer 86 within the contact trench 85 . The cap insulating layer 88 may contain silicon oxide (SiO ₂ ).

3 to 8, n ⁺ -type high-concentration drift region 91 is formed in drift region 54 along the outer wall of trench gate structure 61 . In this form, a plurality of high-concentration drift regions 91 are formed in a one-to-one correspondence relationship with the outer walls of the plurality of trench gate structures 61 .

The high-concentration drift region 91 has an n-type impurity concentration exceeding the n-type impurity concentration of the drift region 54 . The n-type impurity concentration of high-concentration drift region 91 is preferably less than the p-type impurity concentration of body region 55 . The n-type impurity concentration of high-concentration drift region 91 may be 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁹ cm ^{−3 or} less.

High-concentration drift region 91 is formed by introducing an n-type impurity into drift region 54 from the inner wall of gate trench 65 . Therefore, body region 55 includes part of the n-type impurities of high-concentration drift region 91 .

That is, the body region 55 includes a compensation region in which a portion of the p-type impurity is offset by a portion of the n-type impurity in the region along the outer wall of the trench gate structure 61, and is p-type as a whole. of semiconductor regions. "Offset compensation" is also referred to as "offset," "compensation," "carrier offset," or "carrier compensation." The p-type impurity concentration in the offset compensation region is lowered by the amount offset by the n-type impurity.

By forming the high-concentration drift region 91, the concentration of the region serving as the main current path in the drift region 54 can be increased. Thereby, the on-resistance of the drift region 54 can be reduced. Moreover, since the entire drift region 54 does not need to be highly doped, electric field concentration in the semiconductor layer 2 can be suppressed. In particular, by forming the high-concentration drift region 91 along the outer wall of the trench gate structure 61, electric field concentration on the trench gate structure 61 can be suppressed. Therefore, a decrease in breakdown voltage can be suppressed.

When narrowing the pitch PC of the plurality of trench gate structures 61, there is concern that the on-resistance of the drift region 54 will increase due to the reduction of the current path. However, since the current path can be secured by the high-concentration drift region 91, an increase in on-resistance can be suppressed. As a result, it is possible to reduce the channel resistance by narrowing the pitch PC while suppressing an increase in on-resistance and a decrease in breakdown voltage.

Each high concentration drift region 91 includes a sidewall covering portion 92 and a bottom wall covering portion 93 . Sidewall covering portion 92 covers first sidewall 62 and second sidewall 63 of trench gate structure 61 . The bottom wall covering portion 93 covers the bottom wall 64 of the trench gate structure 61 through the corner portions of the trench gate structure 61 . Bottom wall covering portion 93 forms the bottom portion of high-concentration drift region 91 .

The bottom wall covering portion 93 has a high concentration region 94 (see broken line in FIG. 7) having an n-type impurity concentration higher than that of the side wall covering portion 92 . A heavily doped region 94 is formed along the bottom wall 64 of the trench gate structure 61 . By forming the bottom wall covering portion 93, electric field concentration on the bottom wall 64 of the trench gate structure 61 can be appropriately suppressed. Bottom wall covering portion 93 may have a concentration gradient in which the n-type impurity concentration gradually decreases from high concentration region 94 toward drift region 54 .

Each high-concentration drift region 91 has a bottom located in a region on the bottom wall 64 side of each trench gate structure 61 with respect to the bottom of the drift region 54 . The bottom of each high-concentration drift region 91 is formed in the region on the first main surface 3 side with an interval ID of 0.1 μm or more and 3 μm or less from the bottom of the drift region 54 .

The interval ID is 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. There may be. The interval ID is preferably 0.5 μm or more and 2.5 μm or less.

The thickness TDB of the bottom portion (bottom wall covering portion 93 ) of each high-concentration drift region 91 may be equal to or greater than the pitch PS between sidewalls of the trench gate structure 61 (PS≦TDB). The thickness TDB may exceed the pitch PS (PS<thickness TDB). Thickness TDB is the thickness between bottom wall 64 of trench gate structure 61 and the bottom of each heavily doped drift region 91 . The thickness TDB is also the difference IT-ID between the interval IT and the interval ID.

A plurality of high-concentration drift regions 91 are connected to each other in regions between adjacent trench gate structures 61 in this embodiment. Thereby, a high-concentration drift region 91 in which a plurality of high-concentration drift regions 91 are integrated is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 .

The integrated high-concentration drift region 91 collectively covers the plurality of trench gate structures 61 . Integrated heavy drift region 91 includes a first connection 95 and a second connection 96 in the region between adjacent trench gate structures 61 .

First connection portion 95 is a portion where a plurality of high-concentration drift regions 91 are connected to bottom wall 64 of each trench gate structure 61 in a region on the first main surface 3 side. The second connection portion 96 is a portion where the plurality of high-concentration drift regions 91 are connected to the bottom wall 64 of each trench gate structure 61 in the region on the bottom side of the drift region 54 . The second connecting portion 96 may be formed in a concave shape that is recessed toward the first main surface 3 .

The high-concentration drift region 91 exposes the outer surfaces of the plurality of trench contact structures 81 in the drift region 54 in this form. That is, the high-concentration drift region 91 covers the outer surface of the trench gate structure 61 in the drift region 54 at intervals from the plurality of trench contact structures 81 .

A plurality of n ⁺ -type source regions 101 are formed in the surface layer portion of the body region 55 . The n-type impurity concentration of source region 101 exceeds the n-type impurity concentration of drift region 54 . The n-type impurity concentration of source region 101 exceeds the n-type impurity concentration of high concentration drift region 91 . The n-type impurity concentration of the source region 101 may be 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less.

A plurality of source regions 101 are selectively formed along the first side wall 62 and the second side wall 63 of each trench gate structure 61 in the surface layer portion of the body region 55 . The bottoms of the plurality of source regions 101 are located in a region on the first main surface 3 side with respect to the bottoms of the body regions 55 . As a result, the plurality of source regions 101 face the buried electrode 67 (opening side electrode 73) with the insulating layer 66 (opening side insulating layer 69) interposed therebetween.

6 to 8, multiple source regions 101 more specifically include multiple first source regions 101A and multiple second source regions 101B. A plurality of first source regions 101A are spaced apart along the first sidewall 62 of each trench gate structure 61 . A plurality of second source regions 101B are spaced apart along the second sidewall 63 of each trench gate structure 61 .

Each second source region 101B faces each first source region 101A along the second direction Y in this embodiment. Each second source region 101B is integrated with each first source region 101A. Each second source region 101B is formed shifted in the first direction X from each first source region 101A so as not to face part or all of each first source region 101A along the second direction Y. good too.

A plurality of p ⁺ -type contact regions 102 are formed in the surface layer portion of the body region 55 . The p-type impurity concentration of contact region 102 exceeds the p-type impurity concentration of body region 55 . The p-type impurity concentration of the contact region 102 may be 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less.

A plurality of contact regions 102 are formed in regions between the plurality of source regions 101 in the surface layer portion of the body region 55 . Thus, the plurality of contact regions 102 are formed in the surface layer portion of the body region 55 in an alternate arrangement with respect to the plurality of source regions 101 .

6 to 8, multiple contact regions 102 more specifically include multiple first contact regions 102A and multiple second contact regions 102B. A plurality of first contact regions 102A are spaced along the first sidewall 62 of each trench gate structure 61 so as to be interposed between the plurality of first source regions 101A. A plurality of second source regions 101B are spaced apart along the second sidewall 63 of each trench gate structure 61 so as to be interposed between the plurality of second source regions 101B.

Each second contact region 102B faces each first contact region 102A along the second direction Y in this embodiment. Each second contact region 102B is integral with each first contact region 102A. When each second source region 101B is formed shifted in the first direction X from each first source region 101A, each second contact region 102B is formed shifted in the first direction X from each first contact region 102A. may have been

In this embodiment, the source region 101 and the contact region 102 are not formed in a region sandwiched by one ends of the adjacent trench gate structures 61 on the first main surface 3 of the semiconductor layer 2 . A body region 55 is exposed from a region sandwiched between one end portions of the trench gate structures 61 adjacent to each other on the first main surface 3 of the semiconductor layer 2 .

Similarly, although not shown, source region 101 and contact region 102 are not formed in a region sandwiched by the other end portions of adjacent trench gate structures 61 on first main surface 3 of semiconductor layer 2 . As a result, the body region 55 is exposed from the region sandwiched by the other end portions of the trench gate structures 61 adjacent to each other on the first main surface 3 of the semiconductor layer 2 .

Thus, the FET structure 110 is formed on the surface layer portion of the first main surface 3 of the semiconductor layer 2 . A FET structure 110 is formed laterally of each trench gate structure 61 . FET structure 110 includes a plurality of source regions 101 , body regions 55 and high concentration drift regions 91 (drift regions 54 ) formed in this order from first main surface 3 to second main surface 4 .

The FET structure 110 also includes a plurality of contact regions 102 in this form. A channel CH of power MISFET 9 is formed in a region sandwiched between a plurality of source regions 101 and high-concentration drift region 91 in body region 55 .

FET structure 110 more specifically includes a first FET structure 110A and a second FET structure 110B. A first FET structure 110 A is formed in a region along the first sidewall 62 of each trench gate structure 61 . A second FET structure 110 B is formed in a region along the second sidewall 63 of each trench gate structure 61 .

The first FET structure 110A includes a plurality of first source regions 101A, body regions 55 and high concentration drift regions 91 (drift regions 54) formed in this order from the first main surface 3 to the second main surface 4. FIG. The first FET structure 110A also includes a plurality of first contact regions 102A in this form. A first channel CH1 of power MISFET 9 is formed in a region sandwiched between a plurality of first source regions 101A and high-concentration drift region 91 in body region 55 .

The first channel CH1 is formed with the first channel area SCH1 in the region between the trench gate structures 61 adjacent to each other. The first channel area SCH1 is defined by the total planar area of the plurality of first source regions 101A formed in the regions between the trench gate structures 61 adjacent to each other.

The first channel CH1 has a first channel ratio RCH1 between 0% and 50%. The first channel ratio RCH1 is the ratio of the first channel area SCH1 in the region between the trench gate structures 61 adjacent to each other. The first channel ratio RCH1 is adjusted within a range of 0% or more and 50% or less.

The first channel ratio RCH1 is 0% or more and 5% or less, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, 20% or more and 25% or less, 25% or more and 30% or less, 30 % or more and 35% or less, 35% or more and 40% or less, 40% or more and 45% or less, or 45% or more and 50% or less. The first channel ratio RCH1 is preferably 10% or more and 35% or less.

When the first channel ratio RCH1 is 50%, the first source region 101A is formed on substantially the entire first side wall 62 of the trench gate structure 61. As shown in FIG. In this case, the first contact region 102A is not formed on the first sidewall 62 of the trench gate structure 61. FIG. Preferably, the first channel proportion RCH1 is less than 50%.

When the first channel ratio RCH1 is 0%, the first source region 101A is not formed on the first sidewall 62 of the trench gate structure 61. FIG. In this case, only body region 55 and/or first contact region 102A are formed on first sidewall 62 of trench gate structure 61 . Preferably, the first channel proportion RCH1 is greater than 0%. In FIGS. 3-6, an example is shown in which the first channel proportion RCH1 is 25%.

The second FET structure 110B includes a plurality of second source regions 101B, body regions 55 and high-concentration drift regions 91 (drift regions 54) formed in this order from the first main surface 3 to the second main surface 4. As shown in FIG. The second FET structure 110B also includes a plurality of second contact regions 102B in this version. A second channel CH2 of power MISFET 9 is formed in a region sandwiched between a plurality of second source regions 101B and high-concentration drift region 91 in body region 55 .

The second channel CH2 is formed with the second channel area SCH2 in the region between the trench gate structures 61 adjacent to each other. The second channel area SCH2 is defined by the total planar area of the plurality of second source regions 101B formed in the regions between the trench gate structures 61 adjacent to each other.

The second channel CH2 has a second channel ratio RCH2 between 0% and 50%. The second channel ratio RCH2 is the ratio of the second channel area SCH2 to the region between adjacent trench gate structures 61 . The second channel ratio RCH2 is adjusted within a range of 0% or more and 50% or less.

The second channel ratio RCH2 is 0% or more and 5% or less, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, 20% or more and 25% or less, 25% or more and 30% or less, 30 % or more and 35% or less, 35% or more and 40% or less, 40% or more and 45% or less, or 45% or more and 50% or less. The second channel ratio RCH2 is preferably 10% or more and 35% or less.

When the second channel ratio RCH2 is 50%, the second source region 101B is formed on substantially the entire second side wall 63 of the trench gate structure 61. As shown in FIG. In this case, the second contact region 102B is not formed on the second sidewall 63 of the trench gate structure 61. FIG. Therefore, the second channel ratio RCH2 is preferably less than 50%.

When the second channel ratio RCH2 is 0%, the second source region 101B is not formed on the second sidewall 63 of the trench gate structure 61. FIG. In this case, only the body region 55 and/or the second contact region 102B are formed on the second sidewall 63 of the trench gate structure 61 . Therefore, the second channel ratio RCH2 preferably exceeds 0%. In FIGS. 3-6, examples are shown in which the second channel proportion RCH2 is 25%.

The second channel proportion RCH2 may be equal to the first channel proportion RCH1. The second channel proportion RCH2 may differ from the first channel proportion RCH1. The first channel ratio RCH1 and the second channel ratio RCH2 are adjusted to arbitrary values within the range of the total channel ratio RCH1+RCH2 of 0% or more and 100% or less (more specifically, more than 0% and less than 100%).

When the total channel ratio RCH1+RCH2 is increased, there is a trade-off that the ON resistance is decreased while the active clamp resistance is decreased. By setting the total channel ratio RCH1+RCH2 to 20% or more and 70% or less, it is possible to appropriately design the on-resistance and the active clamp resistance. In this case, it is preferable that the first channel ratio RCH1 is 10% or more and 35% or less, and the second channel ratio RCH2 is 10% or more and 35% or less.

A plurality of first FET structures 110A having different first channel fractions RCH1 may be formed, and adjustments may be made to average the total first channel fraction RCH1 per unit area (total channel fraction RCH1+RCH2).

Simultaneously or alternatively, a plurality of second FET structures 110B having second channel ratios RCH2 different from each other are formed to average the total second channel ratio RCH2 per unit area (total channel ratio RCH1+RCH2). may be performed.

The total channel ratio RCH1+RCH2 per unit area may be adjusted according to the temperature distribution of the semiconductor layer 2 . For example, the total channel ratios RCH1+RCH2 in regions where the temperature is likely to rise in the semiconductor layer 2 may be relatively small, and the total channel ratios RCH1+RCH2 in regions where the temperature is difficult to rise in the semiconductor layer 2 may be relatively large. A central portion of the output region 6 can be exemplified as a region in the semiconductor layer 2 where the temperature tends to rise. A peripheral portion of the output region 6 can be exemplified as a region in which the temperature of the semiconductor layer 2 is difficult to rise.

3 and 4, main surface insulating layer 121 is formed on first main surface 3 of semiconductor layer 2 . The main surface insulating layer 121 selectively covers the first main surface 3 of the semiconductor layer 2 . The main surface insulating layer 121 continues to the insulating layer 66 and the contact insulating layer 86 . Main surface insulating layer 121 is at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). including.

The principal surface insulating layer 121 may have a laminated structure including a SiN layer and a SiO ₂ layer laminated in this order from the semiconductor layer 2 side. The main surface insulating layer 121 may have a laminated structure including a SiO ₂ layer and a SiN layer laminated in this order from the semiconductor layer 2 side. The main surface insulating layer 121 may have a single layer structure consisting of a _SiO2 layer or a SiN layer. The main surface insulating layer 121 has a single layer structure consisting of a SiO ₂ layer in this embodiment. The main surface insulating layer 121 is preferably made of the same insulating material as the insulating layer 66 . The main surface insulating layer 121 is integrated with the insulating layer 66 at the opening of the gate trench 65 .

An interlayer insulating layer 122 is formed on the main surface insulating layer 121 . Interlayer insulating layer 122 may have a thickness exceeding the thickness of main surface insulating layer 121 . The interlayer insulating layer 122 covers substantially the entire main surface insulating layer 121 . Interlayer insulating layer 122 contains at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). include.

Interlayer insulating layer 122 in this embodiment includes a USG (Undoped Silica Glass) layer as an example of silicon oxide. The interlayer insulating layer 122 may have a single layer structure made of a USG layer. Interlayer insulating layer 122 may have a flattened main surface. The main surface of interlayer insulating layer 122 may be a ground surface ground by a CMP (Chemical Mechanical Polishing) method.

The interlayer insulating layer 122 may contain PSG (Phosphor Silicate Glass) and/or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide. Interlayer insulating layer 122 may have a laminated structure including a PSG layer and a BPSG layer laminated in this order from the first main surface 3 side of semiconductor layer 2 . Interlayer insulating layer 122 may have a laminated structure including a BPSG layer and a PSG layer laminated in this order from the first main surface 3 side of semiconductor layer 2 .

3, 4, 7 and 8, first plug electrode 123, second plug electrode 124 and third plug electrode 125 are embedded in interlayer insulating layer 122 in output region 6. Referring to FIGS. In this form, a plurality of first plug electrodes 123, a plurality of second plug electrodes 124 and a plurality of third plug electrodes 125 are embedded. The first plug electrode 123, the second plug electrode 124 and the third plug electrode 125 may each contain tungsten.

The plurality of first plug electrodes 123 are embedded in portions of the interlayer insulating layer 122 that cover the opening-side electrodes 73 . In this embodiment, the plurality of first plug electrodes 123 penetrate the interlayer insulating layer 122 in the region on the one end side of the trench gate structure 61 and are connected to the plurality of opening side electrodes 73 in a one-to-one correspondence relationship. . Of course, a plurality of first plug electrodes 123 may be connected to one opening-side electrode 73 .

Although not shown, the plurality of first plug electrodes 123 are also embedded in the region on the other end side of the trench gate structure 61 . A plurality of first plug electrodes 123 penetrate the interlayer insulating layer 122 in a region on the other end side of the trench gate structure 61 and are connected to the plurality of opening side electrodes 73 in a one-to-one correspondence. Of course, a plurality of first plug electrodes 123 may be connected to one opening-side electrode 73 .

In this embodiment, the plurality of first plug electrodes 123 are arranged in a row along the second direction Y in the one end side region and the other end side region of the trench gate structure 61 at intervals. Each first plug electrode 123 may be formed in a polygonal shape such as a triangular shape, a square shape, a pentagonal shape, a hexagonal shape, a circular shape, or an elliptical shape in plan view. Each first plug electrode 123 is formed in a rectangular shape in plan view in this form.

A plurality of second plug electrodes 124 are embedded in portions of the interlayer insulating layer 122 covering the contact electrodes 87 of the trench contact structure 81 on one side. A plurality of second plug electrodes 124 pass through the interlayer insulating layer 122 and are connected to the contact electrodes 87 of the trench contact structure 81 on one side.

Although not shown, the plurality of second plug electrodes 124 are also embedded in a portion of the interlayer insulating layer 122 covering the contact electrode 87 of the trench contact structure 81 on the other side. A plurality of second plug electrodes 124 pass through the interlayer insulating layer 122 and are connected to the contact electrodes 87 of the trench contact structure 81 on the other side.

The plurality of second plug electrodes 124 are arranged in a line along the second direction Y in this form with a space therebetween. Each second plug electrode 124 may be formed in a polygonal shape such as triangular, quadrangular, pentagonal, or hexagonal in plan view, or in a circular or elliptical shape. Each second plug electrode 124 is formed in a rectangular shape in plan view in this form.

A plurality of third plug electrodes 125 are embedded in portions of the interlayer insulating layer 122 covering the FET structure 110 . A plurality of third plug electrodes 125 pass through the interlayer insulating layer 122 and are connected to the corresponding first FET structure 110A and second FET structure 110B, respectively. Each third plug electrode 125 is electrically connected to the corresponding source region 101 and contact region 102 .

Each third plug electrode 125 is formed in a strip shape extending along the trench gate structure 61 in plan view. The length in the first direction X of each third plug electrode 125 may be less than the length in the first direction X of the trench gate structure 61 .

Of course, a plurality of third plug electrodes 125 may be formed at intervals in regions between a plurality of trench gate structures 61 adjacent to each other. In this case, each third plug electrode 125 may be formed in a polygonal shape such as a triangular shape, a square shape, a pentagonal shape, a hexagonal shape, a circular shape, or an elliptical shape in plan view.

The reference potential electrode 14 and the gate control wiring 17 are formed on the interlayer insulating layer 122 in the output region 6 . Reference potential electrode 14 is electrically connected to a plurality of third plug electrodes 125 on interlayer insulating layer 122 . A reference potential is applied to the reference potential electrode 14 . A reference potential is communicated to the first FET structure 110A and the second FET structure 110B via the plurality of third plug electrodes 125. FIG.

A first gate control wiring 17A of the gate control wirings 17 is electrically connected to the plurality of first plug electrodes 123 on the interlayer insulating layer 122 . A gate control signal is applied to the first gate control wiring 17A. A gate control signal is transmitted to the bottom electrode 72 of each trench gate structure 61 via the first gate control wiring 17A and the plurality of first plug electrodes 123 .

The second gate control wiring 17B of the gate control wirings 17 is electrically connected to the plurality of second plug electrodes 124 on the interlayer insulating layer 122 . A gate control signal is applied to the second gate control wiring 17B. A gate control signal is transmitted to the opening side electrode 73 of each trench gate structure 61 via the second gate control wiring 17B and the plurality of second plug electrodes 124 .

When driving the power MISFET 9 (that is, during gate ON control), a gate voltage may be applied to the first gate control wiring 17A and the second gate control wiring 17B. In this case, a gate voltage is applied to the bottom electrode 72 and the opening electrode 73 . This allows the bottom-side electrode 72 and the opening-side electrode 73 to function as gate electrodes.

When driving the power MISFET 9 (that is, during gate ON control), the reference potential may be applied to the first gate control wiring 17A and the gate voltage may be applied to the second gate control wiring 17B. In this case, the reference potential is applied to the bottom electrode 72 and the gate voltage is applied to the opening electrode 73 . This allows the bottom-side electrode 72 to function as a field electrode and the opening-side electrode 73 to function as a gate electrode.

9 is a plan view of the region IX shown in FIG. 1, showing the structure of part of the input region 7 of the semiconductor layer 2. FIG. 10 is a cross-sectional view taken along line X-X shown in FIG. 9. FIG. 11 is a cross-sectional view taken along line XI-XI shown in FIG. 9. FIG.

9 to 11, input region 7 (control IC 10) includes a CMIS (Complementary Metal Insulator Semiconductor) region 131 formed on first main surface 3 of semiconductor layer 2. FIG. The high-concentration drift region 91 described above is not formed in the CMIS region 131 . The CMIS region 131 is formed in the drift region 54 (epitaxial layer 52 ) that is not highly doped by the high concentration drift region 91 .

If the drift region 54 of the CMIS region 131 is highly doped, the on-resistance can be reduced, but the characteristics of the control IC 10 fluctuate. Also, the breakdown voltage may decrease due to the high concentration of the drift region 54 in the CMIS region 131 .

Therefore, by forming the high-concentration drift region 91 only in the output region 6 , it is possible to improve the electrical characteristics of the power MISFET 9 while suppressing fluctuations in the electrical characteristics of the control IC 10 . Further, since the CMIS area 131 does not need to be changed in design, even if the output area 6 (power MISFET 9) is changed in design, the compatibility of the input area 7 (control IC 10) can be maintained before and after the design change.

CMIS region 131 includes n-type MIS region 132 and p-type MIS region 133 formed in an arbitrary region of first main surface 3 of semiconductor layer 2 in input region 7 . The n-type MIS region 132 is a region in which an n-type MISFET 134 is formed. The p-type MIS region 133 is a region in which the p-type MISFET 135 is formed. The p-type MIS region 133 is electrically insulated from the n-type MIS region 132 .

The n-type MIS region 132 may be formed in a polygonal shape such as a triangular, quadrangular, pentagonal, or hexagonal shape, or in a circular or elliptical shape in plan view. In this form, the n-type MIS region 132 is formed in a square shape in plan view.

The p-type MIS region 133 is formed spaced apart from the n-type MIS region 132 . The p-type MIS region 133 may be formed in a polygonal shape such as a triangular shape, a pentagonal shape, or a hexagonal shape, or in a circular or elliptical shape in plan view. In this form, the p-type MIS region 133 is formed in a square shape in plan view.

9 and 10, n-type MIS region 132 is partitioned by first region isolation structure 136. In FIG. First region isolation structure 136 is formed in an annular shape including an inner peripheral wall that partitions n-type MIS region 132, an outer peripheral wall, and a bottom wall that connects the inner peripheral wall and the outer peripheral wall. The first region isolation structure 136 may be formed in a polygonal ring such as a triangular ring, a square ring, a pentagonal ring, or a hexagonal ring, or in a circular ring or an elliptical ring, depending on the planar shape of the n-type MIS region 132 . .

The width WS1 of the first region isolation structure 136 may be 0.5 μm or more and 3 μm or less. Width WS1 is the width in the direction orthogonal to the direction in which first region isolation structure 136 extends. The width WS1 may be 0.5 μm to 1.0 μm, 1.0 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, or 2.5 μm to 3 μm. The width WS1 is preferably 0.8 μm or more and 2 μm or less. Width WS1 is preferably equal to width WT of trench gate structure 61 .

The inner peripheral wall, the outer peripheral wall and the bottom wall of first region isolation structure 136 are located within drift region 54 . A depth DS1 of the first region isolation structure 136 may be 1 μm or more and 10 μm or less. The depth DS1 may be 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm. The depth DS1 is preferably 2 μm or more and 6 μm or less. Depth DS1 is preferably equal to depth DT of trench gate structure 61 .

An inner peripheral wall and an outer peripheral wall of the first region separation structure 136 extend along the normal direction Z. As shown in FIG. The inner peripheral wall and the outer peripheral wall of the first region isolation structure 136 may be formed perpendicular to the first major surface 3 .

The absolute value of the angle (taper angle) formed between the inner peripheral wall of the first region isolation structure 136 and the first main surface 3 in the semiconductor layer 2 is more than 90° and 95° or less (for example, about 91°). There may be. The absolute value of the angle (taper angle) formed between the outer peripheral wall of the first region isolation structure 136 and the first main surface 3 in the semiconductor layer 2 is more than 90° and 95° or less (for example, about 91°). There may be. The first region isolation structure 136 may be formed in a tapered shape (tapered shape) in which the width WS1 narrows from the first main surface 3 side of the semiconductor layer 2 toward the bottom wall side in a cross-sectional view.

The bottom wall of first region isolation structure 136 is located in a region on the first main surface 3 side with respect to the bottom of drift region 54 . The bottom wall of the first region isolation structure 136 is formed in a convex curve (U-shape) toward the bottom of the drift region 54 in the same manner as the bottom wall 64 of the trench gate structure 61 .

The first isolation structure 136 includes a first isolation trench 137 , a first isolation insulating layer 138 and a first isolation electrode 139 . The first isolation trench 137 is formed by digging the first main surface 3 of the semiconductor layer 2 toward the second main surface 4 side. The first isolation trench 137 defines the inner peripheral wall, the outer peripheral wall and the bottom wall of the first isolation structure 136 .

The first region isolation insulating layer 138 is formed in a film shape along the inner wall of the first region isolation trench 137 . The first isolation insulating layer 138 defines a recessed space within the first isolation trench 137 .

A portion of the first isolation insulating layer 138 covering the bottom wall of the first isolation trench 137 is formed along the bottom wall of the first isolation trench 137 . As a result, the first isolation insulating layer 138 is U-shaped at the bottom walls of the first isolation trenches 137 in a manner similar to the bottom side insulating layer 68 of the trench gate structure 61 (the contact insulating layer 86 of the trench contact structure 81). It partitions a U-shaped space that is recessed in the shape of a letter.

The first region isolation insulating layer 138 is made of at least silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), or tantalum oxide (Ta ₂ O ₃ ). Includes 1 species.

The first region isolation insulating layer 138 may have a laminated structure including a SiN layer and a SiO ₂ layer laminated in this order from the semiconductor layer 2 side. The first region isolation insulating layer 138 may have a laminated structure including a SiO ₂ layer and a SiN layer laminated in this order from the semiconductor layer 2 side. The first region isolation insulating layer 138 may have a single layer structure consisting of a _SiO2 layer or a SiN layer. In this form, the first region isolation insulating layer 138 has a single layer structure consisting of a SiO ₂ layer. The first region isolation insulating layer 138 is preferably made of the same insulating material as the insulating layer 66 .

The first region isolation insulating layer 138 has a fifth thickness T5. The fifth thickness T5 may range from 1500 Å to 4000 Å. The fifth thickness T5 may be 1500 Å to 2000 Å, 2000 Å to 2500 Å, 2500 Å to 3000 Å, 3000 Å to 3500 Å, or 3500 Å to 4000 Å. The fifth thickness T5 is preferably 1800 Å or more and 3500 Å or less. The fifth thickness T5 is preferably equal to the first thickness T1 of the bottom insulating layer 68 (T5=T1).

The first isolation electrode 139 is embedded in the first isolation trench 137 with the first isolation insulating layer 138 interposed therebetween. A reference potential is applied to the first segmentation electrode 139 . Unlike the embedded electrode 67 of the trench gate structure 61, the first isolation electrode 139 is embedded in the first isolation trench 137 as an integral body. The first isolation electrode 139 has one end exposed from the first isolation trench 137 and the other end in contact with the first isolation trench 137 .

The other end of the first isolation electrode 139 is convexly curved toward the bottom wall of the first isolation trench 137 in the same manner as the bottom electrode 72 of the trench gate structure 61 (the contact electrode 87 of the trench contact structure 81). formed in the shape of More specifically, the other end of the first region isolation electrode 139 is formed along the bottom wall of the U-shaped space partitioned by the first region isolation insulating layer 138, and is formed along the bottom wall of the first region isolation trench 137. It is formed in a smooth convex curve toward the bottom wall.

The first isolation electrode 139 may include at least one of conductive polysilicon, tungsten, aluminum, copper, aluminum alloy, or copper alloy. The first region isolation electrode 139 comprises conductive polysilicon in this form. The conductive polysilicon may contain n-type impurities or p-type impurities. The conductive polysilicon preferably contains n-type impurities. The first region isolation electrode 139 preferably contains the same conductive material as the embedded electrode 67 .

An exposed portion of the first isolation electrode 139 exposed from the first isolation trench 137 is covered with a cap insulating layer 140 formed in a film shape. The cap insulating layer 140 continues to the first isolation insulating layer 138 within the first isolation trench 137 . The cap insulating layer 140 may contain silicon oxide (SiO ₂ ).

A p-type first well region 141 is formed in a region surrounded by the first region isolation structure 136 in the surface layer portion of the first main surface 3 of the semiconductor layer 2 . A bottom portion of the first well region 141 is formed in a region on the first main surface 3 side with respect to the bottom wall of the first region isolation structure 136 .

The first well region 141 covers the inner peripheral wall of the first isolation trench 137 and exposes the bottom wall of the first isolation structure 136 . The bottom of the first well region 141 is located in the region on the bottom wall side of the first isolation trench 137 with respect to the intermediate portion of the first isolation trench 137 .

An n ⁺ -type first source region 143 and an n ⁺ -type first drain region 144 are formed in the surface layer portion of the first well region 141 . The first drain region 144 is spaced apart from the first source region 143 . The n-type impurity concentration of the first drain region 144 is approximately equal to the n-type impurity concentration of the first source region 143 .

The first source region 143 and the first drain region 144 are formed in the central portion of the first well region 141 in plan view. The first source region 143 and the first drain region 144 may each be formed in a strip shape extending in the same direction in plan view. The bottom of the first source region 143 and the bottom of the first drain region 144 are formed in a region on the first main surface 3 side with respect to the bottom of the first well region 141 .

A p ⁺ -type first contact region 145 is further formed in the surface layer of the first well region 141 . The first contact region 145 has a p-type impurity concentration exceeding the p-type impurity concentration of the first well region 141 .

The first contact region 145 is formed in a ring shape that collectively surrounds the first source region 143 and the first drain region 144 in plan view. The first contact region 145 is spaced apart from the first region isolation structure 136 . The first contact region 145 may cover the inner peripheral wall of the first region isolation structure 136 .

A first planar gate structure 146 is formed in a region surrounded by the first region isolation structure 136 on the first main surface 3 of the semiconductor layer 2 . A first planar gate structure 146 covers the first source region 143 , the first drain region 144 and the region between the first source region 143 and the first drain region 144 . The first planar gate structure 146 is formed in a strip shape extending along the first source region 143 and the first drain region 144 in plan view.

The first planar gate structure 146 has a laminated structure including a first gate insulating layer 147 and a first gate electrode layer 148 . The first gate electrode layer 148 faces the first source region 143 , the first drain region 144 , and the region between the first source region 143 and the first drain region 144 with the first gate insulating layer 147 interposed therebetween. there is A channel of the n-type MISFET 134 is formed in a region between the first source region 143 and the first drain region 144 in the surface layer portion of the first well region 141 .

A first field insulating layer 149 is formed in a region surrounded by the first region isolation structure 136 on the first main surface 3 of the semiconductor layer 2 . The first field insulating layer 149 may be a LOCOS layer.

The first field insulating layer 149 covers the region between the inner periphery of the first planar gate structure 146 and the first contact region 145 and the region between the first region isolation structure 136 and the outer periphery of the first contact region 145. covered. The first field insulating layer 149 is connected to the first isolation insulating layer 138 at the opening of the first isolation trench 137 .

The above-described interlayer insulating layer 122 is formed on the first main surface 3 of the semiconductor layer 2 in the n-type MIS region 132 . A first source plug electrode 150 , a first drain plug electrode 151 and a first contact plug electrode 152 are embedded in the interlayer insulating layer 122 . The first source plug electrode 150, the first drain plug electrode 151 and the first contact plug electrode 152 may each contain tungsten.

The first source plug electrode 150 penetrates the interlayer insulating layer 122 and is connected to the first source region 143 . The first drain plug electrode 151 penetrates the interlayer insulating layer 122 and is connected to the first drain region 144 . The first contact plug electrode 152 penetrates the interlayer insulating layer 122 and is connected to the first contact region 145 .

9 and 11, p-type MIS region 133 is partitioned by second region isolation structure 156. In FIG. The second isolation structure 156 is spaced apart from the first isolation structure 136 in this embodiment. The second region isolation structure 156 faces the first region isolation structure 136 with a partial region of the semiconductor layer 2 interposed therebetween.

The second isolation structure 156 may be formed integrally with the first isolation structure 136 . Second region isolation structure 156 may be integrated with first region isolation structure 136 in a region between n-type MIS region 132 and p-type MIS region 133 .

Second region isolation structure 156 is formed in an annular shape including an inner peripheral wall defining p-type MIS region 133, an outer peripheral wall, and a bottom wall connecting the inner and outer peripheral walls. The second region isolation structure 156 may be formed in a polygonal ring such as a triangular ring, a square ring, a pentagonal ring, or a hexagonal ring, or in a circular ring or an elliptical ring, depending on the planar shape of the p-type MIS region 133 . .

The width WS2 of the second region isolation structure 156 may be 0.5 μm or more and 2.0 μm or less. Width WS2 is the width in the direction orthogonal to the direction in which second region isolation structure 156 extends. The width WS2 may be 0.5 μm to 1.0 μm, 1.0 μm to 1.5 μm, or 1.5 μm to 2.0 μm. The width WS2 is preferably 0.8 μm or more and 1.2 μm or less. Width WS2 is preferably equal to width WT of trench gate structure 61 .

The inner peripheral wall, the outer peripheral wall and the bottom wall of second region isolation structure 156 are located within drift region 54 . The depth DS2 of the second region isolation structure 156 may be 1 μm or more and 10 μm or less. The depth DS2 may be 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm. The depth DS2 is preferably 2 μm or more and 6 μm or less. Depth DS2 is preferably equal to depth DT of trench gate structure 61 .

The inner peripheral wall and the outer peripheral wall of the second region separation structure 156 extend along the normal direction Z. As shown in FIG. The inner peripheral wall and the outer peripheral wall of the second region isolation structure 156 may be formed perpendicular to the first major surface 3 .

The absolute value of the angle (taper angle) formed between the inner peripheral wall of the second region isolation structure 156 and the first main surface 3 in the semiconductor layer 2 is more than 90° and 95° or less (for example, about 91°). There may be. The absolute value of the angle (taper angle) formed between the outer peripheral wall of the second region isolation structure 156 and the first main surface 3 in the semiconductor layer 2 is more than 90° and less than or equal to 95° (for example, about 91°). There may be. The second region isolation structure 156 may be formed in a tapered shape (tapered shape) in which the width WS2 narrows from the first main surface 3 side of the semiconductor layer 2 toward the bottom wall side in a cross-sectional view.

The bottom wall of second region isolation structure 156 is located in a region on the first main surface 3 side with respect to the bottom of drift region 54 . The bottom wall of the second region isolation structure 156 is formed in a convex curved shape (U-shape) toward the bottom of the drift region 54 .

The second isolation structure 156 includes a second isolation trench 157 , a second isolation insulating layer 158 and a second isolation electrode 159 . The second isolation trench 157 is formed by digging the first main surface 3 of the semiconductor layer 2 toward the second main surface 4 side. The second isolation trench 157 defines the inner peripheral wall, the outer peripheral wall and the bottom wall of the second isolation structure 156 .

The second isolation insulating layer 158 is formed in a film shape along the inner wall of the second isolation trench 157 . The second isolation insulating layer 158 defines a recessed space within the second isolation trench 157 .

A portion of the second isolation insulating layer 158 covering the bottom wall of the second isolation trench 157 is formed along the bottom wall of the second isolation trench 157 . As a result, the second isolation insulating layer 158 is U-shaped at the bottom wall of the second isolation trench 157 in the same manner as the bottom side insulating layer 68 of the trench gate structure 61 (the contact insulating layer 86 of the trench contact structure 81). It partitions a U-shaped space that is recessed in the shape of a letter.

The second region isolation insulating layer 158 is made of at least silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), or tantalum oxide (Ta ₂ O ₃ ). Includes 1 species.

The second region isolation insulating layer 158 may have a laminated structure including a SiN layer and a SiO ₂ layer laminated in this order from the semiconductor layer 2 side. The second region isolation insulating layer 158 may have a laminated structure including a SiO ₂ layer and a SiN layer laminated in this order from the semiconductor layer 2 side. The second region isolation insulating layer 158 may have a single layer structure consisting of a _SiO2 layer or a SiN layer. In this form, the second region isolation insulating layer 158 has a single layer structure consisting of a SiO ₂ layer. The second region isolation insulating layer 158 is preferably made of the same insulating material as the insulating layer 66 .

The second region isolation insulating layer 158 has a sixth thickness T6. The sixth thickness T6 may range from 1500 Å to 4000 Å. The sixth thickness T6 may be 1500 Å to 2000 Å, 2000 Å to 2500 Å, 2500 Å to 3000 Å, 3000 Å to 3500 Å, or 3500 Å to 4000 Å. The sixth thickness T6 is preferably 1800 Å or more and 3500 Å or less. The sixth thickness T6 is preferably equal to the first thickness T1 of the bottom insulating layer 68 (T6=T1).

The second isolation electrode 159 is embedded in the second isolation trench 157 with the second isolation insulating layer 158 interposed therebetween. A reference potential is applied to the second segmentation electrode 159 . Unlike the embedded electrode 67 of the trench gate structure 61, the second isolation electrode 159 is embedded in the second isolation trench 157 as an integral body. The second isolation electrode 159 has one end exposed from the second isolation trench 157 and the other end in contact with the second isolation trench 157 .

The other end of the second isolation electrode 159 is convexly curved toward the bottom wall of the second isolation trench 157 in the same manner as the bottom electrode 72 of the trench gate structure 61 (the contact electrode 87 of the trench contact structure 81). formed in the shape of More specifically, the other end of the second region isolation electrode 159 is formed along the bottom wall of the U-shaped space partitioned by the second region isolation insulating layer 158, and is formed along the bottom wall of the second region isolation trench 157. It is formed in a smooth convex curve toward the bottom wall.

The second isolation electrode 159 may include at least one of conductive polysilicon, tungsten, aluminum, copper, an aluminum alloy, or a copper alloy. The second isolation electrode 159 comprises conductive polysilicon in this form. The conductive polysilicon may contain n-type impurities or p-type impurities. The conductive polysilicon preferably contains n-type impurities. The second region separation electrode 159 preferably contains the same conductive material as the embedded electrode 67 .

The exposed portion of the second isolation electrode 159 exposed from the second isolation trench 157 is covered with a film-shaped cap insulating layer 160 . The cap insulating layer 160 continues to the second isolation insulating layer 158 within the second isolation trench 157 . The cap insulating layer 160 may contain silicon oxide (SiO ₂ ).

A p-type second well region 161 is formed in a region surrounded by the second region isolation structure 156 in the surface layer portion of the first main surface 3 of the semiconductor layer 2 . A bottom portion of the second well region 161 is formed in a region on the first main surface 3 side with respect to the bottom wall of the second region isolation structure 156 .

The second well region 161 covers the inner peripheral wall of the second isolation trench 157 and exposes the bottom wall of the second isolation structure 156 . The bottom of the second well region 161 is located in the region on the bottom wall side of the second isolation trench 157 with respect to the intermediate portion of the second isolation trench 157 .

An n-type surface well region 162 is formed in the surface layer portion of the second well region 161 . The surface well region 162 is formed in the central portion of the second well region 161 spaced apart from the inner peripheral wall of the second region isolation structure 156 in plan view. In this form, the surface well region 162 is formed in a square shape having four sides parallel to the inner peripheral wall of the second region isolation structure 156 in plan view. The bottom of the surface well region 162 is formed in a region on the first main surface 3 side with respect to the bottom wall of the second well region 161 .

A p ⁺ -type second source region 163 and a p ⁺ -type second drain region 164 are formed spaced apart from each other in the surface layer portion of the surface well region 162 . The second drain region 164 is spaced apart from the second source region 163 . The p-type impurity concentration of the second drain region 164 is approximately equal to the p-type impurity concentration of the second source region 163 .

The second source region 163 and the second drain region 164 are formed in the central portion of the surface well region 162 in plan view. The second source region 163 and the second drain region 164 may each be formed in a strip shape extending in the same direction in plan view. The bottom of the second source region 163 and the bottom of the second drain region 164 are formed in a region on the first main surface 3 side with respect to the bottom of the surface layer well region 162 .

A p ⁺ -type second contact region 165 is further formed in the surface layer of the second well region 161 . The second contact region 165 has a p-type impurity concentration exceeding the p-type impurity concentration of the second well region 161 .

The second contact region 165 is formed in a region between the second region isolation structure 156 and the surface well region 162 in plan view. The second contact region 165 is formed in an annular shape surrounding the surface well region 162 in plan view.

The second contact region 165 is formed spaced apart from the surface layer well region 162 and the second region isolation structure 156 . The second contact region 165 may be connected to the surface well region 162 . The second contact region 165 may cover the inner peripheral wall of the second region isolation structure 156 .

A second planar gate structure 166 is formed in a region surrounded by the second region isolation structure 156 on the first main surface 3 of the semiconductor layer 2 . A second planar gate structure 166 covers the second source region 163 , the second drain region 164 and the region between the second source region 163 and the second drain region 164 . The second planar gate structure 166 is formed in a strip shape extending along the second source region 163 and the second drain region 164 in plan view.

A second planar gate structure 166 has a laminated structure including a second gate insulating layer 167 and a second gate electrode layer 168 . The second gate electrode layer 168 faces the second source region 163, the second drain region 164, and the region between the second source region 163 and the second drain region 164 with the second gate insulating layer 167 interposed therebetween. there is A channel of the p-type MISFET 135 is formed in a region between the second source region 163 and the second drain region 164 in the surface layer portion of the surface layer well region 162 .

A second field insulating layer 169 is formed in a region surrounded by the second region isolation structure 156 on the first main surface 3 of the semiconductor layer 2 . The second field insulating layer 169 may be a LOCOS layer.

The second field insulating layer 169 covers the region between the inner periphery of the second planar gate structure 166 and the second contact region 165 and the region between the second region isolation structure 156 and the outer periphery of the second contact region 165. covered. The second field insulating layer 169 is connected to the second isolation insulating layer 158 at the opening of the second isolation trench 157 .

The above-described interlayer insulating layer 122 is formed on the first main surface 3 of the semiconductor layer 2 in the p-type MIS region 133 . A second source plug electrode 170 , a second drain plug electrode 171 and a second contact plug electrode 172 are embedded in the interlayer insulating layer 122 . The second source plug electrode 170, the second drain plug electrode 171 and the second contact plug electrode 172 may each contain tungsten.

The second source plug electrode 170 penetrates the interlayer insulating layer 122 and is connected to the second source region 163 . The second drain plug electrode 171 penetrates the interlayer insulating layer 122 and is connected to the second drain region 164 . The second contact plug electrode 172 penetrates the interlayer insulating layer 122 and is connected to the second contact region 165 .

12A to 12V are cross-sectional views of a region corresponding to FIG. 7, and are cross-sectional views for explaining an example of a method of manufacturing the semiconductor device 1 shown in FIG. Below, the manufacturing method for the output region 6 side will be described, and the description for the manufacturing method for the input region 7 side will be omitted.

Referring to FIG. 12A, a semiconductor wafer layer 182 (semiconductor layer) made of silicon that serves as the base of semiconductor layer 2 is prepared. Semiconductor wafer layer 182 has a first major surface 183 and a second major surface 184 . A first main surface 183 and a second main surface 184 of the semiconductor wafer layer 182 correspond to the first main surface 3 and the second main surface 4 of the semiconductor layer 2, respectively.

Semiconductor wafer layer 182 is manufactured through a process of forming epitaxial layer 52 on the main surface of semiconductor wafer 185 . The epitaxial layer 52 is formed by epitaxially growing silicon from the main surface of the semiconductor wafer 185 in this embodiment.

Next, referring to FIG. 12B, gate trenches 65 and contact trenches 85 are formed in the first main surface 183 of the semiconductor wafer layer 182 . In this step, first, an insulating film 186 is formed on the first main surface 183 of the semiconductor wafer layer 182 . The insulating film 186 may be formed by an oxidation treatment method (for example, a thermal oxidation treatment method).

A mask 187 having a predetermined pattern is then formed on the insulating film 186 . Mask 187 has openings 188 that expose regions in first major surface 183 of semiconductor wafer layer 182 where gate trenches 65 and contact trenches 85 are to be formed.

Next, unnecessary portions of the insulating film 186 are removed by an etching method through a mask 187 . Thereby, openings 189 corresponding to the openings 188 are formed in the insulating film 186 . Mask 187 is then removed.

Unwanted portions of the semiconductor wafer layer 182 are then removed by an etching method through the insulating film 186 . Thereby, the gate trench 65 and the contact trench 85 are formed in the first main surface 183 of the semiconductor wafer layer 182 . After that, the insulating film 186 is removed.

Next, referring to FIG. 12C, a sacrificial insulating layer 190 is formed on the first main surface 183 of the semiconductor wafer layer 182 . The sacrificial insulating layer 190 is formed as a film on the first main surface 183 of the semiconductor wafer layer 182 , the inner walls of the gate trenches 65 and the inner walls of the contact trenches 85 . The sacrificial insulating layer 190 may be formed by an oxidation process (for example, a thermal oxidation process). The thickness of the sacrificial insulating layer 190 may range from 100 Å to 2000 Å.

Next, referring to FIG. 12D, n-type impurities are introduced into the inner wall of gate trench 65 via sacrificial insulating layer 190 . The sacrificial insulating layer 190 functions as a protective film that protects the semiconductor wafer layer 182 and suppresses surface roughness caused by the introduction of n-type impurities.

The n-type impurity may be phosphorus. N-type impurities may be introduced into the semiconductor wafer layer 182 by an oblique ion implantation method. When the normal to first main surface 183 is 0°, the absolute value |θ| of the n-type impurity introduction angle with respect to the normal may be greater than 0° and 15° or less.

Absolute value |θ| . The absolute value |θ| is preferably 2° or more and 12° or less.

In this step, the introduction position of the n-type impurity relative to the first main surface 183 of the semiconductor wafer layer 182 is changed while the absolute value |θ| of the introduction angle is maintained. is introduced into the inner wall of the inner wall of the

More specifically, n-type impurities are introduced into the first major surface 183 of the semiconductor wafer layer 182 and the inner walls of the gate trenches 65 so as to impinge on the first sidewalls 62 of the gate trenches 65 . Also, the semiconductor wafer layer 182 is rotated by 90° so that the n-type impurity is introduced into the first main surface 183 of the semiconductor wafer layer 182 and the inner wall (mainly the bottom wall) of the gate trench 65 .

Also, referring to FIG. 12E, semiconductor wafer layer 182 is rotated 90 degrees to impinge on second sidewall 63 of gate trench 65 so that n-type impurities are deposited on first major surface 183 of semiconductor wafer layer 182 and the gate trench. It is introduced into the inner wall of 65. Also, the semiconductor wafer layer 182 is rotated by 90° so that the n-type impurity is introduced into the first main surface 183 of the semiconductor wafer layer 182 and the inner wall (mainly the bottom wall) of the gate trench 65 . The order of introducing n-type impurities into the inner wall of gate trench 65 is arbitrary, and is not limited to the order shown in FIGS. 12D and 12E.

Next, referring to FIG. 12F, the n-type impurities introduced into semiconductor wafer layer 182 are diffused into drift region 54 . Diffusion of n-type impurities is performed by a drive-in process method. Thereby, a high-concentration drift region 91 is formed in the drift region 54 . The sacrificial insulating layer 190 is then removed.

Next, referring to FIG. 12G, a base insulating layer 191 serving as the base of the bottom insulating layer 68 of the insulating layer 66 and the contact insulating layer 86 is formed. The insulating base layer 191 is formed in a film shape along the first main surface 183 of the semiconductor wafer layer 182 , the inner walls of the gate trenches 65 and the inner walls of the contact trenches 85 . Base insulating layer 191 may be formed by an oxidation treatment method (for example, a thermal oxidation treatment method) or a CVD method. The insulating base layer 191 is formed by a thermal oxidation treatment method in this embodiment.

The base insulating layer 191 defines a recessed space within the gate trench 65 . The base insulating layer 191 has a thickness TBA that exceeds the first thickness T1 of the bottom insulating layer 68 to be formed (TBA>T1). The thickness TBA of the base insulating layer 191 is set to a value obtained by adding a thickness TP1 of 100 Å to 1500 Å to the first thickness T1.

Similarly, base insulating layer 191 defines a recessed space within contact trench 85 . The base insulating layer 191 has a thickness TBA exceeding the fourth thickness T4 of the contact insulating layer 86 to be formed (TBA>T4). The thickness TBA of the insulating base layer 191 is set to a value obtained by adding a thickness TP1 of 100 Å to 1500 Å to the thickness T4.

The thickness TP1 may be 100 Å to 300 Å, 300 Å to 600 Å, 600 Å to 900 Å, 900 Å to 1200 Å, or 1200 Å to 1500 Å.

Next, referring to FIG. 12H, base insulating layer 191 is thinned. In this step, the insulating base layer 191 is thinned by removing the surface layer portion of the insulating base layer 191 by an etching method. The etching method may be a wet etching method. The base insulating layer 191 is removed by an amount corresponding to the added thickness TP1.

As a result, the inner wall of the recessed space partitioned by the base insulating layer 191 in the gate trench 65 is extended and smoothed at the same time. Also, the bottom wall of the recessed space is rounded in a U shape toward the bottom wall 64 of the gate trench 65 .

In the gate trench 65, the surface layer portion of the base insulating layer 191 is removed by etching so that the amount of removal of the bottom wall portion of the recessed space is larger than the amount of removal of the side wall portion of the recessed space. As a result, base insulating layer 191 including side wall covering portion 70 and bottom wall covering portion 71 (corner portion 71A and deepest portion 71B) is formed in gate trench 65 .

In addition, the inner wall of the recessed space partitioned by the base insulating layer 191 in the contact trench 85 is expanded and smoothed at the same time. Also, the bottom wall of the recessed space is rounded in a U shape toward the bottom wall 84 of the contact trench 85 .

In the contact trench 85, the surface layer portion of the base insulating layer 191 is removed by an etching method so that the amount of removal of the bottom wall portion of the recessed space is larger than the amount of removal of the side wall portion of the recessed space. As a result, base insulating layer 191 including side wall covering portion 70 and bottom wall covering portion 71 (corner portion 71A and deepest portion 71B) in contact trench 85 is formed.

Next, referring to FIG. 12I, a first base electrode layer 192 serving as the base of the bottom electrode 72 of the embedded electrode 67 and the contact electrode 87 is formed on the first main surface 183 of the semiconductor wafer layer 182. . The first base electrode layer 192 fills the gate trenches 65 and the contact trenches 85 and covers the first major surface 183 of the semiconductor wafer layer 182 . The first base electrode layer 192 comprises conductive polysilicon. The first base electrode layer 192 may be formed by CVD.

Next, referring to FIG. 12J, unnecessary portions of the first base electrode layer 192 are removed to form the bottom-side electrode 72 of the buried electrode 67 and the contact electrode 87 . In this step, after the contact electrode 87 is formed, the bottom electrode 72 of the embedded electrode 67 is formed.

In the step of forming the contact electrode 87, unnecessary portions of the first base electrode layer 192 may be removed by an etching method (etchback method). The etching method may be a wet etching method. The first base electrode layer 192 is removed until the base insulating layer 191 is exposed. Thereby, a contact electrode 87 embedded in the contact trench 85 is formed.

A mask (not shown) having a predetermined pattern is then formed on the first major surface 183 of the semiconductor wafer layer 182 . A mask (not shown) covers the contact electrode 87 and has openings selectively exposing the first base electrode layer 192 .

Next, the first base electrode layer 192 in the gate trench 65 is removed by an etching method through a mask (not shown). The first base electrode layer 192 is removed up to the middle portion of the gate trench 65 in the depth direction. Thereby, the bottom electrode 72 is formed.

The first end portion 72A of the bottom electrode 72 is located in the middle of the gate trench 65 in the depth direction. The second end portion 72B of the bottom electrode 72 is formed in a smooth convex curve toward the bottom wall 64 of the gate trench 65 following the bottom wall (etching surface) of the U-shaped space partitioned by the base insulating layer 191. be done. With such a structure, local electric field concentration on the bottom electrode 72 can be suppressed, so that a decrease in breakdown voltage can be suppressed.

Next, referring to FIG. 12K, unnecessary portions of base insulating layer 191 are removed. In this process, a mask (not shown) having a predetermined pattern is first formed on the first main surface 183 of the semiconductor wafer layer 182 . A mask (not shown) covers the contact trenches 85 and has openings that selectively expose the gate trenches 65 .

Next, unnecessary portions of the base insulating layer 191 are removed by an etching method (etchback method) through a mask (not shown). The etching method may be a wet etching method. The base insulating layer 191 is removed within the gate trench 65 until the first end 72A of the bottom electrode 72 is exposed. A bottom insulating layer 68 is thereby formed in the gate trench 65 .

Next, referring to FIG. 12L, opening side insulating layer 69 , intermediate insulating layer 74 and main surface insulating layer 121 are formed on first main surface 183 of semiconductor wafer layer 182 . Opening-side insulating layer 69, intermediate insulating layer 74 and main surface insulating layer 121 may be formed by an oxidation treatment method (for example, thermal oxidation treatment method) or a CVD method. The opening-side insulating layer 69, the intermediate insulating layer 74, and the main-surface insulating layer 121 are formed by a thermal oxidation treatment method in this embodiment.

Next, referring to FIG. 12M, a second base electrode layer 193 serving as the base of the opening side electrode 73 of the embedded electrode 67 is formed on the first main surface 183 of the semiconductor wafer layer 182 . A second base electrode layer 193 fills the gate trench 65 and covers the first major surface 183 of the semiconductor wafer layer 182 . The second base electrode layer 193 includes conductive polysilicon. The second base electrode layer 193 may be formed by CVD.

Next, referring to FIG. 12N, unnecessary portions of the second base electrode layer 193 are removed to form the opening side electrode 73 of the buried electrode 67. Next, referring to FIG. The second base electrode layer 193 may be removed by an etching method (etchback method). The etching method may be a wet etching method. The second base electrode layer 193 is removed until the main surface insulating layer 121 is exposed. Thereby, the opening side electrode 73 of the embedded electrode 67 is formed in the gate trench 65 .

Next, referring to FIG. 12O, cap insulating layer 75 covering the exposed portion of opening side electrode 73 and cap insulating layer 88 covering the exposed portion of contact electrode 87 are formed. Cap insulating layer 75 and cap insulating layer 88 may be formed by an oxidation treatment method (for example, thermal oxidation treatment method).

Next, referring to FIG. 12P, body region 55 is formed in the surface layer portion of first main surface 183 of semiconductor wafer layer 182 . Body region 55 is formed by introducing p-type impurities into first main surface 183 of semiconductor wafer layer 182 by ion implantation through an ion implantation mask (not shown).

Next, referring to FIG. 12Q, source region 101 is formed in the surface layer portion of body region 55 . Source region 101 is formed by introducing n-type impurities into first major surface 183 of semiconductor wafer layer 182 by ion implantation through an ion implantation mask (not shown).

Also, although not shown, a contact region 102 is formed in the surface layer of the body region 55 . Source region 101 is formed by introducing p-type impurities into first major surface 183 of semiconductor wafer layer 182 by ion implantation through an ion implantation mask (not shown).

Next, referring to FIG. 12R, interlayer insulating layer 122 is formed on first main surface 183 of semiconductor wafer layer 182 . The interlayer insulating layer 122 has a single-layer structure made of a USG layer in this embodiment. Interlayer insulating layer 122 may be formed by a CVD method. A planarization process may be performed on the main surface of interlayer insulating layer 122 . The planarization process of the interlayer insulating layer 122 may be performed by a CMP (Chemical Mechanical Polishing) method.

Next, referring to FIG. 12S, a mask 194 having a predetermined pattern is formed on the main surface of interlayer insulating layer 122. Referring to FIG. The mask 194 has a plurality of openings 195 that expose regions where the plurality of first plug electrodes 123, the plurality of second plug electrodes 124 and the plurality of third plug electrodes 125 are to be embedded.

Unnecessary portions of the interlayer insulating layer 122 are then removed by an etching method through the mask 194 . A plurality of contact holes 196 are thus formed in the interlayer insulating layer 122 . Mask 194 is then removed.

Next, referring to FIG. 12T, a base plug electrode layer 197 serving as the bases of the plurality of first plug electrodes 123, the plurality of second plug electrodes 124 and the plurality of third plug electrodes 125 is the main layer of interlayer insulating layer 122. formed on the surface. Base plug electrode layer 197 contains tungsten. Base plug electrode layer 197 fills contact holes 196 and covers the main surface of interlayer insulating layer 122 .

Next, referring to FIG. 12U, unnecessary portions of base plug electrode layer 197 are removed. Unnecessary portions of base plug electrode layer 197 are removed until the main surface of interlayer insulating layer 122 is exposed. Unnecessary portions of the base plug electrode layer 197 may be removed by etching or CMP. Thus, a plurality of first plug electrodes 123, a plurality of second plug electrodes 124 and a plurality of third plug electrodes 125 are formed.

Next, referring to FIG. 12V, on interlayer insulating layer 122, reference potential electrode 14 and gate control line 17 are formed. The reference potential electrode 14 and the gate control wiring 17 may be formed by sputtering and/or plating. Also, the output electrode 12 is formed on the second major surface 184 of the semiconductor wafer layer 182 . The output electrode 12 may be formed by sputtering and/or plating.

After that, the semiconductor wafer layer 182 is selectively cut to cut out the semiconductor device 1 . The semiconductor device 1 is manufactured through the steps including the above.

As described above, according to the semiconductor device 1 , the region serving as the main current path in the drift region 54 is highly doped by the high-concentration drift region 91 . As a result, it is possible to avoid increasing the concentration of the entire drift region 54, thereby suppressing a decrease in breakdown voltage while reducing the on-resistance.

In particular, according to the semiconductor device 1 , the high-concentration drift region 91 has a bottom located in a region on the first main surface 3 side of the semiconductor layer 2 with respect to the bottom of the drift region 54 . That is, the drift region 54 has a region that is not highly doped by the high concentration drift region 91 .

More specifically, the non-highly doped region in drift region 54 is interposed in the region between the bottom of high-concentration drift region 91 and semiconductor substrate 51 . That is, drift region 54 having a relatively low n-type impurity concentration is interposed in a region between high concentration drift region 91 having a relatively high n-type impurity concentration and semiconductor substrate 51 . A region of the drift region 54 that is not highly doped functions as a breakdown voltage holding region. As a result, it is possible to appropriately suppress a decrease in breakdown voltage.

When narrowing the pitch PC of the plurality of trench gate structures 61, there is concern that the on-resistance of the drift region 54 will increase due to the reduction of the current path. However, since the current path can be secured by the high-concentration drift region 91, an increase in on-resistance can be suppressed.

Accordingly, it is possible to appropriately reduce the channel resistance while suppressing an increase in on-resistance and a decrease in breakdown voltage. According to the semiconductor device 1, for example, the pitch PC of the plurality of trench gate structures 61 can be set to 1 μm or more and 3 μm or less.

Further, according to the semiconductor device 1, the plurality of trench gate structures 61 include first trench gate structures 61A and second trench gate structures 61B spaced apart from each other. A first depletion layer extends into the drift region 54 from the outer wall of the first trench gate structure 61A. A second depletion layer extends into the drift region 54 from the outer wall of the second trench gate structure 61B. A plurality of trench gate structures 61 are arranged such that the first depletion layer overlaps the second depletion layer. As a result, it is possible to appropriately suppress a decrease in breakdown voltage.

FIG. 13A is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which a high-concentration drift region 91 according to the second form example is formed. In the following, structures corresponding to the structures described for the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The high-concentration drift region 91 according to the first embodiment described above includes a bottom portion (bottom wall covering portion 93 ) having a thickness TDB equal to or greater than the pitch PS between sidewalls of the trench gate structure 61 (PS≦TDB). On the other hand, the thickness TDB of the bottom portion (bottom wall covering portion 93) of the high-concentration drift region 91 according to the second embodiment is less than the pitch PS between sidewalls of the trench gate structure 61 (PS>TDB).

The high-concentration drift region 91 according to the second embodiment is formed by adjusting conditions for introducing n-type impurities in the step of forming the high-concentration drift region 91 (see FIGS. 12D to 12E). Even in the case where the high-concentration drift region 91 according to the second embodiment is formed, the same effects as those obtained when the high-concentration drift region 91 according to the first embodiment is formed can be obtained.

FIG. 13B is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which a high-concentration drift region 91 according to the third embodiment is formed. In the following, structures corresponding to the structures described for the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The high-concentration drift region 91 according to the first embodiment described above is formed in a region along the first side wall 62 , the second side wall 63 and the bottom wall 64 of the trench gate structure 61 . On the other hand, the high-concentration drift region 91 according to the third embodiment covers the first sidewall 62 and the second sidewall 63 of the trench gate structure 61 and exposes the bottom wall 64 of the trench gate structure 61 . That is, the high-concentration drift region 91 according to the third embodiment does not have the bottom wall covering portion 93 .

The high-concentration drift region 91 according to the third embodiment is formed by adjusting conditions for introducing n-type impurities in the step of forming the high-concentration drift region 91 (see FIGS. 12D to 12E). Even in the case where the high-concentration drift region 91 according to the third embodiment is formed, the same effects as those obtained when the high-concentration drift region 91 according to the first embodiment is formed can be obtained.

FIG. 13C is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which the high-concentration drift region 91 according to the fourth embodiment is formed. In the following, structures corresponding to the structures described for the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

A plurality of high-concentration drift regions 91 according to the first embodiment described above are connected to each other in regions between trench gate structures 61 adjacent to each other. On the other hand, the plurality of high-concentration drift regions 91 according to the fourth embodiment are formed spaced apart from each other in the region between the trench gate structures 61 adjacent to each other. That is, the plurality of high-concentration drift regions 91 according to the fourth embodiment are independently formed in a one-to-one correspondence with the corresponding trench gate structures 61 .

The high-concentration drift region 91 according to the fourth embodiment is formed by adjusting conditions for introducing n-type impurities in the step of forming the high-concentration drift region 91 (see FIGS. 12D to 12E). Even in the case where the high-concentration drift region 91 according to the fourth embodiment is formed, the same effects as those obtained when the high-concentration drift region 91 according to the first embodiment is formed can be obtained.

FIG. 13D is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which the high-concentration drift region 91 according to the fifth embodiment is formed. In the following, structures corresponding to the structures described for the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

A plurality of high-concentration drift regions 91 according to the first embodiment described above are connected to each other in regions between trench gate structures 61 adjacent to each other. On the other hand, the plurality of high-concentration drift regions 91 according to the fifth embodiment are formed spaced apart from each other in the region between the trench gate structures 61 adjacent to each other. That is, the plurality of high-concentration drift regions 91 according to the fifth embodiment are independently formed in a one-to-one correspondence with the corresponding trench gate structures 61 .

Further, the plurality of high-concentration drift regions 91 according to the fifth embodiment cover the first sidewalls 62 and the second sidewalls 63 of the corresponding trench gate structures 61, exposing the bottom walls 64 of the trench gate structures 61. . That is, the plurality of high-concentration drift regions 91 according to the fifth embodiment do not have the bottom wall covering portion 93 .

The high-concentration drift region 91 according to the fifth embodiment is formed by adjusting conditions for introducing n-type impurities in the step of forming the high-concentration drift region 91 (see FIGS. 12D to 12E). Even in the case where the high-concentration drift region 91 according to the fifth embodiment is formed, the same effects as those obtained when the high-concentration drift region 91 according to the first embodiment is formed can be obtained.

FIG. 13E is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which the high-concentration drift region 91 according to the sixth embodiment is formed. In the following, structures corresponding to the structures described for the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The high-concentration drift region 91 according to the first embodiment described above is formed in a region along the first side wall 62 , the second side wall 63 and the bottom wall 64 of the trench gate structure 61 . On the other hand, the high-concentration drift region 91 according to the sixth embodiment exposes the first sidewall 62 and the second sidewall 63 of the trench gate structure 61 and covers the bottom wall 64 of the trench gate structure 61 . That is, the high-concentration drift region 91 according to the sixth embodiment does not have the sidewall covering portion 92 .

The high-concentration drift region 91 according to the sixth embodiment is formed by adjusting conditions for introducing n-type impurities in the step of forming the high-concentration drift region 91 (see FIGS. 12D to 12E). Even in the case where the high-concentration drift region 91 according to the sixth embodiment is formed, the same effects as those obtained when the high-concentration drift region 91 according to the first embodiment is formed can be obtained.

FIG. 13F is a cross-sectional view of a region corresponding to FIG. 7, and is a cross-sectional view showing a form in which the high-concentration drift region 91 according to the seventh embodiment is formed. In the following, structures corresponding to the structures described for the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The high-concentration drift region 91 according to the first embodiment described above is formed in a region along the first side wall 62 , the second side wall 63 and the bottom wall 64 of the trench gate structure 61 . On the other hand, the high-concentration drift region 91 according to the seventh embodiment exposes the first sidewall 62 and the second sidewall 63 of the trench gate structure 61 and covers the bottom wall 64 of the trench gate structure 61 . That is, the high-concentration drift region 91 according to the seventh embodiment does not have the sidewall covering portion 92 .

Furthermore, the plurality of high-concentration drift regions 91 according to the seventh embodiment are formed spaced apart from each other in regions between the trench gate structures 61 adjacent to each other. That is, the plurality of high-concentration drift regions 91 according to the seventh embodiment are independently formed in a one-to-one correspondence with the bottom walls 64 of the corresponding trench gate structures 61 .

The high-concentration drift region 91 according to the seventh embodiment is formed by adjusting the n-type impurity introduction conditions in the step of forming the high-concentration drift region 91 (see FIGS. 12D to 12E). Even when the high-concentration drift region 91 according to the seventh embodiment is formed, it is possible to obtain the same effects as those obtained when the high-concentration drift region 91 according to the first embodiment is formed.

FIG. 13G is a cross-sectional perspective view of a region corresponding to FIG. 5, and is a cross-sectional perspective view showing a form in which the high-concentration drift region 91 according to the eighth embodiment is formed. In the following, structures corresponding to the structures described for the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

The high-concentration drift region 91 according to the first embodiment described above is formed in a region along the first side wall 62 , the second side wall 63 and the bottom wall 64 of the trench gate structure 61 . On the other hand, the high-concentration drift region 91 according to the eighth embodiment is also formed in regions along the outer surfaces of the plurality of trench contact structures 81 in the drift region 54 .

High-concentration drift region 91 includes sidewall covering portion 92 covering first sidewall 82 and second sidewall 83 of trench contact structure 81 and bottom wall covering portion 93 covering bottom wall 84 on trench contact structure 81 side. include. Sidewall covering portion 92 covering second sidewall 83 of trench contact structure 81 may be exposed from first main surface 3 of semiconductor layer 2 .

High concentration drift region 91 covering trench contact structure 81 is integrated with high concentration drift region 91 covering trench gate structure 61 . As a result, one high-concentration drift region 91 collectively covering the plurality of trench gate structures 61 and the plurality of trench contact structures 81 is formed in the surface layer portion of the drift region 54 .

In addition, since the formation mode of the high-concentration drift region 91 for the trench contact structure 81 is the same as the formation mode for the high-concentration drift region 91 for the trench gate structure 61, a detailed description thereof will be omitted.

First form example, second form example, third form example, fourth form example, fifth form example, sixth form example, seventh form example and eighth form example (hereinafter simply referred to as "first to eighth forms The semiconductor device 1 may simultaneously include at least two of the high-concentration drift regions 91 according to the example.

Further, the features of the high-concentration drift regions 91 according to the first to eighth embodiment examples can be combined in any manner and form among them. That is, the high-concentration drift region 91 having a form in which at least two of the features of the high-concentration drift regions 91 according to the first to eighth embodiments are combined may be employed.

FIG. 14 is a cross-sectional view of a region corresponding to FIG. 7, showing a semiconductor device 201 according to the second embodiment of the present invention. In the following, structures corresponding to the structures described for the semiconductor device 1 are denoted by the same reference numerals, and descriptions thereof are omitted.

Each trench gate structure 61 of the semiconductor device 1 according to the first embodiment includes a buried electrode 67 having an isolation electrode structure including a bottom electrode 72 , an opening electrode 73 and an intermediate insulating layer 74 . In contrast, each trench gate structure 61 of the semiconductor device 201 according to the second embodiment includes an embedded electrode 67 integrally embedded in the gate trench 65 with an insulating layer 66 interposed therebetween.

Each trench gate structure 61 penetrates body region 55 and reaches drift region 54 . The depth DT of each trench gate structure 61 may be 1 μm or more and 5 μm or less. The depth DT may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less.

A bottom wall 64 of each trench gate structure 61 is formed in a region on the first main surface 3 side of the semiconductor layer 2 with an interval IT of 1 μm or more and 15 μm or less from the bottom of the drift region 54 . The interval IT may be 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, or 10 μm or more and 15 μm or less.

The insulating layer 66 defines a recessed space within the gate trench 65 . A portion of the insulating layer 66 covering the bottom wall 64 of the gate trench 65 is formed along the bottom wall 64 of the gate trench 65 . Thus, the insulating layer 66 defines a U-shaped space recessed in a U-shape at the bottom wall 64 of the gate trench 65 .

The insulating layer 66 more specifically includes a side wall covering portion 70 and a bottom wall covering portion 71 . The sidewall covering portion 70 covers the first sidewall 62 and the second sidewall 63 of the gate trench 65 to form the sidewall of the U-shaped space. The bottom wall covering portion 71 covers the bottom wall 64 of the gate trench 65 and forms the bottom wall of the U-shaped space. The thickness TB of the bottom wall covering portion 71 is less than the thickness TS of the side wall covering portion 70 (TB<TS).

A ratio TB/TS of thickness TB of bottom wall covering portion 71 to thickness TS of side wall covering portion 70 may be 0.5 or more and 0.8 or less. The ratio TB/TS is 0.5 or more and 0.55 or less, 0.55 or more and 0.6 or less, 0.6 or more and 0.65 or less, 0.65 or more and 0.7 or less, 0.7 or more and 0.75 or less. , or 0.75 or more and 0.8 or less. The ratio TB/TS is preferably 0.65 or more and 0.75 or less.

The bottom wall covering portion 71 includes a corner portion 71A and a deepest portion 71B. The corner portion 71</b>A defines a boundary portion with the side wall covering portion 70 . The deepest part 71B defines the bottom of the U-shaped space. The deepest portion 71B may have a thickness TD (TD≠TC) different from the thickness TC of the corner portion 71A. The thickness TD of the deepest portion 71B may exceed the thickness TC of the corner portion 71A (TD>TC).

A difference TD-TC between the thickness TD and the thickness TC may be 10 Å or more and 200 Å or less. The difference TD-TC may be 10 Å to 50 Å, 50 Å to 100 Å, 100 Å to 150 Å, or 150 Å to 200 Å. The difference TD-TC is preferably 10 Å or more and 80 Å or less.

The U-shaped space defined by the insulating layer 66 is formed by removing the surface portion of the insulating layer 66 by etching during the manufacturing process (see the process of FIG. 12H). The etching method may be a wet etching method. In other words, the insulating layer 66 has a smooth inner wall surface defining a U-shaped space within the gate trench 65 . The inner wall surface of the insulating layer 66 is an etched surface formed by an etching method.

A predetermined gate control signal including a gate voltage is applied to the buried electrode 67 through the gate control wiring 17 . The embedded electrode 67 has one end exposed from the opening of the gate trench 65 and the other end located on the bottom wall 64 side of the gate trench 65 .

The other end of the embedded electrode 67 is formed in a convex curve toward the bottom wall 64 of the gate trench 65 . More specifically, the other end of the embedded electrode 67 is formed along the bottom wall (etching surface) of the U-shaped space partitioned by the insulating layer 66 and smoothly extends toward the bottom wall 64 of the gate trench 65 . It is formed in a convex curved shape. As a result, local electric field concentration on the embedded electrode 67 can be suppressed, so that a decrease in breakdown voltage can be suppressed.

Although illustration is omitted, the trench contact structure 81 is formed in the same manner as the trench gate structure 61 . That is, the trench contact structure 81 includes a contact electrode 87 embedded as an integral body in the contact trench 85 with the contact insulating layer 86 interposed therebetween. The structures of the contact insulating layer 86 and the contact electrode 87 are the same as the structures of the insulating layer 66 and the embedded electrode 67, and therefore detailed description thereof will be omitted.

Each high-concentration drift region 91 is formed along the outer wall of each trench gate structure 61 in the same manner as in the first embodiment. In this embodiment, the bottom of each high-concentration drift region 91 is formed in a region on the first main surface 3 side of the semiconductor layer 2 with an interval ID of 1 μm or more and 10 μm or less from the bottom of the drift region 54 . The spacing ID may be between 1 μm and 5 μm, between 5 μm and 10 μm, or between 10 μm and 15 μm.

In this form, the high-concentration drift region 91 according to the first form example is applied. However, the high-concentration drift regions 91 according to the second to eighth embodiments may be employed instead of or in addition to the high-concentration drift regions 91 according to the first embodiment. Moreover, the high-concentration drift region 91 having a form in which at least two of the features of the high-concentration drift regions 91 according to the first to eighth embodiments are combined may be employed.

As described above, the semiconductor device 201 according to the second embodiment can also achieve the same effects as those described for the semiconductor device 1 according to the first embodiment.

While embodiments of the invention have been described, the invention may also be embodied in other forms.

In the first embodiment described above, an example was shown in which the width WT of the trench gate structure 61 is 0.5 μm or more and 2 μm or less, and the first thickness T1 of the bottom-side insulating layer 68 is 1500 Å or more and 4000 Å or less. However, the width WT may be 2 μm or more and 5 μm or less. The width WT is 2.0 μm or more and 2.5 μm or less, 2.5 μm or more and 3.0 μm or less, 3.0 μm or more and 3.5 μm or less, 3.5 μm or more and 4.0 μm or less, 4.0 μm or more and 4.5 μm or less, or , 4.5 μm or more and 5.0 μm or less.

Also, the first thickness T1 of the bottom insulating layer 68 may be between 4000 Å and 12000 Å. The first thickness T1 is 4000 Å to 5000 Å, 5000 Å to 6000 Å, 6000 Å to 7000 Å, 7000 Å to 8000 Å, 8000 Å to 9000 Å, 9000 Å to 10000 Å, 10000 Å to 11000 Å, or 11000 Å to 12000 Å. may In such a structure, the breakdown voltage of the semiconductor device 1 can be further increased by thickening the bottom-side insulating layer 68 .

In each of the above-described embodiments, the semiconductor device 1, 201 including the IPD (Intelligent Power Device) having the power MISFET 9 and the control IC 10 has been described. However, semiconductor devices 1 and 201 having only power MISFET 9 may be employed.

In this case, an electric circuit including a semiconductor device 1, 201 having only the power MISFET 9 and a control circuit electrically connected to the semiconductor device 1, 201 for controlling the power MISFET 9 may be employed. A circuit module may be provided in which such an electric circuit is mounted on a circuit board.

The control circuit may have one or more functional circuits corresponding to one or more of the plurality of functional circuits related to the control IC 10 (see also FIG. 2). That is, the control circuit includes the sensor MISFET 21, the input circuit 22, the voltage control circuit 23, the protection circuit 24, the gate control circuit 25, the active clamp circuit 26, the current detection circuit 27, the power supply reverse connection protection circuit 28, or the abnormality detection circuit 29. may include at least one of

In each of the above embodiments, the p-type semiconductor portion may be the n-type semiconductor portion, and the n-type semiconductor portion may be the p-type semiconductor portion. In this case, in the description of each of the above embodiments, “n type” and “n ⁺ type” are read as “p type” and “p ⁺ type” respectively, and “p type” and “p ⁺ type” are read as “n type”. type” and “n ⁺ type” respectively.

The semiconductor devices 1 and 201 according to each of the above embodiments may be incorporated into a semiconductor package as shown in FIGS. 15 and 16. FIG. FIG. 15 is a perspective view showing a semiconductor package 211 incorporating the semiconductor device 1 shown in FIG. 1 through a sealing resin 216. FIG. 16 is a plan view of FIG. 15. FIG.

Here, a mode example in which the semiconductor package 211 includes the semiconductor device 1 according to the first embodiment will be described. 201 may be included.

15 and 16, semiconductor package 211 in this form is a so-called SOP (Small Outline Package). A semiconductor package 211 includes a semiconductor device 1, a die pad 212, a conductive bonding material 213, a plurality of (eight in this embodiment) lead electrodes 214A to 214H, a plurality of (eight in this embodiment) conducting wires 215A to 215H, and a sealing resin. 216. The number of lead electrodes and the number of conductive wires are selected according to the function of semiconductor device 1, and are not limited to the numbers shown in FIGS.

The die pad 212 is made of a rectangular parallelepiped metal plate. Die pad 212 may comprise iron, aluminum or copper. The die pad 212 supports the semiconductor device 1 from the second main surface 4 side. The die pad 212 is connected to the power electrode 11 of the semiconductor device 1 via a conductive bonding material 213 . The conductive bonding material 213 may be metal paste or solder.

The plurality of lead electrodes 214A to 214H are a first lead electrode 214A, a second lead electrode 214B, a third lead electrode 214C, a fourth lead electrode 214D, a fifth lead electrode 214E, a sixth lead electrode 214F, and a seventh lead electrode 214G. and an eighth lead electrode 214H.

The plurality of lead electrodes 214A-214H may comprise iron, aluminum or copper. A plurality of lead electrodes 214A-214H are arranged around the die pad 212 at intervals therefrom.

More specifically, the four lead electrodes 214A-214D are arranged along one side of the die pad 212 at intervals. The remaining four lead electrodes 214E to 214H are arranged at intervals along the side of the die pad 212 opposite to the side on which the lead electrodes 214A to 214D are arranged.

A plurality of lead electrodes 214A to 214H are each formed in a strip shape extending along a direction orthogonal to the arrangement direction. The plurality of lead electrodes 214A-214H have one end facing the die pad 212 and the other end on the opposite side. One ends of the plurality of lead electrodes 214A to 214H are internally connected to the semiconductor device 1. FIG. The other ends of the plurality of lead electrodes 214A to 214H are externally connected to a connection target such as a wiring board.

The plurality of conductors 215A-215H includes a first conductor 215A, a second conductor 215B, a third conductor 215C, a fourth conductor 215D, a fifth conductor 215E, a sixth conductor 215F, a seventh conductor 215G and an eighth conductor 215H.

The first conducting wire 215A is electrically connected to one end of the first lead electrode 214A and the output electrode 12 . 215 A of 1st conductors consist of a metal clip in this form. The first conductor 215A may contain gold, aluminum or copper. The first conducting wire 215A efficiently dissipates heat generated in the power MISFET to the outside. Of course, the first conducting wire 215A may be made of a bonding wire.

The second conducting wire 215B is electrically connected to one end of the second lead electrode 214B and the reference potential electrode 14 . The third conducting wire 215C is electrically connected to one end of the third lead electrode 214C and the ENABLE electrode 15 . The fourth conducting wire 215D is electrically connected to one end of the fourth lead electrode 214D and the SENSE electrode 16. As shown in FIG.

The fifth conductor 215E is electrically connected to one end of the fifth lead electrode 214E and the die pad 212. As shown in FIG. The sixth conductor 215F is electrically connected to one end of the sixth lead electrode 214F and the die pad 212 . The seventh conducting wire 215G is electrically connected to one end of the seventh lead electrode 214G and the input electrode 13 . The eighth conductor 215H is electrically connected to one end of the eighth lead electrode 214H and the die pad 212 .

The second through eighth conductors 215B through 215H are made of bonding wires in this embodiment. The second through eighth conductors 215B-215H may each comprise gold, aluminum or copper. The connection form of the plurality of conductors 215A-215H to the semiconductor device 1 and the plurality of lead electrodes 214A-214H is arbitrary, and is not limited to the connection form shown in FIGS.

The sealing resin 216 seals the semiconductor device 1, the die pad 212, one end of the plurality of lead electrodes 214A to 214H, and the plurality of conducting wires 215A to 215H so that the other ends of the plurality of lead electrodes 214A to 214H are exposed. are doing. The sealing resin 216 is formed in a rectangular parallelepiped shape. The sealing resin 216 may contain an epoxy resin.

The form of the semiconductor package 211 is not limited to SOP. As the semiconductor package 211, TO (Transistor Outline), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package) or various forms similar thereto may be applied.

In addition, various design changes can be made within the scope of the matters described in the claims.

Examples of features extracted from this specification and drawings are given below.

[Claim 1] A semiconductor layer having a first main surface on one side and a second main surface on the other side, and a side wall and a bottom wall, wherein the semiconductor layer has a side wall and a bottom wall. a trench tapered toward a second main surface; a sidewall covering portion having a first thickness and formed in a film shape following the sidewall of the trench; an insulating layer having a second thickness and including a bottom wall covering portion formed in a film shape following the bottom wall of the trench, defining a recessed space within the trench; and the insulating layer within the trench. and an electrode embedded in the recessed space defined by a layer.

When a film-like insulating layer is formed on the inner wall of a trench that is tapered from the first main surface to the second main surface of the semiconductor layer, the opening width of the trench is tapered toward the bottom wall of the trench. A concave space in the shape is defined by an insulating layer.

In this case, the electrode buried in the trench is also tapered along the inner wall of the recessed space. If a tapered electrode is formed, the electric field will be locally concentrated at the bottom wall of the trench. As a result, the breakdown voltage is lowered due to electric field concentration.

Therefore, in this semiconductor device, an insulating layer having a bottom wall covering portion having a second thickness less than the first thickness of the side wall covering portion is formed on the inner wall of the tapered trench. According to this semiconductor device, since the bottom wall covering portion has the second thickness that is less than the first thickness, the recessed space defined by the insulating layer is prevented from becoming tapered.

As a result, the electrode embedded in the recessed space is also prevented from becoming tapered, so that electric field concentration at the bottom wall of the trench can be suppressed. As a result, a decrease in breakdown voltage can be suppressed.

[Section 2] The semiconductor device according to Section 1, wherein the trench has the convexly curved bottom wall facing the second main surface.

[Item 3] The semiconductor device according to item 1, wherein the trench is formed in a tapered shape in which an opening width narrows from the first main surface toward the second main surface in cross-sectional view.

[Item 4] The trench has the bottom wall that is convexly curved toward the second main surface, and has a tapered shape with an opening width narrowing from the first main surface toward the second main surface in a cross-sectional view. Item 1. The semiconductor device according to item 1, wherein:

[Item 5] The semiconductor device according to item 3 or 4, wherein the sidewall of the trench forms a taper angle with the first main surface in the semiconductor layer that exceeds 90 degrees and is 95 degrees or less.

[Item 6] Items 1 to 5, wherein the bottom wall covering portion has a ratio of the second thickness to the first thickness of the side wall covering portion of 0.5 or more and 0.8 or less. The semiconductor device according to any one of 1.

[Item 7] The semiconductor device according to any one of Items 1 to 6, wherein the electrode is in contact with the bottom wall covering portion and includes an end portion formed in a convex curve toward the bottom wall of the trench. .

[Item 8] The electrodes include: a bottom-side electrode embedded on the bottom wall side of the trench with the insulating layer interposed therebetween; an opening-side electrode embedded on the opening side of the trench with the insulating layer interposed therebetween; 7. The semiconductor device according to any one of Items 1 to 6, having an insulation separation type electrode structure including an intermediate insulating layer interposed between the bottom electrode and the opening side electrode.

[Item 9] The semiconductor device according to Item 8, wherein the bottom-side electrode includes an end portion that is in contact with the bottom wall covering portion and is formed in a convex curve toward the bottom wall of the trench.

[Item 10] The insulating layer is formed on the inner wall of the trench on the bottom wall side, and is formed on the bottom insulating layer having the sidewall covering portion and the bottom wall covering portion, and on the inner wall of the trench on the opening side. and an opening-side insulating layer having a thickness less than the thickness of the bottom-side insulating layer, the bottom-side electrode being buried on the bottom wall side of the trench with the bottom-side insulating layer interposed therebetween, and forming the opening. Item 10. The semiconductor device according to Item 8 or 9, wherein a side electrode is embedded in the opening side of the trench with the opening side insulating layer interposed therebetween.

[Item 11] A semiconductor layer having a first main surface on one side and a second main surface on the other side, and a first side wall and a first bottom wall formed on the first main surface of the semiconductor layer The semiconductor layer has a gate trench, a second side wall and a second bottom wall, and is tapered from the first main surface to the second main surface in the first main surface of the semiconductor layer so as to communicate with the gate trench. a formed contact trench, a sidewall covering portion having a first thickness and formed in a film shape following the second sidewall of the contact trench, and a second thickness less than the first thickness. a contact insulating layer including a bottom wall covering portion formed in a film shape following the second bottom wall of the contact trench and partitioning a recessed space in the contact trench; and a contact electrode embedded in the recessed space partitioned by a contact insulating layer.

When a film-like contact insulating layer is formed on the inner wall of the contact trench tapered from the first main surface to the second main surface of the semiconductor layer, the contact insulating layer is formed in the contact trench toward the second bottom wall of the contact trench. The contact insulating layer defines a tapered recessed space whose opening width is narrowed by the contact insulating layer. In this case, the contact electrode buried in the contact trench is also tapered along the inner wall of the recessed space.

When a tapered contact electrode is formed, the electric field is locally concentrated on the bottom wall of the contact trench. As a result, the breakdown voltage is lowered due to electric field concentration.

Therefore, in this semiconductor device, a contact insulating layer having a bottom wall covering portion having a second thickness less than the first thickness of the side wall covering portion is formed on the inner wall of the tapered contact trench. According to this semiconductor device, since the bottom wall covering portion has the second thickness less than the first thickness, the recessed space defined by the contact insulating layer is prevented from becoming tapered.

As a result, the contact electrode buried in the recessed space is also prevented from becoming tapered, so that electric field concentration at the bottom wall of the contact trench can be suppressed. As a result, a decrease in breakdown voltage can be suppressed.

[Item 12] The semiconductor device according to Item 11, wherein the contact trench has the second bottom wall that is convexly curved toward the second main surface.

[Item 13] The semiconductor device according to Item 11, wherein the contact trench is formed in a tapered shape in which an opening width narrows from the first main surface toward the second main surface in cross-sectional view.

[Item 14] The contact trench has the second bottom wall that is convexly curved toward the second main surface, and the opening width narrows from the first main surface toward the second main surface in cross-sectional view. Item 12. The semiconductor device according to Item 11, which is tapered.

[Item 15] Item 13 or 14, wherein a taper angle between the second side wall of the contact trench and the first main surface in the semiconductor layer exceeds 90° and is 95° or less. semiconductor device.

[Item 16] In items 11 to 15, the bottom wall covering portion has the second thickness in which the ratio of the side wall covering portion to the first thickness is 0.5 or more and 0.8 or less. The semiconductor device according to any one of the items.

[Item 17] The contact electrode according to any one of items 11 to 16, wherein the contact electrode includes an end portion that is in contact with the bottom wall covering portion and is formed in a convex curve toward the second bottom wall of the contact trench. The semiconductor device described.

[Item 18] An insulating layer formed on an inner wall of the gate trench, a bottom electrode embedded on the first bottom wall side of the gate trench with the insulating layer interposed therebetween, and the gate trench with the insulating layer interposed therebetween. 18. Any one of items 11 to 17, further comprising an insulation separation type electrode structure including an opening side electrode embedded in the opening side of the and an intermediate insulating layer interposed between the bottom side electrode and the opening side electrode. 1. The semiconductor device according to claim 1.

[Item 19] The semiconductor device according to Item 18, wherein the contact electrode is electrically connected to the bottom electrode of the electrode structure.

[Item 20] The semiconductor device according to Item 19, wherein the contact electrode is connected to the bottom electrode of the electrode structure at a communicating portion between the gate trench and the contact trench.

[Item 21] A step of preparing a semiconductor layer having a first main surface on one side and a second main surface on the other side, and forming a trench having a side wall and a bottom wall in the first main surface of the semiconductor layer. forming an insulating layer along the side wall and the bottom wall of the trench and defining a recessed space in the trench; and exposing the insulating layer from the recessed space by an etching method. and an electrode embedding step of embedding an electrode in the recessed space defined by the insulating layer in the trench by removing a surface portion of the trench. manufacturing method.

According to this method of manufacturing a semiconductor device, it is possible to manufacture and provide a semiconductor device capable of suppressing electric field concentration on the bottom wall of the trench and improving the breakdown voltage.

[Item 22] The method of manufacturing a semiconductor device according to Item 21, wherein in the trench forming step, the trench is formed in a tapered shape from the first main surface of the semiconductor layer toward the second main surface.

[Item 23] The method of manufacturing a semiconductor device according to Item 22, wherein, in the trench forming step, the trench having a convexly curved bottom wall facing the second main surface is formed.

[Item 24] Manufacturing a semiconductor device according to Item 22, wherein in the trench forming step, the trench is formed in a tapered shape with an opening width narrowing from the first main surface toward the second main surface in cross-sectional view. Method.

[Item 25] In the trench forming step, the trench has a tapered shape having a convexly curved bottom wall directed toward the second main surface and having an opening width that narrows from the first main surface toward the second main surface in a cross-sectional view. Item 23. The method of manufacturing a semiconductor device according to Item 22, wherein the trench of is formed.

[Item 26] Manufacturing a semiconductor device according to Item 24 or 25, wherein the sidewall of the trench forms a taper angle with the first main surface in the semiconductor layer that exceeds 90° and is 95° or less. Method.

[Item 27] In the insulating layer forming step, the insulating layer has a film-like sidewall covering portion having a first thickness and conforming to the sidewall of the trench, and a second thickness less than the first thickness, 27. The method of manufacturing a semiconductor device according to any one of Items 21 to 26, wherein the insulating layer including a film-like bottom wall covering portion following the bottom wall of the trench is formed.

[Item 28] In the step of forming the insulating layer, the bottom wall covering portion having the second thickness in which the ratio of the side wall covering portion to the first thickness is 0.5 or more and 0.8 or less is formed. Item 28. The method for manufacturing a semiconductor device according to Item 27.

[Item 29] The semiconductor device according to any one of Items 21 to 28, wherein in the electrode embedding step, the electrode is formed to have an end portion formed in a convex curve toward the bottom wall of the trench. manufacturing method.

[Item 30] The method of manufacturing a semiconductor device according to any one of items 21 to 29, wherein in the insulating layer forming step, the insulating layer is formed by an oxidation treatment method.

[Item 31] The method of manufacturing a semiconductor device according to any one of Items 21 to 30, wherein the recessed space having a smooth inner wall is formed in the etching step.

[Item 32] The method of manufacturing a semiconductor device according to any one of items 21 to 31, wherein the etching method is a wet etching method.

1 semiconductor device 2 semiconductor layer 3 first main surface 51 semiconductor substrate 52 epitaxial layer 54 drift region 55 body region 61 trench gate structure 61A first trench gate structure 61B second trench gate structure 62 first sidewall 63 second sidewall 64 bottom wall 65 Gate trench 66 Insulating layer 67 Buried electrode 68 Bottom side insulating layer 69 Opening side insulating layer 70 Side wall covering portion 71 Bottom wall covering portion 72 Bottom side electrode 72A First end portion 72B Second end portion 73 Opening side electrode 74 Intermediate insulating layer 91 high-concentration drift region 92 sidewall covering portion 93 bottom wall covering portion 101 source region 201 semiconductor device

Claims (38)

a semiconductor layer having a main surface;
a drift region of a first conductivity type formed in a surface layer portion of the main surface;
A trench formed in the main surface and having sidewalls and a bottom wall in the drift region, an insulating layer formed on inner walls of the trench, and embedded in the trench with the insulating layer interposed therebetween, and a gate voltage is applied. a trench gate structure including embedded electrodes;
a first conductivity type high concentration drift region formed in the drift region along an outer wall of the trench gate structure and having a first conductivity type impurity concentration exceeding a first conductivity type impurity concentration of the drift region; ,
the drift region has a thickness of 5 μm or more and 20 μm or less;
The semiconductor device, wherein the high-concentration drift region is formed on the main surface side of the semiconductor layer at a distance of 0.1 μm or more and 3 μm or less from the bottom of the drift region. 2. The semiconductor device according to claim 1, wherein said high-concentration drift region has a sidewall covering portion covering said sidewall of said trench. 3. The semiconductor device according to claim 1, wherein said high-concentration drift region has a bottom wall covering portion covering said bottom wall of said trench. The high-concentration drift region is formed in a sidewall covering portion covering the sidewall of the trench and in a region along the bottom wall of the trench, and has a first conductivity type impurity concentration exceeding the first conductivity type impurity concentration of the sidewall covering portion. 4. The semiconductor device according to claim 1, comprising a bottom wall covering portion having a type impurity concentration. 5. The semiconductor device according to claim 1, wherein said high-concentration drift region has a bottom located in a region on said bottom wall side of said trench with respect to a bottom of said drift region. a plurality of said trench gate structures are formed at intervals on said main surface of said semiconductor layer;
6. The semiconductor device according to claim 1, wherein a plurality of said high-concentration drift regions are formed in a one-to-one correspondence with respect to said plurality of trench gate structures. 7. The semiconductor device according to claim 6, wherein said plurality of high-concentration drift regions are connected to each other in a region between said plurality of adjacent trench gate structures. The plurality of trench gate structures includes a first trench gate structure and a second trench gate structure adjacent to each other, and a first depletion layer extending from the first trench gate structure and a second depletion layer extending from the second trench gate structure. 8. The semiconductor device according to claim 6, wherein the semiconductor layer is formed on the main surface of the semiconductor layer with a space therebetween. 9. The first depletion layer of claim 8, wherein the first depletion layer overlaps the second depletion layer in a region on the bottom side of the drift region with respect to the bottom wall of the first trench gate structure and the bottom wall of the second trench gate structure. The semiconductor device described. 10. The semiconductor device according to claim 6, wherein a pitch between central portions of said plurality of trench gate structures is 1 μm or more and 3 μm or less. The embedded electrodes include a bottom-side electrode embedded on the bottom wall side of the trench with the insulating layer interposed therebetween, an opening-side electrode embedded on the opening side of the trench with the insulating layer interposed therebetween, and the bottom-side electrode. 11. The semiconductor device according to claim 1, having an insulation isolation type electrode structure including an intermediate insulating layer interposed between the electrode and said opening side electrode. A reference potential is applied to the bottom electrode during gate ON control,
12. The semiconductor device according to claim 11, wherein a gate voltage is applied to said opening-side electrode during gate ON control. A gate voltage is applied to the bottom electrode when the gate is turned on,
12. The semiconductor device according to claim 11, wherein a gate voltage is applied to said opening-side electrode during gate ON control. The bottom-side electrode has a first end portion located on the opening side of the trench and a second end portion located on the bottom wall side of the trench and formed in a convex curve toward the bottom wall of the trench. 14. The semiconductor device according to any one of claims 11 to 13, having edges. The insulating layer has a bottom-side insulating layer formed on the inner wall of the trench on the bottom wall side and an inner wall on the opening side of the trench and has a thickness less than the thickness of the bottom-side insulating layer. including an opening side insulating layer,
the bottom-side electrode is embedded on the bottom wall side of the trench with the bottom-side insulating layer interposed therebetween;
15. The semiconductor device according to claim 11, wherein said opening side electrode is embedded in said trench on the opening side with said opening side insulating layer interposed therebetween. The bottom-side insulating layer has a sidewall covering portion covering the sidewall of the trench and a bottom wall covering portion covering the bottom wall of the trench and having a thickness less than the thickness of the sidewall covering portion. 16. The semiconductor device according to claim 15, wherein: 17. The semiconductor device according to claim 16, wherein a ratio of the thickness of said bottom wall covering portion to the thickness of said side wall covering portion is 0.5 or more and 0.8 or less. 18. The semiconductor according to claim 15, wherein said bottom-side insulating layer defines a U-shaped space recessed toward said bottom wall of said trench in a cross-sectional view. Device. 19. The semiconductor device according to claim 1, wherein said trench is tapered from said main surface in the thickness direction. a body region of the second conductivity type formed on the side of the trench gate structure in the surface layer portion of the drift region;
20. The semiconductor device according to claim 1, further comprising a first conductivity type source region formed on a side of said trench gate structure in a surface layer portion of said body region. The semiconductor layer is stacked on a first conductivity type semiconductor substrate and the semiconductor substrate, has a first conductivity type impurity concentration lower than the first conductivity type impurity concentration of the semiconductor substrate, and forms the drift region. 21. The semiconductor device according to claim 1, having a laminated structure including an epitaxial layer of the first conductivity type. a semiconductor layer having a main surface;
a drift region of a first conductivity type formed in a surface layer portion of the main surface;
A trench formed in the main surface and having sidewalls and a bottom wall in the drift region, an insulating layer formed on inner walls of the trench, and embedded in the trench with the insulating layer interposed therebetween, and a gate voltage is applied. a trench gate structure including embedded electrodes;
a first conductivity type high concentration drift region formed in the drift region along an outer wall of the trench gate structure and having a first conductivity type impurity concentration exceeding a first conductivity type impurity concentration of the drift region; ,
The high concentration drift region has a sidewall covering portion covering the sidewall of the trench and a bottom wall covering portion covering the bottom wall of the trench, and the bottom wall covering portion is the high concentration drift region. forms the bottom of
In the bottom wall covering portion, a high-concentration region in which the first conductivity type impurity concentration is further increased is formed along the bottom wall of the trench gate structure,
the bottom surface of the bottom wall covering portion has unevenness corresponding to the high-concentration region,
the drift region has a thickness of 5 μm or more and 20 μm or less;
The semiconductor device, wherein the high-concentration drift region is formed on the main surface side of the semiconductor layer at a distance of 0.1 μm or more and 3 μm or less from the bottom of the drift region. a plurality of said trench gate structures are formed at intervals on said main surface of said semiconductor layer;
23. The semiconductor device according to claim 22, wherein a plurality of said high-concentration drift regions are formed in a one-to-one correspondence with respect to said plurality of trench gate structures. 24. The semiconductor device according to claim 23, wherein said plurality of high-concentration drift regions are continuous with each other in a region between said plurality of adjacent trench gate structures. The plurality of trench gate structures includes a first trench gate structure and a second trench gate structure adjacent to each other, and a first depletion layer extending from the first trench gate structure and a second depletion layer extending from the second trench gate structure. 25. The semiconductor device according to claim 23, which is formed on said main surface of said semiconductor layer with a space therebetween so as to overlap with said semiconductor layer. 26. The method of claim 25, wherein the first depletion layer overlaps the second depletion layer in a region on the bottom side of the drift region with respect to the bottom wall of the first trench gate structure and the bottom wall of the second trench gate structure. The semiconductor device described. 27. The semiconductor device according to claim 23, wherein a pitch between central portions of said plurality of trench gate structures is 1 μm or more and 3 μm or less. The embedded electrodes include a bottom-side electrode embedded on the bottom wall side of the trench with the insulating layer interposed therebetween, an opening-side electrode embedded on the opening side of the trench with the insulating layer interposed therebetween, and the bottom-side electrode. 28. The semiconductor device according to claim 22, having an insulation isolation type electrode structure including an intermediate insulating layer interposed between the electrode and said opening side electrode. A reference potential is applied to the bottom electrode during gate ON control,
29. The semiconductor device according to claim 28, wherein a gate voltage is applied to said opening side electrode during gate ON control. A gate voltage is applied to the bottom electrode when the gate is turned on,
29. The semiconductor device according to claim 28, wherein a gate voltage is applied to said opening side electrode during gate ON control. The bottom-side electrode has a first end portion located on the opening side of the trench and a second end portion located on the bottom wall side of the trench and formed in a convex curve toward the bottom wall of the trench. A semiconductor device according to any one of claims 28 to 30, having an edge. The insulating layer has a bottom-side insulating layer formed on the inner wall of the trench on the bottom wall side and an inner wall on the opening side of the trench and has a thickness less than the thickness of the bottom-side insulating layer. including an opening side insulating layer,
the bottom-side electrode is embedded on the bottom wall side of the trench with the bottom-side insulating layer interposed therebetween;
32. The semiconductor device according to claim 28, wherein said opening side electrode is embedded in said trench on the opening side thereof with said opening side insulating layer interposed therebetween. The bottom-side insulating layer has a sidewall covering portion covering the sidewall of the trench and a bottom wall covering portion covering the bottom wall of the trench and having a thickness less than the thickness of the sidewall covering portion. 33. The semiconductor device of claim 32, wherein: 34. The semiconductor device according to claim 33, wherein a ratio of the thickness of said bottom wall covering portion to the thickness of said side wall covering portion is 0.5 or more and 0.8 or less. 35. The semiconductor according to any one of claims 32 to 34, wherein said bottom-side insulating layer defines a U-shaped space recessed in a U-shape toward said bottom wall of said trench in a cross-sectional view. Device. 36. The semiconductor device according to claim 22, wherein said trench is tapered in the thickness direction from said main surface. a body region of the second conductivity type formed on the side of the trench gate structure in the surface layer portion of the drift region;
37. The semiconductor device according to any one of claims 22 to 36, further comprising a first conductivity type source region formed on a side of said trench gate structure in a surface layer portion of said body region. The semiconductor layer is stacked on a first conductivity type semiconductor substrate and the semiconductor substrate, has a first conductivity type impurity concentration lower than the first conductivity type impurity concentration of the semiconductor substrate, and forms the drift region. 38. The semiconductor device according to claim 22, having a laminated structure including an epitaxial layer of the first conductivity type.

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