JP2023086642A - Semiconductor light element - Google Patents

Abstract

To diffuse stress generated in a semiconductor multilayer.SOLUTION: An uppermost layer 24 contains Au. A lowermost layer 26 is formed of a material with an adhesion to a semiconductor multilayer 16 higher than that of Au. A multistep structure includes three or more sections S that overlap with an optical waveguide 18, are adjacent in a direction where the optical waveguide 18 extends, and have different thicknesses. An adjacent pair among the three or more sections S includes one with a small thickness that is close to an end surface of the semiconductor multilayer 16, and the other with a large thickness that is apart from the end surface of the semiconductor multilayer 16. The three or more sections S include a first section S1 with the minimum thickness including at least the lowermost layer 26, a second section S2 adjacent to the first section S1 including at least a stress relief layer 30 formed of a material with a Young's modulus less than or equal to that of Au in addition to the lowermost layer 26, and a third section S3 with the maximum thickness including all the layers from the uppermost layer 24 to the lowermost layer 26.SELECTED DRAWING: Figure 3

Description

The present disclosure relates to semiconductor optical devices.

A laminated structure of a plurality of metals is applied to the electrodes of semiconductor optical devices. For example, an electrode structure having a three-layer structure of a Ti layer, a Pt layer and an Au layer in order from the semiconductor multilayer is known (Patent Document 1). The bottom layer is intended to form an ohmic contact between the semiconductor multilayer and the electrode, the top layer is intended for electrical and thermal conduction with the outside and the mixing of the solder material and the electrode, and the intermediate layer is The purpose is to prevent mixing of solder materials and semiconductor multilayers.

JP-A-2003-258370

Since there is a difference in the coefficient of thermal expansion between the electrode and the semiconductor multilayer, stress is generated in the semiconductor multilayer, which may cause a decrease in reliability. As a countermeasure, Patent Document 1 discloses an electrode having a two-stage structure in which the uppermost layer (Au layer) is recessed. Due to the two-stage structure, the stress in the multiple semiconductor layers can be reduced at the element end face. However, the receding of the uppermost layer (Au layer) increases the stress inside the element end surface.

The present disclosure is directed to dispersing the stress that occurs in semiconductor multilayers.

A semiconductor optical device has a semiconductor multilayer configured to include an optical waveguide, and a multi-layered structure and a multi-staged electrode in contact with the top surface of the semiconductor multilayer, the top layer of the multilayer structure being made of Au. The bottom layer of the multi-layered structure is made of a material having higher adhesion to the multi-layered semiconductor than Au, and the multi-layered structure overlaps the optical waveguides and is adjacent to each other in the direction in which the optical waveguides extend. three or more sections having different thicknesses, wherein one adjacent pair of the three or more sections has a smaller thickness near the end face of the semiconductor multilayer and a thicker one away from the end face of the semiconductor multilayer. and the three or more sections are composed of a first section composed of at least the bottom layer and having the smallest thickness, and at least the bottom layer plus a material having a Young's modulus equal to or lower than Au. A second section adjacent to the first section, composed of a stress relief layer, and a third section of the maximum thickness, composed of all layers from the top layer to the bottom layer.

1 is a plan view of a semiconductor optical device according to a first embodiment; FIG. 2 is a cross-sectional view of the semiconductor optical device shown in FIG. 1 taken along the line II-II. FIG. It is an enlarged view of the multistage structure of an electrode. 5 is a cross-sectional view of an electrode according to Comparative Example 1. FIG. 6 is a cross-sectional view of an electrode according to Comparative Example 2; FIG. FIG. 10 is a cross-sectional view of an electrode according to Comparative Example 3; 4 is a cross-sectional view of an electrode according to Modification 1. FIG. FIG. 11 is a cross-sectional view of an electrode according to Modification 2; FIG. 10 is a cross-sectional view of an electrode according to Modification 3; FIG. 11 is a cross-sectional view of an electrode according to Modification 4; FIG. 5 is a plan view of a semiconductor optical device according to a second embodiment; 12 is a cross-sectional view of the semiconductor optical device shown in FIG. 11 taken along line XII-XII; FIG. 12 is a cross-sectional view of the semiconductor optical device shown in FIG. 11, taken along line XIII-XIII; FIG. 12 is a cross-sectional view of the semiconductor optical device shown in FIG. 11 taken along line XIV-XIV; FIG. FIG. 10 is a plan view of a semiconductor optical device according to a third embodiment; 16 is a cross-sectional view of the semiconductor optical device shown in FIG. 15, taken along line XVI-XVI; FIG. 16 is a cross-sectional view of the semiconductor optical device shown in FIG. 15, taken along line XVII-XVII; FIG.

Hereinafter, embodiments of the present invention will be described specifically and in detail with reference to the drawings. Members denoted by the same reference numerals in all drawings have the same or equivalent functions, and repeated description thereof will be omitted. Note that the size of the figure does not necessarily match the magnification.

[First Embodiment]
FIG. 1 is a plan view of the semiconductor optical device according to the first embodiment. FIG. 2 is a cross-sectional view of the semiconductor optical device shown in FIG. 1 taken along line II-II. Semiconductor optical devices have the function of guiding, emitting, absorbing or amplifying light, and are, for example, bulk waveguides, lasers, optical modulators or optical amplifiers. FIG. 2 shows a cross section of an edge-emitting laser along the optical axis, and light is emitted from at least one of both end surfaces perpendicular to the optical axis.

[Semiconductor multilayer]
The semiconductor optical device has a semiconductor multilayer 16 in which a lower clad layer 10, an optical function layer 12 and an upper clad layer 14 are laminated. The optical functional layer 12 constitutes at least part of the optical waveguide 18 . The optical functional layer 12 is, for example, a multiple quantum well layer, and functions as an active layer (light emitting layer) in a laser. Alternatively, the optical functional layer 12 may be a bulk semiconductor layer. The lower clad layer 10 may be a semiconductor substrate or a semiconductor layer separate from the semiconductor substrate. Other layers, such as contact layers and optical confinement layers, may also be included in the semiconductor multilayer 16 .

[electrode]
The semiconductor optical device has an electrode 20 and a backside electrode 22 . The electrode 20 and the backside electrode 22 are formed by metal vapor deposition. The metal forming the back electrode 22 includes, for example, AuGe and Ni. On the upper surface of the semiconductor multilayer 16, the portion other than the electrode 20 may be a semiconductor surface, and an insulator film (for example, silicon oxide) formed by a plasma CVD (Chemical Vapor Deposition) method or a thermal CVD method is formed. may Electrode 20 contacts the top surface of semiconductor multilayer 16 .

[Multilayer structure]
[Top layer]
Electrode 20 has a multilayer structure. The top layer 24 of the multilayer structure is thicker than the other layers (eg, 600 nm) for wire bonding and physical contact with the mounting surface of the submount. The top layer 24 is composed of Au. Since Au has a larger coefficient of thermal expansion than semiconductors such as InP, it can cause stress in the semiconductor multilayer 16 .

[Bottom layer]
The bottom layer 26 of the multi-layer structure is composed of a material (eg, Ti, Mo) that has higher adhesion to the semiconductor multi-layer 16 than Au, which allows ohmic contact. The thickness of the bottom layer 26 is, for example, 100 nm.

[Barrier layer]
The multilayer structure includes barrier layer 28 . Barrier layer 28 comprises a material that prevents metal diffusion through electrode 20 between top layer 24 and bottom layer 26 . Materials that prevent metal diffusion are for example Pt, W, Cr, Pd or Ta. Barrier layer 28 contacts bottom layer 26 . The thickness of the barrier layer 28 is, for example, 100 nm.

[Multistage structure]
Electrode 20 has a multi-stage structure. A multistage structure is composed of three or more sections S. Three or more sections S overlap the optical waveguide 18 and are adjacent to each other in the direction in which the optical waveguide 18 extends, and have different thicknesses. One of a pair of adjacent three or more sections S is close to the end surface (element end surface) of the semiconductor multilayer 16 and has a small thickness. The other of the adjacent pair of three or more sections S is thicker away from the end surface of the semiconductor multilayer 16 .

[Section 1]
FIG. 3 is an enlarged view of the multistage structure of the electrode 20. FIG. The three or more sections S include a first section S1. The first section S1 consists of at least the bottom layer 26 . The first section S1 here includes a bottom layer 26 and a barrier layer 28 . The end surfaces of the layers forming the first section S1 match the side surfaces (element end surfaces) of the semiconductor multilayer 16 .

The first section S1 has a first thickness t1. The first thickness t1 is the smallest among the thicknesses of the three or more sections S. The first thickness t1 is less than the thickness of the top layer 24 so that the first section S1 reduces the effects of stress caused by it. Preferably, the first thickness t1 is less than half the thickness of the top layer 24 .

[Second Section]
The three or more sections S include a second section S2. The second section S2 adjoins the first section S1. The thickness by which the second section S2 exceeds the first section S1 is the second thickness t2.

The second section S2 is composed of at least the bottom layer 26 (for example, the bottom layer 26 and the barrier layer 28) and a stress relieving layer 30 made of a material having a Young's modulus lower than Au. The stress relieving layer 30 is part of the top layer 24 (the part forming the bottom surface). The stress relieving layer 30 is made of Au and has excellent heat dissipation. The stress relaxation layer 30 has a Young's modulus equal to or lower than that of Au constituting the top layer 24, so that expansion or contraction of the top layer 24 included in the third section S3 described later is transmitted to the semiconductor layer 16. do.

The stress relief layer 30 is thinner than the overall thickness of the top layer 24 to limit the stress effects it causes. The stress relieving layer 30 is preferably less than half the thickness of the top layer 24 . The second thickness t2 of the stress relieving layer 30 is, for example, 100 nm.

The distance between the tip of the second section S2 and the tip of the first section S1 is, for example, 10 μm. The tip of the second section S2 is positioned inside the side surface of the semiconductor multilayer 16 . In other words, the distance from the tip of the second section S2 to the side surface of the semiconductor multilayer 16 is greater than the distance from the tip of the first section S1 to the side surface of the semiconductor multilayer 16.

[Section 3]
The three or more sections S include a third section S3. The third section S3 consists of all layers from the top layer 24 to the bottom layer 26 and is the thickest of the three or more sections S. The thickness by which the third section S3 exceeds the second section S2 is the third thickness t3. At least one of the first thickness t1 and the second thickness t2 is less than half the third thickness t3.

The tip of the third section S3 is located inside the upper surface of the semiconductor multilayer 16 than the tip of the second section S2. The distance from the tip of the third section S3 to the side surface of the semiconductor multilayer 16 is greater than the distance from the tip of the second section S2 to the side surface of the semiconductor multilayer 16 . The distance between the tip of the first section S1 and the tip of the third section S3 is, for example, 20 μm.

From the viewpoint of stress, it is preferable that the distance between the tips of the first section S1, the second section S2 and the third section S3 is large. However, each layer constituting the electrode 20 also plays a role as a heat dissipation layer, and it is not preferable for the area (volume) to be small. In particular, the amount of heat generated is large near the tips of the first section S1, the second section S2, and the third section S3. From the viewpoint of heat dissipation, it is preferable that the second section S2 and the third section S3 are close to the side surface of the semiconductor multilayer 16 . For example, the distance between the tip of the first section S1 and the tip of the second section S2 may be 5 μm, and the distance between the tip of the first section S1 and the tip of the third section S3 may be 10 μm.

How much the tip of the second section S2 and the tip of the third section S3 should be separated from the tip of the first section S1 may be determined from the viewpoint of stress and heat dissipation. As for the minimum distances, from the viewpoint of manufacturing variations, the distance between the tip of the first section S1 and the tip of the second section S2 is 2 μm, and the distance between the tip of the first section S1 and the tip of the third section S3 is 4 μm or more. preferably.

[Comparative example]
4 is a cross-sectional view of an electrode according to Comparative Example 1. FIG. In Comparative Example 1, the tips of the top layer 4 , the bottom layer 6 and the barrier layer 8 are aligned with the side surfaces of the semiconductor multilayer 2 . Therefore, stress concentrates on the side surface of the semiconductor multilayer 2 .

5 is a cross-sectional view of an electrode according to Comparative Example 2. FIG. In Comparative Example 2, the entire top layer 4 is within the third section S3. That is, the top layer 4 is separated from the side surfaces of the semiconductor multilayer 2 . Therefore, the stress generated on the side surface of the semiconductor multilayer 2 is reduced. However, immediately below the tip of the uppermost layer 4, the stress generated in the semiconductor multilayer 2 is greater than in the first comparative example.

6 is a cross-sectional view of an electrode according to Comparative Example 3. FIG. In Comparative Example 3, the edge of the uppermost layer 4 is two-tiered and the thin tip portion is aligned with the side surface of the semiconductor multilayer 2 , so the stress generated on the side surface of the semiconductor multilayer 2 is smaller than in Comparative Example 1. However, since part of the uppermost layer 4 is aligned with the side surface of the semiconductor multilayer 2 , the stress generated on the side surface of the semiconductor multilayer 2 is greater than that in the second comparative example.

[effect]
In this embodiment, since the electrode 20 has a multi-stage structure, the stress generated in the semiconductor multilayer 16 can be dispersed. For example, the tips of the second section S2 and the third section S3 do not match the side surfaces (element end surfaces) of the semiconductor multilayer 16 . In particular, the uppermost layer 24 made of Au, which causes strong stress generation, does not coincide with the side surfaces. Therefore, the stress generated on the side surfaces can be reduced.

Since the stress relieving layer 30 is a metal having a Young's modulus equal to or lower than that of Au, the expansion or contraction of the uppermost layer 24 of the third section S3 is mitigated from being transmitted to the semiconductor multilayer 16, and the stress applied to the semiconductor multilayer 16 is reduced. The impact can be reduced. In particular, since the tip of the second section S2 and the tip of the third section S3 do not coincide with each other, the stress applied directly below the tip of the third section S3 is reduced, and the stress applied inside the element is reduced. Furthermore, since the uppermost layer 24, which is the Au layer, does not coincide with the side surface, the Au layer is not cut when cutting the semiconductor multilayer 16, and the cleaving property is excellent.

[Production method]
The multistage structure of the electrode 20 can be formed by the following procedure from the viewpoint of mass productivity. First, after forming the semiconductor multilayer 16 , a metal multilayer from the bottom layer 26 to the top layer 24 is vapor-deposited on the entire upper surface of the semiconductor multilayer 16 . Then, the metal multilayer is etched so as to leave the overall planar shape of the electrode 20 .

Next, an etching mask is formed by lithography to cover the planar shapes of the second section S2 and the third section S3. Then, selective etching is performed in which the etching progresses to the uppermost layer 24 but the etching progresses slowly to the layer immediately below it. Thereby, the top layer 24 is removed in the first section S1 to form the tip of the second section S2. That is, a step is formed between the first section S1 and the second section S2.

The top layer 24 is then etched again in the second section S2 through an etch mask that covers the area that will become the third section S3 but not the second section S2. However, by controlling the etching rate and etching time, the uppermost layer 24 is not entirely removed, but part of it is left. This forms the tip of the third section S3 and forms a step between the second section S2 and the third section S3. Together with the previously formed steps, a multi-step structure is formed.

[Modification 1]
7 is a cross-sectional view of an electrode according to Modification 1. FIG. In Modification 1, the stress relieving layer 130 of the second section S2 is a separate layer from the top layer 124 . The stress relieving layer 130 is made of a metal (eg, In) whose Young's modulus is smaller than that of Au forming the top layer 124 . Since the stress relieving layer 130 is made of a metal whose Young's modulus is smaller than that of Au, the expansion or contraction of the top layer 124 is alleviated from being transmitted to the semiconductor multilayer 116, and the stress generated in the semiconductor multilayer 116 can be reduced.

[Modification 2]
8 is a cross-sectional view of an electrode according to Modification 2. FIG. In Modified Example 2, the stress relaxation layer 230 of the second section S2 is a layer (non-contact layer) different from the top layer 224, but is made of the same Au as the top layer 224. FIG. The thickness of the stress relieving layer 230 is 100 nm. The stress relieving layer 230 can reduce the effect of expansion or contraction of the third section S3 on the semiconductor multilayer 216 at its tip.

The multi-layer structure of the electrode 220 includes a partial barrier layer 232 of a material that prevents metal diffusion in at least the third section S3 (eg, the second section S2 and the third section S3) except for the first section S1. The thickness of the partial barrier layer 232 is 100 nm. A partial barrier layer 232 is also included in the second section S2. Materials that prevent metal diffusion are Pt, W, Cr, Pd or Ta.

The layer forming the upper surface of the second section S2 is not limited to the partial barrier layer 232, and may be another layer. For example, it may be a Ti layer. A partial barrier layer 232 and a Ti layer may be stacked between the top layer 224 and the stress relief layer 230 . However, the second thickness t2 of the second section S2 is preferably half or less than the third thickness t3 so as not to increase the stress generated in the semiconductor multilayer 216 immediately below the tip.

The second modification facilitates the process of forming the stepped shape. First, a metal multilayer is deposited over the entire top surface of the semiconductor multilayer 216 . Then, unnecessary portions are removed from the metal multilayer in the first section S1. In the second section S2 and the third section S3 all layers of the metal multilayer are left.

Next, the region to be the third section S3 is masked and etched with a solution for etching only Au. If the layer forming the upper surface of the second section S2 is made of the partial barrier layer 232 (for example, Pt) or Ti, the etching will not progress. As a result, selective etching becomes possible without time control, unnecessary portions can be removed in the second section S2, and large-area and efficient manufacturing becomes possible.

[Modification 3]
9 is a cross-sectional view of an electrode according to Modification 3. FIG. In Modification 3, the barrier layer 328 is thin (eg, 50 nm). As a result, the influence of the tip of the first section S1 on the side surface of the semiconductor multilayer 316 is reduced. However, it is difficult to control the thickness of the film to be thin, and the film may become too thin or may have areas where it is not densely formed. As a result, when Au diffuses into the semiconductor multilayer 316, the reliability is lowered.

Therefore, in Variation 3, the multi-layer structure includes a partial barrier layer 332 in at least the third section S3 (eg, only the third section S3), excluding the first section S1. Partial barrier layer 332 is made of a material that prevents metal diffusion. Materials that prevent metal diffusion are Pt, W, Cr, Pd or Ta. The thickness of the partial barrier layer 332 is 100 nm. By providing the partial barrier layer 332, the effect of preventing the Au forming the uppermost layer 324 from diffusing into the underlying layer can be enhanced. Thereby, the diffusion of Au constituting the top layer 324 can be sufficiently suppressed.

In the third section S3, the top layer 324 has a thickness of 600 nm, but the addition of the partial barrier layer 332 increases the third thickness t3. This increases the impact exerted by expansion or contraction of the third section S3. However, the stress relieving layer 330 of the second section S2 distributes the stress and reduces its effect on the semiconductor multilayer 316 . The stress relieving layer 330 of the second section S2 is a separate layer from the top layer 324 .

[Modification 4]
10 is a cross-sectional view of an electrode according to Modification 4. FIG. In variant 4, the first section S1 includes part of the top layer 424 . A portion of the uppermost layer 424 included in the first section S1 has the effect of improving the heat dissipation at and near the side surfaces of the semiconductor multilayer 416 and improving the characteristics. That is, Modification 4 achieves high heat dissipation and reliability.

On the other hand, if part of the top layer 424 included in the first section S1 is thick, it causes stress and degrades reliability. Thus, the portion of the top layer 424 included in the first section S1 is less than half (eg, 25 nm) thicker than the portion of the top layer 424 included in the second section S2. Note that the thickness of each of the bottom layer 426 and the barrier layer 428 is 100 nm.

[Second embodiment]
FIG. 11 is a plan view of a semiconductor optical device according to the second embodiment. 12 is a cross-sectional view of the semiconductor optical device shown in FIG. 11 taken along line XII-XII. 13 is a cross-sectional view of the semiconductor optical device shown in FIG. 11 taken along the line XIII--XIII. 14 is a cross-sectional view of the semiconductor optical device shown in FIG. 11, taken along line XIV-XIV.

The semiconductor optical device is a distributed feedback semiconductor laser (DFB laser) having a ridge waveguide structure. The optical functional layer 512 forming at least part of the optical waveguide 518 is, for example, a multiple quantum well layer and functions as an active layer (light emitting layer).

Semiconductor multilayer 516 includes lower cladding layer 510 , optical functional layer 512 and upper cladding layer 514 . The lower clad layer 510 and the upper clad layer 514 are InP, and the optical functional layer 512 is InGaAsP. The lower clad layer 510 may be a semiconductor substrate, or may be a semiconductor layer separate from the semiconductor substrate. Between the optical functional layer 512 and the lower clad layer 510, a diffraction grating layer (not shown) having a diffraction grating structure made of InGaAsP is arranged. Note that the diffraction grating layer may be arranged between the optical function layer 512 and the upper clad layer 514 .

Between the optical functional layer 512 and the diffraction grating layer and between the optical functional layer 512 and the upper cladding layer 514, an optical confinement layer (not shown) made of InGaAsP is arranged. The optical function layer 512 and the optical confinement layer are not limited to InGaAsP, and may be InGaAlAs. Semiconductor multilayer 516 may include a contact layer.

Semiconductor multilayer 516 includes a mesa structure that provides optical waveguide 518 . The optical waveguide 518 has a ridge waveguide type mesa structure (hereinafter referred to as a ridge structure). The ridge structure includes a portion of the upper cladding layer 514 , may include a portion of the optical functional layer 512 , and may include a portion of the lower cladding layer 510 .

The electrode 520 includes a main electrode 534 arranged above the optical waveguide 518 along the optical waveguide 518 and a pad electrode 536 led out from the main electrode 534, which are integrally continuous. A wire for transmitting an electric signal from the outside is bonded to the pad electrode 536 . By applying a voltage between the electrode 520 and the back electrode 522, the semiconductor optical device emits laser light from the end face of the device.

In areas where the electrodes 520 are not arranged, the semiconductor multilayer 516 is covered with an insulating layer 538 . The insulating layer 538 is, for example, silicon oxide. The insulating layer 538 is also disposed below a portion of the electrode 520 except for the electrical connection between the main electrode 534 and the semiconductor multilayer 516 (immediately above the optical waveguide 518).

The main electrode 534 has a multistage structure on the upper surface of the ridge structure. The main electrode 534 also has a multi-stage structure on the side surface of the ridge structure or both sides of the ridge structure, and prevents stress concentration occurring in the semiconductor multilayer 516 in these regions as well. The details of the multi-stage structure described in the above embodiments are applicable here.

A semiconductor optical device can be manufactured by the following method. Crystal growth is performed on a semiconductor substrate by metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy, thereby crystal-growing a lower clad layer 510, an optical function layer 512 and an upper clad layer 514, respectively. After that, an etching mask is formed to cover the optical waveguide 518 (mesa structure), and etching (dry etching or wet etching) is performed to form a ridge-shaped optical waveguide 518 .

In order to protect the surface of the semiconductor multilayer 516, an insulating layer 538 (for example, silicon oxide) is formed over the entire surface by plasma CVD or thermal CVD. Then, the insulating layer 538 is etched through an etching mask having an opening in the region (electrical connection portion) directly above the optical waveguide 518 . Subsequently, metal multilayers are formed by vapor deposition in order from the one closest to the semiconductor multilayer 516 .

Next, etching is performed through an etching resist that covers only the region that will become the third section S3, and the surface shape of the third section S3 is formed from the uppermost layer 524. FIG. However, instead of completely removing the region other than the third section S3, the region is thinned by etching back and left.

Next, etching is performed through the etching resist that covers only the regions that will become the second section S2 and the third section S3, and the surface shape (the stress relaxation layer 530) of the second section S2 is formed from the top layer 524. FIG. However, instead of completely removing the regions other than the second section S2 and the third section S3, the regions are thinned by etching back and left.

Next, etching is performed through an etching resist that covers only the regions that will become the first section S1, the second section S2 and the third section S3, and the surface shape of the first section S1 (the layer 526 consisting of the bottom layer and the barrier layer) is etched. ). However, the etch should not extend to the layer below layer 526 (insulating layer 538).

[Third Embodiment]
FIG. 15 is a plan view of a semiconductor optical device according to the third embodiment. 16 is a cross-sectional view of the semiconductor optical device shown in FIG. 15 taken along line XVI--XVI. 17 is a cross-sectional view of the semiconductor optical device shown in FIG. 15 taken along line XVII-XVII.

A semiconductor optical device is an optical modulator (for example, an electro-absorption modulator) adapted to convert continuous light input from one end face into modulated light. The optical functional layer 612 forming at least part of the optical waveguide 618 is, for example, a multiple quantum well layer and functions as a light absorbing layer.

Semiconductor multilayer 616 includes a mesa structure that provides optical waveguide 618 . The optical waveguide 618 has a mesa structure. In FIG. 15, the mesa structure is indicated by broken lines. The mesa structure includes a portion of the lower cladding layer 610 , an optical functional layer 612 and an upper cladding layer 614 . Both sides of the mesa structure are buried with a semiconductor buried layer 642 . Lower clad layer 610 and upper clad layer 614 are InP, and optical functional layer 612 is InGaAsP. Between the optical functional layer 612 and the lower clad layer 610 and between the optical functional layer 612 and the upper clad layer 614, optical confinement layers (not shown) made of InGaAsP are arranged.

The optical waveguide 618 includes a layer of non-absorbing material 640 (window structure). The non-absorbing material layer 640 has the effect of reducing reflection from the light emitting end surface returning to the optical functional layer 612 . The non-absorbing material layer 640 has a larger bandgap than the optical functional layer 612 . The non-absorbing material layer 640 is adjacent to the optical functional layer 612 in the optical waveguide direction. The non-absorbing material layer 640 constitutes part of the side surface (element end surface) of the semiconductor multilayer 616 .

The semiconductor optical device has an electrode 620 and a backside electrode 622 . The electrode 620 includes a main electrode 634 disposed above the optical waveguide 618 along the optical waveguide 618, and a pad electrode 636 extending from the main electrode 634, which are integral and continuous. A wire for transmitting an electric signal from the outside is bonded to the pad electrode 636 . By applying a voltage between the electrode 620 and the back electrode 622, the semiconductor optical device modulates the light incident from the end surface.

The main electrode 634 has a multi-stage structure on the upper surface of the ridge structure. The details of the multi-stage structure described in the above embodiments are applicable here. Above the non-absorbing material layer 640 , the electrode 620 does not reach the edge of the top surface of the semiconductor multilayer 616 (device facet), since no electricity needs to be input to the non-absorbing material layer 640 . On the side where the non-absorbing material layer 640 is arranged, the tip of the first section S1 lies inside the side surface of the semiconductor multilayer 616 . The end faces of the layers that make up the first section S1 are separated from the side surfaces of the semiconductor multilayer 616 . The portion of electrode 620 directly above non-absorbing material layer 640 is insulated from semiconductor multilayer 616 via insulating layer 638 . The configuration of the electrode 620 is merely an example, and the configuration shown in other embodiments may be used.

[Overview of embodiment]
(1) The semiconductor optical device has a semiconductor multilayer 16 configured to include an optical waveguide 18, and an electrode 20 having a multilayer structure and a multistage structure in contact with the upper surface of the semiconductor multilayer 16. The upper layer 24 is made of Au, and the bottom layer 26 of the multilayer structure is made of a material having higher adhesion to the semiconductor multilayer 16 than Au. It is composed of three or more sections S that are adjacent to each other in the direction and have different thicknesses, and one pair of adjacent three or more sections S is close to the end surface of the semiconductor multilayer 16 and has a small thickness, and The three or more sections S consist of a first section S1 of minimum thickness, composed of at least the bottom layer 26, and at least the bottom layer 26 plus Au in Young's modulus. A second section S2 adjacent to the first section S1, composed of a stress relieving layer 30 made of the following materials, and a third section S3 having the maximum thickness, composed of all the layers from the top layer 24 to the bottom layer 26: and including.

(2) In the semiconductor optical device described in (1), the stress relieving layer 30 of the second section S2 may be part of the top layer 24 .

(3) In the semiconductor optical device described in (2), the first section S1 may further include another part of the top layer 424.

(4) In the semiconductor optical device according to (3), the other part of the top layer 424 included in the first section S1 is the thickness of the part of the top layer 424 included in the second section S2. may be less than half of

(5) In the semiconductor optical device described in (1), the stress relieving layer 130 of the second section S2 may be a layer different from the top layer 124 .

(6) The semiconductor optical device according to any one of (1) to (5), wherein the first section S1 has a first thickness t1, and the second section S2 covers the first section S1. The thickness exceeding is the second thickness t2, the thickness exceeding the second section S2 by the third section S3 is the third thickness t3, and at least one of the first thickness t1 and the second thickness t2 may be half or less of the third thickness t3.

(7) The semiconductor optical device according to any one of (1) to (6), wherein the multilayer structure comprises, between the top layer 24 and the bottom layer 26, over three or more sections S, A barrier layer 28 of a material that prevents metal diffusion may be included.

(8) In the semiconductor optical device described in (7), the barrier layer 28 may be a layer in contact with the bottom layer 26 .

(9) The semiconductor optical device according to (7) or (8), wherein the multilayer structure includes a partial barrier layer 232 made of a material that prevents metal diffusion in at least the third section S3 except the first section S1. may include

(10) In the semiconductor optical device according to (9), the partial barrier layer 232 may also be included in the second section S2.

(11) In the semiconductor optical device according to any one of (7) to (10), the material for preventing metal diffusion may be Pt, W, Cr, Pd or Ta.

(12) In the semiconductor optical device according to any one of (1) to (11), the bottom layer 26 may be made of Ti or Mo.

(13) In the semiconductor optical device according to any one of (1) to (12), the layer forming the upper surface of the second section S2 may be made of Pt or Ti.

(14) In the semiconductor optical device according to any one of (1) to (13), the end faces of the layers forming the first section S1 may coincide with the side faces of the semiconductor multilayer 16 .

(15) In the semiconductor optical device according to any one of (1) to (13), the end face of the layer forming the first section S1 may be separated from the side surface of the semiconductor multilayer 616.

(16) In the semiconductor optical device according to any one of (1) to (15), the semiconductor multilayer 516 may include a mesa structure that serves as the optical waveguide 518 .

(17) The semiconductor optical device according to any one of (1) to (16), wherein the semiconductor multilayer 16 may include an active layer or a light absorption layer forming at least part of the optical waveguide 18. .

(18) In the semiconductor optical device according to (17), the optical waveguide 618 includes a non-absorbing material layer 640 having a bandgap larger than that of the active layer or the light absorbing layer, and the non-absorbing material layer 640 is the active layer. Alternatively, the portion of the electrode 620 that is adjacent to the light absorbing layer in the light guiding direction and directly above the non-absorbing material layer 640 may be insulated from the semiconductor multilayer 616 via the insulating layer 638 .
(19) In the semiconductor optical device described in (16), the electrode 520 may have the multistage structure on the upper surface of the mesa structure.
(20) In the semiconductor optical device described in (16), the electrode 520 may have the multistage structure on the side surface of the mesa structure.

The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, the configurations described in the embodiments can be replaced with configurations that are substantially the same, that have the same effects, or that can achieve the same purpose.

2 semiconductor multilayer, 4 top layer, 6 bottom layer, 8 barrier layer, 10 lower clad layer, 12 optical function layer, 14 upper clad layer, 16 semiconductor multilayer, 18 optical waveguide, 20 electrode, 22 back electrode, 24 top layer, 26 bottom layer, 28 barrier layer, 30 stress relaxation layer, 116 semiconductor multilayer, 124 top layer, 130 stress relaxation layer, 216 semiconductor multilayer, 220 electrode, 224 top layer, 230 stress relaxation layer, 232 partial barrier layer, 316 semiconductor multilayer , 324 top layer, 328 barrier layer, 330 stress relaxation layer, 332 partial barrier layer, 416 semiconductor multilayer, 424 top layer, 426 bottom layer, 428 barrier layer, 510 lower clad layer, 512 optical function layer, 514 upper clad layer, 516 semiconductor multilayer, 518 optical waveguide, 520 electrode, 522 rear electrode, 524 uppermost layer, 526 layer, 534 main electrode, 536 pad electrode, 538 insulating layer, 610 lower clad layer, 612 optical function layer, 614 upper clad layer, 616 Semiconductor multilayer 618 Optical waveguide 620 Electrode 622 Rear electrode 634 Main electrode 636 Pad electrode 638 Insulating layer 640 Non-absorbing material layer 642 Buried layer S Section S1 First section S2 Second section S3 Third section.

Claims (20)

a semiconductor multilayer configured to include an optical waveguide;
a multi-layered and multi-staged electrode in contact with the upper surface of the semiconductor multilayer;
has
the top layer of the multilayer structure is composed of Au,
The bottom layer of the multilayer structure is made of a material having higher adhesion to the semiconductor multilayer than Au,
The multi-stage structure is composed of three or more sections each overlapping the optical waveguide and adjacent to each other in the direction in which the optical waveguide extends and having different thicknesses,
an adjacent pair of the three or more sections consists of one having a smaller thickness near the edge of the semiconductor multilayer and the other having a greater thickness away from the edge of the semiconductor multilayer;
The three or more sections include:
a first section of said minimum thickness comprising at least said bottom layer;
a second section, adjacent to the first section, comprising at least the bottom layer and a stress relieving layer made of a material having a Young's modulus of Au or less;
a third section having the maximum thickness and comprising all layers from the top layer to the bottom layer;
A semiconductor optical device comprising: The semiconductor optical device according to claim 1,
The semiconductor optical device, wherein the stress relieving layer of the second section is part of the top layer. The semiconductor optical device according to claim 2,
The semiconductor optical device, wherein the first section further includes another portion of the top layer. The semiconductor optical device according to claim 3,
The other part of the top layer included in the first section is a semiconductor optical device, wherein the thickness is less than half of the part of the top layer included in the second section. The semiconductor optical device according to claim 1,
The semiconductor optical device, wherein the stress relieving layer of the second section is a separate layer from the top layer. The semiconductor optical device according to any one of claims 1 to 5,
the first section has a first thickness;
the thickness by which the second section exceeds the first section is a second thickness;
the thickness by which the third section exceeds the second section is a third thickness;
A semiconductor optical device, wherein at least one of the first thickness and the second thickness is half or less of the third thickness. The semiconductor optical device according to any one of claims 1 to 6,
The semiconductor optical device, wherein the multilayer structure includes a barrier layer made of a material that prevents metal diffusion between the top layer and the bottom layer and throughout the three or more sections. The semiconductor optical device according to claim 7,
The semiconductor optical device, wherein the barrier layer is a layer in contact with the bottom layer. 9. The semiconductor optical device according to claim 7 or 8,
A semiconductor optical device, wherein the multilayer structure includes a partial barrier layer made of a material that prevents metal diffusion in at least the third section except the first section. The semiconductor optical device according to claim 9,
The semiconductor optical device, wherein the partial barrier layer is also included in the second section. The semiconductor optical device according to any one of claims 7 to 10,
The semiconductor optical device, wherein the material for preventing the metal diffusion is Pt, W, Cr, Pd or Ta. The semiconductor optical device according to any one of claims 1 to 11,
The semiconductor optical device, wherein the bottom layer is made of Ti or Mo. The semiconductor optical device according to any one of claims 1 to 12,
The semiconductor optical device, wherein the layer forming the upper surface of the second section is made of Pt or Ti. The semiconductor optical device according to any one of claims 1 to 13,
The semiconductor optical device, wherein an end face of the layer forming the first section is aligned with a side surface of the semiconductor multilayer. The semiconductor optical device according to any one of claims 1 to 13,
The semiconductor optical device, wherein the end surface of the layer forming the first section is separated from the side surface of the semiconductor multilayer. The semiconductor optical device according to any one of claims 1 to 15,
The semiconductor optical device, wherein the semiconductor multilayer includes a mesa structure serving as the optical waveguide. The semiconductor optical device according to any one of claims 1 to 16,
The semiconductor optical device, wherein the semiconductor multilayer includes an active layer or a light absorption layer forming at least a part of the optical waveguide. 18. The semiconductor optical device according to claim 17,
the optical waveguide includes a non-absorbing material layer having a bandgap larger than that of the active layer or the light absorbing layer;
the non-absorbing material layer is adjacent to the active layer or the light absorbing layer in the optical waveguide direction;
A semiconductor optical device, wherein a portion of the electrode directly above the non-absorbing material layer is insulated from the semiconductor multilayer via an insulating layer. 17. The semiconductor optical device according to claim 16,
The semiconductor optical device, wherein the electrode has the multi-stage structure on the upper surface of the mesa structure. 17. The semiconductor optical device according to claim 16,
The semiconductor optical device, wherein the electrode has the multistage structure on the side surface of the mesa structure.

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