JP2023085193A - Oxide semiconductor thin film transistor device and method of manufacturing the same - Google Patents

Abstract

To improve characteristics of an oxide semiconductor thin film transistor.SOLUTION: An oxide semiconductor thin film transistor device includes a gate electrode part, an oxide semiconductor part, a first source/drain electrode part, and a second source/drain electrode part. The oxide semiconductor part has a concentration distribution of elements capable of making an oxide semiconductor high in resistance. The concentration distribution shows a first concentration at a gravity center position of a channel region overlapping with a gate electrode part in plan view, and also shows a concentration higher than the first concentration nearby at least a part of a border defining an outer peripheral end of the channel region.SELECTED DRAWING: Figure 7

Description

The present disclosure relates to an oxide semiconductor thin film transistor device and manufacturing method thereof.

Applications of oxide semiconductor thin film transistors (oxide semiconductor TFTs) are expanding from displays to memories, and there will be a demand for even higher definition and higher density in the future. A semiconductor layer of an oxide semiconductor TFT includes a channel region and source/drain regions sandwiching the channel region. For higher definition and higher density, it is required to reduce the size of the source/drain regions. The source/drain regions are low resistance regions having a lower resistance than the channel region.

U.S. Patent Application Publication No. 2020/0251505 U.S. Patent Application Publication No. 2016/0300954 U.S. Patent Application Publication No. 2019/0207033

In a high-definition oxide semiconductor TFT, it is particularly important that the channel region of the oxide semiconductor portion is configured so as to exhibit characteristics as designed.

One aspect of the present disclosure is an oxide semiconductor thin film transistor device including a gate electrode portion, an oxide semiconductor portion, a first source/drain electrode portion, and a second source/drain electrode portion, wherein the oxidation The physical semiconductor portion has a concentration distribution of an element capable of increasing the resistance of the oxide semiconductor, and the concentration distribution has a first concentration at a center position of the channel region overlapping the gate electrode portion in a plan view. and exhibiting a concentration higher than the first concentration in the vicinity of at least a portion of the boundary defining the outer peripheral edge of the channel region.

Another aspect of the present disclosure is a method for manufacturing an oxide semiconductor thin film transistor device, comprising forming an oxide semiconductor layer, forming a gate electrode, and forming an oxide semiconductor in a selected region of the oxide semiconductor layer. Implanting an element capable of increasing the resistance to form a first source/drain electrode and a second source/drain electrode.

According to one aspect of the present disclosure, characteristics of an oxide semiconductor thin film transistor can be improved.

1 schematically shows a configuration example of an OLED display device 1. FIG. 4 shows a configuration example of a pixel circuit. The cross-sectional structure of a portion of the TFT substrate is schematically shown. An example of a CMOS circuit is shown. 5 schematically shows an example of a cross-sectional structure of the CMOS circuit shown in FIG. 4. FIG. A method of manufacturing an oxide semiconductor TFT is shown. A method of manufacturing an oxide semiconductor TFT is shown. A method of manufacturing an oxide semiconductor TFT is shown. A method of manufacturing an oxide semiconductor TFT is shown. 4 schematically shows oxygen concentration distributions in an oxide semiconductor portion and a gate insulator layer. An example of implanting oxygen ions into the oxide semiconductor portion after forming the source/drain electrode portion will be shown. Another fabrication method for an oxide semiconductor TFT is shown. Another fabrication method for an oxide semiconductor TFT is shown. Another fabrication method for an oxide semiconductor TFT is shown. Another fabrication method for an oxide semiconductor TFT is shown. 9A to 9D schematically show the oxygen concentration distribution in an interlayer insulating film formed by the method described with reference to FIGS. 9A to 9D. Another example of the method for manufacturing an oxide semiconductor TFT will be described. Another example of the method for manufacturing an oxide semiconductor TFT will be described. Another example of the method for manufacturing an oxide semiconductor TFT will be described. Fig. 3 shows experimental results of implanting different ions into IGZO; FIG. 4 is a plan view showing an example of implanting oxygen ions into source/drain regions; FIG. 10 is a plan view showing an example of implanting oxygen ions into width edges of a channel region; An example of a method of implanting oxygen ions into the width edge of the channel region is shown. The structure of the oxide semiconductor part after oxide semiconductor TFT is formed is shown typically. A configuration example of a dual-gate type TFT is shown. A configuration example of a dual-gate type TFT is shown.

Embodiments of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the present embodiment is merely an example for realizing the present disclosure and does not limit the technical scope of the present disclosure. In order to make the description easier to understand, the dimensions and shapes of the illustrated objects may be exaggerated.

[Overview]
An OLED (Organic Light-Emitting Diode) display device will be described below as an example of a device (oxide semiconductor TFT device) including an oxide semiconductor thin film transistor (oxide semiconductor TFT). The OLED display device of the present disclosure includes oxide semiconductor thin film transistors (TFTs) in the pixel circuits and/or in the peripheral circuits. An example of an oxide semiconductor is IGZO (Indium Gallium Zinc Oxide). Oxide semiconductor TFTs can be used not only for OLEDs, but also for flat panel displays such as liquid crystal displays, and electronic devices such as memory devices and high-voltage devices.

Since the leakage current of the oxide semiconductor TFT is small, the oxide semiconductor TFT is used, for example, as a switch transistor connected to a storage capacitor (capacitor element) for maintaining the gate potential of the drive transistor in the pixel circuit. Note that the configuration of the present disclosure can be applied to a device other than the display device.

An oxide semiconductor portion of an oxide semiconductor TFT includes a channel region for controlling the flow of carriers by a gate potential and source/drain regions sandwiching the channel region. The source/drain regions are low resistance regions having a lower resistance than the channel region.

In order for the oxide semiconductor TFT to exhibit desired characteristics, it is important that the channel region has the structure as designed. As the density of oxide semiconductor TFTs increases, the size of the channel region and the size of the source/drain regions decrease. Therefore, there is a strong demand for the channel region to exhibit the designed resistance at the designed channel length and channel width.

The source/drain regions can be made low resistance by several methods. For example, the contact of the source/drain electrodes reduces the resistance of the oxide semiconductor. Specifically, the metal forming the source/drain electrodes extracts oxygen elements from the oxide semiconductor, increasing the oxygen vacancies in the oxide semiconductor, thereby reducing the resistance of the oxide semiconductor. The resistance of the oxide semiconductor can also be reduced by diffusion of hydrogen from an insulating film around the oxide semiconductor, plasma treatment, or impurity ion implantation.

Regions designed as channel regions can be affected by low resistance. In particular, the resistance tends to be low at the periphery of the designed channel region (the region near the outer edge). If the low resistance region of the oxide semiconductor extends to the designed channel region, the oxide semiconductor TFT may not operate as designed.

However, if the distance between the source/drain electrodes and the gate electrode is increased in order to avoid lowering the resistance in the vicinity of the edges that define the channel length, this impedes the densification of oxide semiconductor TFTs. Alternatively, when the vicinity of the edge defining the channel width has a low resistance, the oxide semiconductor TFT may exhibit hump characteristics.

In one embodiment of the present specification, an element capable of increasing the resistance of the oxide semiconductor is implanted into selected regions of the oxide semiconductor. This prevents the region near the edge of the channel from becoming low resistance.

[Display device configuration]
FIG. 1 schematically shows a configuration example of an OLED display device 1. As shown in FIG. The OLED display device 1 includes a TFT (Thin Film Transistor) substrate 10 on which OLED elements and pixel circuits are formed, and a thin film encapsulation (TFE) 20 for encapsulating the organic light emitting element. It is The thin film encapsulation structure 20 is one of the encapsulation structure portions, and as another example, the encapsulation structure portion includes a encapsulation substrate for encapsulating the organic light emitting element, and bonding the TFT substrate 10 and the encapsulation substrate. It can include a joining portion (glass frit seal portion). For example, dry nitrogen or dry air is enclosed between the TFT substrate 10 and the sealing substrate.

A scanning driver 31 , an emission driver 32 , a protection circuit 33 , a driver IC 34 and a demultiplexer 36 are arranged around the cathode electrode forming area 14 outside the display area 25 of the TFT substrate 10 . The driver IC 34 is connected to external equipment via an FPC (Flexible Printed Circuit) 35 . A scanning driver 31 , an emission driver 32 , and a protection circuit 33 are peripheral circuits formed on the TFT substrate 10 .

A scanning driver 31 drives the scanning lines of the TFT substrate 10 . Emission driver 32 drives the emission control line to control the light emission period of each pixel. The driver IC 34 is mounted using, for example, an anisotropic conductive film (ACF).

The protection circuit 33 prevents electrostatic breakdown of elements in the pixel circuit. The driver IC 34 supplies power and timing signals (control signals) to the scanning driver 31 and the emission driver 32 . In addition, driver IC 34 provides power and data signals to demultiplexer 36 .

The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 36 drives d times as many data lines as the number of output pins of the driver IC 34 by switching the output destination data line of the data signal from the driver IC 34 d times within the scanning period.

[Circuit configuration]
A plurality of pixel circuits are formed on the TFT substrate 10 for controlling currents to be supplied to anode electrodes of a plurality of sub-pixels (also simply called pixels). FIG. 2 shows a configuration example of a pixel circuit. Each pixel circuit includes a drive transistor T1, a selection transistor T2, an emission transistor T3, and a storage capacitor C1. The pixel circuit controls light emission of the OLED element E1. The transistors are TFTs. Transistors other than the drive transistor T1 are switch transistors.

A selection transistor T2 is a switch for selecting a sub-pixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and has a gate terminal connected to the scanning line 16 . A source terminal is connected to the data line 15 . The drain terminal is connected to the gate terminal of the drive transistor T1.

The drive transistor T1 is a transistor (drive TFT) for driving the OLED element E1. The drive transistor T1 is a p-channel low-temperature polysilicon TFT, and its gate terminal is connected to the drain terminal of the selection transistor T2. The source terminal of the driving transistor T1 is connected to the drain terminal of the emission transistor T3, and the drain terminal is connected to the OLED element E1. A holding capacitor C1 is formed between the gate terminal of the driving transistor T1 and the power supply line 18 .

The emission transistor T3 is a switch that controls supply and stop of the driving current to the OLED element E1. The emission transistor T3 is a p-channel type low-temperature polysilicon TFT, and its gate terminal is connected to the emission control line 17 . A source terminal of the emission transistor T3 is connected to the power line 18 . The drain terminal is connected to the source terminal of the drive transistor T1.

Next, the operation of the pixel circuit will be described. The scanning driver 31 outputs a selection pulse to the scanning line 16 to turn on the selection transistor T2. A data voltage supplied from the driver IC 34 via the data line 15 is stored in the holding capacitor C1. The holding capacitor C1 holds the stored voltage throughout one frame period. The hold voltage causes the conductance of the driving transistor T1 to change in an analog manner, and the driving transistor T1 supplies a forward bias current corresponding to the emission gradation to the OLED element E1.

The emission transistor T3 is located on the drive current supply path. The emission driver 32 outputs a control signal to the emission control line 17 to control on/off of the emission transistor T3. When the emission transistor T3 is on, a drive current is supplied to the OLED element E1. This supply is stopped when the emission transistor T3 is in the off state. By controlling the on/off of the emission transistor T3, the lighting period (duty ratio) within one frame period can be controlled. Note that the pixel circuit in FIG. 2 is an example, and the pixel circuit may have other configurations.

[Configuration of TFT substrate]
A configuration example of a TFT substrate including a low-temperature polysilicon TFT and an oxide semiconductor TFT will be described below. The oxide semiconductor is, for example, IGZO. The configuration described herein can be applied to TFT substrates including other types of oxide semiconductor TFTs.

FIG. 3 schematically shows a cross-sectional structure of part of the TFT substrate. A low-temperature polysilicon TFT 141 , an oxide semiconductor TFT 142 , a storage capacitor 143 and an OLED element 144 are formed on the insulating substrate 101 . These correspond to the drive transistor T1, selection transistor T2, storage capacitor C1 and OLED element E1 shown in FIG. 2, respectively.

The insulating substrate 101 is a flexible or inflexible substrate made of resin or glass. Low temperature polysilicon TFT 141 includes low temperature polysilicon portion 102 . The low temperature polysilicon portion 102 is included in the low temperature polysilicon layer and is an island-like low temperature polysilicon film or part of a larger low temperature polysilicon film. The low temperature polysilicon portion 102 includes source/drain regions 104 and 105 and a channel region 103 between the source/drain regions 104 and 105 in the in-plane direction.

The source/drain regions 104 and 105 are formed of low-temperature polysilicon whose resistance is lowered by high-concentration impurity implantation, and are connected to the source/drain electrode portions 109 and 110 . The channel region 103 is formed of low-temperature polysilicon (high-resistance low-temperature polysilicon) that is not of low resistance.

A low temperature polysilicon portion 102 is included in the low temperature polysilicon layer. The low temperature polysilicon layer includes low temperature polysilicon portions of low temperature polysilicon TFTs of a plurality of pixel circuits. A low temperature polysilicon layer is formed (directly) on an insulating substrate 101 . Although the low temperature polysilicon portion 102 contacts the insulating substrate 101 in the example of FIG. 3, there may be another insulating layer (eg, a silicon nitride layer) between them.

The low temperature polysilicon TFT 141 has a top gate structure. Low temperature polysilicon TFT 141 may include a bottom gate in addition to a top gate. The low temperature polysilicon TFT 141 further includes a gate electrode portion 107 and a gate insulator portion existing between the gate electrode portion 107 and the channel region 103 in the stacking direction. The gate insulator portion is the portion of the insulator layer 106 between the gate electrode portion 107 and the channel region 103 . Insulator layer 106 comprises the gate insulator portion of other low temperature polysilicon TFTs. The channel region 103 , the gate insulator portion, and the gate electrode portion 107 are stacked in this order from below (from the substrate side), and the gate insulator portion is in contact with the channel region 103 and the gate electrode portion 107 . ing.

The gate electrode portion 107 is formed of a conductor and included in the conductor layer. The gate electrode portion 107 is made of metal, for example. The metal material is arbitrary, and Mo, W, Nb, Al, etc. are used, for example. Insulator layer 106 is formed of silicon oxide in this example.

An interlayer insulating film 108 is formed to cover the low temperature polysilicon portion 102 , the gate insulator portion, and the gate electrode portion 107 . The interlayer insulating film 108 is an insulator layer. The interlayer insulating film 108 is, for example, a silicon nitride film. Source/drain electrode portions 109 and 110 are formed on the interlayer insulating film 108 and connected to the source/drain regions 104 and 105 through contact holes in the interlayer insulating film 108 and the insulator layer 106 . Al or Ti, for example, can be used as the material of the source/drain electrode portions 109 and 110 .

The storage capacitor 143 includes a lower electrode portion 111 , an upper electrode portion 120 facing the lower electrode portion 111 , and an insulator portion between the lower electrode portion 111 and the upper electrode portion 120 . The lower electrode portion 111 is continuous with the source/drain electrode portion 110 on the interlayer insulating film 108 . The lower electrode portion 111 is included in the same conductor layer as the source/drain electrode portions 109 and 110 .

An interlayer insulating film 112 is laminated on the interlayer insulating film 108 . The interlayer insulating film 112 is, for example, a silicon oxide film. The interlayer insulating film 112 is formed so as to cover the lower electrode portion 111 , the source/drain electrode portions 109 and 110 and the interlayer insulating film 108 . In a region between lower electrode portion 111 and upper electrode portion 120, interlayer insulating film 112 forms an insulator portion.

The oxide semiconductor TFT 142 includes the oxide semiconductor portion 113 . The oxide semiconductor portion 113 is, for example, one oxide semiconductor active film or a portion thereof, and includes source/drain regions 115 and 116 and a channel region 114 between the source/drain regions 115 and 116 in the in-plane direction. include. The oxide semiconductor portion 113 is also called an active layer of the oxide semiconductor TFT.

The source/drain regions 115 and 116 are made of IGZO with low resistance and are connected to the source/drain electrode portions 122 and 123 . The channel region 114 is formed of IGZO (high resistance IGZO) that is not of low resistance.

The oxide semiconductor portion 113 is included in the oxide semiconductor layer. The oxide semiconductor layer includes oxide semiconductor portions of the plurality of oxide semiconductor TFTs. The oxide semiconductor layer is formed over the interlayer insulating film 112 .

The oxide semiconductor TFT 142 has a top gate structure. The oxide semiconductor TFT 142 may include a bottom gate in addition to the top gate. The oxide semiconductor TFT 142 further includes a gate electrode portion 119 and a gate insulator portion present between the gate electrode portion 119 and the channel region 114 in the stacking direction. The gate insulator portion is the portion of the insulator layer 117 between the gate electrode portion 119 and the channel region 114 .

The channel region 114 , the gate insulator portion, and the gate electrode portion 119 are stacked in this order from below (from the substrate side), and the gate insulator portion is in contact with the channel region 114 and the gate electrode portion 119 . ing. The gate electrode portion 119 is formed of a conductor and included in the conductor layer. The gate electrode portion 119 is made of metal, for example. The metal material is arbitrary, and Mo, W, Nb, Al, etc. are used, for example. The insulator layer 117 can be made of silicon oxide, for example.

Although FIG. 3 shows one low-temperature polysilicon TFT and one oxide semiconductor TFT as an example, other low-temperature polysilicon TFTs and oxide semiconductor TFTs in the pixel circuit have similar structures.

An interlayer insulating film 121 is formed to cover the oxide semiconductor portion 113 , the gate insulator portion, and the gate electrode portion 119 of the oxide semiconductor TFT 142 and the upper electrode portion 120 of the storage capacitor 143 . The interlayer insulating film 121 partially covers the interlayer insulating film 112 . The interlayer insulating film 121 is, for example, a silicon oxide film.

Source/drain electrode portions 122 and 123 of the oxide semiconductor TFT 142 are formed on the interlayer insulating film 121 . The source/drain electrode portions 122 and 123 are connected to the source/drain regions 115 and 116 of the oxide semiconductor TFT 142 through contact holes formed in the interlayer insulating film 121 and the insulator layer 117 .

Furthermore, the connection portion 129 continuous with the source/drain electrode portion 123 is connected to the upper electrode portion 120 of the storage capacitor 143 through a contact hole formed in the interlayer insulating film 121 and the insulating layer 117, and the interlayer insulating film It is connected to the gate electrode portion 107 of the low-temperature polysilicon TFT 141 through contact holes formed in 121 , 112 , 108 and the insulator layer 117 .

A connection portion 129 interconnects the source/drain electrode portion 123 , the upper electrode portion 120 and the gate electrode portion 107 . The source/drain electrode portions 122, 123 and the connection portion 129 are included in the conductor layer. Any material can be used for the conductor layer, and for example, Al or Ti can be used.

An insulating planarization film 124 is laminated so as to cover the exposed portions of the conductor layer and the interlayer insulating film 121 . The planarizing film 124 can be made of, for example, an organic material. An anode electrode portion 125 is formed on the planarizing film 124 . The anode electrode portion 125 is connected to the source/drain electrode portion 109 of the low-temperature polysilicon TFT 141 through contact holes in the planarizing film 124 , the interlayer insulating films 121 and 112 and the insulator layer 117 .

The anode electrode section 125 includes three layers, for example, a transparent film such as ITO or IZO, a reflective film made of metal such as Ag, Mg, Al, Pt or an alloy containing these metals, and the transparent film. In addition, the three-layer structure of the anode electrode part 125 is an example, and two layers may be sufficient.

An insulating pixel defining layer 126 is formed over the anode electrode portion 125 to separate the OLED elements 144 . Pixel defining layer 126 can be formed of, for example, an organic material. An organic light emitting layer 127 is formed on the anode electrode part 125 . The organic light emitting film 127 is composed of, for example, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer from the bottom layer side. The laminated structure of the organic light-emitting film 127 is determined by design.

Furthermore, a cathode electrode part 128 is formed on the organic light emitting film 127 . The cathode electrode portion 128 of one OLED element 144 is part of a continuous conductor film. The cathode electrode portion 128 transmits part of the visible light from the organic light-emitting film 127 . A laminated film of the anode electrode portion 125 , the organic light emitting film 127 and the cathode electrode portion 128 formed in the opening of the pixel defining layer 126 constitutes the OLED element 144 .

Next, a CMOS (Complementary Metal-Oxide-Semiconductor) circuit configuration included in the driver circuits 31 and 32 on the TFT substrate will be described. FIG. 4 shows an example of a CMOS circuit. The CMOS circuit includes a p-channel low temperature polysilicon TFT 201 and an n-channel oxide semiconductor TFT 202 . A source/drain of the low-temperature polysilicon TFT 201 is connected to a source/drain of the n-channel oxide semiconductor TFT 202 . Gates of the low-temperature polysilicon TFT 201 and the oxide semiconductor TFT 202 are connected, and the same signal is input to them.

FIG. 5 schematically shows a cross-sectional structural example of the CMOS circuit shown in FIG. Differences from the cross-sectional structure example shown in FIG. 3 will be mainly described. In the structural example shown in FIG. 5, the storage capacitor 143 of the structural example shown in FIG. 3 is deleted. Further, the source/drain electrode portion 210 of the low-temperature polysilicon TFT 201 and the source/drain electrode portion 223 of the oxide semiconductor TFT 202 are connected, and the gate electrode portion 207 and the gate electrode portion 219 are connected.

In one example, the low temperature polysilicon TFT 201 in FIG. 5 has a configuration similar to the low temperature polysilicon TFT 141 shown in FIG. These sizes can be different. The low temperature polysilicon TFT 201 includes a low temperature polysilicon portion 208 , a gate insulator portion and a gate electrode portion 207 . The gate insulator portion is the portion of insulator layer 106 between gate electrode portion 207 and low temperature polysilicon portion 208 .

The low temperature polysilicon portion 208 includes a channel region 203 and source/drain regions 204,205. The source/drain electrode portions 209 and 210 are connected to the source/drain regions 204 and 205 through contact holes in the interlayer insulating film 108 and the insulator layer 106 .

The low temperature polysilicon portion 208, the gate insulator portion, the gate electrode portion 207, and the source/drain electrode portions 209, 210 are respectively the low temperature polysilicon portion 102, the gate insulator portion, the gate electrode portion 107 and the gate electrode portion 107 shown in FIG. It corresponds to the source/drain electrode portions 109 and 110 . Corresponding components are included in the same layer.

In one example, the oxide semiconductor TFT 202 in FIG. 5 has the same configuration as the oxide semiconductor TFT 142 shown in FIG. These sizes can be different. The oxide semiconductor TFT 202 includes an oxide semiconductor portion 213 , a gate insulator portion and a gate electrode portion 219 . The gate insulator portion is a portion of the insulator layer 117 between the gate electrode portion 219 and the oxide semiconductor portion 213 .

The oxide semiconductor portion 213 includes a channel region 214 and source/drain regions 215 and 216 . The oxide semiconductor portion 213, the gate insulator portion and the gate electrode portion 219 respectively correspond to the oxide semiconductor portion 113, the gate insulator portion and the gate electrode portion 119 illustrated in FIG. Corresponding components are included in the same layer.

The connecting portion 229 is continuous with the source/drain electrode portion 223 of the oxide semiconductor TFT 202 and is connected to the source/drain electrode portion of the low-temperature polysilicon TFT 201 via a contact hole penetrating the interlayer insulating films 112 and 121 and the insulating layer 117 . 210. The connection portion 230 is connected to the gate electrode portion 219 of the oxide semiconductor TFT 202 via a contact hole penetrating the interlayer insulating film 121 and the planarizing film 124 . The connecting portion 230 is further connected to the gate electrode portion 207 of the low-temperature polysilicon TFT 201 via a contact hole penetrating the interlayer insulating films 108 , 112 , 121 , the planarizing film 124 and the insulating layer 117 .

[Structure and manufacture of oxide semiconductor TFT]
An example of a method for manufacturing an oxide semiconductor TFT is described below. Figures 6A-6D show one method, in which oxygen ions are implanted into the oxide semiconductor through the gate insulator. With reference to FIG. 6A, the manufacturing method forms the oxide semiconductor part 113, after forming the interlayer insulation film 112 using CVD(Chemical Vapor Deposition), for example. The oxide semiconductor portion 113 is formed, for example, by forming an oxide semiconductor layer by a sputtering method or the like, patterning a mask by photolithography, and then etching the oxide semiconductor layer.

Next, the process forms insulator layer 117 using, for example, CVD. Furthermore, the manufacturing method is to form a metal film by a sputtering method or the like, pattern a mask by photolithography, and then etch the metal film to form the gate electrode portion 119 .

Referring to FIG. 6B, the manufacturing method implants oxygen ions into oxide semiconductor portion 113 through insulator layer 117 using gate electrode portion 119 as a mask. As described above, according to one embodiment of the present specification, an oxygen element is introduced in advance into the portions 151 and 152 of the oxide semiconductor portion 113 that will be the source/drain regions as a substance that compensates for oxygen vacancies.

Referring to FIG. 6C, the manufacturing method forms an interlayer insulating film 121 so as to cover the gate electrode portion 119 and the insulator layer 117 . CVD, for example, can be used to form the interlayer insulating film 121 .

Referring to FIG. 6D, the manufacturing method forms contact holes in the interlayer insulating film 121 and the insulator layer 117 by etching after mask patterning by photolithography. Further, the manufacturing method is to form a metal film by a sputtering method or the like, pattern the mask by photolithography, and then etch the metal film to form the source/drain electrode portions 122 and 123 . A heat treatment is then performed.

Oxygen vacancies are formed in the portions 151 and 152 in which the oxygen element is implanted in advance by contact with the metal source/drain electrode portions 122 and 123 . Specifically, the source/drain electrode portions 122 and 123 extract oxygen from the oxide semiconductor, and oxygen vacancies increase in the oxide semiconductor. Oxygen vacancies diffuse from contact portions with source/drain electrode portions 122 and 123 toward channel region 114 . Oxygen vacancies lower the resistance of the portions 151 and 152 to form low-resistance source/drain regions 151 and 152 .

As described above, portions 151 and 152 are pre-implanted with oxygen. Oxygen suppresses the diffusion (generation) of oxygen vacancies. Therefore, it is possible to prevent excessive expansion to the inside of a region (overlap region) that overlaps with the gate electrode portion 119 in a plan view (viewed in the stacking direction). In the example above, the overlap region is the channel region 114 . Oxygen vacancies may be formed by other factors such as hydrogen in the insulator layer, but pre-implanted oxygen can similarly suppress generation of excessive oxygen vacancies.

FIG. 7 schematically shows the oxygen concentration distribution in the oxide semiconductor portion 113 and the gate insulator layer 117 in cross section. The acceleration voltage for the oxygen ion implantation is controlled such that the depthwise implanted oxygen concentration is highest in the oxide semiconductor portion 113 .

Oxygen due to the ion implantation exists not only in the oxide semiconductor portion 113 but also in the gate insulator layer 117 . Oxygen ions are implanted using the gate electrode portion 119 as a mask. Therefore, in plan view, the oxygen concentration in the region 171 outside the gate electrode portion 119 is higher than the oxygen concentration in the region 172 covered with the gate electrode portion 119 . The regions 171 and 172 are adjacent to the lower oxide semiconductor portion 113 . The regions 171 and 172 include positions near the oxide semiconductor portion 113 . In plan view, region 172 includes the center of gravity of gate electrode portion 119 .

A region 171 is a region between the source/drain (S/D) electrode portion 122 and the gate electrode portion 119 , and part of the oxygen ions pass through this region 171 and are implanted into the oxide semiconductor portion 113 . , some of the oxygen ions remain in the region 171 .

An oxygen concentration distribution similar to that of the gate insulator layer 117 may also appear in the interlayer insulating film 112 immediately below the oxide semiconductor portion 113 . Specifically, in the region adjacent to the oxide semiconductor portion 113 in the interlayer insulating film 112 , the oxygen concentration in the portion facing the region 171 is higher than the oxygen concentration in the portion facing the region 172 .

In the oxide semiconductor portion 113, as described above, oxygen is extracted by the source/drain electrode portions 122 and 123, and oxygen vacancies increase from the channel region 114 toward the vicinity of the source/drain electrode portions 122 and 123. The amount of oxygen to be extracted increases as the source/drain electrode portions 122 and 123 are closer.

In the example of FIG. 7, region 155 is closer to source/drain electrode portion 122 than region 156 is. The region 156 is located between the region 155 and the region overlapping the gate electrode portion 119 (the channel region 114 in this example). The oxygen concentration in region 155 is lower than the oxygen concentration in region 156 . Also, the oxygen concentration in region 156 is higher than the oxygen concentration in channel region 114 . This configuration can effectively prevent the low-resistance region from entering the channel region 114 .

The region 156 is located outside the gate electrode portion 119 in a plan view, and located immediately before the outer edge of the gate electrode portion 119 when viewed from the source/drain electrode portion 122 . Channel length is defined in the left-right direction in FIG. That is, region 156 is adjacent to and near the boundary that defines the channel length of channel region 114 .

For example, the oxygen concentration distribution in the oxide semiconductor portion 113 shows a lower oxygen concentration at a position overlapping with the center of gravity of the gate electrode portion 119 in plan view, and a higher oxygen concentration at a position immediately before the channel region 114 in the region 156 . show. Note that the description of regions 155, 156 can also be applied to the opposite source/drain regions.

As described above, by implanting oxygen outside the overlap region with the gate electrode portion 119 in the oxide semiconductor portion 113 , it is possible to effectively suppress a decrease in resistance due to diffusion of oxygen vacancies into the channel region 114 . As a result, an oxide semiconductor TFT having a desired characteristic in which the distance Loff between the gate electrode portion 119 and the source/drain electrode portions 122 and 123 is small becomes possible, and high definition and high density of the TFT substrate are realized. be.

In the above example, oxygen ions are implanted into the oxide semiconductor portion 113 before the source/drain electrode portions 122 and 123 are formed. As another example, oxygen ions may be implanted into the oxide semiconductor portion 113 after the source/drain electrode portions 122 and 123 are formed.

FIG. 8 shows an example of implanting oxygen ions into the oxide semiconductor portion 113 after the source/drain electrode portions 122 and 123 are formed. In the gate insulator layer 117, the oxygen concentration in the region 173 covered with the metal layer including the source/drain electrode portions 122 and 123 and the oxygen concentration in the region 172 under the gate electrode portion 119 are substantially equal. In addition, the oxygen concentration of the region 174 outside the metal layer including (the metal layer including) the gate electrode portion 119 and the source/drain electrode portions 122 and 123 is higher than the oxygen concentration of the regions 172 and 173 . The description with reference to FIG. 7 can be applied to the oxygen concentration of the oxide semiconductor portion 113 .

Next, an example of another method for manufacturing an oxide semiconductor TFT will be described. Figures 9A-9D illustrate another method of fabricating an oxide semiconductor TFT, etching away the gate insulator and implanting impurities into the oxide semiconductor.

Next, referring to FIG. 9A, the manufacturing method forms an oxide semiconductor portion 163 after forming an interlayer insulating film 162 using, for example, CVD. The oxide semiconductor portion 163 is formed, for example, by forming an oxide semiconductor layer by a sputtering method or the like, patterning a mask by photolithography, and then etching the oxide semiconductor layer.

Next, the process forms insulator layer 176 using, for example, CVD. Further, a metal film is formed by a sputtering method or the like, and after patterning a mask by photolithography, the metal film is etched to form the gate electrode portion 169 .

Referring to FIG. 9B, the manufacturing method uses gate electrode portion 169 as a mask to etch insulator layer 176 to form gate insulator portion 177 . Accordingly, the insulator on the region of the oxide semiconductor portion 163 not covered with the gate electrode portion 169 is removed and exposed.

After that, oxygen ions are implanted into the oxide semiconductor portion 163 . As described above, according to one embodiment of the present specification, an oxygen element is introduced in advance into the portions 165 and 166 of the oxide semiconductor portion 163 that will be the source/drain regions as a substance that compensates for oxygen vacancies.

Referring to FIG. 9C, the manufacturing method forms an interlayer insulating film 181 so as to cover the gate electrode portion 169 and the insulator layer 178 . CVD, for example, can be used to form the interlayer insulating film 181 . Referring to FIG. 9D, the manufacturing method forms contact holes in the interlayer insulating film 181 and the insulator layer 178 by etching after mask patterning by photolithography. Further, the manufacturing method is to form a metal film by a sputtering method or the like, pattern the mask by photolithography, and then etch the metal film to form the source/drain electrode portions 182 and 183 . A heat treatment is then performed.

Oxygen vacancies are formed in the portions 165 and 166 where the oxygen element is implanted in advance by contact with the metal source/drain electrode portions 182 and 183 . Specifically, the source/drain electrode portions 182 and 183 extract oxygen from the oxide semiconductor, and oxygen vacancies increase in the oxide semiconductor. Oxygen vacancies diffuse from contact portions with source/drain electrode portions 182 and 183 toward channel region 164 . Due to the oxygen deficiency, the resistance of the portions 165 and 166 is reduced, and low resistance source/drain regions 167 and 168 are formed. As described above, the oxide semiconductor TFT 192 is configured.

FIG. 10 schematically shows the oxygen concentration distribution in the interlayer insulating film 162 formed by the method described with reference to FIGS. 9A-9D. The description of the oxide semiconductor portion 113 with reference to FIG. 7 can be applied to the oxygen concentration distribution of the oxide semiconductor portion 163 . The oxygen ion implantation is controlled such that the implanted oxygen concentration is highest in the oxide semiconductor portion 163 .

As described with reference to FIGS. 9A to 9D, the exposed oxide semiconductor portion 163 is irradiated with oxygen ions using the gate electrode portion 169 as a mask. Therefore, oxygen that has passed through the oxide semiconductor portion 163 is injected into the interlayer insulating film 162 immediately below the oxide semiconductor portion 163 .

The oxygen concentration of the region 621 outside the gate electrode portion 169 in plan view is higher than the oxygen concentration of the region 622 covered with the gate electrode portion 169 . The regions 621 and 622 are adjacent to the oxide semiconductor portion 163 on the upper side. The regions 621 and 622 include positions near the oxide semiconductor portion 163 . In plan view, region 622 includes the center of gravity of gate electrode portion 169 . A region 621 is a region between the source/drain (S/D) electrode portion 182 and the gate electrode portion 169, and part of the oxygen ions pass through the oxide semiconductor portion 163 and are implanted into this region. be.

Another configuration example of an oxide semiconductor TFT and a manufacturing method thereof will be described. In the configuration examples described with reference to FIGS. 7 to 10, the distance Loff between the gate electrode portion and the source/drain electrode portions on both sides is common. In other configuration examples, one distance may be longer than the other distance. Moreover, if there is no problem of diffusion of oxygen vacancies into the channel region due to the long distance Loff, oxygen ions do not need to be implanted into at least part of the source/drain regions with the long distance Loff.

Another example of the method for manufacturing an oxide semiconductor TFT will be described with reference to FIGS. 11A to 11C. Referring to FIG. 11A, the manufacturing method forms an oxide semiconductor portion 313 after forming an interlayer insulating film 312 using, for example, CVD. The oxide semiconductor portion 313 is formed, for example, by forming an oxide semiconductor layer by a sputtering method or the like, patterning a mask by photolithography, and then etching the oxide semiconductor layer.

Next, the method forms insulator layer 317 using, for example, CVD. Further, the manufacturing method is to form a metal film by a sputtering method or the like, pattern the mask by photolithography, and then etch the metal film to form the gate electrode portion 319 .

Further, in the manufacturing method, the entire gate electrode portion 319 and part of the source/drain regions having a long distance Loff are covered with a protective resist 381 . The manufacturing method implants oxygen ions into the region outside the protective resist 381 . Accordingly, oxygen is injected into the portions 352 and 351 of the oxide semiconductor portion 313 . Portion 352 corresponds to the source/drain region with short distance Loff, and portion 351 corresponds to part of the source/drain region with long distance Loff. The portion 352 is adjacent to the gate electrode portion 319 in plan view. The portion 351 is separated from the gate electrode portion 319 in plan view.

Referring to FIG. 11B, the manufacturing method removes protective resist 381 and implants impurity ions into oxide semiconductor portion 313 through insulator layer 317 using gate electrode portion 119 as a mask. Examples of impurity elements are B, He, Ne, Ar, H, P. The resistance of the portions 353 and 354 of the oxide semiconductor portion implanted with impurity ions is reduced.

After that, the manufacturing method is to form an interlayer insulating film (not shown) so as to cover the gate electrode portion 319 and the insulator layer 317, and furthermore, form a contact hole by etching after mask patterning by photolithography. It is formed on the membrane and insulator layer 317 .

Referring to FIG. 11C, the manufacturing method is to form a metal film by a sputtering method or the like, pattern a mask by photolithography, and then etch the metal film to form source/drain electrode portions 322 and 323 . A heat treatment is then performed.

Oxygen vacancies are formed in the oxide semiconductor portion 313 due to the contact with the source/drain electrode portions 322 and 323 . As described with reference to the other examples above, regions 356 and 357 having different oxygen concentrations are formed in the source/drain regions having a short distance Loff. A region 357 adjacent to the channel region 314 has a higher oxygen concentration than the channel region 314 and the region 356 . On the other hand, a region corresponding to the region 357 is not formed in the source/drain region 355 with the long distance Loff.

Note that for the oxygen concentration distributions of the insulators 317 and 312 directly above and below the oxide semiconductor portion 313, the same description as in the other examples above can be applied to the regions into which oxygen ions are implanted.

[Substance that compensates for oxygen deficiency]
Next, a substance that compensates for oxygen deficiency will be described. Among oxygen isotopes, ¹⁶ O is selected as oxygen ions implanted to compensate for oxygen vacancies. Because ¹⁶ O is selectively implanted, the isotope ratio in the oxygen-implanted region differs from the isotope ratio in nature.

The ratio of isotopic elements of oxygen existing in nature is as follows. ¹⁶ O is 99.76%, ¹⁷ O is 0.04% and ¹⁸ O is 0.21%. A region into which ¹⁶ O is ion-implanted has a larger abundance ratio of ¹⁶ O than a region into which it is not implanted. That is, the abundance ratio of ¹⁷ O and ¹⁸ O becomes smaller.

Other than oxygen, for example, fluorine (F), nitrogen (N), or sulfur (S) can be used as a substance that compensates for oxygen deficiency. FIG. 12 shows experimental results of implanting different ions into IGZO. The implanted ions are fluorine ions, nitrogen ions and oxygen ions. In the experiment, after the IGZO single-layer film was produced, ions selected from the above ions were implanted and annealed at 300.degree. In the graph of FIG. 12, the horizontal axis indicates the pre-implantation, post-implantation, and post-annealing phases, and the vertical axis indicates the sheet resistance.

As shown in FIG. 12, fluorine F, nitrogen N and oxygen O all make the IGZO film highly resistive after implantation. The resistance values of fluorine (F) and nitrogen (N) are higher than that of oxygen (O). Annealing causes oxygen O to further increase the resistance. On the other hand, fluorine F and nitrogen N lower the resistance. However, even after annealing, due to the fluorine F or nitrogen N implantation, the resistance value is higher than before the implantation. As shown in FIG. 12, fluorine (F) and nitrogen (N), like oxygen (O), can have the effect of suppressing the resistance of the oxide semiconductor from being lowered. In addition, sulfur S is a homologous element of oxygen O, and can exhibit an effect of compensating for oxygen vacancies like oxygen.

When fluorine F, nitrogen N, or sulfur S is implanted instead of oxygen O, the implantation energy (eV) may be controlled so that the element concentration profile in the stacking direction shows a peak within the oxide semiconductor portion.

[Oxygen ion implantation region]
Another example of the region into which oxygen ions are implanted in the oxide semiconductor portion is described below. The above example implants oxygen ions into the source/drain regions. The example described below implants oxygen ions into the channel region. More specifically, oxygen ions are implanted in the vicinity of the boundary (width edge) that defines the width of the channel region. Thereby, the hump characteristic of the oxide semiconductor TFT can be suppressed.

FIG. 13 is a plan view showing an example of implanting oxygen ions into the source/drain regions 115, 116 as described with reference to FIGS. 6A-7. The channel width is defined in the vertical direction (W direction) in FIG. 13, and the channel length is defined in the horizontal direction (L direction) in FIG. The boundary that defines the channel length is the boundary between the source/drain regions and the channel region.

FIG. 14 is a plan view showing an example of implanting oxygen ions into the width edge of the channel region. In the example of FIG. 14, oxygen ions are implanted into the width edges of the source/drain regions in addition to the channel region. In the configuration example of FIG. 14, there are source/drain regions 415 between the source/drain electrode portion 422 and the gate electrode portion 419, and there are source/drain regions 416 between the source/drain electrode portion 423 and the gate electrode portion 419. There is

Oxygen ion-implanted regions 451 and 452 are formed at both ends of the oxide semiconductor portion in the width direction (W direction). The oxygen concentrations of the regions 451 and 452 are higher than the oxygen concentration at the center (including the center of gravity of the gate electrode portion) in the width direction of the oxide semiconductor portion. Oxygen ion implantation increases the resistance of the oxide semiconductor as described with reference to FIG. In other words, the reduction in resistance at the ends of the channel width is suppressed. Thereby, the hump characteristic of the oxide semiconductor TFT can be suppressed.

Note that, instead of oxygen, other elements described with reference to FIG. 12 may be used. It is not excluded to implant oxygen ions only at one width edge. Oxygen ions may not be implanted into the source/drain regions. In addition to the regions near the width edges of the channel region, oxygen ions may be implanted into the source/drain regions as described with reference to FIGS. 6A-11C.

FIG. 15A is a W-direction cross-sectional view showing an example of a method of implanting oxygen ions into the width end portion of the channel region. The manufacturing method forms the oxide semiconductor portion 414 after forming the interlayer insulating film 412 . These forming methods are as described with reference to FIG. 6A. In the manufacturing method, a protective resist 481 is formed so as to cover the central region of the oxide semiconductor portion 414 and expose the neighboring regions (width end portions) of the width edges. This step is performed prior to forming the metal layer containing the gate electrode portion. In the manufacturing method, oxygen ions are implanted using the protective resist 481 as a mask. Oxygen ions are thereby implanted into the width end regions 451 and 452 shown in FIG.

The interlayer insulating film 412 is directly under the oxide semiconductor portion 414 and is in direct contact therewith. Oxygen ions are implanted into a partial region of the interlayer insulating film 412 . A region 471 outside the oxide semiconductor portion 414 has a higher oxygen concentration than a region 472 covered with the oxide semiconductor portion 414 in plan view. Oxygen in the interlayer insulating film 412 can suppress fixed charges in the interlayer insulating film 412 and further suppress the resistance from becoming low at the ends of the channel width.

FIG. 15B is a W-direction cross-sectional view schematically showing the configuration of the oxide semiconductor portion 414 after the oxide semiconductor TFT is formed. As described with reference to FIG. 14, oxygen ion implantation regions 451 and 452 are formed at both ends defining the channel width. In the channel region, oxygen ions may be implanted in the vicinity of one or both of both ends (long channel ends) defining the channel length.

The configuration example of the oxide semiconductor TFT described with reference to FIGS. 3 to 15B includes a top gate. Features according to embodiments herein may be applied to oxide semiconductor TFTs that include a bottom gate electrode instead of a top gate electrode.

FIG. 16 shows one configuration example of a dual-gate TFT having a bottom gate electrode under the oxide semiconductor portion in addition to the top gate electrode portion over the oxide semiconductor portion. A bottom gate insulator portion 720 is formed on the bottom gate electrode portion 710 . Oxide semiconductor portions 730 and 731 are formed on the bottom gate insulator portion 720 . The resistance of the oxide semiconductor portion 731 is reduced. A top gate insulator portion 740 is formed on the oxide semiconductor portion 730 , and a top gate electrode portion 750 is formed on the top gate insulator portion 740 .

In one embodiment of the present specification, the top gate electrode portion 750 is formed in a pattern (shape) whose length in the channel length direction (horizontal direction in FIG. 16) is shorter than that of the bottom gate electrode portion 710 . In plan view, both ends (right and left ends in FIG. 16) of the top gate electrode portion 750 in the channel length direction are located inside both ends of the bottom gate electrode portion 710 in the channel length direction. An interlayer insulating film 760 is formed over the top gate insulator portion 740 and the oxide semiconductor portion 731 . An S/D electrode portion 770 is formed on the interlayer insulating film 760 and connected to the oxide semiconductor portion 731 through a contact hole 761 formed in the interlayer insulating film 760 .

FIG. 16 shows an example in which the top gate insulator portion 740 is etched along the top gate electrode portion 750. As in FIG. Introduce elements. Therefore, the oxygen concentration in the region 721 outside the bottom gate electrode portion 710 in plan view is substantially equal to the oxygen concentration in the region 722 overlapping the bottom gate electrode portion 710 and not overlapping the top gate electrode portion 750 in plan view. The oxygen concentration is higher than the region 723 overlapping the bottom gate electrode portion 710 and the top gate electrode portion 750 .

With such a configuration, it becomes possible to prevent the resistance from being lowered near the ends defining the channel length, as in the example of FIG. 9D. Since the gate electric field can be applied from both sides, there is an effect that a higher on-current can be obtained.

FIG. 17 shows one configuration example of a dual-gate TFT having a bottom gate electrode under the oxide semiconductor portion in addition to the top gate electrode portion over the oxide semiconductor portion. The difference from FIG. 16 is that the top gate electrode portion 750 is formed in a pattern longer in the channel length direction than the bottom gate electrode portion 710 . Both ends of the top gate electrode portion 750 in the channel length direction extend outside the bottom gate electrode portion 710 .

FIG. 17 shows an example in which the top gate insulator portion 740 is etched along the top gate electrode portion 750. As in the case of FIG. Introduce elements. Therefore, the oxygen concentration in a region 721 outside the bottom gate electrode portion 710 and the top gate electrode portion 750 in plan view is different from that in a region 722 overlapping the top gate electrode portion 750 outside the bottom gate electrode portion 710 in plan view. , higher than the oxygen concentration in a region 723 overlapping with the bottom gate electrode portion 710 and the top gate electrode portion 750 in plan view.

The configuration of FIG. 17, like the configuration of FIG. Since it is possible to apply a gate electric field from .theta.

Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. A person skilled in the art can easily change, add, or convert each element of the above-described embodiments within the scope of the present disclosure. A part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

Reference Signs List 1 OLED display device 10 TFT substrate 31 scanning driver 32 emission driver 101 insulating substrate 102 low-temperature polysilicon portion 106 insulating layer 107 gate electrode portion 111 lower electrode portion 113 oxide semiconductor portion 114 channel Regions 115, 116 Source/drain regions 117 Insulator layer 119 Gate electrode portion 120 Upper electrode portion 122, 123 Source/drain electrode portion 134 OLED element 141 Low-temperature polysilicon TFT 142 Oxide semiconductor TFT 143 retention capacity, 144 OLED element, 156, 171, 174, 621 high oxygen concentration region

Claims (16)

An oxide semiconductor thin film transistor device,
a gate electrode portion;
an oxide semiconductor portion;
a first source/drain electrode portion;
a second source/drain electrode portion;
including
The oxide semiconductor portion has a concentration distribution of an element capable of increasing the resistance of the oxide semiconductor,
The concentration distribution is
showing a first concentration at a center of gravity position of a channel region that overlaps the gate electrode portion in a plan view;
exhibiting a concentration higher than the first concentration in the vicinity of at least a portion of a boundary defining an outer peripheral edge of the channel region;
Oxide semiconductor thin film transistor device. The oxide semiconductor thin film transistor device according to claim 1,
the oxide semiconductor portion includes a first source/drain region on the side of the first source/drain electrode portion outside the channel region;
the concentration distribution exhibits a concentration higher than the first concentration in the vicinity of a boundary of the channel region in the first source/drain region;
Oxide semiconductor thin film transistor device. The oxide semiconductor thin film transistor device according to claim 1,
the element is one element selected from oxygen, fluorine, nitrogen and sulfur;
Oxide semiconductor thin film transistor device. The oxide semiconductor thin film transistor device according to claim 1,
The gate electrode portion is a top gate electrode portion,
Oxide semiconductor thin film transistor device. The oxide semiconductor thin film transistor device according to claim 2,
the oxide semiconductor portion includes a second source/drain region on the second source/drain electrode portion side outside the channel region;
the concentration distribution exhibits a higher concentration than the first concentration in the vicinity of a boundary of the channel region in the second source/drain region;
Oxide semiconductor thin film transistor device. The oxide semiconductor thin film transistor device according to claim 2,
the element is oxygen;
the concentration distribution exhibits a higher concentration in the first source/drain region near the boundary of the channel region than in a region in contact with the first source/drain electrode portion;
Oxide semiconductor thin film transistor device. The oxide semiconductor thin film transistor device according to claim 1,
wherein the concentration distribution exhibits a higher concentration than the first concentration near both ends defining a channel width in the channel region;
Oxide semiconductor thin film transistor device. The oxide semiconductor thin film transistor device according to claim 1,
further comprising a gate insulator layer between the gate electrode portion and the oxide semiconductor portion;
In the gate insulator layer, the oxygen concentration in the region outside the gate electrode portion in plan view is higher than the oxygen concentration in the region overlapping with the gate electrode portion in plan view,
Oxide semiconductor thin film transistor device. The oxide semiconductor thin film transistor device according to claim 1,
further comprising an insulator layer under the oxide semiconductor section;
the gate electrode portion is positioned above the oxide semiconductor portion;
In the insulator layer, the oxygen concentration in the region outside the gate electrode portion in plan view is higher than the oxygen concentration in the region overlapping with the gate electrode portion in plan view,
Oxide semiconductor thin film transistor device. The oxide semiconductor thin film transistor device according to claim 1,
the gate electrode portion is a top gate electrode portion positioned above the oxide semiconductor portion;
an insulating layer under the oxide semiconductor part; and a bottom gate electrode part having a pattern longer than the top gate electrode part in a channel length direction under the insulating layer,
In the insulating layer, the oxygen concentration in the region outside the bottom gate electrode portion in plan view is
is equal to the oxygen concentration of a region that overlaps with the bottom gate electrode portion but does not overlap with the top gate electrode portion in plan view,
higher than the oxygen concentration in a region overlapping with the bottom gate electrode portion and the top gate electrode portion in plan view;
Oxide semiconductor thin film transistor device. The oxide semiconductor thin film transistor device according to claim 1,
the gate electrode portion is a top gate electrode portion positioned above the oxide semiconductor portion;
an insulating layer under the oxide semiconductor part; and a bottom gate electrode part having a pattern shorter in a channel length direction than the top gate electrode part under the insulating layer,
In the insulating layer, the oxygen concentration in the region outside the bottom gate electrode portion and the top gate electrode portion in plan view is the oxygen concentration in the region that does not overlap the bottom gate electrode portion and overlaps the top gate electrode portion in plan view. concentration, and greater than the oxygen concentration in the region overlapping the bottom gate electrode portion and the top gate electrode portion in plan view,
Oxide semiconductor thin film transistor device. A method for manufacturing an oxide semiconductor thin film transistor device,
forming an oxide semiconductor layer;
forming a gate electrode portion;
implanting an element capable of increasing the resistance of the oxide semiconductor into a selected region of the oxide semiconductor layer;
forming a first source/drain electrode and a second source/drain electrode;
A method for manufacturing an oxide semiconductor thin film transistor device, comprising: A method for manufacturing an oxide semiconductor thin film transistor device according to claim 12,
the selected region exists outside the gate electrode portion;
implanting the element using the gate electrode portion as a mask;
A method for manufacturing an oxide semiconductor thin film transistor device. A method for manufacturing an oxide semiconductor thin film transistor device according to claim 12,
the element is an element selected from oxygen, fluorine, nitrogen and sulfur;
A method for manufacturing an oxide semiconductor thin film transistor device. A method for manufacturing an oxide semiconductor thin film transistor device according to claim 12,
the implantation of the element is performed before forming the first source/drain electrode and the second source/drain electrode;
A method for manufacturing an oxide semiconductor thin film transistor device. A method for manufacturing an oxide semiconductor thin film transistor device according to claim 12,
The selected regions are regions near both ends defining a channel width in a channel region overlapping with the gate electrode portion,
A method for manufacturing an oxide semiconductor thin film transistor device.

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