JP2023081268A - Bonding portion, electronic circuit board, and semiconductor package - Google Patents

Abstract

To provide a solder alloy, a solder bonding material, a solder paste and a semiconductor package that are capable of inhibiting separation of a solder bonding portion from a semiconductor element at an interface therebetween.SOLUTION: A solder alloy contains: 1.1 mass% or more and 8 mass% or less of Cu; 6 mass% or more and 20 mass% or less of Sb; 0.01 mass% or more and 0.5 mass% or less of Ni; and 0.001 mass% or more and 1 mass% or less of Co; with the balance being Sn.SELECTED DRAWING: Figure 1

Description

The present invention relates to solder alloys, solder joint materials, solder pastes and semiconductor packages.

2. Description of the Related Art A semiconductor package used in an electronic device is manufactured by bonding (die bonding) a semiconductor element onto a substrate using a bonding material, further performing wire bonding or the like, and then molding with a molding resin or the like.

There are various defects that occur in a semiconductor package, and one of the causes thereof is defective bonding between a semiconductor element and a substrate. This bonding failure is often caused by the bonding material. Soldering materials disclosed in Patent Documents 1 to 3 below, for example, have been proposed as bonding materials that suppress such poor bonding.

Patent Document 1 discloses a technique for suppressing a decrease in thermal conductivity at high temperatures for the purpose of suppressing a decrease in the thermal conductivity of a solder portion due to repeated heat generation of a semiconductor element and deterioration of the solder portion caused by this. Solder material that can be used, specifically, more than 5.0% by mass and 10.0% by mass or less of Sb, 2.0 to 4.0% by mass of Ag, and 0.1 to 0% of Ni A solder material containing 0.4% by mass and the balance being Sn and unavoidable impurities is disclosed.

In Patent Document 2, for the purpose of suppressing cracks in the solder portion caused by repeated heat generation of the semiconductor element and peeling between the solder portion and the substrate caused by this, Sb is added to exceed 5.0% by mass. A solder material containing 10.0% by mass or less, 2.0 to 4.0% by mass of Ag, 0.01 to 1.0% by mass of Ni, and the balance being Sn and inevitable impurities. and an object to be joined, at least one of which is a Cu or Cu alloy member, wherein the solder joint layer includes (Cu, A solder joint is disclosed comprising a first system comprising Ni) ₆ (Sn,Sb) ₅ and a second system comprising (Ni,Cu) ₃ (Sn,Sb) ₄ .

In Patent Document 3, a semiconductor element and a solder material are melted for the purpose of suppressing a decrease in thermal conductivity of the solder part due to repeated heat generation of the semiconductor element and deterioration of the solder part caused by this. A semiconductor device comprising a bonding layer, wherein the solder material contains more than 5.0% by mass and 10.0% by mass or less of Sb, 2.0 to 4.0% by mass of Ag, Ni, A semiconductor device containing 0.1 to 0.4% by mass of Sn and the balance being Sn and unavoidable impurities is disclosed.

Japanese Patent No. 6516013 Japanese Patent No. 6642865 Japanese Patent No. 6773143

By the way, in general, a thin film of Ti, Ni, or the like is formed in order from the semiconductor element side on the back electrode of a semiconductor element, particularly a power semiconductor element. This Ni film is formed for bonding between the power semiconductor element and a bonding material (particularly, a solder bonding material).
In addition, many soldering materials containing Sn are used.
Therefore, when the power semiconductor element and the substrate are soldered together, the Ni film and the Sn contained in the soldering material can precipitate a Ni—Sn intermetallic compound. This Ni—Sn intermetallic compound exists at the interface between the solder joint and the power semiconductor element, and can improve the joint strength between the two.

Here, a power semiconductor device, such as a Si device, self-heats and reaches a high temperature during its operation. In addition, since the heat generated from the Si element is radiated to the outside through the solder joints, the substrate, and the heat dissipation substrate in contact with the power semiconductor package, the Si element that is not in operation is in a cooled state.
Therefore, a repeated heat load is applied to the solder joints in contact with the Si element, which repeats heat generation and cooling. This repeated heat load accelerates the diffusion of the Ni—Sn intermetallic compound present at the interface between the solder joint and the Si element and the Ni film into the solder joint.

As described above, the Ni film and the Ni—Sn intermetallic compound contribute to improving the bonding strength between the Si element and the solder joint. Therefore, when these diffuse into the solder joint, the joint strength between the two is reduced. Further, if this diffusion continues, the composition (component) that contributes to the bonding between the two will disappear, which may cause separation at the interface. This detachment phenomenon also leads to a decrease in reliability of the power semiconductor package (in this specification, it means a semiconductor package using a power semiconductor element).

In recent years, there has been an increasing demand for power semiconductor packages capable of handling even higher voltages and larger currents. Therefore, power semiconductor devices with higher performance and capable of handling higher voltages and larger currents, such as SiC devices, GaN devices and Ga ₂ O ₃ devices (hereinafter referred to as “next-generation power semiconductor devices”). Usage is also on the rise.
Next-generation power semiconductor devices are superior in heat resistance to Si devices, and their operating temperatures are also high. Therefore, in a power semiconductor package using a next-generation power semiconductor element, the heat applied to the solder joints is further increased. Therefore, in this case, the diffusion of the Ni film and the Ni—Sn intermetallic compound into the solder joint and the resulting peeling phenomenon are more likely to occur.

However, regarding such a phenomenon, there is no disclosure or suggestion in Patent Documents 1 to 3 above.

An object of the present invention is to solve the above problems, and to provide a solder alloy, a solder joint material, a solder paste, and a semiconductor package that can suppress the separation of the solder joint and the semiconductor element at the interface between the two. .

The solder alloy of the present invention contains 1.1% by mass or more and 8% by mass or less of Cu, 6% by mass or more and 20% by mass or less of Sb, 0.01% by mass or more and 0.5% by mass or less of Ni, and Co 0.001% by mass or more and 1% by mass or less, and the balance is Sn.

The content of Cu and Ni in the solder alloy preferably satisfies the following formula (A).
Ni/(Cu+Ni)<0.1 (A)

Preferably, the solder alloy further contains 0.1% by mass or more and less than 3% by mass of Ag.

Preferably, the solder alloy further contains at least one of Al, Ti, Si, Fe and Ge in a total amount of 0.003% by mass or more and 0.5% by mass or less.

The solder joint material of the present invention uses the above solder alloy.

Further, the solder paste of the present invention contains powder made of the above solder alloy and flux.

Further, a semiconductor package of the present invention is a semiconductor package having a substrate, a semiconductor element, and a bonding portion for bonding the substrate and the semiconductor element, wherein the bonding portion is formed using the solder bonding material. It is a thing.

Further, a semiconductor package of the present invention is a semiconductor package having a substrate, a semiconductor element, and a joint portion for joining the substrate and the semiconductor element, wherein the joint portion is formed using the above solder paste. It is.

The joint of the present invention is a joint formed using a solder alloy, the solder alloy containing 1.1% by mass or more and 8% by mass or less of Cu and 6% by mass or more and 20% by mass or less of Sb. and 0.01% by mass or more and 0.5% by mass or less of Ni, 0.001% by mass or more and 1% by mass or less of Co, and 0.1% by mass or more and less than 3% by mass of Ag, and the balance is It consists of Sn, and the content of Cu and Ni satisfies the following formula (A).
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively.

Further, a joint according to another embodiment of the present invention is a joint formed using a solder joint material using a solder alloy, wherein the solder alloy contains 1.1% by mass or more and 8% by mass or less of Cu. , 6 mass% or more and 20 mass% or less of Sb, 0.01 mass% or more and 0.5 mass% or less of Ni, 0.001 mass% or more and 1 mass% or less of Co, and 0.1 mass% of Ag % or more and less than 3% by mass, the balance being Sn, and the content of Cu and Ni satisfies the following formula (A).
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively.

Further, a joint according to another embodiment of the present invention is a joint formed using a solder paste using a solder alloy, and the solder alloy contains 1.1% by mass or more and 8% by mass or less of Cu. , 6% by mass to 20% by mass of Sb, 0.01% by mass to 0.5% by mass of Ni, 0.001% by mass to 1% by mass of Co, and 0.1% by mass of Ag The content of Cu and Ni satisfies the following formula (A).
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively.

Further, the solder alloy used for forming the joint portion preferably further contains at least one of Al, Ti, Si, Fe and Ge in a total amount of 0.003% by mass or more and 0.5% by mass or less.

An electronic circuit board of the present invention is an electronic circuit board to which an electronic component is joined, wherein the electronic component is joined to the electronic circuit board by a joint formed using a solder alloy, and the solder alloy contains 1.1% by mass or more and 8% by mass or less of Cu, 6% by mass or more and 20% by mass or less of Sb, 0.01% by mass or more and 0.5% by mass or less of Ni, and 0.001% by mass of Co. % or more and 1% by mass or less, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the content of Cu and Ni satisfies the following formula (A).
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively.

Further, an electronic circuit board according to another aspect of the present invention is an electronic circuit board to which an electronic component is joined, wherein the electronic component is joined by a joint portion formed using a solder joint material using a solder alloy. It is joined to an electronic circuit board, and the solder alloy contains 1.1% to 8% by mass of Cu, 6% to 20% by mass of Sb, and 0.01% to 0.01% by mass of Ni. 5% by mass or less, 0.001% by mass or more and 1% by mass or less of Co, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the content of Cu and Ni is It satisfies the following formula (A).
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively.

Further, an electronic circuit board according to another aspect of the present invention is an electronic circuit board to which an electronic component is joined, wherein the electronic component is connected to the electronic component by a joint formed using a solder paste using a solder alloy. It is joined to a circuit board, and the solder alloy contains 1.1% by mass or more and 8% by mass or less of Cu, 6% by mass or more and 20% by mass or less of Sb, and 0.01% by mass or more and 0.5% by mass of Ni. % by mass or less, 0.001% by mass or more and 1% by mass or less of Co, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the contents of Cu and Ni are as follows. It satisfies the formula (A).
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively.

In the electronic circuit board, the solder alloy used for forming the joint further contains at least one of Al, Ti, Si, Fe and Ge in a total amount of 0.003% by mass or more and 0.5% by mass or less. is preferred.

A semiconductor package according to the present invention includes a substrate, a semiconductor element, a heat dissipation substrate, a joint portion that joins the substrate and the semiconductor element, and a solder joint portion that joins the substrate and the heat dissipation substrate, The solder joint contains 1.1% by mass or more and 8% by mass or less of Cu, 6% by mass or more and 20% by mass or less of Sb, 0.01% by mass or more and 0.5% by mass or less of Ni, and Co. Solder containing 0.001% by mass or more and 1% by mass or less, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the content of Cu and Ni satisfying the following formula (A) It is formed using an alloy.
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively.

A semiconductor package according to another aspect of the present invention includes a substrate, a semiconductor element, a heat dissipation board, a joint portion that joins the board and the semiconductor element, and a solder that joins the board and the heat dissipation board. The solder joint contains 1.1% by mass or more and 8% by mass or less of Cu, 6% by mass or more and 20% by mass or less of Sb, and 0.01% by mass or more and 0.5% by mass of Ni. % by mass or less, 0.001% by mass or more and 1% by mass or less of Co, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the contents of Cu and Ni are as follows. It is formed using a solder joint material using a solder alloy that satisfies formula (A).
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively.

A semiconductor package according to another aspect of the present invention includes a substrate, a semiconductor element, a heat dissipation board, a joint portion that joins the board and the semiconductor element, and a solder that joins the board and the heat dissipation board. The solder joint contains 1.1% by mass or more and 8% by mass or less of Cu, 6% by mass or more and 20% by mass or less of Sb, and 0.01% by mass or more and 0.5% by mass of Ni. % by mass or less, 0.001% by mass or more and 1% by mass or less of Co, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the contents of Cu and Ni are as follows. It is formed using a solder paste using a solder alloy that satisfies formula (A).
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively.

The solder alloy preferably further contains at least one of Al, Ti, Si, Fe and Ge in a total amount of 0.003% by mass or more and 0.5% by mass or less.

The semiconductor package is preferably a power semiconductor package.

The solder alloy, solder joint material, solder paste, and semiconductor package of the present invention can suppress separation between the solder joint and the semiconductor element at the interface.

1 is a schematic cross-sectional view showing a semiconductor package according to this embodiment; FIG. 4 is a temperature profile showing reflow temperature conditions when fabricating a test bonded body used in each test according to Examples and Comparative Examples. It is an example of an image of each test bonded body according to an example and a comparative example taken using an ultrasonic microscope, (a) is a bonded interface image (image A) taken from the Si chip side, and (b) is Fig. 2 represents a bonded interface image (image B) taken from the substrate side;

Hereinafter, one embodiment of the solder alloy, solder joint material, solder paste and semiconductor package of the present invention will be described in detail. It goes without saying that the present invention is not limited to these embodiments.

1. Solder alloy The solder alloy of the present invention contains 1.1% by mass to 8% by mass of Cu, 6% by mass to 20% by mass of Sb, and 0.01% by mass to 0.5% by mass of Ni. , 0.001% by mass or more and 1% by mass or less of Co, and the balance is Sn.

The solder alloy of the present embodiment contains 1.1% by mass or more and 8% by mass or less of Cu, so that intermetallic compounds with Sn, Ni and Co, such as Cu ₆ Sn ₅ intermetallic compounds, are formed in the solder joints formed. Compounds such as (Cu, Ni) ₆ Sn ₅ intermetallic compound, (Cu, Co) ₆ Sn ₅ intermetallic compound and (Cu, Co, Ni) ₆ Sn ₅ intermetallic compound can be deposited.

Among these intermetallic compounds, (Cu, Ni) ₆ Sn ₅ intermetallic compound, (Cu, Co) ₆ Sn ₅ intermetallic compound and (Cu, Co, Ni) ₆ Sn ₅ intermetallic compound (hereinafter referred to as are collectively referred to as "Cu, Ni, and Co-based intermetallic compounds".) are likely to precipitate at and near the interface between the semiconductor element and the solder joint during solder bonding, and these intermetallic compounds form a bond between the semiconductor element and the solder. It is presumed that this can contribute to the suppression of the delamination phenomenon at the interface with the joint.

That is, as described above, the Ni film formed on the back electrode of the semiconductor element, particularly the power semiconductor element, is likely to diffuse into the solder joint due to the heat load repeatedly received from the power semiconductor element. The same applies to Ni—Sn intermetallic compounds precipitated by Sn contained in the Ni film and the solder alloy when the semiconductor element and the substrate are soldered together.
Depending on the type of power semiconductor element, there are also those in which a thin film made of Ag or Au is further formed on the Ni film. However, since both Ag and Au are elements that easily diffuse into the solder joint, it is difficult to suppress the diffusion of the Ni film by the presence of these thin films.

On the other hand, the Ni film contributes to the bonding strength between the power semiconductor element and the solder joint. That is, the Ti film formed on the power semiconductor element side of the Ni film is less likely to deposit an intermetallic compound with Sn contained in the solder alloy. Therefore, the Ni film is formed to facilitate bonding between the power semiconductor element and the solder joint.

Therefore, the more the Ni film and the Ni—Sn intermetallic compound diffuse into the solder joint, the more the joint strength between the power semiconductor element and the solder joint is reduced. Ultimately, a peeling phenomenon may occur at the interface between the power semiconductor element and the solder joint.
The Ti film may be in an oxidized state (TiO ₂ film) depending on the manufacturing conditions of the power semiconductor device. A TiO ₂ film is more difficult to deposit an intermetallic compound with Sn than a Ti film. Therefore, in this case, the peeling phenomenon is more likely to occur.

However, in the solder alloy of the present embodiment, as described above, instead of the Ni—Sn intermetallic compound, the Cu, Ni, Co-based intermetallic compound precipitates in the formed solder joint. These intermetallic compounds are likely to precipitate at and near the interface between the semiconductor element and the solder joint during solder joint, and have a fine structure. Therefore, it is presumed that diffusion of the Ni film into the solder joint is suppressed. And it is presumed that this makes it possible to suppress the peeling phenomenon at the interface between the semiconductor element and the solder joint.

In addition, the repetition of heat generation and cooling of the power semiconductor element described above applies a repeated cold load to the solder joints in contact with the power semiconductor element. This cold load causes thermal fatigue and cold fatigue in the solder joints, and also causes stress in the solder joints. This stress causes cracks in the solder joints. In addition, repeated stress accelerates the development of cracks that have occurred, and finally causes the power semiconductor element to peel off. This crack is particularly likely to occur in a high temperature operating environment of 200° C. or higher.
However, the solder alloy of _the present embodiment causes the _Cu6Sn5 intermetallic compound to precipitate in the solder joint as described above.
This intermetallic compound contributes to the improvement of the strength of the solder joint, and the solder alloy of the present embodiment can deposit this intermetallic compound in the solder joint in a well-balanced manner. Therefore, the solder alloy of the present embodiment can suppress the occurrence and propagation of cracks in the solder joint even in a high-temperature operating environment, and can also suppress the occurrence of the delamination phenomenon of the semiconductor element caused by this. In addition, as described above, the Cu, Ni, and Co-based intermetallic compounds have a fine structure, so they can contribute to the realization of this effect.

As described above, the heat generation amount and temperature of next-generation power semiconductor elements are higher than those of power semiconductors. As a result, diffusion of the Ni film or the like described above into the solder joints is more likely to occur, and cracks are more likely to occur in the solder joints.
However, as described above, the solder alloy of the present embodiment can deposit Cu, Ni, Co-based intermetallic compounds and Cu ₆ Sn ₅ intermetallic compounds in a well-balanced manner in the formed solder joint. Therefore, even when the next-generation power semiconductor device is used, it is possible to suppress the diffusion of the Ni film into the solder joint and the resulting peeling phenomenon at the interface between the semiconductor device and the solder joint. In addition, it is possible to suppress the occurrence of cracks in the solder joints and the peeling phenomenon of the semiconductor element due to the development of the cracks.

A preferable Cu content is 1.5% by mass or more and 7% by mass or less, and 2% by mass or more and 6.5% by mass or less. A more preferable Cu content is 3% by mass or more and 6% by mass or less, and 3% by mass or more and 4% by mass or less. By setting the Cu content within this range, it is possible to further contribute to the suppression of the diffusion of the Ni film into the solder joint and further improve the strength of the solder joint.

In addition, the solder alloy of the present embodiment contains 6% by mass or more and 20% by mass or less of Sb, thereby improving the solid-solution strengthening of Sb in the solder joint, and an SbSn intermetallic compound (for example, Sb ₂ Sn ₃ intermetallic compound) can be deposited. As a result, the strength of the solder joints can be improved, and the occurrence of cracks in the solder joints described above, particularly in a high-temperature operating environment, and the occurrence of delamination of the semiconductor element due to the development of cracks can be suppressed.

A preferable Sb content is 6% by mass or more and 15% by mass or less, 7% by mass or more and 15% by mass or less, or 7% by mass or more and 14% by mass or less. A more preferable Sb content is 8% by mass or more and 13% by mass or less, 9% by mass or more and 12% by mass or less, and 10% by mass or more and 11% by mass or less. By setting the Sb content within this range, the solid solution strengthening of the Sb in the solder joint can be further improved, and the intermetallic compound can be precipitated in a well-balanced manner, further improving the strength of the solder joint. can be made

In addition, the solder alloy of the present embodiment contains 0.01% by mass or more and 0.5% by mass or less of Ni, so that intermetallic compounds with Sn, Cu, and Co, for example, (Cu,Ni) ₆ Sn ₅ intermetallics and (Cu,Co,Ni) ₆ Sn ₅ intermetallics can be deposited. These intermetallic compounds are presumed to contribute to the suppression of the delamination phenomenon at the interface between the semiconductor element and the solder joint, as described above. In addition, since these intermetallic compounds have a fine structure, they can also contribute to the effect of suppressing the progress of cracks occurring in solder joints.

A preferable Ni content is 0.02% by mass or more and 0.4% by mass or less, 0.025% by mass or more and 0.35% by mass or less, and 0.03% by mass or more and 0.3% by mass or less. A more preferable Ni content is 0.035% by mass or more and 0.2% by mass or less. By setting the Ni content within this range, the diffusion of the Ni film into the solder joint can be further suppressed.

In addition, the solder alloy of the present embodiment contains 0.001% by mass or more and 1% by mass or less of Co, so that intermetallic compounds with Sn, Ni, and Cu, such as (Cu , Co) ₆ Sn ₅ intermetallics and (Cu, Co, Ni) ₆ Sn ₅ intermetallics can be deposited.
These intermetallic compounds are presumed to contribute to the suppression of the delamination phenomenon at the interface between the semiconductor element and the solder joint, as described above. In addition, since these intermetallic compounds have a fine structure, they can also contribute to the effect of suppressing the propagation of cracks that occur in solder joints.

A preferable Co content is 0.002% by mass or more and 0.9% by mass or less, 0.003% by mass or more and 0.8% by mass or less, and 0.004% by mass or more and 0.8% by mass or less. A more preferable Co content is 0.005% by mass or more and 0.6% by mass or less. A particularly preferable Co content is 0.006% by mass or more and 0.5% by mass or less, 0.007% by mass or more and 0.4% by mass or less, and 0.007% by mass or more and 0.3% by mass or less. By setting the Co content within this range, the diffusion of the Ni film into the solder joint can be further suppressed.

Thus, in the solder alloy of the present embodiment, a Cu-, Ni-, and Co-based intermetallic compound can be precipitated in the solder joint by adding predetermined amounts of Cu, Ni, and Co to the solder alloy containing Sn. .
It is presumed that the suppression of diffusion of the Ni film into the solder joint can be achieved by the precipitation of these intermetallic compounds and their balance.
Moreover, these intermetallic compounds have a fine structure. Therefore, even when cracks occur in the solder joint, it is thought that the growth of cracks can be suppressed by the precipitation balance of these intermetallic compounds.

In addition, the solder alloy of the present embodiment is obtained by adding predetermined amounts of Cu and Sb to a solder alloy containing Sn, thereby forming a Cu ₆ Sn ₅ intermetallic compound as an intermetallic compound of Sn, Cu, and Sb in the solder joint. and SbSn intermetallic compounds can be deposited.
It is presumed that the above-described effect of suppressing the occurrence of cracks in solder joints can be realized by the precipitation of these intermetallic compounds and their balance.

As described above, the solder alloy of the present embodiment suppresses the delamination phenomenon at the interface between the semiconductor element and the solder joint, and suppresses the delamination phenomenon of the semiconductor element due to cracks occurring in the solder joint and their progress. obtain.
In addition, since the solder alloy of the present embodiment has good strength at the solder joints as described above, cracks in the semiconductor element itself caused by stress generated at the interface between the solder joint and the semiconductor element are also suppressed. be able to.

Therefore, the solder alloy of the present embodiment can be suitably used for joining semiconductor elements, particularly power semiconductor elements including next-generation power semiconductor elements, to substrates.
In addition, the solder alloy of the present embodiment can be suitably used for applications other than bonding between a semiconductor element and a substrate, that is, (solder) bonding between materials to be bonded. Examples of this application include bonding between a substrate in a semiconductor package and a heat dissipation substrate, and bonding between a substrate (electronic circuit board) and an electronic component (particularly, an electronic component having high heat resistance).

Moreover, the content of Cu and Ni in the solder alloy of the present embodiment preferably satisfies the following formula (A).
Ni/(Cu+Ni)<0.1 (A)
When the solder alloy of the present embodiment contains Cu and Ni within this range, diffusion of the Ni film into the solder joint can be further suppressed. Moreover, in this case, the effect of suppressing the peeling of the semiconductor element due to cracks occurring in the solder joints and their progress can be further improved.
In addition, it is more preferable that the content of Cu and Ni in the solder alloy of the present embodiment satisfies the following formula (A').
0.03<Ni/(Cu+Ni)<0.09... (A')
The above formulas (A) and (A') are calculated by rounding off to the third decimal place.

In addition, the solder alloy of the present embodiment can further contain 0.1% by mass or more and less than 3% by mass of Ag. In this case, the Ag ₃ Sn intermetallic compound can be precipitated in the solder joint to reduce the residual stress in the solder joint. In addition, this can improve the mechanical strength of the solder joint.
Moreover, when using such a solder alloy for solder paste, the effect of suppressing void generation can be improved.

A preferable Ag content is 0.2% by mass or more and 2.9% by mass or less, 0.2% by mass or more and 2.5% by mass or less, or 0.2% by mass or more and 2% by mass or less. A more preferable Ag content is 0.5% by mass or more and 1.5% by mass or less. By setting the Ag content within this range, the mechanical strength of the solder joint can be further improved.

Moreover, the solder alloy of the present embodiment can further contain at least one of Al, Ti, Si, Fe and Ge. In this case, the strength of the solder joint can be further improved.
The total content of at least one of Al, Ti, Si, Fe and Ge is preferably 0.003% by mass or more and 0.5% by mass or less, and 0.005% by mass or more and 0.3% by mass or less. It is even more preferable to have By setting the total content of these elements within this range, the strength of the solder joint can be further improved.
The balance of the solder alloy of this embodiment is Sn. The solder alloy naturally contains unavoidable impurities.

2. Solder-Joining Material The solder-joining material of the present embodiment uses the solder alloy of the embodiment described above, and includes, for example, the following.

・Solder preform The solder preform may be of any shape as long as it is in the form of a sheet. For example, disc-shaped, angular, tape-shaped, etc. can be used. Moreover, in manufacturing the solder preform, for example, a known manufacturing method such as a method of rolling an ingot made of the solder alloy of the above-described embodiment using a rolling mill can be used. The shape, size and thickness of the solder preform can be appropriately adjusted depending on the type of substrate, semiconductor element, etc. used. Its thickness is preferably 10 μm or more and 500 μm or less, and more preferably its thickness is 30 μm or more and 300 μm or less.

Also, the surface of the solder preform can be soldered by applying flux, which will be described later. Alternatively, the surface of the solder preform may be flux-coated in advance with an organic acid or the like for soldering. Furthermore, the solder preform can be soldered using, for example, formic acid reflow or hydrogen reflow in a reducing atmosphere.

- Joining material having a solder joint layer As a joining material having a solder joint layer, for example, a joint material having the following structure is exemplified.
That is, the bonding material having the solder bonding layer has, for example, a reinforcing layer and a solder layer. This solder layer is laminated on the upper and lower surfaces of the reinforcing layer using a hot rolling method or the like. The solder layer is formed using the solder alloy of the embodiment described above.
The reinforcing layer also has a core substrate. This core base material is made of, for example, CuMo, Mo, or the like. Incidentally, if necessary, metal layers may be provided on both sides of the core substrate. This metal layer may be, for example, a layer composed of at least one of Ni, Sn, Cu, Au and Ag, a layer containing an intermetallic compound derived from an alloy element thereof, or a combination thereof. The metal layer is formed by, for example, plating.

- Solder paste Regarding the solder paste of this embodiment, the following 3. will be described in detail.

In addition to the solder preform and the solder paste described later, the solder joint material of the present embodiment can be used in any form as long as it can be used for joining a semiconductor element, particularly a power semiconductor element, to a substrate. may be

Since the solder alloy of the embodiment described above is used in the solder joint material of the present embodiment, it is possible to suppress the diffusion of the Ni film described above into the solder joint, and the occurrence of cracks in the solder joint and its occurrence. Progress can be restrained. Therefore, the solder joint material of the present embodiment suppresses the occurrence of both the delamination phenomenon at the interface between the semiconductor element and the solder joint and the delamination phenomenon of the semiconductor element caused by the progress of cracks in the solder joint. can do.
In addition, since the solder joints of the solder joint material of the present embodiment have good strength, it is possible to suppress the occurrence of cracks in the semiconductor element itself caused by the stress generated at the interface between the solder joints and the semiconductor element. .

Therefore, the solder joint material of the present embodiment can be suitably used for joining semiconductor elements, particularly power semiconductor elements including next-generation power semiconductor elements, to substrates.
The solder bonding material of the present embodiment can be suitably used for applications other than bonding between a semiconductor element and a substrate, that is, (solder) bonding between materials to be bonded. Examples of this application include bonding between a substrate in a semiconductor package and a heat dissipation substrate, and bonding between a substrate (electronic circuit board) and an electronic component (especially an electronic component having high heat resistance).

3. Solder paste The solder paste of the present embodiment is produced by, for example, kneading the powdered solder alloy of the above-described embodiment (powder made of the solder alloy) and flux to form a paste.

The powder made of the solder alloy is obtained by pulverizing the solder alloy of the above-described embodiment by a known method. The particle size of the powder made of the solder alloy (measured by a dynamic light scattering method) can be, for example, 1 μm or more and 40 μm or less. Also, the particle size may be 5 μm or more and 35 μm or less, or 10 μm or more and 30 μm or less.

As the flux, for example, a flux containing a resin, a thixotropic agent, an activator and a solvent is used.

Examples of the resin include rosin-based resins; acrylic acid, methacrylic acid, various esters of acrylic acid, various esters of methacrylic acid, crotonic acid, itaconic acid, maleic acid, maleic anhydride, esters of maleic acid, and maleic anhydride. ester, acrylonitrile, methacrylonitrile, acrylamide, methacrylamide, vinyl chloride, acrylic resin obtained by polymerizing at least one monomer such as vinyl acetate; epoxy resin; phenol resin, and the like. These can be used singly or in combination.

Examples of the rosin resin include rosins such as tall oil rosin, gum rosin, and wood rosin; hydrogenated rosin (partially hydrogenated, fully hydrogenated), polymerized rosin, heterogenized rosin, acrylic acid-modified rosin, maleic acid-modified rosin-based modified resins such as rosin and formylated rosin; and derivatives thereof. These can be used singly or in combination.

The acid value of the resin can be, for example, 10 mgKOH/g or more and 250 mgKOH/g or less. Moreover, the compounding quantity of the said resin can be 10 mass % or more and 90 mass % or less with respect to the flux whole quantity, for example.

Examples of the thixotropic agents include hydrogenated castor oil, bisamide-based thixotropic agents (saturated fatty acid bisamides, unsaturated fatty acid bisamides, aromatic bisamides, etc.), dimethyldibenzylidenesorbitol, and the like. These can be used singly or in combination. The compounding amount of the thixotropic agent can be, for example, 3% by mass or more and 15% by mass or less with respect to the total amount of the flux.

Examples of the activator include organic acids, halogen-containing compounds, and amine-based activators. These can be used singly or in combination.

Organic acids include, for example, monocarboxylic acids, dicarboxylic acids, and other organic acids.

Monocarboxylic acids include, for example, propionic acid, butyric acid, valeric acid, caproic acid, enanthic acid, capric acid, lauric acid, myristic acid, pentadecyl acid, palmitic acid, margaric acid, stearic acid, tuberculostearic acid, and arachidic acid. , behenic acid, lignoceric acid, glycolic acid and the like.

Dicarboxylic acids include, for example, oxalic acid, malonic acid, succinic acid, glutaric acid, adipic acid, pimelic acid, suberic acid, azelaic acid, sebacic acid, dodecanedioic acid, eicosanedioic acid, fumaric acid, maleic acid, tartaric acid, diglycolic acid, 1,4-cyclohexanedicarboxylic acid, and the like.

Other organic acids include, for example, dimer acid, levulinic acid, lactic acid, acrylic acid, benzoic acid, salicylic acid, anisic acid, citric acid, picolinic acid, anthranilic acid and the like.

Compounds containing halogen include, for example, non-dissociative halogen compounds (non-dissociative active agents) and dissociative halogen compounds (dissociative active agents).
The non-dissociation type activator includes non-salt organic compounds to which halogen atoms are covalently bonded. The organic compound may be, for example, a compound in which each single element of chlorine, bromine, iodine, and fluorine is covalently bonded, such as chloride, bromide, iodide, and fluoride, and two or more different halogen atoms are covalently bonded. It may be a compound bonded with Moreover, the organic compound preferably has a polar group such as a hydroxyl group, such as a halogenated alcohol, in order to improve the solubility in an aqueous solvent.

Examples of amine-based activators include amines, amine salts, amino acids, amide-based compounds, and the like.

The content of the activator can be 5% by mass or more and 15% by mass or less with respect to the total amount of the flux. Moreover, the compounding amount can also be 7 mass % or more and 13 mass % or less, or 9 mass % or more and 11 mass % or less with respect to the total amount of the flux.

Examples of the solvent include alcohol-based, butyl cellosolve-based, glycol ether-based, and ester-based solvents. These can be used singly or in combination.
The blending amount of the solvent can be 20% by mass or more and 50% by mass or less with respect to the total amount of the flux. Moreover, the compounding amount can also be 20 mass % or more and 40 mass % or less, or 35 mass % or more and 40 mass % or less with respect to the total amount of the flux.

The flux may contain an antioxidant. Examples of the antioxidant include hindered phenol-based antioxidants, phenol-based antioxidants, bisphenol-based antioxidants, polymer-type antioxidants, and the like. Among these, hindered phenol-based antioxidants are particularly preferred.
The types of the antioxidants are not limited to these, and the blending amount thereof is not particularly limited either. The general blending amount thereof is about 0.5% by mass to 5% by mass with respect to the total amount of flux.

Additives such as a matting agent and an antifoaming agent may be added to the flux. The blending amount of this additive can be 10% by mass or less, or 5% by mass or less, relative to the total amount of the flux.

When the solder paste of the present embodiment is produced, the compounding ratio (% by mass) of the solder alloy powder and the flux is 65:35 to 95:5 in terms of the solder alloy powder:flux ratio. can be done. Also, for example, the compounding ratio can be 85:15 to 93:7 or 87:13 to 92:8.

When a semiconductor element and a substrate are joined using the solder paste of the present embodiment, the peeling phenomenon at the interface between the semiconductor element and the solder joint described above, and the peeling phenomenon of the semiconductor element due to cracks in the solder joint and its progress. , the occurrence of both delamination phenomena can be suppressed. Moreover, since the solder paste of the present embodiment can suppress the generation of voids in the solder joints, it is possible to provide solder joints with even higher reliability.
Moreover, as described above, the solder paste of the present embodiment can also be suitably used for applications other than joining a semiconductor element and a substrate.

- Semiconductor Package An example of a semiconductor package manufactured using the solder alloy, solder joint material, and solder paste of the present embodiment will be described with reference to FIG.
The semiconductor package 10 has a substrate 100, a joint portion 11, a semiconductor element 200, a wire 300, a lead frame 400, a solder portion 500, a Cu base substrate 600, a housing 700, and a mold resin 800. . A Ti film and a Ni film are formed in order from the semiconductor element 200 side on the back electrode of the semiconductor element 200 (not shown).
The joint portion 11 is formed using the solder joint material (including solder paste) of the present embodiment. The joint portion 11 joins the substrate 100 and the semiconductor element 200 and is sandwiched between the substrate 100 and the semiconductor element 200 .
As the substrate 100, for example, a Cu substrate, a DBC (Direct Bonded Copper) substrate having Cu layers on both sides, or a DBA (Direct Bonded Aluminum) substrate having Al layers on both sides is preferably used.
The type of semiconductor element 200 is not particularly limited. As the semiconductor element 200, a Si element or a next-generation power semiconductor element may be used.
Wires 300 electrically connect electrodes (not shown) formed on the surface of semiconductor element 200 and lead frame 400 .
The solder part 500 joins the Cu base substrate 600 and the substrate 100 together. The solder part 500 can also be formed using the solder joint material of this embodiment.
The Cu base substrate 600 has heat dissipation properties and serves as a heat dissipation substrate.
The semiconductor package 10 is covered with a housing 700 and filled with a mold resin 800 inside.

The semiconductor package 10 is produced, for example, by the following method.
That is, the solder joint material of the present embodiment is placed (in the case of solder paste, it is applied) on the substrate 100, the semiconductor element 200 is placed thereon, a predetermined load is applied, and these are bonded using a reflow device. Join. After that, the wires 300 are used to join the semiconductor element 200 and the lead frame 400 together. Next, the substrate 100 on which the semiconductor element 200 is mounted and the Cu base substrate 600 are joined by soldering, and then covered with the housing 700 . After that, the semiconductor package 10 is manufactured by filling the inside with the molding resin 800 and curing it.

The joint portion 11 in the semiconductor package 10 is formed using the solder joint material of the embodiment described above, as described above. Therefore, even when a high temperature is applied to the joint portion 11 , diffusion of the Ni film of the semiconductor element 200 into the joint portion 11 can be suppressed. Moreover, since the joint portion 11 has good strength, it is possible to suppress the occurrence of cracks therein.
Therefore, the bonding portion 11 suppresses both the occurrence of delamination at the interface with the semiconductor element 200 and the occurrence of delamination of the semiconductor element 200 due to cracks in the bonding portion 11 and their progress. can be done.
In addition, when the solder paste of the embodiment described above is used to form the joint 11, the occurrence of voids in the joint 11 can be suppressed, so that the joint 11 can be made more reliable.

Moreover, when the solder joint 500 is formed using the solder joint material of the embodiment described above, the solder joint 500 has good strength, so that cracks can be suppressed from occurring therein. Therefore, the solder part 500 can efficiently release the heat transferred from the substrate 100 (originating from the heat generated by the semiconductor element 200 ) to the Cu substrate 600 for a long time, and the reliability of the semiconductor package 10 can be further improved.
In addition, when the solder paste 500 is formed using the solder paste of the embodiment described above, it is possible to suppress the occurrence of voids in the solder paste 500, so that the heat dissipation described above can be further improved.
The same applies when the semiconductor package 10 is a power semiconductor package.

It should be noted that the semiconductor package 10 is not limited to the form described above, and various modifications are possible within a range that does not impede its effects.

Hereinafter, the present invention will be described in detail with reference to examples and comparative examples. However, the present invention is not limited to these examples.

A. Solder Preform Using each solder alloy described in Table 1, each solder preform (6 mm×6 mm, thickness 60 μm) was produced.
In addition, the value of Ni/(Ni+Cu) of each solder alloy described in Table 1 was calculated by rounding off to the third decimal place.

(1) Ni Eating Confirmation Test The following tools were prepared.
・Si chip (size: 5 mm square, thickness: 0.3 mm, Ti film (0.1 μm) and Ni film (0.5 μm) are sequentially stacked on the bonding surface side)
・ Substrate (Electrolytic Ni-plated Cu plate, size: 20 mm square, thickness: 1 mm, Ni-plated thickness: 5 μm)
Each solder preform coated with flux (product name: EC-19S-8, manufactured by Tamura Seisakusho Co., Ltd.) and dried was placed on the substrate (center). Then, the Si chip was placed on each solder preform (center portion).
Then, these were reflowed under the following conditions to produce each test bonded body having the substrate, the Si chip, and a bonding portion for bonding them.

· Reflow conditions Mounting load conditions are set to 30 g, and a reflow device (product name: SMT Scope SK-5000, manufactured by Sanyo Seiko Co., Ltd.) is used, based on the temperature profile conditions (peak temperature: 350 ° C.) shown in FIG. Reflow was performed.
In reflow, heating is started in an atmosphere with an oxygen concentration of 100 ppm and atmospheric pressure, and when the reflow temperature reaches 240 ° C., evacuation is started, and the pressure in the reflow device is reduced to 100 Pa. maintained. After the reflow temperature reached 350° C., the temperature was maintained for 30 seconds, the pressure reduction was released, and the pressure in the reflow device was returned to the atmospheric pressure for cooling. FIG. 2 also shows the change in pressure (indicated by a dotted line) in the reflow device along with the temperature profile.

Then, for each test joint, an ultrasonic microscope (product name: C-SAM Gen6, manufactured by Nordson Advanced Technologies, Inc.) was used to obtain a joint interface image (image A, FIG. 3 ( a) see) was obtained.
Then, in the area A where the Si chip and the bonding portion appear to overlap on the image A, the area (area X) of the region where the two are bonded was calculated by the following method.
That is, the area (area Y) of the area A and the area (area Z) of the unbonded portion in the area A (the portion showing white in the area A shown in FIG. 3A) are calculated, and the area is calculated from the area Y The area X was obtained by subtracting Z.
Then, a value obtained by dividing the calculated area X by the area Y was defined as a joining ratio 1.

Next, each test joined body was heated at 210° C. for 500 hours using a blower constant temperature thermostat (product name: DKN402, manufactured by Yamato Scientific Co., Ltd.). Then, the bonding rate (bonding rate 2) was calculated in the same manner as above for each test bonding body after heating.
The difference between the bonding rate 1 and the bonding rate 2, that is, the increase rate of the unbonded portion was defined as the Ni erosion rate and evaluated based on the following criteria. Table 2 shows the results.
◎: Less than 5% Ni erosion rate ○: 5% or more and less than 10% Ni erosion rate △: 10% or more and less than 20% Ni erosion rate ×: 20% or more Ni erosion rate

(2) Detachment Occurrence Confirmation Test By the same method as the above (1) Ni erosion confirmation test, bonded bodies for each test were produced. Then, for each test joint, an ultrasonic microscope (product name: C-SAM Gen6, manufactured by Nordson Advanced Technologies, Inc.) was used to obtain a joint interface image (image A, FIG. 3 ( a)) and a bonding interface image taken from the substrate side (image B, see FIG. 3(b)).
Then, the area of the region where the Si chip and the bonding portion are bonded in the region A where the Si chip and the bonding portion appear to overlap on the image A, and the bonding portion and the substrate appear to overlap on the image B. The total value (area X') of the area of the region where both of the regions B are joined was calculated by the following method.
That is, the total value of the area of the region A and the area of the region B (area Y′), and the unbonded portion in the region A and the region B (in the region A in FIG. 3A and in the region B in FIG. 3B) The total value of the areas (area Z') of the portion showing white in ) was calculated, and the value obtained by subtracting the area Z' from the area Y' was defined as the area X'.
Then, the value obtained by dividing the calculated area X' by the area Y' was defined as the bonding ratio 1'.
Then, using a thermal shock tester (product name: ES-76LMS, manufactured by Hitachi Appliances Co., Ltd.) set to conditions from -40 ° C (15 minutes) to 200 ° C (15 minutes), the thermal shock cycle is repeated 500 cycles. After exposing each of the test conjugates to the environment, they were removed. The bonding rate (bonding rate 2′) was calculated in the same manner as described above for each test bonded body after this thermal shock cycle.
The difference between the bonding rate 1' and the bonding rate 2', that is, the increase rate of the unbonded portion was taken as the peeling rate, and evaluated based on the following criteria. Table 2 shows the results.
○: Peeling rate is less than 10% △: Peeling rate is 10% or more and less than 20% ×: Peeling rate is 20% or more

(3) Si chip crack confirmation test For each test bonded body after the thermal shock cycle was performed in the above (2) delamination confirmation test, the surface was examined with an ultrasonic microscope (product name: C-SAM Gen6, Nordson Advanced・Technology Co., Ltd.) to confirm whether or not the Si chip was cracked. Table 2 shows the results (presence or absence of cracks).
〇: No cracks ×: Cracks present

B. Solder paste Flux was obtained by adjusting each component below.
Resin: KE-604 (acrylic-modified hydrogenated rosin, manufactured by Arakawa Chemical Industries, Ltd.) 50% by mass
Activator: 2% by weight of suberic acid, 0.5% by weight of malonic acid, 1% by weight of dibromobutenediol
Solvent: Diethylene glycol monohexyl ether (DEH) 38.5% by mass
Thixotropic agent: Himako (12-hydroxystearic acid triglyceride, manufactured by KEF Trading Co., Ltd.) 5% by mass
Additive: Irganox 245 (hindered phenolic antioxidant, manufactured by BASF Japan Ltd.) 3% by mass
11.0% by mass of the flux and 89.0% by mass of each solder alloy powder (powder particle size 20 μm to 38 μm) listed in Table 1 were mixed to prepare each solder paste according to Examples and Comparative Examples. .

(4) Void Occurrence Confirmation Test The same tool as used in the above (1) Ni erosion confirmation test and a metal mask (opening: 3.5 mm×3.5 mm, thickness: 0.2 mm) were prepared.
Each solder paste was printed on the substrate (center) using the metal mask. Then, the Si chip was placed on the surface (center) of each printed solder paste.
These were reflowed under the same conditions as in the above (1) Ni erosion confirmation test to fabricate test bonded bodies each having the substrate, the Si chip, and a bonding portion for bonding them.

Then, the surface state of each test bonded body was observed from the upper surface (the Si chip side) with an X-ray inspection device (product name: XD7600NT Diamond, manufactured by Nordson), and the Si chip and the test bonded body were observed. The area of the overlapping region with the joint and the area of voids generated in the joint were measured.
Then, the void area ratio was calculated based on the following formula for each test joined body. Table 2 shows the results.
Total area of voids generated in the junction/area of the overlapping region of the Si chip and the junction x 100 (%)
Incidentally, in this example, the evaluation is judged to be x when the void area ratio is 5% or more.

From the above, it can be seen that the joint formed using the solder preform according to the example can suppress the diffusion of the Ni film of the Si chip into the joint even when a high temperature is applied. Moreover, since such a joint has good strength, it can be seen that the occurrence of cracks therein can be suppressed.
For this reason, the solder preforms according to the examples exhibited both the delamination phenomenon at the interface between the Si chip and the joint, and the delamination of the Si chip due to cracks and cracks in the joint. It turns out that it can be suppressed.
In addition, the solder paste according to the present example can suppress the generation of voids in the joints formed using the solder paste, so it can be seen that the joints with higher reliability can be provided.

On the other hand, in the case of the solder preform and solder paste of the comparative example using a solder alloy containing Cu, Sb, Ni, Co, and Sn, but the content of each alloying element is outside the predetermined range, at least the above test results It can be seen that one of them is x.

Therefore, the solder alloy, solder joint and solder paste of the present invention are suitable for use in semiconductor packages, particularly power semiconductor packages.
In addition, in this embodiment, each test is performed using a Si chip as a semiconductor element. However, under each of the test conditions described above, good results were obtained even though a high heat of 200° C. was applied to the test bonded body including the Si chip. Therefore, from this result, it is clear that similar effects can be obtained even when next-generation power semiconductor elements are used in place of the Si chips in the examples.

DESCRIPTION OF SYMBOLS 10... Semiconductor package 100... Substrate 200... Semiconductor element 300... Wire 400... Lead frame 500... Solder part 600... Cu base substrate 700... Case 800... Mold resin

Claims (12)

A joint formed using a solder alloy,
The solder alloy contains 1.1% by mass to 8% by mass of Cu, 6% by mass to 20% by mass of Sb, 0.01% by mass to 0.5% by mass of Ni, and 0% by mass of Co. 001% by mass or more and 1% by mass or less, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the content of Cu and Ni satisfying the following formula (A). Department.
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively. A joint formed using a solder joint material using a solder alloy,
The solder alloy contains 1.1% by mass to 8% by mass of Cu, 6% by mass to 20% by mass of Sb, 0.01% by mass to 0.5% by mass of Ni, and 0% by mass of Co. 001% by mass or more and 1% by mass or less, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the content of Cu and Ni satisfying the following formula (A). Department.
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively. A joint formed using a solder paste that uses a solder alloy,
The solder alloy contains 1.1% by mass to 8% by mass of Cu, 6% by mass to 20% by mass of Sb, 0.01% by mass to 0.5% by mass of Ni, and 0% by mass of Co. 001% by mass or more and 1% by mass or less, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the content of Cu and Ni satisfying the following formula (A). Department.
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively. 4. The solder alloy according to any one of claims 1 to 3, wherein the solder alloy further contains at least one of Al, Ti, Si, Fe and Ge in a total amount of 0.003% by mass or more and 0.5% by mass or less. junction. An electronic circuit board on which electronic components are bonded,
The electronic component is joined to the electronic circuit board by a joint formed using a solder alloy,
The solder alloy contains 1.1% by mass to 8% by mass of Cu, 6% by mass to 20% by mass of Sb, 0.01% by mass to 0.5% by mass of Ni, and 0% by mass of Co. The electronic circuit board.
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively. An electronic circuit board on which electronic components are bonded,
The electronic component is joined to the electronic circuit board by a joint formed using a solder joint material using a solder alloy,
The solder alloy contains 1.1% by mass to 8% by mass of Cu, 6% by mass to 20% by mass of Sb, 0.01% by mass to 0.5% by mass of Ni, and 0% by mass of Co. The electronic circuit board.
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively. An electronic circuit board on which electronic components are bonded,
The electronic component is joined to the electronic circuit board by a joint formed using a solder paste using a solder alloy,
The solder alloy contains 1.1% by mass to 8% by mass of Cu, 6% by mass to 20% by mass of Sb, 0.01% by mass to 0.5% by mass of Ni, and 0% by mass of Co. The electronic circuit board.
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively. 8. The solder alloy according to any one of claims 5 to 7, wherein the solder alloy further contains at least one of Al, Ti, Si, Fe and Ge in a total amount of 0.003% by mass or more and 0.5% by mass or less. electronic circuit board. A semiconductor package comprising a substrate, a semiconductor element, a heat dissipation substrate, a joint portion for joining the substrate and the semiconductor element, and a solder joint portion for joining the substrate and the heat dissipation substrate,
The solder joint contains 1.1% by mass or more and 8% by mass or less of Cu, 6% by mass or more and 20% by mass or less of Sb, 0.01% by mass or more and 0.5% by mass or less of Ni, and Co. Solder containing 0.001% by mass or more and 1% by mass or less, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the content of Cu and Ni satisfying the following formula (A) A semiconductor package formed using an alloy.
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively. A semiconductor package comprising a substrate, a semiconductor element, a heat dissipation substrate, a joint portion for joining the substrate and the semiconductor element, and a solder joint portion for joining the substrate and the heat dissipation substrate,
The solder joint contains 1.1% by mass or more and 8% by mass or less of Cu, 6% by mass or more and 20% by mass or less of Sb, 0.01% by mass or more and 0.5% by mass or less of Ni, and Co. Solder containing 0.001% by mass or more and 1% by mass or less, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the content of Cu and Ni satisfying the following formula (A) A semiconductor package formed using a solder joint material using an alloy.
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively. A semiconductor package comprising a substrate, a semiconductor element, a heat dissipation substrate, a joint portion for joining the substrate and the semiconductor element, and a solder joint portion for joining the substrate and the heat dissipation substrate,
The solder joint contains 1.1% by mass or more and 8% by mass or less of Cu, 6% by mass or more and 20% by mass or less of Sb, 0.01% by mass or more and 0.5% by mass or less of Ni, and Co. Solder containing 0.001% by mass or more and 1% by mass or less, 0.1% by mass or more and less than 3% by mass of Ag, the balance being Sn, and the content of Cu and Ni satisfying the following formula (A) A semiconductor package formed using a solder paste that uses an alloy.
Ni/(Cu+Ni)<0.1 (A)
In the above formula (A), Ni and Cu represent the contents (% by mass) of Ni and Cu, respectively. 12. The solder alloy according to any one of claims 9 to 11, wherein the solder alloy further contains at least one of Al, Ti, Si, Fe and Ge in a total amount of 0.003% by mass or more and 0.5% by mass or less. semiconductor package.

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