JP2023072096A - Charge pump circuit and boosting method - Google Patents

Abstract

To provide a charge pump circuit capable of suppressing noise.SOLUTION: A charge pump circuit includes: a clock signal generator for outputting a clock signal of a predetermined period; a delay unit for delaying the clock signal; a plurality of booster circuits for performing boosting operation at different timings based on the clock signal or a delayed clock signal obtained by delaying the clock signal by the delay unit; and an output unit that is commonly connected to the plurality of booster circuits to output power boosted by the plurality of booster circuits.SELECTED DRAWING: Figure 3

Description

The present disclosure relates to charge pump circuits and boosting methods.

Mobile objects such as automobiles are equipped with various wireless communication functions and are easily affected by electromagnetic waves (noise) radiated from other electronic devices. One of the main causes of noise from such electronic equipment is a charge pump circuit.

The charge pump circuit repeats charging and discharging according to clock cycles in order to generate the power supply voltage necessary for the load. The flow of charge due to this charge/discharge operation causes noise.

JP-A-2008-005650 JP-A-2000-195297

A charge pump circuit and a boosting method capable of suppressing noise are provided.

A charge pump circuit according to one aspect of the present disclosure includes a clock signal generation unit that outputs a clock signal with a predetermined cycle, a delay unit that delays the clock signal, and a clock signal or a delayed clock signal obtained by delaying the clock signal by the delay unit. a plurality of booster circuits that perform boosting operations at mutually different timings based on the above; and an output unit that is commonly connected to the plurality of booster circuits and outputs power boosted by the plurality of booster circuits.

A comparator may be further provided which compares a first voltage corresponding to the voltage of the output section with a predetermined reference voltage and outputs the result of comparison between the first voltage and the reference voltage to the plurality of booster circuits.

It may further include a voltage source that generates a reference voltage, and a resistor that is provided between the voltage source and the output and generates a first voltage based on the voltage of the output and the voltage of the voltage source.

The plurality of booster circuits includes first to n-th (n is an integer equal to or greater than 2) booster circuits, the delay unit includes first to n-1th delay circuits, and the first to n-1th delay circuits are , the first delay circuit is provided between the second booster circuit and the clock signal generator, and the first and second delay circuits are not interposed between the first booster circuit and the clock signal generator; The first to n-1 delay circuits may be provided between the n-th booster circuit and the clock signal generator.

The first through n-1 delay circuits may each be circuits having substantially equal time constants.

The plurality of booster circuits includes first to n-th (n is an integer equal to or greater than 2) booster circuits, the delay unit includes first to n-1th delay circuits, and the first to n-1th delay circuits are , may be provided between the second to n-th booster circuits and the clock signal generator without being interposed between the first booster circuit and the clock signal generator.

The 1 st to n-1 th delay circuits may have different time constants.

The booster circuit includes first and second transistors connected in series between the power supply for boosting and the comparator, third and fourth transistors connected in series between the ground potential source and the output section, A first capacitor connected between a first node between the first and second transistors and a second node between the third and fourth transistors.

Some of the plurality of boosting circuits perform boosting operations at mutually different timings based on the clock signal or the delayed clock signal, and the other portions of the plurality of boosting circuits are inverted signals of the clock signal or inverted signals of the delayed clock signal. , the boosting operation may be performed at different timings.

A boosting method according to one aspect of the present disclosure includes: a delay unit that delays a clock signal; a plurality of boosting circuits that receive the clock signal or a delayed clock signal obtained by delaying the clock signal by the delaying unit; A voltage boosting method using a charge pump circuit, comprising: a voltage boosting circuit that performs boosting operations at mutually different timings based on a clock signal or a delayed clock signal; and voltages boosted by a plurality of boosting circuits and outputting

The charge pump circuit further includes a comparator for inputting a first voltage corresponding to the voltage of the output section and a predetermined reference voltage, comparing the first voltage corresponding to the voltage of the output section and the predetermined reference voltage, It may further include outputting a comparison result between the first voltage and the reference voltage to a plurality of booster circuits.

The plurality of booster circuits may or may not boost the voltage of the output part according to the voltage level of the comparison result.

The plurality of booster circuits includes first to nth (n is an integer equal to or greater than 2) booster circuits, the delay unit includes first to n-1th delay circuits, and the first booster circuit is delayed by the delay unit. The second boost circuit performs the boost operation using the clock signal that is not delayed by the first delay circuit, the third boost circuit performs the boost operation using the delayed clock signal delayed by the first delay circuit, and the third boost circuit performs the boost operation using the first and third clock signals. The boosting operation is performed using the delayed clock signal delayed by the second delay circuit, and the n-th boosting circuit performs the boosting operation using the delayed clock signal delayed by the first to n-1 delay circuits. good.

The plurality of booster circuits includes first to nth (n is an integer equal to or greater than 2) booster circuits, the delay unit includes first to n-1th delay circuits, and the first booster circuit is delayed by the delay unit. The second to n-th boosting circuits may perform the boosting operation using the delayed clock signals delayed by the first to n-1th delay circuits, respectively. good.

Some of the plurality of boosting circuits perform boosting operations at mutually different timings based on the clock signal or the delayed clock signal, and the other portions of the plurality of boosting circuits are inverted signals of the clock signal or inverted signals of the delayed clock signal. , the boosting operation may be performed at different timings.

Schematic which shows the structural example of the solid-state image sensor in 1st Embodiment of this technique. FIG. 2 is a block diagram showing a configuration example of a semiconductor chip having a peripheral circuit section; The schematic diagram which shows an example of a structure of the charge-pump circuit by 1st Embodiment. FIG. 2 is a circuit diagram showing a configuration example of a delay circuit; FIG. 2 is a circuit diagram showing a configuration example of a delay circuit; FIG. 2 is a circuit diagram showing a configuration example of a delay circuit; FIG. 2 is a circuit diagram showing a configuration example of a delay circuit; FIG. 2 is a circuit diagram showing an internal configuration of a booster circuit; FIG. 4 is a timing diagram showing the operation of drive signals; 4 is a timing diagram showing the feedback voltage, reference voltage and comparator output voltage; FIG. FIG. 4 is a timing diagram showing drive signals for each of the booster circuits; The schematic diagram which shows an example of a structure of the charge-pump circuit by 2nd Embodiment. The schematic diagram which shows an example of a structure of the charge-pump circuit by 3rd Embodiment. The schematic diagram which shows an example of a structure of the charge-pump circuit by 4th Embodiment. 4 is a graph showing peak currents flowing through the charge pump circuit; 1 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which technology according to the present disclosure can be applied; FIG. FIG. 4 is a diagram showing an example of an installation position of an imaging unit;

Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings. The drawings are schematic or conceptual, and the ratio of each part is not necessarily the same as the actual one. In the specification and drawings, the same reference numerals are given to the same elements as those described above with respect to the previous drawings, and detailed description thereof will be omitted as appropriate.

The following embodiments are examples in which the charge pump circuit of the present technology is applied to a solid-state imaging device. However, the charge pump circuit of the present technology can also be applied to electronic devices other than solid-state imaging devices.

(First embodiment)
FIG. 1 is a schematic diagram showing a configuration example of a solid-state imaging device according to the first embodiment. The solid-state imaging device 1 includes a semiconductor chip 511 having a pixel array section 240 and a semiconductor chip 512 having a peripheral circuit section 15 . The semiconductor chips 511 and 512 are formed as separate semiconductor chips and stacked on top of each other. The solid-state imaging device 1 may be configured as one semiconductor chip as a whole, or may be stacked in three or more layers as three or more semiconductor chips.

Each pixel of the pixel array section 240 of the semiconductor chip 511 and elements of the peripheral circuit section 15 of the semiconductor chip 512 are provided with through electrodes such as TSVs (Through Silicon Via) provided in the via regions 513 and 514, for example. are electrically connected using Alternatively, both semiconductor chips may be bonded together so that the wiring of the semiconductor chip 511 of the pixel array section 240 and the wiring of the semiconductor chip 511 of the peripheral circuit section 15 are in contact with each other (Cu--Cu bonding). Further, part of the pixel array section 240 and the peripheral circuit section 15 may be configured as one semiconductor chip, and the other components may be configured as another semiconductor chip.

A plurality of pixel circuits (not shown) are arranged in a two-dimensional lattice in the pixel array section 240 of the semiconductor chip 511 . Each pixel circuit generates an analog pixel signal by photoelectric conversion. The configuration of the pixel array section 240 is not directly related to the essence of the present embodiment, so detailed description thereof will be omitted.

FIG. 2 is a block diagram showing a configuration example of the semiconductor chip 512 having the peripheral circuit section 15. As shown in FIG. The semiconductor chip 512 has a peripheral circuit section 15 that controls the pixel array section 240 . The peripheral circuit section 15 includes a vertical scanning circuit VS, a comparator CMP, a counter CNT, a power supply circuit LM, a signal processing circuit SP, and a charge pump circuit CP.

The vertical scanning circuit VS sequentially drives the rows of the pixel array section 240 of the semiconductor chip 511 to output pixel signals from the pixel circuits.

The comparator CMP compares the pixel signal and the reference signal and outputs the comparison result. The reference signal is a signal whose voltage changes over time with a predetermined slope from an initial value, and is used to detect the voltage level of the pixel signal.

The counter CNT counts clock signals over a period from when the reference signal starts to change until the comparison result of the comparator CMP is inverted. The counter CNT outputs this count value as a digital signal. The count value corresponds to the level of the pixel signal and indicates the digital signal of the pixel signal. Thus, the pixel signal is AD (Analog to Digital) converted. The counter CNT outputs a digital signal of the reset level (dark current component) in the unexposed pixel circuit and a digital signal of the signal level of the exposed pixel signal.

The signal processing circuit SP performs so-called CDS (Correlated Double Sampling) processing by obtaining the difference between the reset level and the signal level. Thereby, the signal level of the light received in each pixel circuit is detected.

The power supply circuit LM is a current source for operating the pixel array section 240 as a source follower.

The charge pump circuit CP is provided to change the level of the power supply voltage and generate a desired level of voltage required for the vertical scanning circuit VS.

FIG. 3 is a schematic diagram showing an example of the configuration of the charge pump circuit according to the first embodiment. The charge pump circuit CP includes a clock signal generation section 10, a delay section 20, a plurality of booster circuits 31 to 35, an output section 40, a comparator 50, a voltage source 60, and a variable resistor 70. .

The clock signal generator 10 outputs a clock signal CLK1 with a predetermined cycle. The clock signal generation unit 10 is connected to the booster circuit 31 by wiring without passing through the delay unit 20 . Therefore, the clock signal CLK1 is supplied to the booster circuit 31 as it is without being delayed by the delay section 20 .

The delay section 20 is connected between the clock signal generation section 10 and the boost circuits 32-35. The delay unit 20 generates delayed clock signals CLK2 to CLK5 by delaying the clock signal CLK1, and supplies the delayed clock signals CLK2 to CLK5 to the boost circuits 32 to 35, respectively.

The delay unit 20 includes delay circuits 21-24. The delay circuit 21 is connected between the clock signal generator 10 and the booster circuit 32 and supplies the booster circuit 32 with a delayed clock signal CLK2 obtained by delaying the clock signal CLK1 by a predetermined time constant. Delay circuit 22 is connected between delay circuit 21 and booster circuit 33 and supplies booster circuit 33 with delayed clock signal CLK3 obtained by further delaying delayed clock signal CLK2 by a predetermined time constant. Delay circuit 23 is connected between delay circuit 22 and booster circuit 34, and supplies booster circuit 34 with delayed clock signal CLK3 obtained by further delaying delayed clock signal CLK2 by a predetermined time constant. Delay circuit 24 is connected between delay circuit 23 and booster circuit 35 , and supplies booster circuit 35 with delayed clock signal CLK 4 obtained by further delaying delayed clock signal CLK 2 by a predetermined time constant.

The configuration of the delay circuits 21 to 24, which will be described later, may be circuits having substantially equal time constants. Equalizing the configurations of the delay circuits 21 to 24 facilitates their design and manufacture. Of course, there is no problem even if some or all of the delay circuits 21 to 24 have different time constants.

For example, if the time constants of the delay circuits 21-24 are TC1-TC4, the delayed clock signal CLK2 is delayed from the original clock signal CLK1 by TC1. Delayed clock signal CLK3 is delayed from original clock signal CLK1 by TC1+TC2. Delayed clock signal CLK4 is delayed from original clock signal CLK1 by TC1+TC2+TC3. Delayed clock signal CLK5 is delayed from original clock signal CLK1 by TC1+TC2+TC3+TC4. As described above, the delay unit 20 according to the first embodiment can supply the clock signal CLK1 and the delayed clock signals CLK2 to CLK5 at different timings regardless of whether the time constants TC1 to TC4 are the same or different. can.

Boosting circuits 31-35 perform boosting operations at different timings based on clock signal CLK1 or delayed clock signals CLK2-CLK5 obtained by delaying clock signal CLK1. For example, the booster circuit 31 repeats the charging operation and the discharging operation according to the clock signal CLK1, and supplies charges to the output section 40. FIG. The booster circuit 32 repeats the charging operation and the discharging operation according to the delayed clock signal CLK2, and supplies charges to the output section 40. FIG. The booster circuit 33 repeats the charge operation and the discharge operation according to the delayed clock signal CLK3 and supplies charges to the output section 40 . The booster circuit 34 repeats the charging operation and the discharging operation according to the delayed clock signal CLK4, and supplies charges to the output section 40. FIG. The booster circuit 35 repeats the charge operation and the discharge operation according to the delayed clock signal CLK5 and supplies charges to the output section 40 .

The output unit 40 is commonly connected to the boost circuits 31-35 and outputs power boosted by the boost circuits 31-35. A capacitor 80 as a second capacitor is connected to the output section 40 . The capacitor 80 is provided to store electric charges supplied from the boost circuits 31 to 35 and supply stable power to the load LD. The load LD receives power from the charge pump circuit CP and performs a predetermined operation.

Although the configurations of the booster circuits 31 to 35 will be described later, they may have substantially the same configuration. Equalizing the configuration of the booster circuits 31 to 35 facilitates their design and manufacture. Of course, there is no problem even if some or all of the booster circuits 31 to 35 have different configurations.

In the first embodiment, four delay circuits 21-24 are provided, and five booster circuits 31-35 are provided. However, the number of delay circuits and booster circuits is not particularly limited. Therefore, the charge pump circuit CP may include first to nth (n is an integer of 2 or more) booster circuits and first to n-1th delay circuits. Since the original clock signal CLK1 is input to the first booster circuit 31 without going through the delay section 20, the number of delay circuits is one less than the number of booster circuits.

The 1st to n-1th delay circuits are not interposed between the first booster circuit 31 and the clock signal generator 10 . On the other hand, the first delay circuit 21 is provided between the second booster circuit 32 and the clock signal generator 10, and the first and second delay circuits 21 and 22 are provided between the third booster circuit 33 and the clock signal generator. , the first to third delay circuits 21 to 23 are provided between the fourth booster circuit 34 and the clock signal generator, and the first to fourth delay circuits 21 to 24 are provided between the fifth It is provided between the booster circuit 35 and the clock signal generator. Generally speaking, the 1st to n-1 delay circuits are provided between the nth booster circuit and the clock signal generator. As a result, the first to n boosting circuits perform boosting operations based on the clock signal CLK1 or the delayed clock signals CLK2 to CLKn-1 at different timings. Delayed clock signals CLK2 to CLKn-1 are signals obtained by delaying original clock signal CLK1, and therefore have the same period as clock signal CLK1. Therefore, if the configurations of the booster circuits 31 to 35 are the same, the respective boosting operations of the booster circuits 31 to 35 are the same although the timings are different.

Voltage source 60 is connected between ground and the first input of comparator 50 and produces a reference voltage Vref. The reference voltage Vref is a constant voltage that serves as a reference for comparison with the feedback voltage Vfb. Voltage source 60 is also connected between ground and variable resistor 70 and is used to generate feedback voltage Vfb at variable resistor 70 .

The variable resistor 70 is connected between the voltage source 60 and the output section 40, and generates a feedback voltage Vfb as a first voltage based on the output voltage Vout of the output section 40 and the power supply voltage V60 of the voltage source 60. do. The feedback voltage Vfb is a voltage between the power supply voltage V60 and the output voltage Vout, and is a voltage obtained by dividing the voltage difference between the power supply voltage V60 and the output voltage Vout by the variable resistor 70 . Since the power supply voltage V60 is a constant voltage, the feedback voltage Vfb fluctuates according to the output voltage Vout. That is, the feedback voltage Vfb is a monitor voltage that fluctuates following fluctuations in the output voltage Vout.

Comparator 50 inputs reference voltage Vref and feedback voltage Vfb and compares them. Comparator 50 amplifies the voltage difference between reference voltage Vref and feedback voltage Vfb and outputs voltage Vamp as a comparison result. For example, when the feedback voltage Vfb is higher than the reference voltage Vref, the voltage Vamp becomes the ground potential (0 V, low level), and when the feedback voltage Vfb falls below the reference voltage Vref, the voltage Vamp becomes the power supply voltage (high level). . When the feedback voltage Vfb is equal to or higher than the reference voltage Vref, the voltage Vamp becomes an intermediate voltage between the ground potential and the power supply voltage.

Comparator 50 commonly outputs voltage Vamp to boost circuits 31-35. The boost circuits 31 to 35 boost or do not boost the voltage of the output section 40 according to the voltage level of the voltage Vamp. For example, in this embodiment, when the voltage Vamp is at low level, the booster circuits 31 to 35 can supply charge to the output section 40 by boosting operation, and boost the output voltage Vout. On the other hand, when the voltage Vamp becomes equal to or higher than the intermediate voltage, the boosting circuits 31 to 35 do not supply charges to the output section 40 by the boosting operation, and stop boosting the output voltage Vout. As will be described later, the charge pump circuit CP according to the present embodiment is a negative voltage charge pump that supplies negative charges, but it is needless to say that it can also be applied to a positive voltage charge pump that supplies positive charges. Details of the boosting operation will be described later with reference to FIGS. 6 and 7. FIG.

4A to 4D are circuit diagrams showing configuration examples of delay circuits. Since the delay circuits 21 to 24 may have the same configuration, the configuration of the delay circuit 21 will be explained here, and the explanation of the configurations of the other delay circuits 22 to 24 will be omitted.

As shown in FIG. 4A, the delay circuit 21 may be composed of a plurality (even number) of inverter circuits INV1 and INV2 connected in series. The inverter circuits INV1 and INV2 are made up of, for example, CMOS (Complementary Metal Oxide Semiconductor), and the time constant of the delay time can be adjusted by changing the size (gate width/gate length) of the transistors that make up the CMOS. can be done.

The number of inverter circuits connected in series is not limited to two, and may be four or more as shown in FIG. 4B. The delay circuit 21 of FIG. 4B is composed of four inverter circuits INV1 to INV4 connected in series. The inverter circuits INV1 to INV4 may have the same configuration.

As shown in FIG. 4C, delay circuit 21 may be an RC delay circuit. In this case, the delay circuit 21 has a resistor Rdly connected between the input of the clock signal CLK1 and the output of the delayed clock signal CLK2, and a capacitor Cdly connected between the input and ground. In FIG. 4C, delay circuit 21 comprises only one such RC delay circuit. However, the delay circuit 21 may be composed of a plurality of RC delay circuits connected in series.

As shown in FIG. 4D, the delay circuit 21 may be a circuit combining an inverter circuit and an RC delay circuit. In FIG. 4D, the delay circuit 21 is composed of a plurality (even number) of inverter circuits INV1, INV2 and an RC delay circuit connected in series. The RC delay circuit is provided between the inverter circuit INV1 and the inverter circuit INV2. Also in this example, the number of inverter circuits and the number of RC delay circuits connected in series are not particularly limited.

FIG. 5 is a circuit diagram showing the internal configuration of the booster circuit. Since the booster circuits 31 to 35 may have the same configuration, the configuration of the booster circuit 31 will be described here, and the description of the configurations of the other booster circuits 32 to 35 will be omitted.

The booster circuit 31 includes transistors Tr1 to Tr4 as first to fourth transistors and a capacitor Ccp as a first capacitor.

The transistors Tr1 and Tr2 are connected in series between the boosting power supply Vdd and the output of the comparator 50 . The transistor Tr1 is, for example, an n-type MOSFET (Field Effect Transistor). The transistor Tr2 is, for example, a p-type MOSFET. Since the transistor Tr2 is a p-type MOSFET, a relatively large current can flow to the capacitor Ccp.

The transistors Tr3 and Tr4 are connected in series between the ground GND and the output section 40 . The transistors Tr3 and Tr4 are, for example, n-type MOSFETs.

The capacitor Ccp is connected between a first node N1 between the transistors Tr1 and Tr2 and a second node N2 between the transistors Tr3 and Tr4.

Each gate of the transistors Tr1 to Tr4 receives drive signals CKSW2, XCKSW1, CKSW1 and CKSW2. The drive signals CKSW2, XCKSW1, and CKSW1 are all pulse signals internally generated using the clock signal CLK1. The drive signal XCKSW1 is an inverted signal of the drive signal CKSW1. The drive signals CKSW2, XCKSW1, and CKSW1 are internally generated in the charge pump circuit CP, thereby suppressing variation (skew) in shape and timing of each drive signal.

Next, the boosting operation of the charge pump circuit CP will be described.

FIG. 6 is a timing chart showing operations of the drive signals CKSW2, XCKSW1, and CKSW1. The horizontal axis indicates time, and the vertical axis indicates the level of the drive signal.

At time t1, the driving signal CKSW1 rises and the driving signal XCKSW1 falls. The drive signal CKSW2 remains at the low level. As a result, the transistors Tr2 and Tr3 become conductive while the transistors Tr1 and Tr4 remain non-conductive. Therefore, the capacitor Ccp is connected between the boosting power supply Vdd and the ground GND and charged. That is, t1-t2 is the charging period during which the capacitor Ccp is charged.

Next, at time t2, the drive signal CKSW1 falls and the drive signal XCKSW1 rises. This completes the charging period. At this time, the drive signal CKSW2 is maintained at the low level. In this manner, the drive signals CKSW1, XCKSW1 and the drive signal CKSW2 are operated at different times. This is to prevent a through current from flowing between the boosting power supply Vdd and the comparator 50 due to the transistors Tr1 and Tr2 becoming conductive at the same time. Also, this is to prevent a through current from flowing between the ground GND and the output section 40 due to the transistors Tr3 and Tr4 becoming conductive at the same time.

Next, at time t3, the drive signal CKSW2 rises. The drive signals CKSW1 and XCKSW1 remain at low level and high level, respectively. As a result, the transistors Tr1 and Tr4 become conductive while the transistors Tr2 and Tr3 remain non-conductive. Accordingly, a capacitor Ccp is connected between the output of comparator 50 and output 40 to discharge charge to output 40 . That is, t3 to t4 is a discharge period during which the capacitor Ccp discharges and charges are supplied to the output section 40. FIG.

Next, at time t4, the drive signal CKSW2 falls. This completes the discharge period. At this time, the drive signals CKSW1 and XCKSW1 are maintained at low level and high level, respectively. This is to suppress through current between the boosting power supply Vdd and the comparator 50 and between the ground GND and the output section 40 as described above.

The subsequent operations from t5 to t8 are the same as the operations from t1 to t4. By repeating the charging operation and the discharging operation to the capacitor Ccp in this manner, charges are repeatedly supplied (pumped) to the output unit 40 . Charge is stored, for example, in a capacitor 80 connected to the output section 40 and supplied to the load LD.

Note that the booster circuit 31 according to the present embodiment supplies negative charges (for example, electrons) to the output section 40 and accumulates the negative charges in the capacitor 80 . Therefore, the output voltage Vout is boosted to the negative voltage side by the boosting operation of the booster circuit 31 . However, the boost circuit 31 may supply positive charge (eg, holes) to the output section 40 and store the positive charge in the capacitor 80 . In this case, the connection positions of the power supply Vdd and the ground should be reversed.

FIG. 7 is a timing diagram showing the feedback voltage, the reference voltage and the output voltage of the comparator. First, in the initial state, voltage source 60 and/or variable resistor 70 are set so that feedback voltage Vfb is higher than reference voltage Vref.

When the feedback voltage Vfb is higher than the reference voltage Vref, the comparator 50 maintains the voltage Vamp at low level (ground potential (0V)). As a result, in the discharge operation, the booster circuit 31 shown in FIG. 5 extracts positive charges from the node N1 side electrode of the capacitor Ccp and supplies negative charges from the node N2 side electrode to the output section 40 . That is, the booster circuit 31 can pump negative charges to the output section 40 by the comparator 50 setting the voltage Vamp to a low level.

From t10 to t11, the booster circuit 31 repeats the boosting operation, so that the output voltage Vout is boosted to the negative voltage side. In the present embodiment, the output voltage Vout is boosted to a negative voltage, so the feedback voltage Vfb is also gradually lowered by the boosting operation.

At t11, when the feedback voltage Vfb becomes substantially equal to the reference voltage Vref, the comparator 50 raises the voltage Vamp to an intermediate voltage between high level (eg Vdd) and low level (eg GND). As a result, the booster circuits 31 to 35 supply less charge due to the boosting operation, and substantially stop boosting the output voltage Vout.

At t12, when the load reduces the current consumption and the output voltage Vout drops to the negative side, the feedback voltage Vfb falls below the reference voltage Vref. At the same time, the comparator 50 raises the voltage Vamp to a high level (for example, Vdd). As a result, in the discharge operation, the positive charge of the node N1 side electrode of the capacitor Ccp in FIG. 5 is not discharged. Accordingly, the negative charge of the node N2 side electrode is not supplied to the output section 40, and the output voltage Vout is not boosted to the negative voltage side. That is, when the comparator 50 sets the voltage Vamp to an intermediate voltage or higher, the booster circuit 31 becomes incapable of pumping negative charges to the output section 40 . At this time, although the boosting operation itself of the transistors Tr1 to Tr4 is repeated, the output voltage Vout is not boosted to the negative voltage side.

From t12 onwards when the voltage Vamp maintains the high level, the feedback voltage Vfb is substantially equal to or lower than the reference voltage Vref, and the output voltage Vout is not boosted.

Thus, the comparator 50 feedback-controls the booster circuit 31 so that the feedback voltage Vfb becomes substantially equal to the reference voltage Vref. On the other hand, when the load reduces the current consumption, the feedback voltage Vfb falls below the reference voltage Vref, and the comparator 50 raises the voltage Vamp to high level (for example, Vdd). Although the boosting operation itself of the boosting circuit 31 is repeated, the output voltage Vout is not boosted to the negative voltage side.

The configuration and boosting operation of boosting circuits 32 to 35 are substantially the same as the configuration and boosting operation of boosting circuit 31 described above. On the other hand, the boosting operation timings of the boosting circuits 31 to 35 are different as described with reference to FIG.

FIG. 8 is a timing chart showing drive signals CKSW1 and CKSW2 for booster circuits 31-35, respectively. Note that the drive signal XCKSW1 is an inverted signal of the drive signal CKSW1 and is not illustrated here because it can be easily understood from the operation of the drive signal CKSW1. Boosting circuits 31-35 have the same configuration, but clock signal CLK1 and delayed clock signals CLK2-CLK5 are supplied to boosting circuits 31-35 at different timings. Therefore, the drive signals CKSW1 and CKSW2 of the booster circuits 31 to 35 also operate at different timings.

For convenience, the drive signals CKSW1 for the booster circuits 31 to 35 are CKSW1_1 to CKSW1_5, and the drive signals CKSW2 for the booster circuits 31 to 35 are CKSW2_1 to CKSW2_5.

In this case, for example, the drive signals CKSW1_1 to CKSW1_5 rise in this order at different timings and fall in this order at different timings. When the delay circuits 21 to 25 have the same time constant, the drive signals CKSW1_1 to CKSW1_5 rise or fall sequentially at equal time intervals.

The drive signals CKSW2_1 to CKSW2_5 also rise in this order at different timings and fall in this order at different timings. When the delay circuits 21 to 25 have the same time constant, the drive signals CKSW2_1 to CKSW2_5 rise or fall sequentially at equal time intervals.

In this case, the charging period of the booster circuit 31 is t1 to t2, but the charging period of the booster circuits 32 to 35 is delayed from the charging period of the booster circuit 31 . On the other hand, if the charging operation of the booster circuits 32 to 35 overlaps with the discharging operation of the booster circuit 31, there is a risk that the noise peak will increase, and the charged charge will be discharged to the ground without being supplied to the output section 40. There is a risk. Therefore, the charging operation of the booster circuits 32 to 35 must be completed by t3 when the discharge period of the booster circuit 31 starts. That is, the drive signals CKSW1_1 to CKSW1_5 must fall by t3.

Similarly, the discharge period of the booster circuit 31 is t3-t4, but the discharge period of the booster circuits 32-35 is delayed from the charge period of the booster circuit 31. FIG. On the other hand, if the discharging operation of the booster circuits 32 to 35 overlaps with the charging operation of the booster circuit 31, the noise peak may increase, and the charged charge may leak to the ground, making it impossible to charge the booster circuit 31. be. Therefore, the discharge operation of the booster circuits 32 to 35 must be completed by t4 when the next charging period of the booster circuit 31 starts. That is, the drive signals CKSW2_1 to CKSW2_5 must fall by t4.

That is, the delay time of the delayed clock signals CLK2 to CLK5 with respect to the clock signal CLK1 must be at least shorter than the period between the charging and discharging operations of the booster circuit 31. FIG. As a result, overlapping of the charging operation and the discharging operation of any of the booster circuits 31 to 35 can be suppressed, and noise peaks can be suppressed.

By making the timings of the boosting operations of the boosting circuits 31 to 35 different from each other in this manner, the charges supplied to the output section 40 are averaged, and the current peak is reduced. Noise caused by the charging operation is suppressed by reducing the current peak.

As described above, in the case of a positive voltage charge pump, the connection positions of the power supply Vdd and the ground GND may be reversed. The operations of the clock signal CLK1, the delayed clock signals CLK2 to CLK5, and the drive signals CKSW1, CKSW2, and XCKSW1 may be the same. However, since the feedback voltage Vfb increases due to the boosting operation, the feedback voltage Vfb is initially set to be lower than the reference voltage Vref. The output voltage Vamp of the comparator 50 is at a high level (for example, Vdd) when the feedback voltage Vfb is lower than the reference voltage Vref, and the boosting operation is performed. After that, when the feedback voltage Vfb exceeds the reference voltage Vref, it falls to a low level (for example, 0V). As a result, the boosting operation of the output section 40 is stopped. When the feedback voltage Vfb falls below the reference voltage Vref again, the output voltage Vamp of the comparator 50 rises to high level again, and the boosting operation of the output section 40 is resumed.

Even in the positive voltage charge pump circuit CP, the charge supplied to the output section 40 is averaged by differentiating the timings of the boosting operations of the boosting circuits 31 to 35 as in the present embodiment, and the charge peaks. (current peak) becomes smaller. Noise caused by the charging operation is suppressed by reducing the current peak. Therefore, the positive voltage charge pump circuit CP can also obtain the effects of the present embodiment.

(Second embodiment)
FIG. 9 is a schematic diagram showing an example of the configuration of the charge pump circuit according to the second embodiment. In the second embodiment, the positions and configurations of the delay circuits 21-24 are different. Other configurations of the second embodiment may be the same as corresponding configurations of the first embodiment.

The delay circuits 21-24 are connected between the clock signal generator 10 and the boost circuits 32-35, respectively, and have time constants different from each other.

For example, the delay circuit 21 is connected between the clock signal generator 10 and the booster circuit 32 and supplies the booster circuit 32 with a delayed clock signal CLK2 obtained by delaying the clock signal CLK1 by a predetermined time constant TC1. The delay circuit 22 is connected between the clock signal generator 10 and the booster circuit 33 and supplies the booster circuit 33 with a delayed clock signal CLK3 obtained by delaying the delayed clock signal CLK2 by a predetermined time constant TC2. The delay circuit 23 is connected between the clock signal generator 10 and the booster circuit 34, and supplies the booster circuit 34 with a delayed clock signal CLK3 obtained by delaying the delayed clock signal CLK2 by a predetermined time constant TC3. The delay circuit 24 is connected between the clock signal generator 10 and the booster circuit 35 and supplies the booster circuit 35 with a delayed clock signal CLK4 obtained by delaying the delayed clock signal CLK2 by a predetermined time constant TC4.

Delay circuits 21-24 have different time constants TC1-TC4. The time constants TC1-TC4 can be varied by changing the number of serially connected inverters or the number of RC delay circuits in FIGS. 4A-4D. Also, the time constants TC1 to TC4 may be varied by changing the size (gate width/gate length) of the CMOS transistors forming the inverter or the resistance or capacitance of the RC delay circuit.

By making the time constants TC1 to TC4 of the delay circuits 21 to 24 different from each other in this way, the delay section 20 supplies the clock signal CLK1 and the delayed clock signals CLK2 to CLK5 to the boosting circuits 31 to 35 at different timings. be able to.

Also in the second embodiment, the number of delay circuits and booster circuits is not particularly limited. Therefore, the charge pump circuit CP may include first to nth (n is an integer of 2 or more) booster circuits and first to n-1th delay circuits. Since the original clock signal CLK1 is input to the first booster circuit 31 without going through the delay section 20, the number of delay circuits is one less than the number of booster circuits.

The 1st to n-1th delay circuits are not interposed between the first booster circuit 31 and the clock signal generator 10 . On the other hand, the first delay circuit 21 is provided between the second booster circuit 32 and the clock signal generator 10, and the second delay circuit 22 is provided between the third booster circuit 33 and the clock signal generator. . The third delay circuit 23 is provided between the fourth booster circuit 34 and the clock signal generator, and the fourth delay circuit 24 is provided between the fifth booster circuit 35 and the clock signal generator. Generally speaking, the 1st to n-1 delay circuits have different time constants and are provided between the 2nd to nth booster circuits and the clock signal generator 10, respectively. As a result, the first to n boosting circuits can perform boosting operations based on the clock signal CLK1 or the delayed clock signals CLK2 to CLKn-1 at different timings.

Since the configuration and operation of the charge pump circuit CP of the second embodiment are the same as those of the first embodiment, detailed description thereof will be omitted.

The charge pump circuit CP according to the second embodiment can average the charges supplied to the output section 40 and reduce the peak current by making the timings of the boosting operations of the boosting circuits 31 to 35 different from each other. As a result, the second embodiment can suppress noise caused by the charging operation, as in the first embodiment.

(Third Embodiment)
FIG. 10 is a schematic diagram showing an example of the configuration of the charge pump circuit according to the third embodiment. The charge pump circuit CP according to the third embodiment includes boosting circuits 31a to 35a that operate based on the clock signal CLK1a and its delayed clock signals CLK2a to CLK5a, and operates based on the clock signal CLK1b and its delayed clock signals CLK2b to CLK5b. It includes booster circuits 31b to 35b.

The clock signal CLK1b is a signal obtained by shifting the phase of the clock signal CLK1a by half a cycle. Therefore, the booster circuits 31a-35a and the booster circuits 31b-35b operate complementarily. That is, when the boosting circuits 31a to 35a are performing charging operations, the boosting circuits 31b to 35b perform discharging operations. Conversely, when the boosting circuits 31a to 35a are performing discharging operations, boosting Circuits 31b-35b perform the charging operation.

Delay circuits 21a to 24a use clock signal CLK1a to generate delayed clock signals CLK2a to CLK5a, respectively, as in the first embodiment. Delay circuits 21b to 24b also generate delayed clock signals CLK2b to CLK5b, respectively, using clock signal CLK1b, as in the first embodiment.

Thus, in the third embodiment, some of the booster circuits 31a to 35a and 31b to 35b that share the comparator 50 and the output section 40 use the clock signal CLK1a or the delayed clock signals CLK2a to CLK5a. , the boosting operation is performed at mutually different timings. The other booster circuits 31b-35b perform boosting operations at different timings based on the clock signal CLK1b and the delayed clock signals CLK2b-CLK5b obtained by shifting the phase of the clock signal CLK1a or the delayed clock signals CLK2a-CLK5b by half a cycle. do.

The booster circuits 31a-35a, 31b-35b share the comparator 50, the voltage source 60, the variable resistor 70 and the output section 40. FIG. Therefore, the booster circuits 31a to 35a and the booster circuits 31b to 35b perform complementary boosting operations, whereby the capacitor 80 is charged in a short time. That is, according to the third embodiment, the slope of the feedback voltage Vfb in FIG. 7 can be steep.

(Fourth embodiment)
FIG. 11 is a schematic diagram showing an example of the configuration of the charge pump circuit according to the fourth embodiment. The charge pump circuit CP according to the fourth embodiment is a combination of the second and third embodiments.

Therefore, the delay circuits 21a-24a are connected between the clock signal generator 10 and the booster circuits 32a-35a, respectively, and have different time constants. The delay circuits 21b-24b are connected between the clock signal generator 10 and the boost circuits 32b-35b, respectively, and have time constants different from each other.

Other configurations of the fourth embodiment may be the same as corresponding configurations of the third embodiment. Thereby, the fourth embodiment can obtain the effects of the second and third embodiments.

FIG. 12 is a graph showing the peak current Ipeak flowing through the charge pump circuit. A comparative example REF shows the peak current Ipeak when the boosting circuits 31 to 35 perform the boosting operation at the same timing. EMB1 and EMB2 represent the peak current Ipeak of the first and second embodiments. EMB3 and EMB4 represent the peak current Ipeak of the third and fourth embodiments. The peak current Ipeak may be either the current of the boosting power supply Vdd or the current of the ground GND.

In the comparative example REF, the booster circuits 31 to 35 supply charges to the output section 40 at the same timing. When the voltage boosting circuits 31 to 35 perform voltage boosting operations at the same timing, the voltage boosting circuits 31 to 35 supply charges to the output section 40 at the same timing, so the peak current Ipeak becomes very large. As the peak current Ipeak increases, so does the noise.

On the other hand, in EMB1 to EMB4, the boost circuits 31 to 35 supply charges to the output section 40 at different timings, so the charges supplied to the output section 40 are averaged and the peak current Ipeak becomes smaller. As a result, the noise generated from the charge pump circuit CP is drastically reduced. This effect can be similarly obtained in both negative voltage and positive voltage charge pump circuits.

<14. Example of application to a moving object>
The technology (the present technology) according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may

FIG. 13 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.

Vehicle control system 12000 comprises a plurality of electronic control units connected via communication network 12001 . In the example shown in FIG. 13 , the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Also, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.

Drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.

Body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps. In this case, body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.

External information detection unit 12030 detects information external to the vehicle in which vehicle control system 12000 is mounted. For example, the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 . The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of received light. The imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information. Also, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.

The vehicle interior information detection unit 12040 detects vehicle interior information. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.

The microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit. A control command can be output to 12010 . For example, the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, etc. Cooperative control can be performed for the purpose of

In addition, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.

The audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle. In the example of FIG. 13, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

FIG. 14 is a diagram showing an example of the installation position of the imaging unit 12031. As shown in FIG.

In FIG. 14, the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105. In FIG.

The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and windshield of the vehicle 12100, for example. An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 . Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 . An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 . The imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

Note that FIG. 14 shows an example of the imaging range of the imaging units 12101 to 12104 . The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively, and the imaging range 12114 The imaging range of an imaging unit 12104 provided in the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the course of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 . Such recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. This is done by a procedure that determines When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, the solid-state imaging device 1 can be applied to the imaging section 12031 . By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.

Embodiments according to the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.
(1)
a clock signal generator that outputs a clock signal with a predetermined cycle;
a delay unit that delays the clock signal;
a plurality of boosting circuits that perform boosting operations at different timings based on the clock signal or a delayed clock signal obtained by delaying the clock signal by the delay unit;
and an output unit commonly connected to the plurality of booster circuits for outputting power boosted by the plurality of booster circuits.
(2)
(1 ).
(3)
a voltage source that generates the reference voltage;
The charge pump according to (2), further comprising a resistor provided between the voltage source and the output section, the resistor generating the first voltage based on the voltage of the output section and the voltage of the voltage source. circuit.
(4)
The plurality of booster circuits includes first to n-th (n is an integer equal to or greater than 2) booster circuits,
The delay unit includes first to n-1th delay circuits,
wherein the first to n-1th delay circuits are not interposed between the first booster circuit and the clock signal generator,
the first delay circuit is provided between the second booster circuit and the clock signal generator,
the first and second delay circuits are provided between the third booster circuit and the clock signal generator;
The charge pump circuit according to any one of (1) to (3), wherein the first to n-1 delay circuits are provided between the nth booster circuit and the clock signal generator.
(5)
The charge pump circuit according to (4), wherein the first to n-1 delay circuits are circuits having substantially equal time constants.
(6)
The plurality of booster circuits includes first to n-th (n is an integer equal to or greater than 2) booster circuits,
The delay unit includes first to n-1th delay circuits,
The first to n-1th delay circuits are not interposed between the first booster circuit and the clock signal generator, and are respectively between the second to nth booster circuits and the clock signal generator. The charge pump circuit according to any one of (1) to (3), provided in
(7)
The charge pump circuit according to (6), wherein the first to n-1th delay circuits have different time constants.
(8)
The booster circuit
first and second transistors connected in series between the boosting power supply and the comparator;
third and fourth transistors connected in series between a source of ground potential and said output;
a first capacitor connected between a first node between the first transistor and the second transistor and a second node between the third transistor and the fourth transistor; ) The charge pump circuit described in 2 above.
(9)
some of the plurality of boosting circuits perform boosting operations at different timings based on the clock signal or the delayed clock signal;
(1) to (9), wherein the other parts of the plurality of booster circuits perform boosting operations at different timings based on the phase-shifted signal of the clock signal or the phase-shifted signal of the delayed clock signal; ).
(10)
a delay unit that delays a clock signal; a plurality of boost circuits that receive the clock signal or a delayed clock signal obtained by delaying the clock signal by the delay unit; an output unit that is commonly connected to the plurality of boost circuits; A boosting method using a charge pump circuit comprising
performing boosting operations at different timings based on the clock signal or the delayed clock signal;
A boosting method comprising outputting a voltage boosted by the plurality of boosting circuits.
(11)
The charge pump circuit further includes a comparator for inputting a first voltage corresponding to the voltage of the output section and a predetermined reference voltage,
comparing a first voltage corresponding to the voltage of the output section with a predetermined reference voltage;
The method according to (10), further comprising: outputting a comparison result between the first voltage and a reference voltage to the plurality of boost circuits.
(12)
The method according to (11), wherein the plurality of booster circuits boost or stop boosting the voltage of the output section according to the voltage level of the comparison result.
(13)
the plurality of booster circuits include first to n-th (n is an integer equal to or greater than 2) booster circuits, and the delay section includes first to n-1th delay circuits;
the first booster circuit performs a boosting operation using the clock signal not delayed by the delay unit;
the second booster circuit performs a boosting operation using the delayed clock signal delayed by the first delay circuit;
the third boost circuit performs a boost operation using the delayed clock signal delayed by the first and second delay circuits;
The method according to any one of (10) to (12), wherein the n-th boost circuit performs a boost operation using the delayed clock signal delayed by the first to n-1 delay circuits.
(14)
the plurality of booster circuits include first to n-th (n is an integer equal to or greater than 2) booster circuits, and the delay section includes first to n-1th delay circuits;
the first booster circuit performs a boosting operation using the clock signal not delayed by the delay unit;
Any one of (10) to (12), wherein the second to nth booster circuits perform boosting operations using the delayed clock signals delayed by the first to n-1th delay circuits, respectively. The method described in .
(15)
some of the plurality of boosting circuits perform boosting operations at different timings based on the clock signal or the delayed clock signal;
(10) to (14), wherein the other parts of the plurality of booster circuits perform boosting operations at different timings based on the phase-shifted signal of the clock signal or the phase-shifted signal of the delayed clock signal; ).

The present disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the gist of the present disclosure. Also, the effects described in this specification are only examples and are not limited, and other effects may be provided.

1 solid-state imaging device, 240 pixel array section, 511 semiconductor chip, 15 peripheral circuit section, 512 semiconductor chip, VS vertical scanning circuit, CMP comparator, CNT counter, LM power supply circuit, SP signal processing circuit, CP charge pump circuit, 10 clock signal generation unit 20 delay unit 21 to 24 delay circuit 31 to 35 booster circuit 40 output unit 50 comparator 60 voltage source 70 variable resistor

Claims (15)

a clock signal generator that outputs a clock signal with a predetermined cycle;
a delay unit that delays the clock signal;
a plurality of boosting circuits that perform boosting operations at different timings based on the clock signal or a delayed clock signal obtained by delaying the clock signal by the delay unit;
and an output unit commonly connected to the plurality of booster circuits for outputting power boosted by the plurality of booster circuits. 2. A comparator that compares a first voltage corresponding to the voltage of said output section with a predetermined reference voltage and outputs a comparison result between said first voltage and said reference voltage to said plurality of booster circuits. 2. The charge pump circuit according to 1. a voltage source that generates the reference voltage;
3. The charge pump of claim 2, further comprising a resistor provided between said voltage source and said output for generating said first voltage based on the voltage of said output and the voltage of said voltage source. circuit. The plurality of booster circuits includes first to n-th (n is an integer equal to or greater than 2) booster circuits,
The delay unit includes first to n-1th delay circuits,
wherein the first to n-1th delay circuits are not interposed between the first booster circuit and the clock signal generator,
the first delay circuit is provided between the second booster circuit and the clock signal generator,
the first and second delay circuits are provided between the third booster circuit and the clock signal generator;
2. The charge pump circuit according to claim 1, wherein said first to n-1 delay circuits are provided between said n-th booster circuit and said clock signal generator. 5. The charge pump circuit according to claim 4, wherein said first to n-1 delay circuits are circuits having substantially equal time constants. The plurality of booster circuits includes first to n-th (n is an integer equal to or greater than 2) booster circuits,
The delay unit includes first to n-1th delay circuits,
The first to n-1th delay circuits are not interposed between the first booster circuit and the clock signal generator, and are respectively between the second to nth booster circuits and the clock signal generator. 2. The charge pump circuit of claim 1, wherein the charge pump circuit is provided in 7. The charge pump circuit according to claim 6, wherein said first to n-1th delay circuits have different time constants. The booster circuit
first and second transistors connected in series between the boosting power supply and the comparator;
third and fourth transistors connected in series between a source of ground potential and said output;
a first capacitor connected between a first node between the first transistor and the second transistor and a second node between the third transistor and the fourth transistor. 2. The charge pump circuit according to claim 2. some of the plurality of boosting circuits perform boosting operations at different timings based on the clock signal or the delayed clock signal;
2. The other part of the plurality of boosting circuits according to claim 1, wherein the boosting operation is performed at different timings based on the phase-shifted signal of the clock signal or the phase-shifted signal of the delayed clock signal. charge pump circuit. a delay unit that delays a clock signal; a plurality of boost circuits that receive the clock signal or a delayed clock signal obtained by delaying the clock signal by the delay unit; an output unit that is commonly connected to the plurality of boost circuits; A boosting method using a charge pump circuit comprising
performing boosting operations at different timings based on the clock signal or the delayed clock signal;
A boosting method comprising outputting a voltage boosted by the plurality of boosting circuits. The charge pump circuit further includes a comparator for inputting a first voltage corresponding to the voltage of the output section and a predetermined reference voltage,
comparing a first voltage corresponding to the voltage of the output section with a predetermined reference voltage;
11. The method of claim 10, further comprising outputting a result of comparing the first voltage and a reference voltage to the plurality of boost circuits. 12. The method according to claim 11, wherein said plurality of booster circuits boost or do not boost the voltage of said output section according to the voltage level of said comparison result. the plurality of booster circuits include first to n-th (n is an integer equal to or greater than 2) booster circuits, and the delay unit includes first to n-1th delay circuits;
the first booster circuit performs a boosting operation using the clock signal not delayed by the delay unit;
the second booster circuit performs a boosting operation using the delayed clock signal delayed by the first delay circuit;
the third boost circuit performs a boost operation using the delayed clock signal delayed by the first and second delay circuits;
11. The method of claim 10, wherein said nth boost circuit performs a boost operation using said delayed clock signal delayed by said first through n-1 delay circuits. the plurality of booster circuits includes first to n-th (n is an integer equal to or greater than 2) booster circuits, the delay unit includes first to n-1th delay circuits,
the first booster circuit performs a boosting operation using the clock signal not delayed by the delay unit;
11. The method according to claim 10, wherein said second to nth booster circuits perform boosting operations using said delayed clock signals delayed by said first to n-1th delay circuits, respectively. some of the plurality of boosting circuits perform boosting operations at different timings based on the clock signal or the delayed clock signal;
11. The other part of the plurality of boosting circuits according to claim 10, wherein the boosting operation is performed at different timings based on the phase-shifted signal of the clock signal or the phase-shifted signal of the delayed clock signal. Method.

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