JP2023069476A - Imaging element and imaging apparatus - Google Patents

Abstract

To suppress current consumption by reducing a current flowing during reading, in an imaging element for processing signals outputted from a plurality of pixels in parallel.SOLUTION: In the imaging element, a processing circuit part 210 includes a conversion part (pixel circuit) which converts an analog signal outputted from a pixel to a digital signal and stores it in a pixel memory, a first output line 302 which is connected to a plurality of first conversion parts in a plurality of conversion parts and to which a signal stored in the pixel memory of the first conversion part is outputted, and a second output line 304 which is connected to a plurality of second conversion parts in the plurality of conversion parts and to which the signal stored in the pixel memory of the second conversion part is outputted. The processing circuit part 210 may further include a first sub output line 270 to which the signal of one conversion part of the plurality of first conversion parts is outputted, a second sub output line 272 to which the signal of another conversion part of the plurality of first conversion parts is outputted, and a first switching part which switches connection to the first output line to one of the first sub output line and the second sub output line.SELECTED DRAWING: Figure 5

Description

The present invention relates to an imaging device and an imaging device.

An imaging device capable of processing signals output from a plurality of pixels in parallel is known (for example, Japanese Unexamined Patent Application Publication No. 2002-100003). Conventionally, an increase in current consumption due to parallel processing of signals from pixels has been a problem.
[Prior art documents]
[Patent Literature]
[Patent Document 1] International Publication WO2013/129202

In a first aspect of the present invention, an imaging device includes a plurality of conversion units arranged in a row direction for converting analog signals into digital signals, and a plurality of first conversion units among the plurality of conversion units. connected to a first output line for outputting a signal converted into a digital signal by the first conversion unit; and a second output line through which the converted signal is output.

According to a second aspect of the present invention, there is provided an image pickup apparatus including the above image pickup device.

It should be noted that the above summary of the invention does not list all the features of the invention. Subcombinations of these feature groups can also be inventions.

It is a figure which shows the outline|summary of the image pick-up element 400 which concerns on this embodiment. An example of a planar layout of the first semiconductor substrate 100 is shown. An example of a planar layout of the second semiconductor substrate 200 is shown. An example of the circuit configuration of the pixel 112 and the pixel circuit 212 is shown. 3 is a schematic diagram illustrating a circuit for reading out a pixel memory 220; FIG. An example of a planar layout of the third semiconductor substrate 300 is shown. A memory block 312 is shown schematically. FIG. 4 is a schematic diagram illustrating another circuit for reading out data in the pixel memory 220 to the memory section 310; 8 schematically shows an example of the arrangement of pixel circuits 212 and 213 adjacent in the row direction of FIG. 8. FIG. FIG. 11 is a schematic diagram illustrating still another circuit for reading out data in the pixel memory 220 to the memory section 310; FIG. 11 is a schematic diagram illustrating still another circuit for reading out data in the pixel memory 220 to the memory section 310; FIG. 11 is a schematic diagram illustrating still another circuit for reading out data in the pixel memory 220 to the memory section 310; FIG. 11 is a schematic diagram illustrating still another circuit for reading out data in the pixel memory 220 to the memory section 310; 4 is a diagram showing an outline of another imaging device 402. FIG. A CDS block 316 is shown schematically. Another CDS block 318 is shown schematically. 2 is a block diagram showing a configuration example of an imaging device 500 according to an embodiment; FIG.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

FIG. 1 is a diagram showing an overview of an imaging device 400 according to this embodiment. The imaging element 400 images a subject. The imaging device 400 generates image data of a captured subject. The imaging device 400 includes a first semiconductor substrate 100 , a second semiconductor substrate 200 and a third semiconductor substrate 300 . As shown in FIG. 1 , the first semiconductor substrate 100 is laminated on the second semiconductor substrate 200 . A second semiconductor substrate 200 is stacked on a third semiconductor substrate 300 .

The first semiconductor substrate 100 has a pixel portion 110 . The pixel unit 110 outputs pixel signals based on incident light. Note that the first semiconductor substrate 100 is sometimes called a pixel chip.

The second semiconductor substrate 200 has a processing circuit section 210 and a peripheral circuit section 230 . Note that the second semiconductor substrate 200 may be called a signal processing chip.

The third semiconductor substrate 300 has a memory section 310 and a peripheral circuit section 320 . Note that the third semiconductor substrate 300 may be called a memory chip.

A pixel signal output from the first semiconductor substrate 100 is input to the processing circuit unit 210 . The processing circuit unit 210 processes input pixel signals. For example, the processing circuit unit 210 performs processing for converting analog signals into digital signals. Specifically, the processing circuit unit 210 performs a process of converting an input pixel signal into a digital signal. Processing circuitry 210 may perform other signal processing.

The processing circuit section 210 of this example is arranged at a position facing the pixel section 110 on the second semiconductor substrate 200 . That is, the processing circuit section 210 is arranged so as to at least partially overlap the pixel section 110 in the optical axis direction. The processing circuit section 210 may output a control signal for controlling driving of the pixel section 110 to the pixel section 110 .

The peripheral circuit section 230 controls driving of the processing circuit section 210 . The peripheral circuit section 230 is arranged around the processing circuit section 210 on the second semiconductor substrate 200 . Also, the peripheral circuit section 230 may be electrically connected to the first semiconductor substrate 100 to control driving of the pixel section 110 .

The memory section 310 receives and stores the pixel signals processed by the processing circuit section 210 via the output lines 302 and 304 . In FIG. 1, the image sensor 400 is drawn in an exploded view, so the output lines 203 and 304 look long. It can be shorter than wiring.

The peripheral circuit section 320 performs image processing such as noise removal on the pixel signals stored in the memory section 310 . Note that the structure of the imaging element 400 may be of a backside illumination type or a frontside illumination type. An example of the backside illumination type will be described below.

FIG. 2 shows an example of a planar layout of the first semiconductor substrate 100. As shown in FIG. A pixel portion 110 is arranged near the center of the surface of the first semiconductor substrate 100 .

The pixel section 110 has a plurality of pixels 112 arranged side by side along the row direction and the column direction. The pixel unit 110 of this example has M×N (M and N are natural numbers) pixels 112 . Although this example illustrates the case where M is different from N, M and N may be equal.

FIG. 3 shows an example of a planar layout of the second semiconductor substrate 200. As shown in FIG. A processing circuit section 210 is arranged near the center of the surface of the second semiconductor substrate 200 .

The processing circuit section 210 has a plurality of pixel circuits 212 arranged side by side along the row direction and the column direction. The processing circuit section 210 of this example has M×N pixel circuits 212 .

In this embodiment, the pixel circuit 212 and the pixel 112 are arranged at overlapping positions when viewed from the optical axis direction. In this case, the areas of the pixel circuits 212 and the pixels 112 may be substantially the same including margins between adjacent blocks.

The pixel circuit 212 controls driving of the electrically connected pixels 112 . Electrical connection between the pixel circuit 212 and the pixel 112 may be referred to as corresponding.

In the present embodiment, the pixel circuits 212 and the pixels 112 that are arranged in overlapping positions are connected. However, instead of connecting the pixel circuit 212 and the pixel 112 arranged at the overlapping position, the pixel circuit 212 and the pixel 112 arranged at the position not overlapping with each other may be connected.

A pixel control circuit 250 and a readout control circuit 260 as an example of the peripheral circuit section 230 are arranged around the processing circuit section 210 . Pixel control circuit 250 controls pixel 112 and pixel circuit 212 . The pixel control circuit 250 supplies, for example, a control signal for the pixel circuit 212 to AD-convert the signal from the pixel 112 . The pixel control circuit 250 also controls the exposure time of the pixels 112, for example. The readout control circuit 260 controls readout for outputting pixel signals stored in the pixel circuit 212 to the memory section 310 .

FIG. 4 shows an example of the circuit configuration of the pixel 112 and the pixel circuit 212. As shown in FIG. The pixel 112 includes a photoelectric conversion section 130 , a reset section 132 , an accumulation section 134 and a transfer section 136 .

The photoelectric conversion unit 130 has a photoelectric conversion function of converting light into electric charge and an accumulation function of accumulating the photoelectrically converted electric charge. The photoelectric conversion unit 130 is, for example, a photodiode.

The storage unit 134 converts the charge generated in the photoelectric conversion unit 130 into a voltage corresponding to the amount. The storage unit 134 is an example of a floating diffusion (FD).

The reset unit 132 discharges the electric charges of the storage unit 134 to a power supply line supplied with a predetermined power supply voltage VDD based on the control signal φRST. The reset unit 132 resets the potential of the storage unit 134 to a predetermined power supply voltage VDD based on the control signal φRST. A gate terminal of the reset unit 132 is connected to the pixel control circuit 250 .

The transfer unit 136 transfers the charge accumulated in the photoelectric conversion unit 130 to the storage unit 134 based on the control signal φTX. In addition, the transfer unit 136 discharges the charge accumulated in the photoelectric conversion unit 130 to the power supply wiring supplied with the predetermined power supply voltage VDD based on the control signal φTX. For example, the transfer unit 136 supplies the control signal φTX and the control signal φRST at the same time, thereby discharging the charge accumulated in the photoelectric conversion unit 130 to the power supply wiring supplied with the predetermined power supply voltage VDD. The transfer unit 136 is an example of a transfer gate that transfers charges of the photoelectric conversion unit 130 . In other words, the transfer section 136 as a gate, the photoelectric conversion section 130 as a source, and the storage section 134 as a drain constitute a so-called transfer transistor.

The pixel circuit 212 comprises a comparator 216 , a control circuit 214 and a pixel memory 220 . The comparator 216 compares the voltage of the storage section 134 with the reference voltage RAMP supplied from the pixel control circuit 250 and outputs the comparison result to the control circuit 214 . The comparator 216 is composed of, for example, a differential pair. In addition, for example, a source follower circuit may be arranged between the comparator 216 and the storage unit 134 . The control circuit 214 controls the pixel memory 220 based on the signal from the comparator 216 and the φCTL signal.

The pixel memory 220 stores pixel signals converted into digital signals. For example, the pixel memory 220 receives the count signal supplied from the pixel control circuit 250 and stores the value of the count signal when the control signal output from the control circuit 214 is inverted. The pixel memory 220 further outputs the stored pixel signal based on the selection signal φSEL. An example of pixel memory 220 is SRAM.

An example of the operation of the pixel 112 and the pixel circuit 212 for one frame will be described. First, at the start of accumulation of one frame, the pixel control circuit 250 simultaneously supplies the control signal φTX and the control signal φRST to reset the charge accumulated in the photoelectric conversion section 130 . Next, in a readout period at the end of one frame, the pixel control circuit 250 supplies a control signal φRST to reset the voltage of the storage section 134 to a predetermined voltage. After that, the pixel control circuit 250 controls the control signal φCTL, the reference voltage RAMP, and the count signal supplied to the pixel memory 220 to store the value corresponding to the reset voltage of the storage section 134 in the pixel memory 220 ( DARK conversion). Then, the read control circuit 260 reads the DARK conversion result data stored in the pixel memory 220 to the memory unit 310 by controlling the selection signal φSEL. Data reading from the pixel memory 220 will be further described later. Furthermore, the pixel control circuit 250 transfers the charge accumulated in the photoelectric conversion section 130 to the accumulation section 134 by supplying the control signal φTX. After that, the pixel control circuit 250 controls the control signal φCTL, the reference voltage RAMP, and the count signal to be supplied to the pixel memory 220 so that the value corresponding to the voltage of the storage section 134 after the charge transfer is transferred to the pixel memory 220. Store (SIG conversion). Finally, the readout control circuit 260 reads out the SIG conversion result data stored in the pixel memory 220 to the memory unit 310 by controlling the selection signal φSEL.

In this embodiment, one pixel circuit 212 is provided for one pixel 112, and all pixels 112 and pixel circuits 212 are controlled simultaneously. Therefore, a so-called global shutter operation in which a plurality of pixels 112 included in the pixel portion 110 are exposed at the same time is possible. It is also possible to perform an operation in which individual pixels 112 are exposed at separate times.

FIG. 5 is a schematic diagram illustrating a circuit for reading out data in the pixel memory 220 to the memory section 310. As shown in FIG. Configurations that are not described are omitted from the drawing.

The processing circuit unit 210 is provided with M×N pixel memories 220 corresponding to the M×N pixels 121 . Here, if the readout operation is performed from many pixel memories 220 at once, the current at the time of readout increases. Therefore, in the present embodiment, as described below, by bundling the output lines of the pixel signals read out from the plurality of pixel memories 220, or by temporarily storing the read out pixel signals in the memory unit 310, curb the current.

In FIG. 5, six pixel memories 220 arranged in three rows and two columns are commonly connected to an output line 302 . A pixel signal read from the pixel memory 220 is output to the output line 266 . Output lines 266 are sometimes referred to as bit lines. More specifically, three pixel memories 220 arranged in three rows and one column are connected to one sub output line 270, and three pixel memories 220 arranged in three rows and one column adjacent to them in the column direction are connected to each other. , and the sub-output lines 270 and 272 are connected to the output line 302 .

Here, since the pixel memory 220 stores a digital signal having a number of bits corresponding to the gradation of the image signal, each pixel 112 has a memory cell corresponding to the number of bits. For example, if 8 bits are used to express a pixel signal of one pixel in 256 monochrome gradations, 8 memory cells are used. Therefore, if the output from the pixel memory 220 is not time-divided, at least the output lines 302 corresponding to the number of bits are used for each column of the pixel memory 220 . In FIG. 5 and subsequent figures, wirings are hatched like the output line 302 in FIG. 5 to indicate that a plurality of wirings are represented by one wiring.

Furthermore, in the example of FIG. 5, the six pixel memories 220 arranged in three rows and two columns connected to the output line 302 and the six pixel memories 220 arranged in three rows and two columns adjacent to each other in the row direction output A line 304 is connected in common. More specifically, three pixel memories 220 arranged in three rows and one column are connected to one sub-output line 280, and three pixel memories 220 arranged in three rows and one column adjacent to them in the column direction are connected to the other. , and the sub-output lines 280 and 282 are connected to the output line 304 .

With the above configuration, it can be said that the six pixel memories 220 arranged in three rows and two columns are grouped into one with respect to readout. For convenience of explanation, the grouped pixel memories 220 are sometimes referred to as groups 290 and 291 .

Among the plurality of groups 290 and 291 , the pixel memories 220 at corresponding positions are commonly connected to row selection lines 264 and 265 of the readout control circuit 260 . A selection signal φSEL as an example of a control signal for reading pixel signals stored in the pixel memory 220 is output to the row selection lines 264 and 265 . Row select lines 264 are sometimes referred to as word select lines.

One pixel memory 220 included in each group 290 and 291 is selected by a selection signal φSEL, and pixel signals of the selected pixel memory 220 are output to output lines 302 and 304, respectively. In other words, it can be said that the reading is performed sequentially within each of the groups 290 and 291 and the reading is performed simultaneously between the groups.

Each group 290 , 291 preferably includes at least two row-wise pixel memories 220 . On the other hand, from the viewpoint of speeding up reading, it is preferable that the processing circuit unit 210 as a whole be grouped into two or more in the row direction. Similarly, each group 290, 291 preferably includes at least two pixel memories 220 arranged in the column direction, but the processing circuit unit 210 as a whole is grouped into two or more in the column direction. is preferred.

FIG. 6 shows an example of a planar layout of the third semiconductor substrate 300. As shown in FIG. A memory section 310 is arranged near the center of the surface of the third semiconductor substrate 300 .

The memory unit 310 has a plurality of memory blocks 312 arranged side by side along the row and column directions. The number of memory blocks 312 may be the same as the number of groups of pixel memories 220 included in the processing circuitry 210 . For example, if the pixel memories 220 are grouped into p rows and q columns, the memory section 310 may have (M/p)×(N/q) memory blocks 312 . The electrical connection between the memory block 312 and the group 290 via the output line 302 may be called corresponding.

In this embodiment, the memory block 312 and the corresponding group 290 of the pixel memories 220 are arranged at overlapping positions when viewed from the optical axis direction. In this case, the areas of memory block 312 and group 290 may be substantially the same, including margins between adjacent blocks. However, the number and arrangement of the memory blocks 312 are not limited to the example in FIG.

A peripheral circuit section 320 is arranged around the memory section 310 . The peripheral circuit section 320 includes a CDS circuit 322 . The CDS circuit 322 is an example of a noise removal unit that performs CDS (correlated double sampling) by subtracting, for each pixel, the result of DARK conversion from the result of SIG conversion.

FIG. 7 schematically shows memory block 312 . The memory block 312 has memory pairs 350 for k pixels for one output line 302 . Each memory pair 350 has a DARK memory 352 for storing the result of DARK conversion and a SIG memory 354 for storing the result of SIG conversion for one pixel. DARK memory 352 and SIG memory 354 may each be SRAM.

Therefore, one memory block 312 has 2k memories corresponding to k pixels included in one corresponding group 290 . If group 290 has pixel memories 220 corresponding to 6 pixels as in FIG. 5, then memory block 312 has 2×6=12 memories. Note that 2k or more memories may be provided.

As described with reference to FIG. 5, the pixel signals resulting from the DARK conversion are sequentially read from the plurality of pixel memories 220 in the group 290 to the output line 302 , so each pixel signal is stored in each DARK memory 352 . Next, pixel signals resulting from the SIG conversion are sequentially read out from the plurality of pixel memories 220 in the group 290 to the output line 302 , so that each pixel signal is stored in each SIG memory 354 . After that, the DARK conversion result and the SIG conversion result stored in each memory pair 350 corresponding to each pixel are read out to the CDS circuit 322 and subjected to noise removal processing.

In addition, in this embodiment, a memory block 312 is provided downstream separately from the pixel memory 220 as a latch for temporarily storing the pixel signal converted into a digital signal by the comparator 216 . As a result, it is possible to shorten the section in which the data must be read out quickly, and to reduce the current that flows during the readout.

FIG. 8 is a schematic diagram illustrating another circuit for reading out data in the pixel memory 220 to the memory section 310. As shown in FIG. The same reference numerals are assigned to the same configurations as those in FIGS. 1 to 7, and the description thereof is omitted. Also, one group 292 is illustrated in FIG.

In FIG. 8, six pixel memories 220 arranged in three rows and two columns are commonly connected to an output line 302 . However, unlike FIG. 5, the pixel memories 220 adjacent in the row direction are directly connected to the common output line 302 . This can further reduce the number of wirings for the output.

FIG. 9 schematically shows an arrangement example of pixel circuits 212 and 213 adjacent in the row direction of FIG. In FIG. 9, the pixel circuits 212 on one side and the pixel circuits 213 on the other side are at least partially arranged line-symmetrically with respect to the output line 302 . In the example of FIG. 9, the order of arrangement of the comparator 216, the control circuit 214 and the pixel memory 220 is line symmetrical. The arrangement of the elements of each circuit may also be axisymmetric. Furthermore, the arrangement including the pixels 112 may be line-symmetrical.

FIG. 10 is a schematic diagram illustrating still another circuit for reading out data in the pixel memory 220 to the memory section 310. As shown in FIG. The same reference numerals are assigned to the same configurations as those in FIGS. 1 to 9, and the description thereof is omitted. Also, one group 293 is illustrated in FIG.

In FIG. 10, three pixel memories 220 arranged in three rows and one column are connected to one sub-output line 270, and three pixel memories 220 arranged in three rows and one column adjacent to them in the column direction are connected to each other. is connected to the sub-output line 272 of . One of the two sub-output lines 270 and 272 is connected to the output line 302 via a switching section 274 .

The switching unit 274 is operated in conjunction with the selection signal φSEL. The switching unit 274 connects the sub-output line 270 to the output line 302 when a pixel signal is output to the sub-output line 270 . On the other hand, the switching unit 274 connects the sub-output line 272 to the output line 302 when a pixel signal is output to the sub-output line 272 . This makes it possible to further reduce the wiring capacity.

FIG. 11 is a schematic diagram illustrating still another circuit for reading out data in the pixel memory 220 to the memory section 310. As shown in FIG. The same reference numerals are assigned to the same configurations as in FIGS. 1 to 10, and the description thereof is omitted. Also, one group 294 is illustrated in FIG.

Group 294 in FIG. 11 is a combination of group 292 in FIG. 8 and group 293 in FIG. First, 6 pixel memories 220 arranged in 3 rows and 2 columns are directly connected to the sub-output line 270 , and the other 6 pixel memories 220 arranged in 3 rows and 2 columns are directly connected to the sub-output line 272 . properly connected. One of the two sub-output lines 270 and 272 is connected to the output line 302 via a switching section 274 . This makes it possible to further reduce the wiring capacity.

FIG. 12 is a schematic diagram illustrating still another circuit for reading the data in the pixel memory 220 to the memory section 310. As shown in FIG. The same reference numerals are assigned to the same configurations as those in FIGS. 1 to 11, and the description thereof is omitted. Also, one group 295 is illustrated in FIG.

Group 295 corresponds to group 293 of FIG. 10 with row select line 265 omitted. In each group 295, the output from the pixel memory 220 in the row direction can be substantially switched by the switching unit 274. Therefore, even if the number of row selection lines for selecting the row direction is omitted, sequential readout can be performed within the group 293. can do.

FIG. 13 is a schematic diagram illustrating still another circuit for reading the data in the pixel memory 220 to the memory section 310. As shown in FIG. The same reference numerals are assigned to the same configurations as in FIGS. 1 to 12, and the description thereof is omitted. Also, one group 296 is illustrated in FIG.

Group 296 corresponds to group 294 of FIG. 11 with row select line 265 omitted. In each group 295, the output from the pixel memory 220 in the row direction can be substantially switched by the switching unit 274. Therefore, even if the number of row selection lines for selecting the row direction is omitted, sequential readout can be performed within the group 295. can do.

FIG. 14 is a diagram showing an outline of another imaging device 402. As shown in FIG. In the imaging device 402, the same reference numerals are assigned to the same configurations as in the imaging device 400, and the description thereof is omitted.

The imaging element 402 differs from the imaging element 400 in that it has a CDS section 314 and an output section 326 instead of the memory section 310 and the peripheral circuit section 320 on the third semiconductor substrate 300 . CDS section 314 has a plurality of CDS blocks 316 . The number, arrangement, and connection relationship with the pixel memory 220 of the CDS blocks 316 may be the same as those of the memory blocks 312 of the image sensor 400 . The output unit 326 reads out pixel signals stored in the CDS unit 314 .

FIG. 15 schematically shows the CDS block 316. As shown in FIG. The CDS block 316 has a Gray code to binary conversion circuit 360 , a CDS circuit 362 and a plurality of dual purpose memories 364 .

The Gray code/binary conversion circuit 360 converts the pixel signal output to the output line 302 from Gray code to binary, and outputs it to the CDS circuit 362 . CDS circuit 362 has the same function as CDS circuit 322 described above, except where noted.

Each of the multiple shared memories 364 is selectively connected to the signal line 367 via the switch 366 and selectively connected to the signal line 369 via the switch 368 . The dual-purpose memory 364 preferably has k+1 pixels in the corresponding pixel memory 220 group. For example, if group 290 includes pixel memory 600 for 6 pixels in the example of FIG. 5, CDS block 316 preferably includes shared memory 364 for 7 pixels. Note that the number of shared memories 364 may be larger than that. The shared memories 364 may each be an SRAM. For the sake of explanation, the shared memories are numbered from (0) to (k) to distinguish them.

In the CDS block 316 , the results of the DARK conversion are sequentially output from the corresponding plurality of pixel memories 220 , and converted from Gray code to binary by the Gray code/binary conversion circuit 360 . Further, the φBYPS signal is supplied to the CDS circuit to bypass the circuit, and the result of the DARK conversion after conversion from Gray code to binary is stored in the shared memory as it is. In this case, by sequentially turning on and off the switches 368 of shared memories (1) to (k), the results of the DARK conversion from the first pixel to the k-th pixel output to the signal line 369 are stored respectively.

Next, the results of the SIG conversion are sequentially output from the corresponding plurality of pixel memories 220 and converted from Gray code to binary by the Gray code/binary conversion circuit 360 . Here, when the result of SIG conversion of the j-th pixel (j is an integer from 1 to k) is converted from Gray code to binary, the result of DARK conversion stored in dual-purpose memory (j) is transferred to switch 366. is turned on, it is output to the signal line 367 and input to the CDS circuit 362 , and the result of SIG conversion is also input to the CDS circuit 362 . As a result, the CDS circuit 362 performs CDS processing, and the result is stored by turning on the switch 368 of the shared memory (j-1). This is repeated from j=1 to k.

In addition, the shared memory (j) is a memory for storing the result of the jth DARK conversion and also a memory for storing the result of the (j+1)th CDS processing. In this embodiment, apart from the pixel memory 220 as a latch for temporarily storing pixel signals converted into digital signals by the comparator 216, a plurality of shared memories 364 are provided downstream thereof. As a result, it is possible to shorten the section in which the data must be read out quickly, and to reduce the current that flows during the readout.

FIG. 16 schematically shows another CDS block 318. As shown in FIG. In the CDS block 318, the same reference numerals are given to the same configurations as those of the CDS block 316 in FIG. 15, and the description thereof will be omitted.

The CDS block 318 has k shared memories 364 and one buffer memory 370 . The buffer memory 370 may be an SRAM, and there may be two or more.

First, in the CDS block 318 , the results of the DARK conversion are sequentially output from the corresponding plurality of pixel memories 220 and converted from Gray code to binary by the Gray code/binary conversion circuit 360 . Further, the φBYPS signal is applied to the CDS circuit to bypass the circuit, and the results of DARK conversion after conversion from Gray code to binary are sequentially stored in shared memories (0) to (k−1) as they are.

Next, the results of the SIG conversion are sequentially output from the corresponding plurality of pixel memories 220 and converted from Gray code to binary by the Gray code/binary conversion circuit 360 . Here, when the SIG conversion result of the j-th pixel (j is an integer from 1 to k) is converted from Gray code to binary, the DARK conversion result stored in the shared memory (j-1) is By turning on the switch 366 , the signal is buffered in the buffer memory 370 via the signal line 367 . The DRAK conversion result of the buffer memory 370 and the j-th SIG conversion result output from the Gray code/binary conversion circuit 360 are input to the CDS circuit 362 . As a result, the CDS circuit 362 performs CDS processing, and the result is stored by turning on the switch 368 of the dual-purpose memory (j-1), which is already empty.

In addition, shared memory (j) is a memory for storing the result of the jth DARK conversion and also a memory for storing the result of the jth CDS processing. Buffer memory 370 is a buffer used for storing k pixels. In this embodiment, a plurality of shared memories 364 and at least one buffer memory 370 are provided downstream of the pixel memory 220 as a latch for temporarily storing the pixel signal converted into a digital signal by the comparator 216. . As a result, it is possible to shorten the section in which the data must be read out quickly, and to reduce the current that flows during the readout.

As described above, according to the present embodiment, it is possible to reduce the current that flows during reading. Note that one control circuit 214 is provided for one pixel 112 in the above embodiment. Alternatively, one control circuit 214 may be provided for multiple pixels 112 . In this case, if a plurality of pixels 112 corresponding to one control circuit 214 is called a pixel block, the pixels 112 included in one pixel block are m rows and n columns (m is a natural number of 2 or more and less than M, n is a natural number equal to or greater than 2 and smaller than N), and a plurality of the pixel blocks may be arranged in the matrix direction.

It should be noted that each of the above-described embodiments has a three-layer structure having a first semiconductor substrate 100, a second semiconductor substrate 300 and a third semiconductor substrate 300. FIG. Alternatively, the second semiconductor substrate 200 may have the configuration and functions of the third semiconductor substrate of the above embodiment. That is, even if the processing circuit portion 210 and the like and the memory portion 310 and the like (or the CDS portion 314) are provided on the same semiconductor substrate while maintaining the wiring structure of at least one of FIGS. good.

FIG. 17 is a block diagram showing a configuration example of an imaging device 500 according to the embodiment. The imaging apparatus 500 includes an imaging device 400, a system control unit 501, a driving unit 502, a photometry unit 503, a work memory 504, a recording unit 505, a display unit 506, a driving unit 514, and an imaging lens 520. Prepare. An imaging device 402 may be used instead of the imaging device 400 .

The photographing lens 520 guides subject light beams incident along the optical axis OA to the image sensor 400 . The photographing lens 520 is composed of a plurality of optical lens groups, and forms an image of subject light flux from a scene in the vicinity of its focal plane. The imaging lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500 . In addition, in FIG. 17, the photographing lens 520 is represented by one virtual lens arranged in the vicinity of the pupil.

A driving unit 514 drives a photographing lens 520 . In one example, the drive unit 514 moves the optical lens group of the taking lens 520 to change the focus position. Further, the driving unit 514 may drive the iris diaphragm in the photographing lens 520 to control the light amount of the subject light flux incident on the imaging device 400 .

The drive unit 502 has a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 400 according to instructions from the system control unit 501 . Further, the operation unit 508 receives instructions from the photographer using a release button or the like.

The image pickup device 400 transfers pixel signals to the image processing unit 511 of the system control unit 501 . The image processing unit 511 generates image data by performing various image processing using the work memory 504 as a workspace. For example, when generating image data in the JPEG file format, compression processing is executed after a color video signal is generated from the signal obtained in the Bayer array. The generated image data is recorded in the recording unit 505, converted into a display signal, and displayed on the display unit 506 for a preset time.

A photometry unit 503 detects the luminance distribution of a scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor with approximately one million pixels. A calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the brightness for each area of the scene.

A calculation unit 512 determines the shutter speed, the aperture value, and the ISO sensitivity according to the calculated luminance distribution. The photometry unit 503 may also be used by the image sensor 400 . Note that the calculation unit 512 also executes various calculations for operating the imaging device 500 . The drive unit 502 may be partially or wholly mounted on the imaging device 400 . A part of the system control unit 501 may be mounted on the imaging device 400 .

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the scope of claims that forms with such modifications or improvements can also be included in the technical scope of the present invention.

The execution order of each process such as actions, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly "before", "before etc., and it should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if the description is made using "first," "next," etc. for the sake of convenience, it means that it is essential to carry out in this order. not a thing

100 first semiconductor substrate 110 pixel unit 112 pixel 130 photoelectric conversion unit 132 reset unit 134 storage unit 136 transfer unit 200 second semiconductor substrate 210 processing circuit unit 212, 213 pixel circuit 214 control circuit , 216 comparator, 220 pixel memory, 230 peripheral circuit section, 250 pixel control circuit, 260 readout control circuit, 264, 265 row selection line, 270, 272, 280, 282 sub-output line, 274 switching section, 290, 291, 292 groups, 302, 304 output lines, 310 memory section, 312 memory block, 314 CDS section, 316, 318 CDS block, 320 peripheral circuit section, 322, 362 CDS circuit, 326 output section, 350 memory pair, 352 DARK memory, 354 SIG memory, 360 Gray code/binary conversion circuit, 364 shared memory, 366, 368 switch, 367, 369 signal line, 370 buffer memory, 400, 402 imaging device, 500 imaging device, 501 system control unit, 502 driving unit, 503 photometry unit, 504 work memory, 505 recording unit, 506 display unit, 508 operation unit, 511 image processing unit, 512 calculation unit, 514 driving unit, 520 photographing lens

Claims (10)

a plurality of conversion units arranged side by side in the row direction for converting analog signals into digital signals;
a first output line connected to a plurality of first conversion units among the plurality of conversion units and outputting a signal converted into a digital signal by the first conversion unit;
a second output line connected to a plurality of second conversion units among the plurality of conversion units and outputting a signal converted into a digital signal by the second conversion unit;
An image sensor. a first sub-output line for outputting a signal from one of the plurality of first conversion units;
a second sub-output line for outputting a signal from another one of the plurality of first converters;
2. The imaging device according to claim 1, further comprising a first switching unit that switches connection with the first output line to either the first sub-output line or the second sub-output line. 3. An arrangement of at least a part of one conversion portion among the plurality of first conversion portions and another conversion portion adjacent to the one conversion portion in a column direction is line symmetrical with each other. The imaging device according to . further comprising a storage unit that stores the signal output to the first output line;
The imaging device according to any one of claims 1 to 3, wherein the storage section has at least the same number of storage areas as the plurality of first conversion sections. 5. The imaging device according to claim 4, further comprising a noise removal section that performs noise removal processing based on the signal stored in the storage section. 6. The imaging device according to claim 5, wherein the number of the storage areas is at least twice the number of the plurality of first conversion units. 5. The imaging device according to claim 4, further comprising a noise removal section that stores a noise-processed signal in the storage section based on the signal output to the first output line. 8. The imaging device according to claim 7, wherein the number of the storage areas is at least one larger than the number of the plurality of first conversion units. a first semiconductor substrate on which the plurality of conversion units are arranged;
9. The imaging device according to any one of claims 4 to 8, further comprising a second semiconductor substrate laminated with the first semiconductor substrate and provided with the storage section. An imaging apparatus comprising the imaging device according to claim 1 .

Images