JP2024006293A - Imaging element and imaging device - Google Patents

Abstract

To provide an imaging element and an imaging device capable of performing wide dynamic range imaging.SOLUTION: In a processing circuit part of an imaging element, an exposure control part 10 of a processing block includes a signal generation part (register 300) for generating a signal which is timing reference for pixel control, and a delay circuit 306 for delaying the reference signal to output it as a timing signal. The delay circuit delays the signal using a clock on a frequency according to a delay amount within a plurality of clocks having different frequencies. The signal generation part outputs one signal within a plurality of reference signals having mutually different timing to the delay circuit. The delay circuit delays the one signal and outputs a timing signal having timing between the timing by the one signal and the timing by other signals.SELECTED DRAWING: Figure 7

Description

The present invention relates to an imaging device and an imaging device.

A solid-state image sensor in which unit pixels are two-dimensionally arranged in a matrix is known (for example, Patent Document 1). Expansion of dynamic range has been required for a long time.
[Prior art documents]
[Patent document]
[Patent Document 1] Unexamined Japanese Patent Publication No. 2011-244309

In a first aspect of the present invention, the image sensor includes a signal generation unit that generates a signal that serves as a reference timing for controlling pixels, and a delay unit that delays the reference signal and outputs it as a timing signal. circuit.

In a second aspect of the present invention, there is provided an imaging device including the above-mentioned imaging element.

Note that the above summary of the invention does not list all the features of the invention. Furthermore, subcombinations of these features may also constitute inventions.

FIG. 4 is a diagram showing an outline of an image sensor 400 according to the present embodiment. An example of a specific configuration of the pixel section 110 is shown. An example of the circuit configuration of the pixel 112 is shown. An example of a more specific configuration of the processing circuit section 210 is shown. FIG. 4 is a schematic cross-sectional view for explaining an example of a wiring method for an image sensor 400. FIG. A timing chart of exposure and readout is schematically shown. 3 shows a circuit block of the exposure control unit 10 that specifically generates the signal DLY_HIT. A timing chart for generating the signal DLY_HIT is shown. Another example of a timing chart for generating the signal DLY_HIT is shown. In particular, a circuit block for generating the signal DLY_HIT of the other exposure control section 12 is shown. A timing chart for generating the signal DLY_HIT by the exposure control unit 12 is shown. FIG. 2 is a block diagram showing a configuration example of an imaging device 500 according to an embodiment.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are essential to the solution of the invention.

In this specification, the X axis and the Y axis are orthogonal to each other, and the Z axis is orthogonal to the XY plane. The XYZ axes constitute a right-handed system. The direction parallel to the Z-axis is sometimes referred to as the stacking direction of the image sensor 400. In this specification, the terms "upper" and "lower" are not limited to the vertical direction in the direction of gravity. These terms only refer to relative directions in the Z-axis direction. In this specification, the arrangement in the X-axis direction is referred to as a "row" and the arrangement in the Y-axis direction is referred to as a "column," but the matrix direction is not limited to this. Further, the Z-axis direction is the optical axis direction in which light from the subject is incident.

FIG. 1 is a diagram showing an outline of an image sensor 400 according to this embodiment. The image sensor 400 images a subject. The image sensor 400 generates image data of a photographed subject. The image sensor 400 includes a first substrate 100 and a second substrate 200. As shown in FIG. 1, the first substrate 100 is stacked on the second substrate 200.

The first substrate 100 has a pixel section 110. The pixel unit 110 outputs a pixel signal based on the incident light. Note that the first substrate 100 may be referred to as a pixel chip.

The second substrate 200 has a processing circuit section 210 and a peripheral circuit section 230. Note that the second substrate 200 may be referred to as a signal processing chip.

The processing circuit unit 210 receives pixel signals output from the first substrate 100. The processing circuit unit 210 processes input pixel signals. For example, the processing circuit unit 210 performs a process of converting an analog signal into a digital signal. Specifically, the processing circuit unit 210 performs a process of converting an input pixel signal into a digital signal. The processing circuit section 210 may perform other signal processing.

The processing circuit section 210 in this example is arranged on the second substrate 200 at a position facing the pixel section 110. That is, the processing circuit section 210 is arranged so as to at least partially overlap the pixel section 110 in the optical axis direction. The processing circuit section 210 may output a control signal to the pixel section 110 to control driving of the pixel section 110.

The peripheral circuit section 230 controls driving of the processing circuit section 210. The peripheral circuit section 230 is arranged around the processing circuit section 210 on the second substrate 200 . Further, the peripheral circuit section 230 may be electrically connected to the first substrate 100 to control driving of the pixel section 110.

In addition to the first substrate 100 and the second substrate 200, the image sensor 400 may include a third substrate laminated on the second substrate 200. For example, the third substrate is a memory chip, and performs image processing according to the signal output by the second substrate 200. Further, the structure of the image sensor 400 may be a back-illuminated type or a front-illuminated type. An example of a back-illuminated type will be explained below.

FIG. 2 shows an example of a specific configuration of the pixel section 110. In this example, an enlarged view of a pixel section 110 and a pixel block 120 provided in the pixel section 110 is shown.

The pixel section 110 has a plurality of pixel blocks 120 arranged in line along the row and column directions. The pixel section 110 of this example has M×N pixel blocks 120 (M and N are natural numbers). Although this example shows a case where M is equal to N, M and N may be different.

Pixel block 120 has at least one pixel 112. The pixel block 120 in this example has m×n pixels 112 (m and n are natural numbers). For example, pixel block 120 has 16×16 pixels 112. The number of pixels 112 corresponding to the pixel block 120 is not limited to this. In this example, a case where m is equal to n is illustrated, but m may be different from n. The pixel block 120 has a plurality of pixels 112 connected to a common control line in the row direction. For example, each pixel 112 of the pixel block 120 is connected to a common control line so as to be set to the same exposure time. In one example, n pixels 112 arranged in a row are connected by a common control line.

On the other hand, different exposure times may be set for the plurality of pixel blocks 120. That is, each pixel 112 of the pixel block 120 has the same exposure time, but other pixel blocks 120 may be set to different exposure times. For example, when pixels 112 of a pixel block 120 are connected in the row direction by a common control line, pixels 112 of other pixel blocks 120 are commonly connected by different control lines.

Pixel blocks 120 are arranged corresponding to processing blocks 220, which will be described later. In this embodiment, one pixel block 120 is arranged for one processing block 220.

The pixel 112 has a photoelectric conversion function that converts light into charge. The pixel 112 accumulates photoelectrically converted charges. The m pixels 112 are arranged side by side along the column direction and connected to a common signal line 122. The m pixels 112 are arranged in n columns in the row direction in the pixel block 120.

In other words, the pixel block 120 is a collection of a plurality of pixels 112 connected by a common control line and/or signal line. Furthermore, it can be said that the pixel block 120 is the minimum unit of a circuit of a plurality of pixels 112 to which the same exposure time is set.

FIG. 3 shows an example of the circuit configuration of the pixel 112. The pixel 112 includes a photoelectric conversion section 104, a transfer section 123, an ejection section 124, a reset section 126, and a pixel output section 127. The pixel output section 127 includes an amplification section 128 and a selection section 129. In this example, the transfer section 123, the discharge section 124, the reset section 126, the amplification section 128, and the selection section 129 are described as N-channel FETs, but the types of transistors are not limited to this.

The photoelectric conversion unit 104 has a photoelectric conversion function of converting light into charges. The photoelectric conversion unit 104 accumulates photoelectrically converted charges. The photoelectric conversion unit 104 is, for example, a photodiode.

The transfer unit 123 transfers the charges accumulated in the photoelectric conversion unit 104 to the accumulation unit 125. The transfer unit 123 is an example of a transfer gate that transfers the charge of the photoelectric conversion unit 104. In other words, the transfer section 123 serves as a gate, the photoelectric conversion section 104 serves as a source, and the storage section 125 serves as a drain, which constitute a so-called transfer transistor.

The discharge unit 124 discharges the charges accumulated in the photoelectric conversion unit 104 to the power supply wiring to which the power supply voltage VDD is supplied. In this example, the discharge unit 124 has been described as discharging the charge of the photoelectric conversion unit 104 to the power supply wiring to which the power supply voltage VDD is supplied, but the discharge unit 124 discharges the charge from the photoelectric conversion unit 104 to the power supply wiring to which a power supply voltage different from the power supply voltage VDD is supplied. May be discharged.

The charge from the photoelectric conversion unit 104 is transferred to the storage unit 125 by the transfer unit 123 . The storage unit 125 is an example of a floating diffusion (FD).

The reset unit 126 discharges the charge in the storage unit 125 to a power supply wiring to which a predetermined power supply voltage VDD is supplied.

The pixel output section 127 outputs a signal based on the potential of the storage section 125 to the signal line 122. The pixel output section 127 includes an amplification section 128 and a selection section 129. The amplifier section 128 has a gate terminal connected to the storage section 125 , a drain terminal connected to a power supply wiring to which power supply voltage VDD is supplied, and a source terminal connected to the drain terminal of the selection section 129 .

The selection unit 129 controls the electrical connection between the pixel 112 and the signal line 122. When the pixel 112 and the signal line 122 are electrically connected by the selection unit 129, a pixel signal is output from the pixel 112 to the signal line 122. A source terminal of the selection section 129 is connected to the load current source 121.

Load current source 121 supplies current to signal line 122 . The load current source 121 may be provided on the first substrate 100 or the second substrate 200.

Hereinafter, any one of the charges accumulated in the photoelectric conversion unit 104, the charges transferred to the accumulation unit 125, and the signal based on the potential of the accumulation unit 125, or these may be collectively referred to as a pixel signal.

In addition, the pixel 112 includes at least one photoelectric conversion section 104 and a pixel output section 127 serving as a readout section that reads out an image signal from the at least one photoelectric conversion section 104 onto the signal line 122. The pixel 112 can also be said to be the minimum unit of a circuit that outputs pixel signals constituting an image to the signal line 122.

FIG. 4 shows an example of a more specific configuration of the processing circuit section 210. In this example, an enlarged view of a processing circuit section 210 and a processing block 220 provided in the processing circuit section 210 is shown.

The processing circuit section 210 has processing blocks 220 arranged in parallel along the row and column directions. The processing circuit section 210 of this example has M×N processing blocks 220.

In this embodiment, the processing block 220 and the pixel block 120 are arranged at overlapping positions when viewed from the optical axis direction. In this case, the processing block 220 and the pixel block 120 may have approximately the same area including the margin between adjacent blocks.

The processing block 220 controls the driving of the pixel blocks 120 to which it is electrically connected. The fact that the processing block 220 and the pixel block 120 are electrically connected is sometimes called "corresponding". In this embodiment, the processing block 220 and the pixel block 120, which are arranged in overlapping positions, are connected. However, instead of connecting the processing block 220 and the pixel block 120 arranged in overlapping positions, the processing block 220 and the pixel block 120 arranged in non-overlapping positions may be connected.

For example, processing block 220 controls the exposure time of the corresponding pixel block 120. Furthermore, the processing block 220 includes a processing circuit such as an AD converter 42, and processes the signal output from the corresponding pixel block 120. In one example, processing block 220 converts an analog pixel signal output from a corresponding pixel block 120 into a digital signal. The processing block 220 in this example includes an exposure control section 10, a pixel drive section 20, a joining section 30, a signal conversion section 40, and a signal output section 50.

The exposure control unit 10 controls exposure of the plurality of pixels 112. The exposure control unit 10 generates a signal for controlling the exposure time of the pixel 112. In one example, the exposure control unit 10 controls the exposure time for each pixel block 120 by adjusting at least one of the start timing and end timing of exposure.

The pixel driving section 20 is electrically connected to the plurality of pixels 112. The pixel drive section 20 selects and drives an arbitrary pixel 112 from the plurality of pixels 112 based on a signal from the exposure control section 10 . Since the image sensor 400 can set the exposure time for each pixel block 120 according to the intensity of incident light, the dynamic range can be expanded.

The joining portion 30 joins the first substrate 100 and the second substrate 200. The junction section 30 inputs the pixel signal input from the first substrate 100 to the signal conversion section 40 . The junction section 30 is provided corresponding to the n pixels 112 arranged in the row direction, and inputs pixel signals to the signal conversion section 40 for each column.

The signal converter 40 converts the analog signal output from the pixel unit 110 into a digital signal. The signal converter 40 of this example converts an analog pixel signal into a digital signal. The signal converter 40 sequentially converts analog signals from the m pixels 112 arranged in the column direction into digital signals. The signal converter 40 includes n AD converters 42 arranged in the row direction. Each of the AD converters 42 converts analog signals from the pixels 112 in the corresponding column of the corresponding pixel block 120 into digital signals in parallel. This can be said to be a so-called column ADC method for one pixel block 120.

The signal output section 50 receives the digital signal from the signal conversion section 40. In one example, the signal output unit 50 temporarily stores the digital signal. The signal output section 50 may include a latch circuit for storing digital signals.

Note that instead of providing one processing block 220 for one pixel block 120, one processing block 220 may be provided for N pixel blocks 120 (N is a natural number of 2 or more). N pixel blocks 120 corresponding to one processing block may be referred to as a pixel block group. For example, one processing block 220 may be provided with two pixel blocks 120 arranged side by side along the column direction as one pixel block group. In this case, the processing block 220 may control the exposure time for each pixel block 120.

In addition, the processing block 220 can be said to be the minimum unit of a circuit that is electrically connected to at least one pixel block 120 and processes a pixel signal of the at least one pixel block 120. Furthermore, it can be said that the processing circuit section 210 is composed of a group of processing blocks 220.

FIG. 5 is a schematic cross-sectional view for explaining an example of a wiring method for the image sensor 400. In FIG. 5, a plurality of signal lines (for example, mutually parallel signal lines corresponding to the number of bits) may be represented by one signal line.

The peripheral circuit section 230 includes a block control section 240 that supplies signals for individually controlling each of the processing blocks 220, and a common control section 250 that supplies common control signals to the processing circuit section 210. The block control section 240 is connected to the exposure control section 10 of each processing block 220 by a signal line 242. The common control section 250 is connected to the exposure control section 10 of each processing block 220 through a signal line 252 and to the signal conversion section 40 through a signal line 254.

The pixel driving section 20 is connected to the gate terminal of the reset section 126 through a signal line 141. The signal line 142 is connected to the gate terminal of the transfer section 123. The signal line 143 is connected to the gate terminal of the discharge section 124. The signal line 144 is connected to the gate terminal of the selection section 129.

A signal line 130 from the junction 30 supplies the power supply voltage, and a signal line 132 is the ground. Pixel signals are read out to the signal line 122 as described above.

The plurality of bumps 152 are provided on the bonding surface where the first substrate 100 and the second substrate 200 are bonded to each other. The bumps 152 on the first substrate 100 are aligned with the bumps 152 on the second substrate 200. The plurality of bumps 152 facing each other are joined together by applying pressure to the first substrate 100 and the second substrate 200, and are electrically connected.

FIG. 6 schematically shows a timing chart of exposure and readout. In FIG. 6, signals other than those related to frame (n) are omitted.

In the example of FIG. 6, the time of one frame is fixed, for example, 1 ms. In FIG. 6, the FRM timing is also illustrated to explain the frame division. Let T0 be the start time of frame (n).

The exposure time is controlled by the emission control signal φTX2. First, at time T1, a signal DLY_HIT indicating the timing of generating the emission control signal φTX2 is generated. Generation of the signal DLY_HIT will be described later.

After the signal DLY_HIT is turned on, the discharge control signals φTX2<n> of n rows in the pixel block 120 are sequentially turned on based on the counter RST_CNT. Exposure starts at the falling edge after which it turns off (time T2 for the <0> row pixels).

Next, the transfer control signal φTX1 is sequentially turned on based on the counter RST_CNT. Exposure ends at the falling edge when the light is then turned off (time T4 for the pixels in the <0> row). Thereby, the charges accumulated in the photoelectric conversion section 104 are transferred to the accumulation section 125 and read out to the signal line 122 as a pixel signal.

In addition, for the pixels in the <0> row, the exposure time is from time T2 to T4. Note that when the exposure time is longer than one frame, the transfer control signal φTX1 and the selection control signal φSEL<n> are skipped. Further, in the example of FIG. 6, the reset control signal φRST and the discharge control signal φTX2 are at the same timing, but they do not necessarily have to be at the same timing. Similarly, in the example of FIG. 6, the selection control signal φSEL<n> and the transfer control signal φTX1 are at the same timing, but they do not necessarily have to be at the same timing.

According to the example of FIG. 6, by generating the signal DLY_HIT for each processing block 220, the exposure start time can be controlled for each pixel block 120 corresponding to the processing block 220. On the other hand, the timing of transfer and readout is common in the processing circuit section 210.

FIG. 7 shows a circuit block of the exposure control section 10, particularly for generating the signal DLY_HIT. The exposure control section 10 includes a register 300, a trigger selection circuit 302, a clock selection circuit 304, a delay circuit 306, and a counter 308.

FIG. 8 shows a timing chart for generating the signal DLY_HIT. In FIG. 8, signals other than those related to frame (n) are omitted.

The register 300 is supplied with data REG_DAT regarding exposure of the processing block 220 in synchronization with the clock REG_CLK from the block control unit 240 before the start of frame (n), that is, within the time of frame (n-1). Data REG_DAT includes information on time T1 at which signal DLY_HIT is generated.

A signal TRG_SIG is input to the trigger selection circuit 302 from the common control section 250. The signal TRG_SIG is a signal generated at different predetermined timings from frame start time T0, such as 1/1 frame, 1/2 frame, and 1/4 frame. Eight types of signals TRG_SIG#1 to #8 of, for example, 1/(2n) frames (n is a natural number from 1 to 8) are input to the trigger selection circuit 302.

The clock GLB_CLK is input to the clock selection circuit 304 from the common control unit 250 . In this example, the clock GLB_CLK is common to the plurality of block control units 240. Furthermore, in this example, the clock GLB_CLK is shared with the AD converter 42 as an example of another circuit. The AD converter 42 may be of a single slope type, for example. Clock selection circuit 304 receives clocks GLB_CLK #1 to #12 of types corresponding to the number of bits of AD converter 42 . The clocks GLB_CLK #1 to #12 have a sufficiently high frequency compared to the time between the respective signals TRG_SIG described above. Here, the clock GLB_CLK corresponding to the lower bit has a higher frequency, for example, twice the frequency.

Based on data REG_DAT, register 300 determines the type of signal TRG_SIG, the type of clock GLB_CLK, and the number of clocks used to generate signal DLY_HIT at time T1. For example, the register 300 first selects the closest signal TRG_SIG before time T1 (signal TRG_SIG#2 in the example of FIG. 8). Next, the type and number of clocks GLB_CLK are determined based on the difference between time T1 and time TA of signal TRG_SIG. Here, it is preferable to select the type of clock GLB_CLK so that the delay amount is counted using a clock GLB_CLK with a lower frequency, that is, the number of clocks to be counted is smaller (in the example of FIG. 8, clock GLB_CLK #1). . The type of signal TRG_SIG to be selected and the type of clock GLB_CLK used for its delay may be associated in advance. Then, the number of clocks is determined (7 clocks in the example of FIG. 8).

The register 300 outputs the selected type of signal TRG_SIG to the trigger selection circuit 302 as a signal TRG_SEL. When the signal TRG_SIG specified by the signal TRG_SEL is turned on, the trigger selection circuit 302 inputs it to the delay circuit 306 as a reference signal ORG_HIT.

Further, the register 300 outputs the type of the selected clock GLB_CLK to the clock selection circuit 304 as a signal CLK_SEL. The clock selection circuit 304 inputs the clock specified by the signal CLK_SEL to the delay circuit 306 as a delay clock DLY_CLK.

Further, the register 300 inputs the determined number of clocks to the delay circuit 306 as a signal DLY_CNT. The delay circuit 306 generates a signal DLY_HIT by delaying the signal ORG_HIT by counting the clock DLY_CLK by the count number specified by the signal DLY_CNT after the signal ORG_HIT is turned on. The delay circuit 306 inputs the generated signal DLY_HIT to the counter 308.

When the counter 308 receives the signal DLY_HIT, it outputs a counter RST_CNT that sequentially counts rows based on the clock COL_CLK to the pixel driving unit 20. The pixel driving unit 20 turns on the reset control signal φRST and the discharge control signal φTX2<n> of the pixel 112 in row n indicated by the counter RST_CNT.

As described above, by delaying the reference signal ORG_HIT using the clock GLB_CLK input from the common control unit 250, the signal DLY_HIT at the timing to control the pixel 112 is generated. This makes it possible to generate a signal with a timing different from that of the signal TRG_SIG, which is the source of the reference signal ORG_HIT. For example, a signal with a timing between signal TRG_SIG#1 and signal TRG_SIG#2 can be generated. In this case, by sharing the clock GLB_CLK with other circuits, it is possible to finely control the exposure time, that is, increase the number of exposure stages, while suppressing the circuit scale.

FIG. 9 shows another example of a timing chart for generating the signal DLY_HIT. In FIG. 9, description of the same configuration and operation as in FIG. 8 will be omitted.

In the example of FIG. 9, signal TRG_SIG#3 is selected as the reference signal ORG_HIT. Furthermore, clock GLB_CLK#2 is selected as delay clock DLY_CLK for delaying signal ORG_HIT. By delaying the signal ORG_HIT from time TB by seven clocks using the clock GLB_CLK#2, the signal DLY_HIT at the timing T5 is generated.

Comparing FIG. 9 with FIG. 8, the number of clocks to be delayed is the same, but since the frequency of the delay clocks is different, the amount of delay is different. More specifically, since the clock GLB_CLK#2 has a lower frequency than the clock GLB_CLK#1, the amount of delay is greater. Here, in the case of FIG. 9 as well, although it is possible to delay using the high frequency clock GLB_CLK#1, the number of clocks to be counted can be reduced by using the low frequency clock GLB_CLK#2. By reducing the number of clocks to be counted, the circuit scale of the delay circuit 306 can be reduced.

Note that in the examples of FIGS. 7 to 9, the signal ORG_HIT is delayed. Alternatively, the signal TRG_SIG from the common control unit 250 may be delayed by the delay circuit 306, and one of them may be selected by the trigger selection circuit 302 as the timing signal DLY_HIT.

FIG. 10 shows another circuit block of the exposure control section 12, particularly for generating the signal DLY_HIT. FIG. 11 shows a timing chart when the exposure control unit 12 generates the signal DLY_HIT.

In the exposure control section 12, the same components as the exposure control section 10 of FIG. 7 are given the same reference numerals, and a description thereof will be omitted. The main difference is that the exposure control section 12 does not use the trigger selection circuit 302 of the exposure control section 10.

In the exposure control unit 12, the signal DLY_HIT is generated by counting the clock GLB_CLK selected by the clock selection circuit 304 by the count number DLY_CNT in the delay circuit 312. This can be said to generate the signal DLY_HIT at time T6 by delaying the frame start signal FRM as a reference. Furthermore, it can be said that the signal DLY_HIT is generated from the clock GLB_CLK.

As described above, the exposure time can be controlled without preparing a plurality of reference signals TRG_SIG in the examples shown in FIGS. 10 and 11. Furthermore, by sharing the clock GLB_CLK with other circuits, it is possible to finely control the exposure time, that is, increase the number of exposure stages, while suppressing the circuit scale.

In any of the above examples, the transfer control signal φTX1 and the selection control signal φSEL are commonly controlled in the pixel section 110, while the reset control signal φRST and the discharge control signal φTX2 are individually controlled by the signal DLY_HIT for each pixel block 120. controlled by. However, instead of this, the reset control signal φRST and the discharge control signal φTX2 are commonly controlled in the pixel section 110, while the transfer control signal φTX1 and the selection control signal φSEL are individually controlled for each pixel block 120 by the signal DLY_HIT. may be done. This allows the exposure end time to be controlled for each pixel block 120.

Furthermore, in the above example, the clock GLB_CLK of the AD converter 42 is used to delay the signal DLY_HIT. Instead, another circuit, for example, a clock used for data transfer in the signal output section 50, may be used to delay the signal DLY_HIT.

Note that in any of the embodiments described above, the discharge section 124 of the pixel 112 may be omitted. Further, the transfer section 123 may also be omitted, but in that case, the storage section 125 no longer functions as a floating diffusion. Further, the storage section 125 and the pixel output section 127 may be shared with other pixels. Furthermore, the pixel 112 may be configured with a plurality of photoelectric conversion units 104 and transfer units 123.

FIG. 12 is a block diagram illustrating a configuration example of an imaging device 500 according to an embodiment. The imaging device 500 includes an imaging element 400, a system control section 501, a drive section 502, a photometry section 503, a work memory 504, a recording section 505, a display section 506, a drive section 514, and a photographic lens 520. Equipped with Although an example will be described in which the image sensor 400 is provided, an image sensor 900 may be provided instead.

The photographing lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The photographing lens 520 is composed of a plurality of optical lens groups, and forms an image of the object light beam from the scene near its focal plane. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. In addition, in FIG. 12, the photographing lens 520 is represented by one virtual lens arranged near the pupil.

The driving section 514 drives the photographing lens 520. In one example, the drive unit 514 moves the optical lens group of the photographic lens 520 to change the focus position. Further, the driving unit 514 may drive an iris diaphragm in the photographing lens 520 to control the amount of light from the subject that enters the image sensor 400.

The drive unit 502 has a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 400 in accordance with instructions from the system control unit 501. The operation unit 508 also receives instructions from the photographer using a release button or the like.

The image sensor 400 delivers pixel signals to the image processing unit 511 of the system control unit 501. The image processing unit 511 uses the work memory 504 as a work space to generate image data subjected to various image processing. For example, when generating image data in the JPEG file format, compression processing is performed after generating a color video signal from a signal obtained in a Bayer array. The generated image data is recorded in the recording section 505, and is also converted into a display signal and displayed on the display section 506 for a preset time.

The photometry unit 503 detects the brightness distribution of a scene prior to a series of shooting sequences that generate image data. The photometry unit 503 includes, for example, an AE sensor with about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output from the photometry unit 503 and calculates the brightness for each region of the scene.

The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated brightness distribution. The photometry unit 503 may also be used by the image sensor 400. Note that the calculation unit 512 also executes various calculations for operating the imaging device 500. A part or all of the drive unit 502 may be mounted on the image sensor 400. A part of the system control unit 501 may be mounted on the image sensor 400.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the range described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the embodiments described above. It is clear from the claims that such modifications or improvements may be included within the technical scope of the present invention.

The order of execution of each process, such as the operation, procedure, step, and stage in the apparatus, system, program, and method shown in the claims, specification, and drawings, is specifically defined as "before" or "before". It should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Even if the claims, specifications, and operational flows in the drawings are explained using "first," "next," etc. for convenience, this does not mean that it is essential to carry out the operations in this order. It's not a thing.

10, 12 exposure control section, 20 pixel drive section, 30 junction section, 40 signal conversion section, 42 ADC, 50 signal output section, 100 first substrate, 104 photoelectric conversion section, 110 pixel section, 112 pixels, 120 pixel block, 121 Load current source, 122, 130, 132, 141, 142, 143, 144, 242, 252, 254 Signal line, 123 Transfer section, 124 Discharge section, 125 Accumulation section, 126 Reset section, 127 Pixel output section, 128 Amplification section , 129 selection section, 152 bump, 200 second substrate, 210 processing circuit section, 220 processing block, 230 peripheral circuit section, 240 block control section, 250 common control section, 300 register, 302 trigger selection circuit, 304 clock selection circuit, 306 delay circuit, 308 counter, 400 imaging element, 500 imaging device, 501 system control unit, 502 drive unit, 503 photometry unit, 504 work memory, 505 recording unit, 506 display unit, 508 operation unit, 511 image processing unit, 512 Arithmetic unit, 514 Drive unit, 520 Photographic lens

Claims (8)

a signal generation unit that generates a signal that serves as a reference timing for pixel control;
An image sensor including a delay circuit that delays the reference signal and outputs the signal as the timing signal. The image sensor according to claim 1, wherein the delay circuit delays the signal using a clock having a frequency based on the amount of delay among a plurality of clocks having different frequencies. The signal generation unit outputs one signal among a plurality of reference signals having mutually different timings to the delay circuit,
The image sensor according to claim 1, wherein the delay circuit delays the one signal and outputs a signal having a timing between the timing of the one signal and the timing of another signal. The image sensor according to claim 1, wherein the delay circuit delays the signal based on a clock shared with other circuits. The image sensor according to claim 4, wherein the other circuit is a conversion circuit that converts a pixel signal from the pixel into a digital signal. The image sensor according to claim 1, wherein the timing is one of the start of exposure and the end of exposure of the pixel. The delay circuit includes a first delay circuit that outputs a signal for controlling a first pixel among the plurality of pixels, and a second delay circuit that outputs a signal for controlling a second pixel among the plurality of pixels. including,
The image sensor according to claim 1, wherein the first delay circuit and the second delay circuit delay respective signals by different amounts. An imaging device comprising the imaging device according to claim 1.

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