JP2023031696A - Imaging element and imaging device - Google Patents

Abstract

To provide an imaging element and an imaging device capable of achieving independent autonomous light exposure of each of a plurality of pixels.SOLUTION: An imaging element 10A has: a first semiconductor substrate 110 that has a pixel part 101; and a second semiconductor substrate 120 that has a control circuit part 102 and peripheral circuit parts 121. The control circuit part has: a first pixel control part that includes a first light exposure control circuit for controlling a storage time in which electric charges converted by a photoelectric conversion part of a first pixel among a plurality of pixels are stored; and a second pixel control part that includes a second light exposure control circuit for controlling a storage time in which electric charges converted by a photoelectric conversion part of a second pixel among the plurality of pixels are stored. The peripheral circuit part is arranged outside the control circuit part, and has: a first arithmetic circuit that performs calculation by using a first signal read out from the first pixel and outputs a first calculation result; and a second arithmetic circuit that performs calculation by using a second signal read out from the second pixel and outputs a second calculation result.SELECTED DRAWING: Figure 1

Description

The present invention relates to an imaging device and an imaging device.

A solid-state imaging device including a plurality of pixel cells is known (for example, Patent Document 1). There has been a demand for expansion of the dynamic range.

JP 2014-75767 A

The imaging device of the first disclosed technology has a first semiconductor substrate having a plurality of pixels including a photoelectric conversion section that converts light into electric charge, and a second semiconductor substrate having a control circuit section and a peripheral circuit section. , the control circuit section includes a first pixel control section including a first exposure control circuit for controlling an accumulation time for accumulating electric charges converted by the photoelectric conversion section of a first pixel among the plurality of pixels; a second pixel control section including a second exposure control circuit for controlling an accumulation time for accumulating charges converted by the photoelectric conversion section of the second pixel among the pixels; a first arithmetic circuit arranged outside the control circuit portion and performing arithmetic using the first signal read from the first pixel and outputting a first arithmetic result; and a second arithmetic circuit that performs arithmetic using the two signals and outputs a second arithmetic result.

The imaging device of the second disclosed technology includes the imaging element of the first disclosed technology.

FIG. 1 is an exploded perspective view showing an example of an imaging device. FIG. 2 is an explanatory diagram showing an example of a specific configuration of a pixel portion. FIG. 3 is a circuit diagram showing an example of the circuit configuration of a pixel. FIG. 4 is an explanatory diagram showing an example of a specific configuration of the control circuit section. FIG. 5 is an explanatory diagram showing an example of the internal configuration of a control block. FIG. 6 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate and the second semiconductor substrate in the imaging device. FIG. 7 is an explanatory diagram showing an example of a cross section in the XZ direction of the imaging element according to this embodiment. FIG. 8 is a timing chart showing an imaging operation example 1 of the imaging device. FIG. 9 is a timing chart showing an imaging operation example 2 of the imaging device. FIG. 10 is a timing chart showing imaging operations of an imaging device according to a comparative example. FIG. 11 is an explanatory diagram showing an example of a subject imaged by an imaging device. FIG. 12 is a timing chart showing exposure time for each of regions 1 to 5 shown in FIG. FIG. 13 is a plan view showing a layout example of a plurality of control blocks. FIG. 14 is a circuit diagram showing another example of the circuit configuration of a pixel. FIG. 15 is a timing chart showing example 3 of imaging operation of the imaging element. FIG. 16 is an exploded perspective view showing another example of the imaging device. FIG. 17 is an explanatory diagram showing another example of the specific configuration of the control circuit section. FIG. 18 is an explanatory diagram showing the connection relationship between the first semiconductor substrate and the second semiconductor substrate in the imaging device. FIG. 19 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate and the second semiconductor substrate in the imaging device. FIG. 20 is an explanatory diagram showing the connection relationship between the ADC section and the pixel blocks. FIG. 21 is a timing chart showing imaging operations within a pixel block of the imaging device. FIG. 22 is an explanatory diagram showing an example of exposure timing for each pixel block. FIG. 23 is a block diagram showing a configuration example of the autonomous exposure control method 1. As shown in FIG. FIG. 24 is a block diagram showing a configuration example of the autonomous exposure control method 2. As shown in FIG. FIG. 25 is a block diagram showing a configuration example of the autonomous exposure control method 3. As shown in FIG. FIG. 26 is a block diagram showing a layout example when autonomous exposure processing units are mounted in adjacent control blocks. FIG. 27 is a block diagram showing a layout example when an autonomous exposure processing section is mounted on a peripheral circuit. FIG. 28 is a block diagram showing the detailed internal configuration of the peripheral circuit portion shown in FIG. 27. Referring to FIG. FIG. 29 is an explanatory diagram showing an example of a delay in the exposure time reflection period. FIG. 30 is an explanatory diagram showing Example 1 of shortening the reflection period of the exposure time. FIG. 31 is an explanatory diagram showing Example 2 of shortening the reflection period of the exposure time. FIG. 32 is a timing chart 1-1 when exposure time change occurs. FIG. 33 is a timing chart 1-2 when exposure time change occurs. FIG. 34 is a timing chart 2-1 when exposure time change occurs. FIG. 35 is a timing chart 2-2 when exposure time change occurs. FIG. 36 is a timing chart 3-1 when exposure time change occurs. FIG. 37 is a timing chart 3-2 when the exposure time change occurs. FIG. 38 is a timing chart 3-3 when the exposure time change occurs. FIG. 39 is an explanatory diagram showing Method 1 for reading exposure values to the outside of the second semiconductor substrate. FIG. 40 is an explanatory diagram showing Method 2 for reading exposure values to the outside of the second semiconductor substrate. FIG. 41 is a block diagram showing Example 1 of increasing the speed of autonomous exposure control inside a control block. FIG. 42 is an explanatory diagram showing an example of a counter latch in Example 1 of increasing the speed of autonomous exposure control inside a control block. FIG. 43 is an explanatory diagram showing a specific example of autonomous exposure control in speeding up example 1 of autonomous exposure control inside a control block. FIG. 44 is an explanatory diagram showing an example of a counter latch in Example 2 of increasing the speed of autonomous exposure control inside a control block. FIG. 45 is an explanatory diagram showing a specific example of autonomous exposure control in example 2 of increasing the speed of autonomous exposure control inside a control block. FIG. 46 is a block diagram showing Example 3 of increasing the speed of autonomous exposure control inside the control block. FIG. 47 is a circuit diagram showing an example of a comparator. FIG. 48 is an explanatory diagram showing an exposure control example 1 by switching exposure values inside and outside control blocks. FIG. 49 is an explanatory diagram showing an exposure control example 2 by switching exposure values inside and outside control blocks. FIG. 50 is an explanatory diagram showing Example 3 of exposure control by switching exposure values inside and outside control blocks. FIG. 51 is an explanatory diagram showing Example 1 of reading the exposure value for each control block. FIG. 52 is an explanatory diagram showing Example 2 of reading the exposure value for each control block. FIG. 53 is a block diagram showing a detailed block configuration example of a control block in Example 2 of reading an exposure value for each control block. 54 is a block diagram illustrating an example of the internal configuration of a preprocessing unit in Example 1 of reducing color misregistration; FIG. FIG. 55 is an explanatory diagram showing an example of a pixel block in Example 2 of reducing color misregistration. FIG. 56 is a block diagram showing an example of the internal configuration of a preprocessing unit in Example 3 of reducing color misregistration. FIG. 57 is a block diagram showing an example of the internal configuration of an imaging device in example 4 of reducing color misregistration. FIG. 58 is a circuit diagram showing an example of failure analysis of bonding pads between semiconductor substrates in pixel drive signal lines. FIG. 59 is a circuit diagram showing failure analysis example 1 of a bonding pad between semiconductor substrates in a vertical signal line. FIG. 60 is a circuit diagram showing failure analysis example 2-1 of bonding pads between semiconductor substrates in vertical signal lines. FIG. 61 is a circuit diagram showing failure analysis example 2-2 of bonding pads between semiconductor substrates in vertical signal 2. In FIG. FIG. 62 is a circuit diagram showing an example of failure analysis of bonding pads between semiconductor substrates when a signal path is shared between a plurality of circuits. FIG. 63 is a circuit diagram showing a setting example after failure analysis of bonding pads between semiconductor substrates when a signal path is shared between a plurality of circuits. FIG. 64 is a circuit diagram showing a failure analysis example 1 of bonding pads between semiconductor substrates when a bonding portion is shared between a plurality of circuits. FIG. 65 is a circuit diagram showing a failure analysis example 2 of bonding pads between semiconductor substrates when a bonding portion is shared between a plurality of circuits. FIG. 66 is a block diagram illustrating a configuration example of an imaging device according to the example.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

In this specification, the X-axis and the Y-axis are orthogonal to each other, and the Z-axis is orthogonal to the XY plane. The XYZ axes constitute a right-handed system. A direction parallel to the Z-axis may be referred to as a stacking direction of the imaging device 100 . As used herein, the terms "upper" and "lower" are not limited to vertical directions in the direction of gravity. These terms refer only to relative directions in the Z-axis direction. In this specification, the arrangement in the X-axis direction is described as a "row" and the arrangement in the Y-axis direction is described as a "column," but the matrix direction is not limited to this.

<Structure of image sensor>
First, the configuration of the imaging element will be described with reference to FIGS. 1 to 22. FIG. The structure of the imaging device may be of a backside illumination type or a frontside illumination type.

FIG. 1 is an exploded perspective view showing an example of an imaging device 100A. The imaging element 100A images a subject. The imaging device 100A generates image data of the captured subject. The imaging element 100A includes a first semiconductor substrate 110, a second semiconductor substrate 120 and a third semiconductor substrate . As shown in FIG. 1 , the first semiconductor substrate 110 is stacked on the second semiconductor substrate 120 , and the second semiconductor substrate 120 is stacked on the third semiconductor substrate 130 .

The first semiconductor substrate 110 has a pixel portion 101 . The pixel unit 101 outputs pixel signals based on incident light.

The second semiconductor substrate 120 has a control circuit section 102 and a peripheral circuit section 121 .

The control circuit unit 102 receives pixel signals output from the first semiconductor substrate 110 . The control circuit unit 102 processes input pixel signals. The control circuit section 102 is arranged at a position facing the pixel section 101 on the second semiconductor substrate 120 . For example, the control circuit section 102 is arranged so as to overlap the pixel section 101 in the direction in which the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked. The control circuit unit 102 may output a control signal for controlling driving of the pixel unit 101 to the pixel unit 101 .

The peripheral circuit section 121 controls driving of the control circuit section 102 . The peripheral circuit section 121 is arranged around the control circuit section 102 on the second semiconductor substrate 120 . Specifically, the peripheral circuit section 121 is arranged in a region outside the region where the control circuit section 102 is arranged in the second semiconductor substrate 120 . Also, the peripheral circuit section 121 may be electrically connected to the first semiconductor substrate 110 to control driving of the pixel section 101 . The peripheral circuit section 121 is arranged along two sides of the second semiconductor substrate 120, but the arrangement method of the peripheral circuit section 121 is not limited to this example.

The third semiconductor substrate 130 has the data processing section 103 . The data processing unit 103 uses the digital data output from the second semiconductor substrate 120 to perform addition processing, thinning processing, and other image processing.

FIG. 2 is an explanatory diagram showing an example of a specific configuration of the pixel unit 101. As shown in FIG. The pixel section 101 has a plurality of pixel blocks 200 . A plurality of pixel blocks 200 are arranged side by side in the row direction and the column direction in the pixel portion 101 . Specifically, the plurality of pixel blocks 200 has M×N (M and N are natural numbers) pixel blocks 200 arranged in the row direction and the column direction in the pixel unit 101 . Although M is shown equal to N, M and N may be different.

A pixel block 200 has a plurality of pixels 201 . A plurality of pixels 201 are arranged side by side in the row direction and the column direction in the pixel block 200 . The pixel block 200 has m×n (m and n are natural numbers) pixels 201 arranged in rows and columns. For example, pixel block 200 has 16×16 pixels 201 arranged in rows and columns. The number of pixels 201 corresponding to the pixel block 200 is not limited to this. Although m is shown to be equal to n, m may be different from n.

The pixel block 200 has a plurality of pixels 201 connected to common control lines (for example, transfer control lines 311 and discharge control lines 312, which will be described later) in the row direction. For example, each pixel 201 of the pixel block 200 is connected to the common control line so as to be set to the same exposure time. Specifically, for example, every n pixels 201 arranged in the row direction are connected by the common control line.

On the other hand, between different pixel blocks 200 , one pixel block 200 may be set to a different exposure time than the other pixel block 200 . For example, when one pixel block 200 and the other pixel block 200 are arranged side by side in the row direction, the plurality of pixels 201 of one pixel block 200 and the plurality of pixels 201 of the other pixel block 200 are different. Connected by a control line. A plurality of pixels 201 in the m-th row of one pixel block 200 are commonly connected by a control line different from the common control line to which the plurality of pixels 201 in the m-th row of the other pixel block 200 are connected. . Also, when one pixel block 200 and the other pixel block 200 are arranged side by side in the column direction, the plurality of pixels 201 of one pixel block 200 and the plurality of pixels 201 of the other pixel block 200 are different. Connected by a control line. A plurality of pixels 201 in the m-th row of one pixel block 200 are commonly connected by a control line different from the common control line to which the plurality of pixels 201 in the m-th row of the other pixel block 200 are connected. .

Further, for example, when one pixel block 200 and the other pixel block 200 are arranged side by side in the row direction, the plurality of pixels 201 of one pixel block 200 and the plurality of pixels 201 of the other pixel block 200 are connected by different signal lines 202 . A plurality of pixels 201 in the n-th column of one pixel block 200 are commonly connected by a signal line 202 different from the common signal line 202 to which the plurality of pixels 201 in the n-th column of the other pixel block 200 are connected. be. Also, when one pixel block 200 and the other pixel block 200 are arranged side by side in the column direction, the plurality of pixels 201 of one pixel block 200 and the plurality of pixels 201 of the other pixel block 200 are different. They are connected by a signal line 202 . A plurality of pixels 201 in the n-th column of one pixel block 200 are commonly connected by a signal line 202 different from the common signal line 202 to which the plurality of pixels 201 in the n-th column of the other pixel block 200 are connected. be done.

The pixel block 200 is arranged corresponding to control blocks 400A and 400B (see FIGS. 4 and 17), which will be described later. That is, one pixel block 200 is arranged for one control block 400A, 400B.

Also, a plurality of pixel blocks 200 may be arranged for one control block 400A, 400B. Even when a plurality of pixel blocks 200 are arranged for one control block 400A, 400B, each pixel block 200 may be set to a different exposure time. When two pixel blocks 200 aligned in the column direction are arranged for one control block, the control blocks 400A and 400B control 2m×n pixels 201 . Specifically, the control blocks 400A and 400B control 32×16 pixels 201, for example. The number of pixels 201 corresponding to control blocks 400A and 400B is not limited to this.

FIG. 3 is a circuit diagram showing an example of the circuit configuration of the pixel 201. As shown in FIG. A pixel 201 includes a photoelectric conversion unit 300 and a readout unit 310 . The readout unit 310 includes a transfer unit 301, a discharge unit 302, an FD (floating diffusion) 303, a reset unit 304, and a pixel output unit 305. A pixel based on the charge converted by the photoelectric conversion unit 300 A signal is read out on the signal line 202 . The pixel output section 305 has an amplification section 351 and a selection section 352 . Transfer section 301 , discharge section 302 , FD 303 , reset section 304 , amplification section 351 and selection section 352 are referred to as reading section 310 . The reading unit 310 is described as an N-channel FET, but the type of transistor is not limited to this.

The photoelectric conversion unit 300 has a photoelectric conversion function of converting light into charge. The photoelectric conversion unit 300 accumulates photoelectrically converted charges. Photoelectric conversion unit 300 is configured by, for example, a photodiode.

A transfer unit 301 transfers the charge of the photoelectric conversion unit 300 to the FD 303 . The transfer section 301 controls electrical connection between the photoelectric conversion section 300 and the FD 303 . The transfer unit 301 is composed of, for example, transistors. Further, the transfer unit 301 may be an element that constitutes a part of a transistor that has at least a gate terminal, a part of the photoelectric conversion part 300 as a source terminal, and a part of the FD 303 as a drain terminal. A gate terminal of the transfer unit 301 is connected to a transfer control line 311 for inputting a transfer control signal φTX. The transfer control line 311 will be described later.

The discharge unit 302 discharges the charge accumulated in the photoelectric conversion unit 300 to the power supply wiring supplied with the power supply voltage VDD. The discharge unit 302 controls connection between the photoelectric conversion unit 300 and the power wiring. The discharge unit 302 is configured by, for example, a transistor. The discharge portion 302 is an element that constitutes part of a transistor that has at least a gate terminal, a portion of the photoelectric conversion portion 300 as a source terminal, and a portion of the diffusion region connected to the power supply wiring as a drain terminal. There may be. A gate terminal of discharge unit 302 is connected to discharge control line 312 for inputting discharge control signal φPDRST. Although the discharge unit 302 discharges the charge of the photoelectric conversion unit 300 to the power supply wiring to which the power supply voltage VDD is supplied, the electric charge may be discharged to the power supply wiring to which the power supply voltage different from the power supply voltage VDD is supplied. good.

The FD 303 is transferred from the photoelectric conversion unit 300 by the transfer unit 301 . The FD 303 accumulates charges transferred from the photoelectric conversion unit 300 .

The reset unit 304 discharges the charges accumulated in the FD 303 to the power supply wiring supplied with the power supply voltage VDD. The reset unit 304 resets the potential of the FD 303 to the power supply voltage VDD, which is the reference potential. The reset unit 304 controls electrical connection between the FD 303 and power wiring. Reset unit 304 is configured by, for example, a transistor. Further, the reset unit 304 may be an element that constitutes part of a transistor that has at least a gate terminal, a part of the FD 303 as a source terminal, and a part of the diffusion region connected to the power supply wiring as a drain terminal. good. A gate terminal of the reset unit 304 is connected to a reset control line 313 for inputting a reset control signal φRST. The reset control line 313 will be described later.

A pixel output unit 305 outputs a pixel signal based on the potential of the FD 303 to the signal line 202 . The pixel output section 305 has an amplification section 351 and a selection section 352 . The amplifier section 351 is configured by a transistor. The amplification unit 351 has a gate terminal connected to the FD 303 , a drain terminal connected to a power supply line supplied with a power supply voltage VDD, and a source terminal connected to the drain terminal of the selection unit 352 .

The selection unit 352 controls electrical connection between the pixels 201 and the signal lines 202 . When the pixel 201 and the signal line 202 are electrically connected by the selection unit 352 , a pixel signal is output from the pixel 201 to the signal line 202 . The selection unit 352 is configured by a transistor. The selection unit 352 is an element that constitutes part of a transistor that has at least a gate terminal, a part of the amplification part 351 as a source terminal, and a part of the diffusion region connected to the signal line 202 as a drain terminal. There may be. A gate terminal of the selection section 352 is connected to a selection control line 314 extending over a plurality of pixel blocks 200 for inputting a selection control signal φSEL. A source terminal of the selector 352 is connected to the load current source 306 .

A load current source 306 is connected to the signal line 202 and supplies current for reading pixel signals from the pixels 201 . Thereby, the operation of the amplifier 351 can be stabilized. A load current source 306 is also connected to the signal line 202 . The load current source 306 may be provided on the first semiconductor substrate 110 or may be provided on the second semiconductor substrate 120 .

Also, the FD 303 and the pixel output unit 305 may be shared with other pixels 201 . For example, the FD 303 and the pixel output unit 305 may be shared by a plurality of pixels 201 arranged in rows or columns. Further, the pixel 201 may be composed of a plurality of photoelectric conversion units 300 and transfer units 301 .

FIG. 4 is an explanatory diagram showing an example of a specific configuration of the control circuit section 102. As shown in FIG. The control circuit section 102 has a plurality of control blocks 400A. A plurality of control blocks 400A are arranged side by side in the row direction and the column direction in the control circuit portion 102 . Specifically, the control circuit section 102 has M×N control blocks 400A. When one pixel block 200 is arranged for one control block 400A, the control circuit section 102 has the control block 400A immediately below the pixel block 200. FIG. One pixel block 200 and one control block 400A have substantially the same shape and size. Further, when a plurality of pixel blocks 200 arranged in the column direction are arranged for one control block 400A, the control circuit unit 102 arranges one control block 400A immediately below the plurality of pixel blocks 200 arranged in the column direction. It has a control block 400A.

Control block 400 A is provided corresponding to pixel block 200 . As an example of the correspondence relationship between the control blocks and the pixel blocks, for example, the control block 400A is positioned directly below the pixel block 200 in the direction in which the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked (stacking direction). . Also, the control block 400A is electrically connected to the pixel block 200 by the signal line 202, the transfer control line 311 and the discharge control line 312. FIG. Specifically, the control block 400A positioned immediately below the pixel block 200 in the stacking direction is controlled by local control lines such as the transfer control line 311 and the discharge control line 312 to control the pixel block 200 directly above in the stacking direction. It is electrically connected to the pixel block 200). Also, the control block 400A inputs pixel signals output from the pixels 201 of the corresponding pixel block 200 via the signal line 202 .

The control block 400A controls driving of the corresponding pixel block 200. FIG. For example, control block 400A controls the exposure time of pixels 201 included in corresponding pixel block 200 . The control block 400A also has a signal processing unit 402 that processes the input signal, and processes the pixel signal output from the pixel 201 included in the corresponding pixel block 200. FIG. For example, the control block 400A converts analog pixel signals output from the pixels 201 included in the corresponding pixel block 200 into digital signals.

The control block 400A has a pixel control section 401 and a signal processing section 402 . The pixel control unit 401 has an autonomous exposure processing unit 411 , an exposure control unit 412 and a pixel driving unit 413 and controls the pixels 201 of the pixel unit 101 . The signal processing unit 402 includes a signal input unit 421, a signal conversion unit 422, and a signal output unit 423, converts analog pixel signals from the pixel unit 101 into digital signals, and outputs them to the pixel control unit 401 and data processing. transfer to unit 103;

The autonomous exposure processing unit 411 is a circuit that calculates the exposure time of the pixels 201 included in the corresponding pixel block 200 based on the pixel signals converted into digital signals by the signal processing unit 402 . Details of the autonomous exposure processing unit 411 will be described later.

The exposure control unit 412 is a circuit that controls exposure of the pixels 201 included in the corresponding pixel block 200 based on the exposure time calculated by the autonomous exposure processing unit 411 . Specifically, the exposure control unit 412 generates a control signal for controlling the exposure time of the pixels 201 included in the corresponding pixel block 200 (the charge accumulation time of the photoelectric conversion unit 300). For example, the exposure control unit 412 controls the exposure time of each pixel block 200 by adjusting the exposure start timing or end timing of the pixels 201 included in the corresponding pixel block 200 . The exposure controller 412 is provided extending in the row direction in the control block 400A.

The pixel drive section 413 outputs the control signal generated by the exposure control section 412 to the pixels 201 included in the corresponding pixel block 200 . The pixel drive section 413 is a drive circuit that drives the pixels 201 included in the corresponding pixel block 200 . The pixel driving section 413 drives the pixels 201 in the pixel row selected from the pixels 201 included in the corresponding pixel block 200 . The pixel driving unit 413 is provided extending in the column direction. Accordingly, the pixel drive unit 413 is arranged at a position corresponding to the m pixels 201 arranged in the column direction. In the control block 400A, the pixel driving section 413 extends in the column direction, and the autonomous exposure processing section 411 and the exposure control section 412 extend in the row direction. Therefore, they are arranged in an L shape.

The signal input unit 421 inputs pixel signals output from the pixels 201 included in the corresponding pixel block 200 . The signal input section 421 outputs the input pixel signal to the signal conversion section 422 . The signal input section 421 may be provided for every n pixels 201 arranged in the row direction in the corresponding pixel block 200 . The signal input unit 421 may have a processing circuit that performs signal processing such as noise removal processing on pixel signals output from the first semiconductor substrate 110 . Also, the signal input unit 421 may have a voltage adjustment circuit that adjusts the voltage of the signal line 202 connected to the pixel 201 included in the corresponding pixel block 200 so that the voltage does not fall below a predetermined value. When the load current source 306 is arranged on the second semiconductor substrate, it may be arranged on the signal input section 421 included in the corresponding control block 400A.

The signal conversion section 422 converts the pixel signal output from the signal input section 421 into a digital signal. The signal conversion unit 422 sequentially converts the pixel signals output from the m pixels 201 arranged in the column direction in the corresponding pixel block 200 into digital signals. The signal conversion unit 422 converts pixel signals output from the pixels 201 arranged in n columns in the row direction in the corresponding pixel block 200 into digital signals in parallel.

The signal output unit 423 stores the pixel signals converted into digital signals by the signal conversion unit 422 . The signal output section 423 may have a latch circuit for storing digital signals. The signal output section 423 is arranged between the signal conversion section 422 and the autonomous exposure processing section 411 in the column direction. The signal output unit 423 outputs the pixel signal converted into the digital signal to the outside of the control circuit unit 102 . The signal output unit 423 is provided extending in the row direction in the control block 400A. The signal output section 423 is arranged between the signal conversion section 422 and the autonomous exposure processing section 411 in the column direction.

FIG. 5 is an explanatory diagram showing an example of the internal configuration of the control block 400A. The signal conversion unit 422 includes n comparators 501 and n storage units 502 . The exposure controller 412 includes a pixel block controller 503 and a level shifter 504 . A combination of one comparator 501 and a storage unit 502 connected to the comparator 501 constitutes one ADC (Analog-to-Digital Converter) 500 .

The comparator 501 is provided extending in the column direction in the control block 400A. The n comparators 501 are arranged side by side in the row direction. The comparator 501 is arranged for every m pixels 201 arranged in the column direction in the corresponding pixel block 200 . The comparator 501 sequentially reads pixel signals of m pixels 201 arranged in the column direction in the corresponding pixel block 200 and converts them into digital signals.

A storage unit 502 stores pixel signals converted into digital signals using the comparator 501 . The storage unit 502 is provided on the negative side in the Y-axis direction of the comparator 501 in the signal conversion unit 422 . For example, storage unit 502 has a latch circuit. The storage unit 502 may have a memory configured by an SRAM or the like.

The pixel block control unit 503 controls operations of the transfer unit 301 and the discharge unit 302 included in the pixels 201 included in the corresponding pixel block 200 . Specifically, the pixel block control unit 503 controls the transfer control signal φTX for controlling the transfer unit 301 included in the pixel 201 included in the corresponding pixel block 200, and the discharge unit included in the pixel 201 included in the corresponding pixel block 200. A discharge control signal φPDRST for controlling 302 is output. The pixel block control section 503 is provided extending in the row direction in the control block 400A. The pixel block controller 503 is arranged between the level shifter 504 and the autonomous exposure processor 411 in the column direction.

A level shifter 504 adjusts the voltage level of the control signal output from the pixel block controller 503 . Specifically, the level shifter 504 boosts the voltage level of the transfer control signal φTX output from the pixel block controller 503 . Also, the level shifter 504 boosts the voltage level of the discharge control signal φPDRST output from the pixel block controller 503 .

The transfer unit 301 inputs the transfer control signal φTX boosted by the pixel block control unit 503 via the transfer control line 311 . The discharge unit 302 inputs the discharge control signal φPDRST boosted by the pixel block control unit 503 via the discharge control line 312 .

In this way, the pixel block control section 503 boosts the transfer control signal φTX and the discharge control signal φPDRST to the voltage levels used in the transfer section 301 and the discharge section 302 of the readout section 310 of the pixel 201 . The level shifter 504 is provided extending in the row direction in the control block 400A.

The level shifter 504 is provided closer to the outer circumference of the control block 400A than the pixel block controller 503 is. The positive end in the X-axis direction and the negative end in the Y-axis direction of the level shifter 504 are located on the outermost side of the control block 400A. The negative end of the level shifter 504 in the X-axis direction is in contact with the pixel driver 413 .

The level shifter 504 and the pixel driver 413 handle signals after the level shift. On the other hand, the autonomous exposure processing unit 411 , pixel block control unit 503 , level shift unit 504 and pixel driving unit 413 handle pixel signals output from the first semiconductor substrate 110 .

Here, each configuration of the control block 400A is formed in a well region provided in the second semiconductor substrate 120. FIG. The well regions are separated according to the voltage level of the signal to be handled. The well regions are separated depending on whether the power supply used is a digital power supply or an analog power supply. Further, even when the same analog power supply is used, the signal conversion section 422 may be separated from areas using other analog power supplies from the viewpoint of noise. Separation of well regions requires well isolation regions spaced according to manufacturing process rules.

The control block 400A separates well regions for forming the level shifter 504 and the pixel driver 413 from other well regions. For example, the level shifter 504 and the pixel driver 413 can share the well region of the level shifter 504 and the pixel driver 413 by being provided in an L shape. By sharing the well region, the well isolation region can be omitted, thereby improving layout efficiency.

The L-shaped pixel control section 401 forms part of the outer periphery of the control block 400A. This allows the well region to be shared with other control blocks 400A adjacent in the row and column directions.

FIG. 6 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the imaging element 100A. The global driving section 600 is provided in the peripheral circuit section 121 arranged on both sides of the control circuit section 102 .

The transfer control line 311a and the discharge control line 312a are each connected to the pixels 201 included in the pixel block 200a. The transfer control line 311a is connected to the gate terminal of the transfer section 301 of the pixel 201 included in the pixel block 200a, and the discharge control line 312a is connected to the gate terminal of the discharge section 302 of the pixel 201 included in the pixel block 200a. be done. The transfer control line 311a supplies the transfer control signal φTX output from the control block 400Aa to the transfer units 301 of the pixels 201 included in the pixel block 200a. The discharge control line 312a supplies the discharge control signal φPDRST output from the control block 400Aa to the discharge section 302 of the pixel 201 included in the pixel block 200a.

Similarly, transfer control line 311b and discharge control line 312b are each connected to pixels 201 included in pixel block 200b. The transfer control line 311b is connected to the gate terminal of the transfer section 301 of the pixel 201 included in the pixel block 200b, and the discharge control line 312b is connected to the gate terminal of the discharge section 302 of the pixel 201 included in the pixel block 200b. be done. The transfer control line 311b supplies the transfer control signal φTX output from the control block 400Ab to the transfer units 301 of the pixels 201 included in the pixel block 200b. The discharge control line 312b supplies the discharge control signal φPDRST output from the control block 400Ab to the discharge units 302 of the pixels 201 included in the pixel block 200b.

The transfer control lines 311a and 311b are referred to as a transfer control line 311 when not distinguished. The emission control line 312a and the emission control line 312b are referred to as the emission control line 312 when they are not distinguished from each other.

Transfer control line 311 and discharge control line 312 are examples of local control lines connected to the first pixel of pixel block 200 . The transfer control line 311 and the discharge control line 312 are commonly connected to the n pixels 201 arranged in the row direction in the pixel block 200 .

The global driver 600 outputs a reset control signal φRST, a selection control signal φSEL and a transfer selection control signal φTXSEL. The global driver 600 is connected to reset control lines 313 , select control lines 314 , and transfer select control lines 603 that output control signals to respective pixel blocks 200 .

The global driving section 600 supplies a reset control signal φRST and a selection control signal φSEL to the plurality of pixel blocks 200 via the reset control line 313 and the selection control line 314 . The global driver 600 supplies a transfer selection control signal φTXSEL to the plurality of control blocks 400A through the transfer selection control line 603. FIG.

A transfer selection control signal φTXSEL is supplied from the global driver 600 to the control block 400A in order to control the exposure time of each pixel block 200. FIG. The control block 400 A supplied with the transfer selection control signal φTXSEL outputs the transfer selection control signal φTXSEL to the corresponding pixel block 200 . The control block 400A determines whether to input the transfer selection control signal φTXSEL to the pixel 201 as the transfer control signal φTX or the discharge control signal φPDRST. As a result, the input of the transfer control signal φTX or the discharge control signal φPDRST to the pixel 201 is skipped.

For example, the control block 400A extends the exposure time by skipping the transfer control signal φTX when the transfer control signal φTX determines the end time of the exposure. Further, when the transfer control signal φTX determines the exposure start time, the control block 400A can shorten the exposure time by skipping the transfer control signal φTX. Thus, the exposure time of the pixel block 200 can be adjusted by the transfer selection control signal φTXSEL. The same is true when the discharge control signal φPDRST determines the start time or end time of exposure.

A reset control line 313 , a selection control line 314 , and a transfer selection control line 603 are commonly provided for a plurality of pixel blocks 200 . The reset control lines 313, the selection control lines 314, and the transfer selection control lines 603 are wired across the first semiconductor substrate 110 in the row direction. The reset control lines 313, the selection control lines 314, and the transfer selection control lines 603 may be wired across the first semiconductor substrate 110 in the column direction.

For example, the reset control line 313 is connected to the gate terminal of the reset section 304 of the pixel 201 in the pixel block 200 and supplies the reset control signal φRST. The selection control line 314 is connected to the gate terminal of the selection section 352 of the pixel 201 in the pixel block 200 and supplies the selection control signal φSEL. A transfer selection control line 603 is connected to each of the plurality of control blocks 400A and supplies a transfer selection control signal φTXSEL to the pixel control section 401 .

Note that the global drive unit 600 outputs the transfer selection control signal φTXSEL from the second semiconductor substrate 120 via the first semiconductor substrate 110 to the control block 400A. A transfer selection control signal φTXSEL may be output to the block 400A. In this case, the transfer selection control line 603 is provided on the second semiconductor substrate 120 .

The bonding portion 610 is provided on a bonding surface where the first semiconductor substrate 110 and the second semiconductor substrate 120 are bonded to each other. The junction 610 aligns the transfer control line 311 , the discharge control line 312 , and the transfer selection control line 603 between the first semiconductor substrate 110 and the second semiconductor substrate 120 . Each of the joints 610 is composed of a pair of conductive joint pads, which are joined by pressure treatment or the like on the first semiconductor substrate 110 and the second semiconductor substrate 120 to be electrically connected.

The imaging element 100A controls the exposure time for each pixel block 200 by changing the timing of at least one of the transfer section 301 and the discharge section 302 by local control lines such as the transfer control line 311 and the discharge control line 312. . By combining local control lines such as transfer control line 311 and discharge control line 312 with global control lines such as reset control line 313, select control line 314, and transfer select control line 603, imager 100A can achieve more Control of the exposure time can be realized with a small number of control lines.

FIG. 7 is an explanatory diagram showing an example of an XZ-direction cross section of the imaging element 100A according to this embodiment. Although FIG. 7 shows a backside illumination type imaging device 100A, the imaging device 100A is not limited to a backside illumination type. The imaging device 100A includes a microlens layer 700, a color filter layer 702, a first semiconductor substrate 110, a second semiconductor substrate 120, and a third semiconductor substrate . As shown in the figure, the light from the object is incident in the direction indicated by the white arrow (negative Z-axis direction in the figure). The surface of the first semiconductor substrate 110 on which light is incident (the Z-axis positive side in the drawing) may be referred to as the front surface, and the opposite surface (the Z-axis negative side in the drawing) may be referred to as the back surface. .

The microlens layer 700 has a plurality of microlenses 701 . A plurality of microlenses 701 are stacked on the Z-axis positive side of the color filter layer 702 . Light is incident on the microlens 701 . The microlens 701 converges incident light onto the photoelectric conversion unit 300 . A microlens 701 may be provided for each photoelectric conversion unit 300 . The optical axis L of the microlens 701 is the stacking direction (direction parallel to the Z-axis) of the first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate .

The color filter layer 702 has multiple color filters 703 and a passivation film 704 . The color filter layer 702 is stacked on the Z-axis positive side of the first semiconductor layer 711 . A color filter 703 is an optical filter that transmits light in a specific wavelength range. A color filter 703 is an optical filter having specific spectral characteristics. The plurality of color filters 703 have a plurality of optical filters with different spectral characteristics and transmit light in different wavelength regions. A plurality of color filters 703 are provided in a specific arrangement (eg, Bayer arrangement).

An example of the first semiconductor substrate 110 is a back-illuminated CMOS image sensor. The first semiconductor substrate 110 has a first semiconductor layer 711 and a first wiring layer 712 . The first semiconductor layer 711 is provided on the Z-axis positive side of the first wiring layer 712 . The first semiconductor layer 711 has a plurality of pixel blocks 200 two-dimensionally arranged in the row direction and the column direction. The first semiconductor layer 711 has a plurality of pixels 201 two-dimensionally arranged in the row direction and the column direction. The pixels 201 each have a plurality of photoelectric conversion units 300 that accumulate charges based on incident light, and a plurality of readout units 310 .

The first wiring layer 712 is provided closer to the second semiconductor substrate 120 than the first semiconductor layer 711 (the Z-axis negative side in the figure). The first wiring layer 712 has a plurality of wirings 713 made of a conductor film (metal film), a plurality of bonding pads 714, and an insulating film (insulating layer).

The first wiring layer 712 has a plurality of wirings 713 electrically connected to a power supply, a circuit, or the like. In the first semiconductor substrate 110 , the wiring 713 is specifically, for example, a power supply wiring to which a predetermined power supply voltage is supplied, and transmits pixel signals from the first semiconductor substrate 110 (pixels) to the second semiconductor substrate 120 . Signal line 202, transfer control line 311 for transmitting control signals from second semiconductor substrate 120 to first semiconductor substrate 110 (pixels), discharge control line 312, reset control line 313, selection control line 314, and transfer selection control line 603. The first wiring layer 712 may be multi-layered and may be provided with passive elements and active elements.

The bonding pad 714 is provided on the surface (surface on the Z-axis negative side) of the first wiring layer 712 and connected to the wiring 713 . Bond pads 714 are also used to assist in connecting layers, as described below. Bond pads 714 are formed of a conductive material such as, for example, copper. Note that the bond pads 714 may be made of gold, silver, or aluminum. An insulating layer (insulating film) is formed between the plurality of wirings 713 and between the plurality of bonding pads 714 .

The second semiconductor substrate 120 has a second semiconductor layer 721 , a second wiring layer 722 and a wiring layer 723 . The second wiring layer 722 is provided closer to the first semiconductor substrate 110 than the second semiconductor layer 721 (on the Z-axis positive side in the figure). The wiring layer 723 is provided closer to the third semiconductor substrate 130 than the second semiconductor layer 721 (the Z-axis negative side in the drawing), and is provided between the second semiconductor layer 721 and the third semiconductor substrate 130 . . The second semiconductor layer 721 has the control circuit section 102 and the peripheral circuit section 121 . The control circuit section 102 has a plurality of control blocks 400A arranged two-dimensionally in the row direction and the column direction.

As with the first semiconductor substrate 110 , the second semiconductor substrate 120 includes a plurality of wirings 713 provided on the second wiring layer 722 and a plurality of bonding pads 714 provided on the second wiring layer 722 and the wiring layer 723 . , and insulating films (insulating layers) provided in the second wiring layer 722 and the wiring layer 723 .

The second wiring layer 722 is used to electrically connect to a power source, a circuit, or the like, to transmit signals from the pixel portion 101 to the control circuit portion 102, and to transmit signals from the control circuit portion 102 to the pixel portion 101. , a plurality of traces 713 and bonding pads 714 . In the second semiconductor substrate 120 , the wiring 713 is specifically, for example, a power supply wiring to which a predetermined power supply voltage is supplied, and transmits pixel signals from the first semiconductor substrate 110 (pixels) to the second semiconductor substrate 120 . Signal line 202, transfer control line 311 for transmitting control signals from second semiconductor substrate 120 to first semiconductor substrate 110 (pixels), discharge control line 312, reset control line 313, selection control line 314, and transfer selection control line 603. The second wiring layer 722 may be multi-layered and may be provided with passive elements and active elements. Wiring 713 and bond pads 714 may be further provided on wiring layer 723 .

The second semiconductor substrate 120 further has a TSV (Through Silicon Via) 724 that connects the circuits provided on the front and back surfaces thereof. TSVs 724 are preferably provided in the peripheral region. The TSV 724 transmits image data and the like generated by the data processing unit 103 to the first semiconductor substrate 110 . The TSV 724 may also be provided on the first semiconductor substrate 110 and the third semiconductor substrate 130 .

The third semiconductor substrate 130 has a third semiconductor layer 731 provided with the data processing section 103 and a third wiring layer 732 . The third wiring layer 732 is provided between the third semiconductor layer 731 and the second semiconductor substrate 120 .

Similar to the first semiconductor substrate 110 , the third semiconductor substrate 130 has wiring 713 and a plurality of bonding pads 714 provided in a third wiring layer 732 . The third wiring layer 732 is for electrically connecting to a power supply or a circuit, etc., for transmitting signals from the control circuit section 102 to the data processing section 103, and for transmitting signals from the data processing section 103 to the second semiconductor substrate. It has a plurality of wires 713 and bonding pads 714 for transmission to the control circuitry 102 of 120 .

The first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 are laminated by electrical connection between the bonding pads 714 provided on each layer and bonding between wiring layers (insulating layers) on each layer. be done.

When the first semiconductor substrate 110 and the second semiconductor substrate 120 are laminated, the surface of the first wiring layer 712 on the Z-axis negative side and the surface of the second wiring layer 722 on the Z-axis positive side form a boundary surface 720. be done. Similarly, when the second semiconductor substrate 120 and the third semiconductor substrate 130 are laminated, a boundary surface 730 is formed between the surface of the wiring layer 723 on the Z-axis negative side and the surface of the third wiring layer 732 on the Z-axis positive side. Configured. A plurality of bond pads 714 are disposed on interface 720 and interface 730 . Specifically, corresponding bond pads 714 are aligned and the two layers are laminated to electrically connect the aligned bonds.

The first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 may be stacked in the state of wafers before chipping, and formed (individualized) by dicing the stacked wafers. Alternatively, the first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 may be formed by laminating after dicing each wafer.

FIG. 8 is a timing chart showing an imaging operation example 1 of the imaging device 100A. FIG. 8 shows an example of an imaging operation in which driving of the imaging element 100A is controlled by the transfer control signal φTX, discharge control signal φPDRST, reset control signal φRST, and selection control signal φSEL. In FIG. 8, discharge control signal φPDRST is locally controlled, and transfer control signal φTX, reset control signal φRST and select control signal φSEL are globally controlled. <1>, <2>, .

The discharge control signal φPDRST controls the timing of starting exposure. The exposure start timing corresponds to the fall timing of the discharge control signal φPDRST (for example, time T1). That is, before the exposure start time T1, the discharge control signal φPDRST turns on the discharge unit 302 to discharge the charges accumulated in the photoelectric conversion unit 300, and the exposure starts at the fall of the discharge control signal φPDRST. do. Since the discharge control signal φPDRST is locally controlled, the exposure time can be adjusted for each pixel block 200 .

The transfer control signal φTX controls the timing of ending exposure. At time T<b>3 , the transfer control signal φTX turns on the transfer unit 301 to transfer the charge accumulated in the photoelectric conversion unit 300 to the FD 303 . The end timing of exposure corresponds to the falling timing of the transfer control signal φTX (for example, time T4). Since the transfer control signal φTX is a globally controlled signal, the timing of ending exposure in each pixel block 200 is the same.

A reset control signal φRST controls the timing of discharge of charges accumulated in the FD 303 . At time T2, the reset control signal φRST turns on the reset section 304 to discharge the charge of the FD 303 . By discharging the charge of the FD 303 before the timing of the end of exposure, the influence of the charge remaining in the FD 303 can be suppressed when the charge is transferred from the photoelectric conversion unit 300 .

A selection control signal φSEL is a signal for selecting an arbitrary pixel 201 . The selection control signal φSEL controls on/off of the selection section 352 . At time T2, the selection control signal φSEL is set high. At time T3, the pixels 201 for which the selection control signal φSEL is set to high output pixel signals to the signal lines 202 in response to the turn-on of the transfer control signal φTX. On the other hand, the pixels 201 for which the selection control signal φSEL is not set to high output no pixel signal.

The image sensor 100A can change the exposure start timing for each pixel block 200 and control the exposure time for each pixel block 200 by locally controlling the discharge control signal φPDRST. Further, the imaging device 100A may control the end timing of exposure for each pixel block 200 by locally controlling the transfer control signal φTX. The imaging element 100A may control both the start timing and the end timing of exposure for each pixel block 200 by locally controlling both the transfer control signal φTX and the discharge control signal φPDRST.

FIG. 9 is a timing chart showing an imaging operation example 2 of the imaging element 100A. FIG. 9 shows an example of an imaging operation in which driving of the imaging element 100A is controlled by the transfer control signal φTX, reset control signal φRST, and selection control signal φSEL. The imaging element 100A differs from the case of FIG. 8 in that the timing of starting exposure is controlled by the transfer control signal φTX. Points different from FIG. 8 will be particularly described.

The transfer control signal φTX controls the timing of starting and ending exposure. In frame (n), exposure starts at time T5 and ends at time T7.

At exposure start time T5, exposure starts when the transfer control signal φTX falls. That is, before the exposure start time T5, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is turned on, thereby discharging the charge accumulated in the photoelectric conversion unit 300. Exposure starts at the fall of the transfer control signal φTX. Since the transfer control signal φTX is a locally controlled signal, it is possible to change the timing of starting exposure in each pixel block 200 . However, the timing of starting exposure in each pixel block 200 may be matched.

Also, at the end time T7 of the exposure, the transfer control signal φTX falls, thereby ending the exposure. That is, before the exposure end time T7, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is turned off, thereby transferring the charge accumulated in the photoelectric conversion unit 300 to the FD 303. Then, the exposure ends when the transfer control signal φTX falls. Since the transfer control signal φTX is a locally controlled signal, it is possible to change the timing of ending exposure in each pixel block 200 . However, the timing of ending exposure in each pixel block 200 may be matched.

A selection control signal φSEL is a signal for selecting an arbitrary pixel 201 . At time T<b>6 , the pixels 201 whose selection control signal φSEL is set to high output pixel signals to the signal lines 202 .

A reset control signal φRST controls the timing of discharge of charges accumulated in the FD 303 . Reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the read timing, the FD 303 is not charged. On the other hand, by turning off the reset control signal φRST and turning on the transfer control signal φTX at the read timing, charges are transferred from the photoelectric conversion unit 300 to the FD 303 . Since the reset control signal φRST has the same switching timing during reading, it can be shared with the pulse of the selection control signal φSEL.

By locally controlling the transfer control signal φTX, the imaging device 100A can change the timing of starting or ending exposure for each pixel block 200 and control the exposure time for each pixel block 200 . In addition, since the imaging element 100A shares the pulses of the reset control signal φRST and the selection control signal φSEL, the control circuit can be further simplified.

FIG. 10 is a timing chart showing imaging operations of an imaging device according to a comparative example. FIG. 10 shows an imaging operation example in which driving of the imaging device is controlled by the transfer control signal φTX, reset control signal φRST, and selection control signal φSEL, and the exposure time is not controlled for each pixel block 200 .

In the comparative example, the start of exposure is controlled by the transfer control signal φTX and the reset control signal φRST. The exposure start timing is the fall timing (time t1) of the transfer control signal φTX and the reset control signal φRST. The end timing of exposure is the fall timing (time t2) of the transfer control signal φTX. In the comparative example, the exposure start timing and end timing are globally controlled, and the exposure time is not controlled for each pixel block 200 .

FIG. 11 is an explanatory diagram showing an example of a subject imaged by the imaging element 100A. In FIG. 11, the imaging device 100A controls the exposure time for each pixel block 200 in a situation where the afternoon sun is shining outside the tunnel.

Areas 1 to 5 are five areas divided according to brightness. Regions 1 to 5 are numbered in ascending order of brightness. Area 1 is the brightest area where the afternoon sun is directly visible. Region 2 is the region corresponding to the tunnel exit and is darker than region 1 . Area 3 is an area where the afternoon sun is reflected inside the tunnel and is darker than area 2 . Area 4 is an area in which the afternoon sun from the exit of the tunnel is inserted, and is darker than area 3 . Region 5 is the darkest region in the tunnel that is not exposed to the western sun from the exit.

The imaging device 100A controls the exposure time for each pixel block 200 according to the brightness of each area. The image pickup device 100A performs control so that the exposure time of the pixel block 200 in a brighter area becomes shorter. The exposure time for area 1 is set to be the shortest, and the exposure time for area 5 is set to be the longest. For example, the exposure times for regions 1 to 5 are 1/19200 s, 1/1920 s, 1/960 s, 1/240 s and 1/120 s.

FIG. 12 is a timing chart showing exposure time for each of regions 1 to 5 shown in FIG. In FIG. 12, the imaging device 100A controls the exposure time for each pixel block 200 of regions 1 to 5 shown in FIG. A section from time T11 to time T19 corresponds to the video frame rate.

In region 1, the control block 400A controls driving such that the exposure time in the pixel block 200 is the predetermined exposure time ET1. The control block 400A controls the start of exposure with a discharge control signal φPDRST and the end of exposure with a transfer control signal φTX. In region 1, exposure is completed at each of time T12 to time T19.

In region 2, the control block 400A controls driving such that the exposure time in the pixel block 200 is an exposure time ET2 longer than ET1. The control block 400A makes the exposure start time of the area 2 earlier than that of the area 1, and makes the exposure end time of the area 1 match. Therefore, in region 2, exposure is completed at each of time T12 to time T19. The exposure time ET2 of region 2 is shorter than the period of the sensor rate.

In region 3, the control block 400A controls driving such that the exposure time in the pixel block 200 is an exposure time ET3 longer than ET2. The control block 400A makes the exposure start time of the area 3 earlier than that of the area 2, and matches the exposure end time of the area 2. FIG. Therefore, in region 3, exposure is completed at each of time T12 to time T19. The exposure time ET3 of region 3 is set to be the same as the period of the sensor rate.

In region 4, the control block 400A controls driving such that the exposure time in the pixel block 200 is an exposure time ET4 longer than ET3. The control block 400A sets the exposure start time for the area 4 to be the same as that for the area 3, but skips the exposure end time by the transfer selection control signal φTXSEL. The control block 400A realizes an exposure time four times that of the area 3 by skipping three times with the transfer selection control signal φTXSEL. In the region 4, the transfer selection control signal φTXSEL is supplied at each time from time T12 to time T14.

In region 5, the control block 400A controls driving such that the exposure time in the pixel block 200 is an exposure time ET5 longer than ET4. The control block 400A sets the exposure start time for region 5 to be the same as that for region 4, while increasing the number of times the exposure end time is skipped by the transfer selection control signal φTXSEL. The control block 400A realizes twice the exposure time of the area 4 by skipping seven times with the transfer selection control signal φTXSEL. The exposure time ET5 of the area 5 is set to be the same as the cycle of the moving picture frame rate. In the region 5, the transfer selection control signal φTXSEL is supplied at each time from time T12 to time T18.

The imaging device 100A realizes short-second exposure by shortening the interval between the transfer control signal φTX and the discharge control signal φPDRST. Further, the imaging device 100 realizes long exposure by skipping the control of the transfer control signal φTX by the transfer selection control signal φTXSEL. Thereby, the dynamic range can be expanded.

FIG. 13 is a plan view showing a layout example of a plurality of control blocks 400A. The plurality of control blocks 400A are reversely arranged with respect to adjacent control blocks 400A. FIG. 13 illustrates 12 control blocks 400A out of the plurality of control blocks 400A provided in the control circuit section 102. As shown in FIG.

The reverse arrangement means that the regions in which each component of the control block 400A (for example, the exposure control unit 412, the pixel driving unit 413, the signal input unit 421, the signal conversion unit 422, and the signal output unit 423) are formed are arranged in the control blocks 400A. mirror-inverted arrangement (arranged symmetrically) around the boundary line. Even the circuits of each component of the control block 400A do not have to be reversed. Also, the readout order of each pixel in the control block 400A is not limited to being read out in reverse order.

For example, when a plurality of control blocks 400A arranged next to each other in the row direction are reversed, each configuration of the control block 400A is reversed in the row direction. The drive units 413 are arranged adjacent to each other. As a result, a plurality of pixel driving units 413 arranged side by side in the row direction can be laid out as one pixel driving unit 413, and the layout efficiency of the control block 400A can be improved.

Similarly, when a plurality of control blocks 400A arranged next to each other in the column direction are reversed, each configuration of the control blocks 400A is reversed in the column direction, so that the boundary between both control blocks 400A is the same. The configurations will be placed side by side. As a result, a plurality of signal input sections 421 arranged side by side in the column direction can be laid out as one signal input section 421, and the layout efficiency of the control block 400A can be improved.

The control blocks 400A are reversely arranged with the adjacent control blocks 400A. All the control blocks 400A are reversed in the row direction and the column direction, but may be reversed in either the row direction or the column direction. For example, the signal conversion section 422 of the control block 400A is reversely arranged with respect to the signal conversion section 422 of the adjacent control block 400A in the row direction. In addition, the signal conversion section 422 of the control block 400A is also reversely arranged with the signal conversion section 422 of the control block 400A adjacent in the column direction.

Control block 400Aa and control block 400Ab are arranged next to each other in the row direction. The control block 400Aa is reversed from the control block 400Ab. The level shifter 504 of the control block 400Aa is provided in the same well region as the level shifter 504 of the control block 400Ab. Similarly, the pixel block control section 503, the storage section 502 and the signal output section 423 are provided in the same well region in the control block 400Aa and the control block 400Ab.

Control block 400Ab and control block 400Ac are arranged next to each other in the row direction. The control block 400Ab is reversed from the control block 400Ac. The pixel driving section 413 of the control block 400Ab is provided in the same well region as the pixel driving section 413 of the control block 400Ac. The well region of the pixel driver 413 may also be shared with the well region of the level shifter 504 .

Control block 400Aa and control block 400Ad are arranged next to each other in the column direction. The control block 400Aa is reversed from the control block 400Ad. The pixel driving section 413 of the control block 400Aa is provided in the same well region as the pixel driving section 413 of the control block 400Ad. Further, the signal conversion section 422 of the control block 400Aa is provided in the same well region as the signal conversion section 422 of the control block 400Ad.

Control block 400Ad and control block 400Ae are provided adjacent to each other in the column direction. The control block 400Ad is reversely arranged with respect to the control block 400Ae. The pixel drive section 413 and the level shift section 504 of the control block 400Ad are provided in the same well region as the pixel drive section 413 and the level shift section 504 of the control block 400Ae.

By inverting the control block 400A, the imaging device 100 can make the layout more efficient even when signal processing is performed in parallel for each control block 400A. In the imaging device 100A, adjacent control blocks 400A can share a well region by reversely arranging a plurality of control blocks 400A on the XY plane. This reduces the number of times the well regions are switched and improves area efficiency.

FIG. 14 is a circuit diagram showing another example of the circuit configuration of the pixel 201. As shown in FIG. In the pixel 201, the same reference numerals are assigned to the same configurations as in FIG. 3, and the description thereof is omitted. The pixel 201 is not provided with the discharge section 302 provided in the pixel 201 . When the charge accumulated in the photoelectric conversion unit 300 is discharged to the power supply wiring supplied with the power supply voltage VDD, the transfer control signal φTX is input to the gate terminal of the transfer unit 301 and the reset control signal is applied to the gate terminal of the reset unit 304 . A signal φRST is input.

FIG. 15 is a timing chart showing example 3 of imaging operation of the imaging element 100A. FIG. 15 shows an image pickup operation example in which the pixel 201 shown in FIG. 14 uses the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL to control driving of the image sensor 100A. The imaging element 100A differs from the case of FIG. 12 in that the timing of starting exposure is controlled by the transfer control signal φTX. Differences from FIG. 12 will be particularly described.

The transfer control signal φTX controls the timing of starting and ending exposure. In frame (n), exposure starts at time T5 and ends at time T7.

At exposure start time T5, exposure starts when the transfer control signal φTX falls. That is, before the exposure start time T5, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is turned on, thereby discharging the charge accumulated in the photoelectric conversion unit 300. Exposure starts at the fall of the transfer control signal φTX. Since the transfer control signal φTX is a locally controlled signal, it is possible to change the timing of starting exposure in each pixel block 200 .

Also, at the end time T7 of the exposure, the transfer control signal φTX falls, thereby ending the exposure. That is, before the exposure end time T7, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is turned off, thereby transferring the charge accumulated in the photoelectric conversion unit 300 to the FD 303. Then, the exposure ends when the transfer control signal φTX falls. Since the transfer control signal φTX is a locally controlled signal, it is possible to change the timing of ending exposure in each pixel block 200 .

A selection control signal φSEL is a signal for selecting an arbitrary pixel 201 . At time T<b>6 , the pixels 201 whose selection control signal φSEL is set to high output pixel signals to the signal lines 202 .

A reset control signal φRST controls the timing of discharge of charges accumulated in the FD 303 . Reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the read timing, the FD 303 is not charged. On the other hand, by turning off the reset control signal φRST and turning on the transfer control signal φTX at the read timing, charges are transferred from the photoelectric conversion unit 300 to the FD 303 . Since the reset control signal φRST has the same switching timing during reading, it can be shared with the pulse of the selection control signal φSEL.

As described above, according to the configuration of the image sensor 100A shown in FIGS. 1 to 15, the pixel block 200 composed of a plurality of pixels 201 is exposed, and the control block 400A corresponding to the pixel block 200 is exposed. Pixel signals from 200 can be read out and converted from analog signals to digital signals. Further, the image sensor 100A reads pixel signals in parallel for each pixel block 200 by means of a control block 400A provided for each pixel block 200. FIG. Therefore, the imaging element 100A can set the exposure time for each pixel block 200 according to the intensity of the incident light, so that the dynamic range can be expanded.

Next, with reference to FIGS. 16 to 22, the configuration of the image pickup device 100B that performs exposure in units of pixel blocks 200, sequentially reads out pixel signals for each pixel row, and performs AD conversion for each pixel column will be described.

FIG. 16 is an exploded perspective view showing another example of the imaging device. The imaging device 100B includes a first semiconductor substrate 110, a second semiconductor substrate 120 and a third semiconductor substrate . As shown in FIG. 16 , the first semiconductor substrate 110 is laminated on the second semiconductor substrate 120 , and the second semiconductor substrate 120 is laminated on the third semiconductor substrate 130 .

The first semiconductor substrate 110 has a pixel portion 101 and a connection region 1601 . The pixel unit 101 outputs pixel signals based on incident light. A connection region 1601 is arranged around the pixel portion 101 . In the example of FIG. 16, a pair of connection regions 1601 are arranged along two opposite sides of the first semiconductor substrate 110 on the front and back of the pixel portion 101 .

The second semiconductor substrate 120 has a control circuit section 102 , a peripheral circuit section 121 and a signal processing section 1602 .

The control circuit unit 102 outputs control signals for controlling driving of the pixel unit 101 to the pixel unit 101 . The control circuit section 102 is arranged at a position facing the pixel section 101 on the second semiconductor substrate 120 .

The peripheral circuit section 121 controls driving of the control circuit section 102 . The peripheral circuit section 121 is arranged around the control circuit section 102 on the second semiconductor substrate 120 . Also, the peripheral circuit section 121 may be electrically connected to the first semiconductor substrate 110 to control driving of the pixel section 101 . The peripheral circuit section 121 is arranged along two opposite sides of the second semiconductor substrate 120, but the arrangement method of the peripheral circuit section 121 is not limited to this example.

Analog pixel signals output from the first semiconductor substrate 110 are input to the signal processing unit 1602 . A signal processing unit 1602 performs signal processing on pixel signals. For example, the signal processing unit 1602 performs processing for converting analog pixel signals into digital signals. The signal processing unit 1602 may perform other signal processing. Examples of other signal processing include noise reduction processing such as analog or digital CDS (Correlated Double Sampling). The signal processing unit 1602 is arranged around the control circuit unit 102, that is, outside. In the example of FIG. 16 , a pair of signal processing units 1602 are arranged along two sides facing each other of the second semiconductor substrate 120 in front and behind the control circuit unit 102 . The signal processing section 1602 may be a circuit included in the peripheral circuit section 121 .

The third semiconductor substrate 130 has the data processing section 103 . The data processing unit 103 uses the digital data output from the second semiconductor substrate 120 to perform addition processing, thinning processing, and other image processing.

FIG. 17 is an explanatory diagram showing another example of a specific configuration of the control circuit section 102. As shown in FIG. In FIG. 17, the control block 400B has the pixel control section 401 (autonomous exposure processing section 411, exposure control section 412, pixel driving section 413) but does not have the signal processing section 402. FIG.

Instead of providing one control block 400B for one pixel block 200, one control block 400B may be provided for N pixel blocks 200 (N is a natural number of 2 or more). The N pixel blocks 200 corresponding to one pixel block are sometimes called a pixel block group. For example, one control block 400B may be provided with two pixel blocks 200 arranged side by side in the column direction as one pixel block group. In this case, the control block 400B may control the exposure time for each pixel block 200. FIG.

In addition, the control block 400B is electrically connected to at least one pixel block 200 and can be said to be the minimum unit of a circuit that controls the exposure of the pixels 201 of the at least one pixel block 200. FIG.

FIG. 18 is an explanatory diagram showing the connection relationship between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the imaging device 100B. The first semiconductor substrate 110 includes a connection region 1801 and a connection region 1601 provided around the pixel portion 101 and electrically connected to the pixel portion 101 . The second semiconductor substrate 120 includes a connection region 1802 and a connection region 1803 provided around the control circuit section 102 and electrically connected to the control circuit section 102 .

A pair of connection regions 1801 are connected to a pair of connection regions 1802 located opposite to each other. A connection region 1801 and a connection region 1802 connected to each other input a control signal from the global driving section 600 to the pixel section 101 using a global control line.

A pair of connection regions 1601 are connected to a pair of connection regions 1803 located opposite to each other. The connection region 1601 and the connection region 1803 connected to each other input pixel signals from the pixel unit 101 to the corresponding ADC units 1820 and 1830 using a common signal line.

FIG. 19 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the imaging device 100B. The global driver 600 outputs a reset control signal φRST, a selection control signal φSEL and a transfer selection control signal φTXSEL. The global driver 600 is connected to reset control lines 1903 and select control lines 1904 that output signals to the respective pixel blocks 200 . The global driving section 600 supplies a reset control signal φRST to the plurality of pixel blocks 200 through a reset control line 1903 and supplies a selection control signal φSEL through a selection control line 1904 . The global driver 600 supplies a transfer selection control signal φTXSEL to the plurality of control blocks 400B via the transfer selection control line 1905. FIG.

A transfer selection control signal φTXSEL is supplied from the global driving section 600 to the control block 400B in order to control the exposure time of each pixel block 200. FIG. The control block 400 B supplied with the transfer selection control signal φTXSEL outputs the transfer selection control signal φTXSEL to the corresponding pixel block 200 . The pixel block 200 determines whether to input the transfer selection control signal φTXSEL to the pixel 201 as the transfer control signal φTX or the discharge control signal φPDRST. As a result, the input of the transfer control signal φTX or the discharge control signal φPDRST to the pixel 201 is skipped.

For example, the control block 400B extends the exposure time by skipping the transfer control signal φTX when the transfer control signal φTX determines the end time of the exposure. Further, when the transfer control signal φTX determines the exposure start time, the control block 400B can shorten the exposure time by skipping the transfer control signal φTX. Thus, the exposure time of the pixel block 200 can be adjusted by the transfer selection control signal φTXSEL. The same is true when the discharge control signal φPDRST determines the start time or end time of exposure.

A reset control line 1903 , a selection control line 1904 and a transfer selection control line 1905 are wired globally, that is, provided in common to a plurality of pixel blocks 200 . A reset control line 1903, a selection control line 1904, and a transfer selection control line 1905 are wired across the pixel portion 101 in the row direction. The reset control line 1903, the selection control line 1904, and the transfer selection control line 1905 may be wired across the pixel portion 101 in the column direction.

For example, the reset control line 1903 is connected to the gate terminal of the reset section 304 of the pixel block 200 and supplies the reset control signal φRST. A selection control line 1904 is connected to the gate terminal of the selection section 352 of the pixel block 200 and supplies a selection control signal φSEL. Also, the transfer selection control line 1905 is connected to each of the plurality of control blocks 400B to supply the pixel control section 401 with a transfer selection control signal φTXSEL.

Although the global driver 600 outputs the transfer selection control signal φTXSEL from the second semiconductor substrate 120 to the first semiconductor substrate 110, the transfer selection control signal φTXSEL is not supplied to the first semiconductor substrate 110 and is sent to the control block 400B. φTXSEL may be output. In this case, the transfer selection control line 1905 is provided on the second semiconductor substrate 120 .

On the other hand, the transfer control line 1901a and the discharge control line 1902a are connected to the pixel block 200a. The transfer control line 1901a is connected to the gate terminal of the transfer section 301 provided in the pixel block 200a. The transfer control line 1901a supplies the transfer control signal φTX output from the control block 400Ba to the pixel block 200a. The discharge control line 1902a is connected to the gate terminal of the discharge section 302 provided in the pixel block 200a. The discharge control line 1902a supplies the discharge control signal φPDRST output from the control block 400Ba to the pixel block 200a.

Transfer control line 1901b and discharge control line 1902b are connected to pixel block 200b. The transfer control line 1901b is connected to the gate terminal of the transfer section 301 provided in the pixel block 200b. The transfer control line 1901b supplies the transfer control signal φTX output from the control block 400Bb to the pixel block 200b. The discharge control line 1902b is connected to the gate terminal of the discharge section 302 provided in the pixel block 200b. The discharge control line 1902b supplies the discharge control signal φPDRST output from the control block 400Bb to the pixel block 200b.

A plurality of bonding portions 610 are provided on bonding surfaces where the first semiconductor substrate 110 and the second semiconductor substrate 120 are bonded to each other. The bonding portion 610 of the first semiconductor substrate 110 is aligned with the bonding portion 610 of the second semiconductor substrate 120 . A plurality of bonding portions 610 that face each other are electrically connected by being bonded by pressure treatment or the like of the first semiconductor substrate 110 and the second semiconductor substrate 120 . In this case, the global control line junction 610 may be under the corresponding pixel block 200 or in the connection regions 1801 and 1802 . On the other hand, the local control line junction 610 is provided below the corresponding pixel block 200 (also above the control block 400B).

The imaging device 100B controls the exposure time for each pixel block 200 by changing the timing of at least one of the transfer section 301 and the discharge section 302 using local control lines. By combining local control lines and global control lines, the imaging device 100B can realize exposure time control with fewer control lines.

FIG. 20 is an explanatory diagram showing the connection relationship between the ADC section and the pixel blocks. As shown in FIG. 20, a common signal line 202 extending in the column direction is arranged for each column inside the pixel block 200c. Further, this signal line 202 is also common to a plurality of pixel blocks 200c and 200d arranged in the column direction. Therefore, in this example, one signal line 202 is connected to m×M pixels 201 arranged in one column, and pixel signals from these pixels 201 are output.

An ADC 2000 is connected to each of the signal lines 202 on the second semiconductor substrate 120 side via a junction 610 . A plurality of ADCs 2000 corresponding to a plurality of signal lines 202 constitute ADC section 1820 .

In the example of FIG. 20, the ADC section 1820 is provided with ADCs 2000 corresponding to the odd-numbered pixel blocks 200c and 200d, and the ADC section 1830 is provided with ADCs 2000 corresponding to the even-numbered pixel blocks 200e and 200f. However, the arrangement relationship between the pixel block 200c etc. and the corresponding ADC unit 1820 etc. is not limited to this.

With the above configuration, each ADC 2000 converts pixel signals sequentially output from the connected m×M pixels 201 in one column into digital signals and outputs the digital signals. In this case, the ADC units 1820 and 1830 as a whole convert pixel signals from the pixels 201 arranged in n×N columns in the row direction into digital signals in parallel. From this point of view, this digital conversion can be said to be a kind of so-called column ADC. Note that although a single-slope ADC is given as an example of the ADC, other digital conversion methods may be used. Also, the connection position of each pixel 201 and the signal line 202 is not limited to the form shown in FIG. 20, and may be in each pixel block 200c or the like as another example.

FIG. 21 is a timing chart showing imaging operations in the pixel block 200 of the imaging device 100B. Driving of the pixel block 200 is controlled by a transfer control signal φTX, a discharge control signal φPDRST, a reset control signal φRST and a selection control signal φSEL.

The discharge control signal φPDRST controls the timing of starting exposure. The exposure start timing corresponds to the fall timing of the discharge control signal φPDRST (for example, time T1). That is, before the exposure start time T1, the discharge control signal φPDRST turns on the discharge unit 302 to discharge the charges accumulated in the photoelectric conversion unit 300, and the exposure starts at the fall of the discharge control signal φPDRST. do. Since the discharge control signal φPDRST is locally controlled, the exposure time can be adjusted for each pixel block 200 .

The transfer control signal φTX controls the timing of ending exposure. At time T<b>3 , the transfer control signal φTX turns on the transfer unit 301 to transfer the charge accumulated in the photoelectric conversion unit 300 to the FD 303 . The end timing of exposure corresponds to the falling timing of the transfer control signal φTX (for example, time T4).

A reset control signal φRST controls the timing of discharge of charges accumulated in the FD 303 . At time T2, the reset control signal φRST turns on the reset section 304 to discharge the charge of the FD 303 . By discharging the charge of the FD 303 before the timing of the end of exposure, the influence of the charge remaining in the FD 303 can be suppressed when the charge is transferred from the photoelectric conversion unit 300 .

A selection control signal φSEL is a signal for selecting an arbitrary pixel 201 . The selection control signal φSEL controls on/off of the selection section 352 . At time T2, the selection control signal φSEL is set high. At time T3, the pixels 201 for which the selection control signal φSEL is set to high output pixel signals to the signal lines 202 in response to the turn-on of the transfer control signal φTX. On the other hand, the pixels 201 for which the selection control signal φSEL is not set to high output no pixel signal.

By locally controlling the discharge control signal φPDRST, the imaging device 100B can change the exposure start timing for each pixel block 200 and control the exposure time for each pixel block 200 . Further, the imaging device 100B may control the end timing of exposure for each pixel block 200 by locally controlling the transfer control signal φTX. The imaging element 100B may control both the start timing and end timing of exposure for each pixel block 200 by locally controlling both the transfer control signal φTX and the discharge control signal φPDRST.

A pixel signal of each pixel 201 corresponds to the charge amount accumulated in the photoelectric conversion unit 300 . Therefore, controlling the timing of exposure of the pixels 201 can be said to control the timing of charge accumulation in the photoelectric conversion unit 300 . More specifically, controlling the timing of exposure of the pixels 201 can be said to control the timing and length of the charge accumulation time from charge discharge to charge transfer.

FIG. 22 is an explanatory diagram showing an example of exposure timing for each pixel block 200. As shown in FIG. The exposure time is controlled for each of the three pixel blocks 200 arranged in one row. Here, the image pickup device 100B changes the exposure amount by shifting the pixel reset time for each pixel block 200 .

On the other hand, the pixel signal readout timing is in order from the pixel block 200 on the top. That is, the pixel signal is read from the pixel 201 of "pixel block 1", then the pixel signal is read from the pixel 201 of "pixel block 2", and then the pixel signal is read from the pixel 201 of "pixel block 3".

Furthermore, within the pixel block 200, pixel signals are sequentially read out from the pixels 201 in the upper row as described with reference to FIG. Therefore, when the pixel unit 101 is viewed as a whole, pixel signals are sequentially read from the top row of the m×M pixels 201 in the same column connected to the common signal line 202 . In other words, the global driving section 600 sets the selection control signal φSEL to high row by row across the plurality of pixel blocks 200 arranged in one column from the first row to the m×Mth row.

In this case, as described with reference to FIG. 20, for a plurality of pixel blocks 200 arranged in one row, a common selection control line 1904 is connected to n×N pixels arranged in the same row. Therefore, pixel signals are read out in parallel from the n×N pixels 201 connected to the row in which the selection control signal φSEL is set to high. Accordingly, pixel signals for one frame can be output.

These pixel signals are digitally converted by the ADC units 1820 and 252 as described with reference to FIG. The digital-converted pixel signals are output to subsequent image processing to form an image for one frame.

As described above, from the viewpoint that pixel signals are sequentially read out from the upper row in the same column among a plurality of pixel blocks 200, the readout method of the present embodiment is the so-called rolling shutter method for the entire pixel unit 101. It can also be said that However, even in that case, it is possible to set a different exposure time for each pixel block 200 .

In this manner, the image sensor 100B shown in FIGS. 16 to 22 performs exposure in units of pixel blocks 200, but sequentially reads pixel signals for each pixel row and performs AD conversion for each pixel column. Specifically, the image sensor 100B reads pixel signals from the pixels 201 of the upper pixel block 200 among the plurality of pixel blocks 200 arranged in a row, and then reads the pixel signals from the pixels 201 of the lower pixel block 200. Read out the signal. Therefore, when a moving subject is captured, the distortion of the image due to the readout order is smoothed, and the viewer's discomfort with the image can be reduced. More specifically, when a moving subject is read out in parallel from a plurality of pixel blocks 200 arranged in a row, the pixel blocks 200 correspond to the vertical direction of the image (that is, the pixel column direction). A plurality of saw-toothed steps appear to cause discomfort to the observer. In contrast, according to the imaging device 100B shown in FIGS. 16 to 22, the plurality of steps do not appear in the image.

16 to 22, the signal processing section 1602 is arranged outside the control circuit section 102 without providing the ADC section for converting analog signals into digital signals in the control block 400B. Therefore, the area of the control block 400B can be reduced, and the size of the pixel block 200 arranged at the position corresponding to the control block 400B can be reduced. can be done. As a result, it is possible to finely control the exposure time within the image, and to make the boundaries of the pixel blocks 200 inconspicuous on the image. Furthermore, since digital conversion is not performed immediately below the pixel 201, the influence of noise on the pixel 201 due to heat generation can be suppressed.

Note that the signal processing unit 1602 does not have to be provided in a plurality of separate regions, and may be provided in one region for the entire pixel portion 101 .

As described above, similarly to the image pickup device 100A, pixel signals are read out in order from the upper row of the same column in the plurality of pixel blocks 200. Therefore, the readout method of the image pickup device 100B is also As a whole, it can be said that it is a so-called rolling shutter system. However, even in this case, different exposure times can be set for each pixel block 200, as in the image sensor 100A. As a result, in the image pickup device 100B, similarly to the image pickup device 100A, the image distortion due to the readout order when capturing an image of a moving subject is smoothed, and the viewer's sense of discomfort in the image can be reduced.

[Autonomous exposure processing unit 411]
Next, the details of the above-described autonomous exposure processing unit 411 will be described. In the following description, the image sensor 100 is used when the image sensors 100A and 100B are not distinguished, and the control block 400 is used when the control blocks 400A and 400B are not distinguished.

The autonomous exposure processor 411 is implemented in the control block 400 as shown in FIGS. 4 and 17. FIG. Also, the autonomous exposure processing unit 411 can be mounted in the peripheral circuit unit 121 instead of the control block 400, or can be mounted in both the control block 400 and the peripheral circuit unit 121. is. These three patterns will be described below with reference to FIGS. 23 to 25. FIG.

FIG. 23 is a block diagram showing a configuration example of the autonomous exposure control method 1. As shown in FIG. Autonomous exposure control method 1 is a configuration example in which the autonomous exposure processing unit 411 is implemented in the control block 400 . The addition of the autonomous exposure processing unit 411 to the control block 400 increases the circuit scale of the control block 400, but each pixel 201 of the pixel block 200 may increase accordingly, so the light receiving area is increased. Is possible.

In FIG. 23, the control block 400A will be described as an example (the same applies to FIG. 25). The control block 400A has a signal conversion section 422, a signal output section 423, an autonomous exposure processing section 411, an exposure control section 412, and a pixel driving section 413. For convenience of explanation, the signal input unit 421 is omitted. In the control block 400B, the signal input section 421, the signal conversion section 422 and the signal output section 423 are not included in the control block 400B, but are arranged on the second semiconductor substrate 120 as the signal processing section 1602 (FIG. 25). as well).

The signal converter 422 has n ADCs 500 . Each of the n ADCs 500 converts analog pixel signals from m pixels 201 connected in the column direction into digital signals. The ADC 500 is composed of a comparator 501 and a storage section 502 .

Column selection circuit 2301 is included in signal output section 423 . The column selection circuit 2301 sequentially selects columns of the pixel block 200 each time a readout column selection signal is input from the external K. Each time a horizontal transfer clock is input from the outside, the column selection circuit 2301 outputs digital pixel signals from the m pixels 201 in the selected column to the peripheral circuit section 121 via the horizontal transfer line 2300. Output to the autonomous exposure processing unit 411 .

The autonomous exposure processing section 411 calculates an exposure value indicating the exposure time of the pixel block 200 . Specifically, for example, the autonomous exposure processing section 411 has a preprocessing section 2311 , a controller 2312 , and an exposure value calculation section 2313 .

A preprocessing unit 2311 acquires a digital pixel signal for each pixel column of the pixel block 200 from the column selection circuit 2301 . Then, the preprocessing unit 2311 calculates a statistical value (for example, average value, median value, maximum value, or minimum value) of the acquired pixel signals. The preprocessing unit 2311 outputs this calculation result to the exposure value calculation unit 2313 .

The controller 2312 inputs a reset signal to the preprocessing section 2311 to reset the preprocessing by the preprocessing section 2311 . Thereby, the preprocessing unit 2311 calculates the statistic value of the pixel signals from the pixel block 200 each time reset is performed, that is, for each frame.

The exposure value calculation unit 2313 determines the next exposure value based on the calculation result (statistical value of pixel signals) from the preprocessing unit 2311 . Specifically, for example, the exposure value calculator determines the next exposure value based on the calculation result so as not to cause underexposure or overexposure. For example, exposure value calculator 2313 holds a first threshold value and a second threshold value. The first threshold is a threshold for determining whether or not the calculation result is underexposure. The second threshold is a threshold larger than the first threshold, and is a threshold for determining whether or not the calculation result is overexposure.

The exposure value calculator 2313 determines whether or not the calculation result is equal to or greater than the first threshold value and equal to or less than the second threshold value. If the calculation result is greater than or equal to the first threshold value and less than or equal to the second threshold value, the exposure value calculation section outputs the calculation result to the latch circuit 2321 of the exposure control section 412 as an exposure value. If the calculation result is less than the first threshold, the exposure value calculator 2313 outputs the first threshold to the latch circuit 2321 of the exposure controller 412 as the exposure value. If the calculation result exceeds the second threshold, the exposure value calculator outputs the second threshold to the latch circuit 2321 of the exposure controller 412 as the exposure value.

Also, the exposure value calculator 2313 may hold a plurality of exposure value ranges. In this case, if the calculation result is greater than or equal to the first threshold value and less than or equal to the second threshold value, the exposure value calculation unit 2313 sets the number of steps in the exposure value range that includes the calculation result as the exposure value, and latches the exposure control unit 412. Output to circuit 2321 .

If the calculation result is less than the first threshold value, the exposure value calculation unit 2313 sets the number of steps that is one or more steps higher than the number of steps in the exposure value range that includes the calculation result as the exposure value of the exposure control unit 412. Output to latch circuit 2321 . Further, if the calculation result exceeds the second threshold, the exposure value calculation unit 2313 sets the number of steps lower than the number of steps of the exposure value range including the calculation result by one step or more as the exposure value. 412 latch circuit 2321.

The exposure controller 412 has, for example, a latch circuit 2321, a shift register 2322, a pixel block controller, and a level shifter. A latch circuit 2321 holds the exposure value from the autonomous exposure processing section. The latch circuit 2321 outputs the held exposure value to the pixel block control section and the shift register 2322 each time a latch pulse is input from the outside.

The shift register 2322 converts the exposure value from the latch circuit 2321 into a parallel-to-serial signal, converts it into a serial signal, and outputs it to the data processing unit.

If the exposure time is calculated by an external system outside the image pickup device 100 and the calculated result is fed back to the image pickup device 100, it takes time to reflect the calculation result in the exposure time of the image pickup device 100, increasing power consumption. On the other hand, by providing the autonomous exposure processing unit 411 in the control block 400, it is possible to improve the reflection speed of the exposure time to the pixel block 200 and reduce the power consumption.

In FIG. 23, the case where one pixel block 200 is subjected to exposure control by one control block 400 has been described. , one pixel block 200 may be sequentially selected from a plurality of pixel blocks 200 in synchronization with , and the exposure value calculated. A selector is provided on the output side of the exposure value calculation unit 2313 , and the controller 2312 outputs a selection signal for selecting one pixel block 200 from a plurality of pixel blocks 200 to the selector.

Also, in this case, the exposure control section 412 has a latch circuit 2321 and a shift register 2322 for each pixel block 200 . Each of the latch circuits 2321 is connected to a selector (not shown) in the autonomous exposure processing unit 411, and when an exposure value is input from the selector, the held exposure value is transferred to the pixel block control unit 503 each time a latch pulse is input. and output to the shift register 2322 . Thereby, autonomous exposure can be realized even when exposure control is performed for a plurality of pixel blocks 200 by one control block 400 .

FIG. 24 is a block diagram showing a configuration example of the autonomous exposure control method 2. As shown in FIG. Autonomous exposure control method 2 is a configuration example in which the autonomous exposure processing unit 411 is implemented in the peripheral circuit unit 121 . The autonomous exposure processing section 411 is mounted in the peripheral circuit section 121 instead of within the control block. Therefore, the circuit scale of the control block 400 can be made smaller than in the case of FIG.

The peripheral circuit section 121 is connected to the pixel section 101 via the horizontal transfer section 2410 . The horizontal transfer section 2410 is connected to each pixel block 200 arranged in the row direction (hereinafter referred to as pixel block row), and transfers pixel signals to the peripheral circuit section 121 for each pixel block row. Since the pixel unit 101 is a set of pixel blocks 200 of M rows and N columns, the horizontal transfer unit 2410 transfers pixel signals to the peripheral circuit unit 121 for each M pixel block rows.

The peripheral circuit section 121 has row-direction autonomous exposure processing section groups 2400-1 to 2400-M (simply referred to as row-direction autonomous exposure processing section group 2400 when not distinguished) for each pixel block row. The row-direction autonomous exposure processing unit group 2400 includes a data sampling unit 2411 and autonomous exposure processing units 411 (pre-processing unit 2311, controller 2312, and exposure value calculation unit 2313) for N columns of pixel blocks. Since N=4 in FIG. 24, four sets of the preprocessing unit 2311, the controller 2312, and the exposure value calculation unit 2313 are implemented.

The data sampling unit 2411 equally divides the pixel signal train of the pixel block row from the horizontal transfer unit 2410 into N and samples them. The data sampling section 2411 outputs each sampled pixel signal sequence to the corresponding preprocessing section 2311 .

The preprocessing unit 2311 calculates statistical values of pixel signals from the corresponding pixel block 200 as described above. Further, since the peripheral circuit unit 121 can have a circuit scale larger than that of the control block 400, the preprocessing unit 2311 can execute processing other than the calculation of the statistical value of the pixel signal.

For example, the preprocessing unit 2311 has a memory for storing the pixel number of the defective pixel in the corresponding pixel block 200 at the time of manufacture, and when the data sampling unit 2411 samples the pixel signal of the pixel number, the preprocessing unit 2311 The unit 2311 is not used for calculating the statistical value of the pixel signal. As a result, it is possible to improve the accuracy of calculating the statistical value of the pixel signal.

Further, the preprocessing unit 2311 obtains the calculation result from another preprocessing unit 2311 in charge of the pixel block 200 adjacent to the corresponding pixel block 200, and based on the calculation result obtained from the other preprocessing unit 2311, performs the corresponding processing. Statistics of pixel signals from pixel block 200 may be calculated. As a result, the exposure step between adjacent pixel blocks 200 can be smoothed.

A first threshold value and a second threshold value are set in the exposure value calculation unit 2313, and the first threshold value and the second threshold value are set according to the imaging mode of the imaging apparatus in which the imaging element 100 is mounted. At least one of the second thresholds may be changeable. This makes it possible to calculate the optimum exposure according to the shooting mode.

The peripheral circuit section 121 also has a latch circuit 2321 and a shift register 2322 for each exposure value calculation section 2313 . The shift register 2322 parallel-serial converts the exposure value from the latch circuit 2321, outputs the serial signal to the data processing unit 103, Output the exposure value.

With the configuration shown in FIG. 24, the circuit scale of the control block 400 can be made smaller than in the case of FIG. 23, and the size of the corresponding pixel block 200 can be made small. Therefore, the number of pixel blocks is increased, and fine autonomous exposure control becomes possible. Also, the exposure control section 412 and the pixel driving section 413 may be mounted in the peripheral circuit section 121 . Thereby, the circuit scale of the control block 400 can be further reduced, and the size of the corresponding pixel block 200 can be reduced.

FIG. 25 is a block diagram showing a configuration example of the autonomous exposure control method 3. As shown in FIG. Autonomous exposure control method 3 is a configuration example in which the autonomous exposure processing unit 411 is implemented in both the control block 400A and the peripheral circuit unit 121 . When automatic exposure control is executed within the control block 400A, data transmission such as sending pixel signals from the control block 400A to the peripheral circuit section 121 and sending exposure values from the peripheral circuit section 121 to the pixel block 200 is unnecessary. Become. Therefore, the feedback to the corresponding pixel block 200 is faster than when it is executed in the peripheral circuit section 121 .

On the other hand, since the area of the control block 400A is restricted by the area of the corresponding pixel block 200, the circuit scale of the autonomous exposure processing section 411 is increased by mounting it in the peripheral circuit section 121 rather than mounting it in the control block 400A. can do. For this reason, it is better to implement more advanced functions for autonomous exposure control in the peripheral circuit section 121 (for example, removal of pixel signals of defective pixels described in FIG. 24, exposure step control with the adjacent pixel block 200, Calculation of optimum exposure according to the exposure) can be implemented.

Therefore, according to the autonomous exposure control method 3, the imaging device 100 uses the peripheral circuit unit 121 when performing highly functional calculations related to autonomous exposure control, and the control unit 121 when performing feedback of the exposure value at high speed, depending on the situation. At block 400A, autonomous exposure control is performed. In FIG. 25, as an example, in autonomous exposure control method 3, autonomous exposure control is executed by the row direction autonomous exposure processing unit group 2400 in the peripheral circuit unit 121. If given, perform autonomous exposure control for each control block 400A.

For example, the image pickup device 100 operates in the peripheral circuit unit 121 when high-performance calculation related to autonomous exposure control is selected by user operation, and in the control block 400A when high-speed execution of exposure value feedback is selected. , to perform autonomous exposure control. Further, when the remaining battery level becomes equal to or less than a predetermined amount, the imaging device 100 may select and execute low power consumption processing among high-speed execution of highly functional calculations related to autonomous exposure control and exposure value feedback. good.

A row-direction autonomous exposure processing unit group 2400 mounted in the peripheral circuit unit 121 has the same configuration as that shown in FIG. 24, and is therefore omitted in FIG.

The column selection circuit 2301 outputs n-bit digital pixel signals to n OR circuits 2501 . An autonomous exposure processing unit 2500 in the control block 400A has a controller 2312, n OR circuits 2501, an output data latch circuit 2502, and an n-bit AND circuit 2503.

Controller 2312 inputs a reset signal to output data latch circuit 2502 when an n-bit signal is output from output data latch circuit 2502 .

The OR circuit 2501 is a logic circuit with two inputs and one output. One input of OR circuit 2501 is connected to the column selection circuit and the other input is connected to the output of n-bit AND circuit 2503 .

The n OR circuits 2501 are connected to the input of the output data latch circuit 2502 . Output data latch circuit 2502 holds n-bit signals from n OR circuits 2501 . The output data latch circuit 2502 outputs an n-bit signal to the n-bit AND circuit 2503 when the horizontal transfer clock is input. Further, when a reset signal is input from the controller 2312, the output data latch circuit 2502 resets the held n-bit signal, and converts the n-bit signal having at least one bit of 0 out of the n bits to an n-bit AND circuit. 2503 for output.

The n-bit AND circuit 2503 is an n-input 1-output AND circuit, and the output of the output data latch circuit 2502 is connected to the input of the n-bit AND circuit 2503 . The output of the n-bit AND circuit 2503 is connected to the selector 2512 of the exposure control section 412 and the input of each OR circuit 2501 . If the output from the n-bit AND circuit 2503 is "0", it indicates that the pixel column outputting the n-bit digital pixel signal is not saturated. If the output from the n-bit AND circuit 2503 is "1", it indicates that the pixel column outputting the n-bit digital pixel signal is saturated. A 1-bit signal of "1" output from the n-bit AND circuit 2503 is hereinafter referred to as a saturation detection signal.

A digital pixel signal value of "1" from a pixel 201 in a pixel column indicates that the pixel 201 is saturated. If the value of the n-bit signal from the column selection circuit 2301 is all "1", it indicates that the entire pixel column is saturated. In this case, since "1" is input to one input of each OR circuit 2501, each OR circuit 2501 outputs a 1-bit signal whose value is "1" to the output data latch circuit 2502. FIG.

The output data latch circuit 2502 holds these n bit signals whose values are all "1", and outputs the held n bit signals to the n bit AND circuit 2503 when the horizontal transfer clock is input. do.

The n-bit AND circuit 2503 outputs a saturation detection signal having a value of “1” to the selector 2512 and each OR circuit 2501 when an n-bit signal whose value is all “1” is input. As a result, the output data latch circuit 2502 outputs an n-bit signal whose value is all "1" to the n-bit AND circuit 2503 until the reset signal is input. Therefore, n-bit AND circuit 2503 outputs the saturation detection signal until output data latch circuit 2502 receives a reset signal from controller 2312 .

The exposure control unit 412 has a shift register 2511 and a selector 2512 in addition to the configuration shown in FIG. The shift register 2511 serial-parallel converts the exposure value from the peripheral circuit section 121 and outputs it to the level shift section 504 and the selector 2512 .

A selector 2512 inputs the exposure value and the set exposure value from the shift register 2511 . Selector 2512 selects either the exposure value from shift register 2511 or the set exposure value based on the output signal from n-bit AND circuit 2503 and outputs the selected exposure value to latch circuit 2321 . The set exposure value is an exposure value corresponding to an exposure time that does not saturate the pixels 201, for example, an exposure value that is set so that the exposure time is the shortest.

The set exposure value is calculated and set by an external system outside the control block 400A, for example. The set exposure value may be a fixed value or may be selected from an external system. The external system is, for example, the peripheral circuit unit 121 in the image pickup device 100, the data processing unit 103 in the third semiconductor substrate 130, or the image processing unit connected to the image pickup device 100 in an image pickup apparatus having the image pickup device 100. be.

More specifically, selector 2512 selects the exposure value from shift register 2511 and outputs it to latch circuit 2321 when the output signal from n-bit AND circuit 2503 is not a saturation detection signal, for example. On the other hand, when the output signal from the n-bit AND circuit 2503 is the saturation detection signal, the selector 2512 selects the set exposure value and outputs it to the latch circuit 2321 .

Autonomous exposure control is performed by the autonomic exposure processing section 2500 and the exposure control section 412 in the control block 400A using the exposure value from the peripheral circuit section 121 until saturation is detected in the control block 400A. When saturation is detected in the control block 400A, autonomous exposure control is executed using the set exposure value in the exposure control section 412. FIG.

As a result, a process of setting highly accurate exposure values for non-saturated pixel columns based on the exposure values from the peripheral circuit unit 121 and setting exposure values for saturated pixel columns to non-saturated states are performed. A process that allows simple and fast feedback to change can be made selectable.

Also, the autonomous exposure processing section 2500 in the control block 400 may be the autonomous exposure processing section 411 shown in FIG. In this case, for example, the autonomous exposure processing section 411 in the peripheral circuit section 121 and the autonomous exposure processing section 411 in the control block 400 may be selectable by user setting.

For example, an image capturing apparatus equipped with the image sensor 100 may be made selectable between the autonomous exposure processing section 411 in the peripheral circuit section 121 and the autonomous exposure processing section 411 in the control block 400 based on the remaining battery level. In this case, the imaging apparatus selects autonomous exposure control by the autonomous exposure processing section 411 in the peripheral circuit section 121 if the remaining battery level is equal to or greater than a predetermined value, and if not equal to or greater than the predetermined value, the autonomous exposure control in the control block 400 is performed. Autonomous exposure control by the exposure processing unit 411 may be selected. Further, the user selects the autonomous exposure processing unit 411 in the peripheral circuit unit 121 to perform high-quality imaging, and selects the autonomous exposure processing unit 411 in the control block 400 to reduce power consumption. do it.

<Layout of autonomous exposure control method>
Next, the layout of the autonomous exposure control system will be explained. The autonomous exposure processing section 411 may be implemented in the control block 400 as shown in FIGS. 23 and 25, or may be implemented in the peripheral circuit section 121 as shown in FIGS. 24 and 25. . The former will be explained in FIG. 26, and the latter will be explained in FIGS. 27 and 28. FIG. 26 to 28, the circuit configuration of the control block 400A will be described as an example. In the case of the control block 400B, the signal processing unit 402 in the control block 400A serves as the signal processing unit 1602 in the second control block 400B outside the control block 400B. It is laid out on the semiconductor substrate 120 .

FIG. 26 is a block diagram showing a layout example when autonomous exposure processing units are mounted in adjacent control blocks. FIG. 13 shows a layout example of a plurality of control blocks 400A. 26, in the configuration of the autonomous exposure control method 1 shown in FIG. 23, the internal configuration of two control blocks 400Aa and 400Ab that are adjacent in the row direction without intervening the pixel driving unit 413 in FIG. 13 will be described in detail. do.

Specifically, for example, in FIG. 26, two control blocks 400Aa and 400Ab that are adjacent in the row direction shown in FIG. In order to indicate which of the control blocks 400Aa and 400Ab is the internal configuration, the internal configuration of the control block 400Aa is given a suffix a, and the internal configuration of the control block 400Ab is suffixed with a b.

In addition, the connection relationship of the internal configuration is indicated by the signal lines shown in the legend. Solid arrows are global pixel signal lines 2601G, and dotted arrows are local pixel signal lines 2601L. A solid bold arrow is the global control signal line 2602G, and a dotted bold arrow is the local control signal line 2602L. A dashed-dotted line is a data line 2603 between control blocks. A pixel signal line is a signal line that transmits a pixel signal, and a control signal line is a signal line that transmits a control signal.

A global pixel signal line 2601G is a pixel signal line (horizontal transfer line) shared by the control blocks 400A in the row direction. A local pixel signal line 2601L is a pixel signal line within the control block 400A. The global control signal line 2602G is a control signal line shared by the control blocks 400A in the row direction. Local control signal line 2602L is a control signal line within that control block 400A. A data line between control blocks 2603 is a data line for transmitting and receiving data between the exposure value calculation units 2313a and 2313b.

In the control blocks 400Aa and 400Ab, as described with reference to FIG. 13, signal converters 422a and 422b, autonomous exposure processors 411a and 411b, and exposure controllers 412a and 412b are mirror-arranged.

A signal output unit 423 common to the control blocks 400Aa and 400Ab is arranged between the signal conversion units 422a and 422b. This improves the layout efficiency between the control blocks 400Aa and 400Ab.

Since mirrors are also arranged inside the autonomous exposure processing units 411a and 411b, the preprocessing units 2311a and 2311b are arranged along the row direction. Digital pixel signals from the signal conversion units 422a and 422b are horizontally transferred to the global pixel signal line 2601G via the signal output unit 423. FIG. Therefore, preprocessing units 2311a and 2311b are arranged close to signal conversion units 422a and 422b and signal output unit 423 (column selection circuit 2301).

As a result, the local pixel signal line 2601L between the preprocessing units 2311a and 2311b and the signal output unit 423 can be wired without bypassing other internal configurations. Therefore, the transmission efficiency of digital pixel signals between the preprocessing units 2311a and 2311b and the signal output unit 423 is improved.

Controllers 2312a and 2312b and exposure value calculators 2313a and 2313b are also arranged along the row direction. Specifically, for example, in the row direction, the exposure value calculators 2313a and 2313b are arranged close to each other, and the controllers 2312a and 2312b are arranged apart from each other. For example, when the exposure value calculator 2313b calculates the exposure value using the exposure value from the exposure value calculator 2313a, communication occurs between the exposure value calculators 2313a and 2313b. This communication distance is shortened compared to the case where the controllers 2312a and 2312b are spaced apart. Therefore, the calculation efficiency in the exposure value calculator 2313b is improved.

The local pixel signal line 2601L includes the signal output unit 423 and preprocessing units 2311a and 2311b, the preprocessing units 2311a and 2311b and exposure value calculation units 2313a and 2313b, and the exposure value calculation units 2313a and 2313b and exposure control units 412a and 412b. to connect. Therefore, in order to shorten the wiring length of the local pixel signal line 2601L, the preprocessing units 2311a and 2311b, the exposure value calculation units 2313a and 2313b, and the exposure control units 412a and 412b are arranged closer to the pixel driving units 413a and 413b than to the pixel driving units 413a and 413b. , are arranged close to the boundary between the control blocks 400Aa and 400Ab.

With such arrangement, the wiring scale in the control blocks 400Aa and 400Ab can be reduced.

FIG. 27 is a block diagram showing a layout example when the autonomous exposure processing section 411 is mounted in the peripheral circuit section 121. As shown in FIG. FIG. 28 is a block diagram showing the detailed internal configuration of the peripheral circuit section 121 shown in FIG. 27. As shown in FIG. Peripheral circuit sections 121 a and 121 b are arranged on both sides of the control circuit section 102 on the second semiconductor substrate 120 .

The control circuit unit 102 has a signal processing unit 402 (a signal input unit 421, a signal conversion unit 422, and a signal output unit 423) and an exposure control unit 412 for each control block 400A.

The peripheral circuit section 121 has a pixel drive section 413 , a row direction autonomous exposure processing section group 2400 and a digital signal processing circuit 2701 . The peripheral circuit section 121 also has a timing generator 2702 .

In addition, an output IF 2703 is arranged outside the peripheral circuit section 121 and close to the digital signal processing circuit 2701 . Similarly, outside the peripheral circuit section 121, a PLL circuit 2704 is arranged adjacent to the timing generator 2702, respectively.

The timing generator 2702 sequentially outputs all column addresses of the pixel block columns to the data sampling section 2411 during one frame. Also, the timing generator 2702 outputs a reset signal to each autonomous exposure processing unit.

As shown in FIG. 28, the signal output section 423 in the control block 400A outputs digital pixel signals to the data sampling section 2401. As shown in FIG. The data sampling unit 2401 refers to the column address of the pixel block column from the timing generator 2702 , sorts the digital pixel signals from the control block 400 A for each pixel block column, and outputs the digital pixel signal to the autonomous exposure processing unit 411 . Also, the data sampling unit 2401 outputs digital pixel signals to the digital signal processing unit.

The autonomous exposure processing unit 411 calculates an exposure value and outputs it to the exposure control unit 412 . The autonomous exposure processing unit 411 resets the exposure value upon receiving the reset signal from the timing generator.

In row direction autonomous exposure processing unit groups 2400-1 to 2400-M, data sampling units 2401 and row direction autonomous exposure processing units 411 are alternately arranged in the column direction. This reduces the wiring lengths of the control signal lines and the data signal lines.

The digital signal processing circuit 2701 uses the output signal from the PLL circuit 2704 to serially convert the exposure value from the row direction autonomous exposure processing unit group 2400 and sends it to the output IF 2703 . The timing generator 2702 supplies the row-direction autonomous exposure processing unit group 2400 with clock signals for generating various timing signals used in the row-direction autonomous exposure processing unit group 2400 .

In FIG. 27, a signal (for example, a digital pixel signal) from the control circuit section 102 is output to the autonomous exposure processing section 411 via the pixel driving section 413, and the exposure value from the autonomous exposure processing section 411 is output to the digital signal processing circuit 2701. , and the output from the digital signal processing circuit 2701 is output to the output IF 2703 . Therefore, between the control circuit unit 102 and the output IF 2703, the pixel driving unit 413, the autonomous exposure processing unit 411, and the digital signal processing circuit 2701 are arranged in order of proximity from the control circuit unit 102. FIG.

In addition, the row-direction autonomous exposure processing unit group 2400 communicates with the timing generator 2702 , so it is also arranged close to the timing generator 2702 . A digital signal processing circuit 2701 and a timing generator 2702 are closely arranged in an automatic placement and routing area 2700 where placement and routing are automatically performed by a computer (not shown).

In this manner, the autonomous exposure processing section 411 is arranged close to the automatic placement and routing area 2700 in the peripheral circuit section 121 according to the signal flow. Therefore, the wiring scale in the peripheral circuit section 121 can be reduced.

<Shortening the reflection period when changing the exposure time>
Next, shortening of the reflection period when changing the exposure time will be described with reference to FIGS. 29 to 38. FIG.

FIG. 29 is an explanatory diagram showing an example of a delay in the exposure time reflection period. In FIG. 29, an example will be described in which the exposure time for 1/2 frame (hereinafter referred to as 1/2 frame exposure) is changed to the exposure time for 1 frame (hereinafter referred to as 1 frame exposure). The horizontal axis in FIG. 29 is time, and the vertical axis is the row number within the pixel block. In FIG. 29, the number m of pixel rows in the pixel block 200 is assumed to be 32 rows.

In 1/2 frame exposure, when the discharge control signal φPDRST is sequentially input to the gate terminal of the discharge unit 302 for each pixel 201 in the pixel row of the pixel block 200, the pixel 201 in each pixel row accumulates charge, that is, exposes the pixel. is started (reset 1-3).

In the half-frame exposure, the transfer control signal φTX is sequentially input to the gate terminal of the transfer unit 301 for each pixel 201 in the pixel row of the pixel block 200 when the half-frame exposure has elapsed from each of resets 1 to 3. Then, readout 1 of the pixel block 200 in frame Fi is started, and readout period i of the pixel block 200 in frame F1 ends when analog pixel signals are read out from the last pixel row.

The pixel signal read out in the readout period i is subjected to data transfer i to the outside as a digital signal by the signal processing unit 402 . In addition, the control block 400 executes the exposure value calculation i for the pixel signal read out in the readout period i and digitally converted.

Assume that an instruction to change from 1/2 frame exposure to 1 frame exposure is input to the control block 400 before the readout period i elapses. When the calculation result of the exposure value calculation i is to be reflected in the one-frame exposure of the frame F(i+1), it must be after the exposure value calculation i is completed. Therefore, reset 4 is executed at the timing of the first readout start time (readout 3) after the end of exposure value calculation i. That is, since the reset 2 is started before the end of the exposure value calculation i, the calculation result of the exposure value calculation i cannot be reflected in the 1-frame exposure of the frame F(i+1) at the readout 2 timing.

In one frame exposure after updating, when the transfer control signal φTX is sequentially input to the gate terminal of the transfer unit 301 for each pixel 201 in the pixel row of the pixel block 200 when one frame exposure has passed since reset 4, frame Readout 4 of the pixel block 200 in F(i+1) is started, and readout period i+1 of the pixel block 200 in frame F(i+1) ends when analog pixel signals are read out from the last pixel row.

The pixel signal read out in the readout period i+1 is subjected to data transfer i+1 to the outside as a digital signal by the signal processing unit 402 . Also, the control block 400 executes exposure value calculation i+1 for the pixel signal read out and digitally converted in the readout period i+1.

Thus, in FIG. 29, when changing from 1/2 frame exposure to 1 frame exposure, a delay of 2 frames occurs before 1 frame exposure is reflected. The same applies when changing from less than 1/2 frame exposure to 1 frame exposure.

FIG. 30 is an explanatory diagram showing Example 1 of shortening the reflection period of the exposure time. In FIG. 30, similarly to FIG. 29, the case of changing from 1/2 frame exposure to 1 frame exposure will be described as an example. The difference from FIG. 29 is that in FIG. 30, forced resets 1 to 4 for one-frame exposure are input at the timings of readouts 1 to 4. FIG.

Forced resets 1 to 4 are discharge control signals φPDRST that are sequentially input to the gate terminal of the discharge unit 302 for each pixel 201 in the pixel row of the pixel block 200, similar to the resets 1 to 4. charge accumulation, that is, exposure, starts in the pixels 201 of .

Assume that an instruction to change from 1/2 frame exposure to 1 frame exposure is input to the control block 400 before the readout period i elapses. In FIG. 29, when the calculation result of the exposure value calculation i is reflected in the one-frame exposure of the frame F(i+1), it must be after the exposure value calculation i ends, but in FIG. Then, without waiting for the end of the exposure value calculation i, the pixels 201 of each pixel row start accumulating charge in the pixel block 200 in the frame F(i+1). In this case, the control block 400 drives and controls the pixels 201 so that reset 3 is not input.

After that, one frame exposure continues. That is, read 4 is started at the timing of the end of read period i+1, and forced reset 4 is applied. This initiates charge accumulation in pixel block 200 in frame F(i+2). In this case, the control block 400 drives and controls the pixels 201 so that reset 5 is not input.

Thus, in FIG. 30, when changing from 1/2 frame exposure to 1 frame exposure, the delay until 1 frame exposure is reflected is shortened to 1 frame. Such shortening is similar when changing from less than 1/2 frame exposure to 1 frame exposure.

Also, even when changing from 1-frame exposure to 1/2 or less exposure, the forced reset continues to be input, but the reset is also input. For example, if an instruction to change from 1-frame exposure to 1/2 or less exposure is input to control block 400 before the end of exposure value calculation i+1, the calculation result of exposure value calculation i+1 (for example, 1/2-frame exposure) is , reflected by reset 5, which arrives first after the end of exposure value calculation i+1, to start charge accumulation in pixel block 200 in frame F(i+2).

FIG. 31 is an explanatory diagram showing Example 2 of shortening the reflection period of the exposure time. FIG. 31 shows an example in which all pixels 201 in one pixel block 200 are controllable in each of K (K is an integer equal to or greater than 2) pixel regions. FIG. 31 shows an example in which one pixel block 200 has 32 rows, one pixel block 200 has 8 rows, and one control block 400 controls four pixel regions 3101 to 3104 .

In FIG. 30, the exposure value calculation and the exposure value could not be reflected until the readout of 32 rows of the pixel block 200 was completed, but in FIG. The control block 400 can execute the exposure value calculation and exposure value reflection of the pixel area 3101 even if the readout of 3104 is not finished.

In this way, even when a plurality of pixel regions 3102 to 3104 are controlled by one control block 400, the delay until the reflection of one frame exposure is reduced to one frame. of data can be output for each of the pixel regions 3101-3104.

FIG. 32 is a timing chart 1-1 when exposure time change occurs, and FIG. 33 is a timing chart 1-2 when exposure time change occurs. 32 and 33 are timing charts in the example of FIG.

In FIGS. 32 and 33, 1/2 frame exposure is started for frame Fi, and if there is a change to 1 frame exposure after that, it is changed to 1 frame exposure at frame F (i+3) after 3 frames from frame Fi. indicates that

FIG. 34 is a timing chart 2-1 when exposure time change occurs, and FIG. 35 is a timing chart 2-2 when exposure time change occurs. 34 and 35 are timing charts in the example of FIG.

In FIGS. 34 and 35, 1/2 frame exposure is started for frame Fi, and if there is a change to 1 frame exposure after that, it is changed to 1 frame exposure at frame F(i+2) two frames after frame Fi. indicates that After frame F(i+2), when one frame exposure continues, only the forced reset is driven.

FIG. 36 is a timing chart 3-1 when the exposure time is changed, FIG. 37 is a timing chart 3-2 when the exposure time is changed, and FIG. 38 is a timing chart when the exposure time is changed. FIG. 3 is a timing chart 3-3 in the case of FIG. 36 to 38 are timing charts in the case of driving the forced reset as shown in FIG. 30 and changing from 1-frame exposure to 1/2-frame exposure.

For 1-frame exposure, forced resets 0 to 3 are driven every N frames. When frame N is changed to 1/2 frame exposure, reset 1 of 1/2 frame exposure is driven for frame F(i+2) after the calculation of the exposure value for frame N is completed. After that, reset 2 of 1/2 frame exposure is driven at the same timing also for frame F(i+3). In FIG. 38, a forced reset and a half-frame exposure reset are driven within one frame. It is not reflected by reset driving, and the exposure time becomes 1/2 frame exposure.

<Reading of exposure value to the outside of second semiconductor substrate 120>
Next, reading of the exposure value to the outside of the second semiconductor substrate 120 will be described. There are two methods for reading the exposure value to the outside of the second semiconductor substrate 120, in addition to the method of outputting from the shift register shown in FIGS.

One method is to read the exposure value through a different path from the pixel signals for one pixel block of 200 (hereinafter referred to as an image signal) and output it as a header of the image signal, which will be described with reference to FIG. The other method is to read the exposure value together with the digital pixel signal via the horizontal transfer line and output it to the outside of the second semiconductor substrate 120 together with the image signal, which will be described with reference to FIG.

FIG. 39 is an explanatory diagram showing Method 1 for reading exposure values to the outside of the second semiconductor substrate 120. As shown in FIG. Horizontal transfer line 3900 is, for example, a 16-bit transfer line and connects each control block 400A and digital signal processing circuit 2701 . A data line 3901 connects the pixel control section 401 of each control block 400A and the digital signal processing circuit 2701 .

A digital pixel signal for each pixel 201 from the signal processing unit 402 of each control block 400A is output to the digital signal processing circuit 2701 through the horizontal transfer line 3900 . Reading of the exposure value is a different path from the horizontal transfer line 3900 . Therefore, the signal line 4100 can output the exposure value at a frequency lower than that of the horizontal transfer line 3900. FIG.

The digital signal processing circuit 2701 gives the exposure value from the signal line 4100 as a header (or footer) of the image signal, and outputs image data including the header and the image signal to the data processing unit 103 . According to the configuration of FIG. 39, the amount of image data to be transmitted to the data processing unit 103 is reduced compared to the case of FIG. 41, which will be described later.

FIG. 40 is an explanatory diagram showing Method 2 for reading exposure values to the outside of the second semiconductor substrate 120. As shown in FIG. The horizontal transfer line 3900 is, for example, a 16-bit transfer line and connects each control block 400 and the digital signal processing circuit 2701 . A digital pixel signal for each pixel 201 from the signal processing unit 402 of each control block 400 is output to the digital signal processing circuit 2701 through the horizontal transfer line 3900 . The exposure value from the pixel control section 401 of each control block 400 is output to the outside of the second semiconductor substrate 120 through the horizontal transfer line 3900 at the same timing as the corresponding digital pixel signal.

The digital signal processing circuit 2701 is connected to the data processing section 103 of the third semiconductor substrate 130 via the output IF 2703 . The digital signal processing circuit 2701 embeds the exposure value from the pixel control unit 401 of the same control block 400 in the image signal from the signal processing unit 402 and outputs the image signal to the data processing unit 103 . For example, if the digital pixel signal for one pixel is 12 bits and the exposure value is 4 bits, it is output to the outside of the second semiconductor substrate 120 as a 16-bit digital pixel signal.

In this way, since the exposure value is included in part of the digital pixel signal for one pixel, the data processing unit 103 can easily correct the exposure time for each pixel.

39 and 40, in the case of the control block 400B, instead of the signal processing unit 402, a signal processing unit 1602 outside the control circuit unit 210 is connected to the horizontal transfer line 3900, and the pixel from the signal processing unit 1602 is connected. A digital pixel signal for each 201 is output to the digital signal processing circuit 2701 through the horizontal transfer line 3900 .

<Speeding Up Autonomous Exposure Control Inside Control Block 400 and Increasing Accuracy of Exposure Control by Switching Exposure Values Inside and Outside Control Block 400>
Next, another example of the autonomous exposure control shown in FIG. 23 will be explained using FIGS. 41 to 51. FIG. 41 to 51, high-speed autonomous exposure control within the control block 400 and exposure control by switching the exposure value inside and outside the control block 400 are realized. First, speeding up of the autonomous exposure control inside the control block 400 will be described with reference to FIGS. 41 to 47. FIG. 41 to 47, the control block 400A will be described as an example, but the control block 400B also has the same configuration as that of the signal processing unit 402, so that the signal processing unit 1602 may have the same configuration. Implementable.

[Acceleration of autonomous exposure control inside control block 400]
FIG. 41 is a block diagram showing Example 1 of increasing the speed of autonomous exposure control inside the control block 400A. The control block 400A has n ADCs 500 and an SRAM 4100 that is an example of the signal output section 423 . In FIG. 41, one ADC 500 is used for simplification of explanation.

In this example, the pixel signal for each pixel 201 digitally converted by the ADC 500 is assumed to be a 13-bit digital pixel signal. This digital pixel signal is held in the SRAM 4100 and is output to the peripheral circuit section 121 via the column selection circuit 2301 and horizontal transfer line 2300 as shown in FIG. Also, the upper 4-bit signal of the 13-bit digital pixel signal is output to the autonomous exposure processing unit 4101 .

The autonomous exposure processing section 4101 is connected to a selector 4103 within the exposure control section 412 . The exposure control unit 412 also has a shift register 4102 and a selector 4103 in addition to the pixel block control unit 503 , the level shift unit 504 and the latch circuit 2321 . The shift register 4102 holds set exposure values.

The selector 4103 is connected to the shift register 4102 and the autonomous exposure processing section 4101 on the input side, and is connected to the latch circuit 2321 on the output side. A selector 4103 selects one of the set exposure value from the shift register 4102 and the exposure value from the autonomous exposure processing unit 4101 based on the selection signal. The selection signal is a signal for selecting either the set exposure value or the exposure value from the autonomous exposure processing unit 4101 . A selection signal is input to the selector 4103 from the external system described above. The exposure value selected by selector 4103 is output to latch circuit 2321 .

FIG. 42 is an explanatory diagram showing an example of a counter latch in Example 1 of increasing the speed of autonomous exposure control inside the control block 400A. A counter latch (storage unit) 502 holds a 13-bit digital pixel signal and outputs it to the SRAM 4100 . In FIG. 42, "x" indicates "0" or "1". The hatched high-order 4-bit digital signal is output to the autonomous exposure processing section 4101 via the SRAM 4100 .

FIG. 43 is an explanatory diagram showing a specific example of autonomous exposure control in speeding up example 1 of autonomous exposure control inside the control block 400A. An autonomous exposure processing unit 4101 holds a lookup table 4300 . The lookup table 4300 is a table in which the upper 4 bits 4301 and the exposure time 4302 are associated with each other. For convenience, the range of possible values of the 13-bit digital pixel signal that associates the upper 4 bits 4301 with the exposure time 4302 is described.

When the upper 4-bit signal is input from the SRAM 4100 , the autonomous exposure processing section 4101 refers to the lookup table 4300 to identify the upper 4 bits 4301 and reads out the corresponding exposure time 4302 . The autonomous exposure processing unit 4101 outputs a 4-bit signal indicating the read exposure time 4302 to the selector 4103 .

The shift register 4102 has a setting value table 4310 in which setting values 4311 and exposure times 4312 are associated with each other. The shift register 4102 outputs a set value 4311 that matches the 4-bit input set value from the external system or a set value 4311 that corresponds to the exposure time 4312 that matches the input exposure time to the selector 4103 as the set exposure value. .

Since it is important whether the pixels 201 are saturated or not, a counter latch (hereinafter referred to as the counter latch 502), which is an example of the storage unit 502, must output all 13 bits of the digital pixel signal to the autonomous exposure processing unit 4101. no. Also, since the lower 9 bits contain noise, it does not matter whether the pixel 201 is saturated or not. Therefore, the autonomous exposure processing unit 4101 refers to the lookup table 4300 and specifies the exposure time 4302 with the high-order 4-bit signal. As a result, the processing speed of the autonomous exposure processing unit 4101 can be increased.

Next, Example 2 of increasing the speed of the autonomous exposure control inside the control block 400A will be described. In example 2 of increasing the speed of autonomous exposure control inside the control block 400A, the high-order bit of the digital pixel signal is used to select one of the exposure value output last time, the one step increase, and the one step decrease. , is an example of determining the exposure value. The block configuration is the same as that of FIG. 41, so it is omitted.

FIG. 44 is an explanatory diagram showing an example of the counter latch 502 in Example 2 of speeding up the autonomous exposure control inside the control block 400A. In the application example 2, the counter latch 502 outputs the hatched high-order 3-bit digital signal to the autonomous exposure processing unit 4101 via the SRAM 4100 .

FIG. 45 is an explanatory diagram showing a specific example of autonomous exposure control in speed-up example 2 of autonomous exposure control inside the control block 400A. The autonomous exposure processing unit 4101 holds a lookup table 4500 . A lookup table 4500 is a table in which upper 3 bits 4501 and actions 4502 are associated with each other. For the sake of convenience, the range of possible values of the 13-bit digital pixel signal that associates the upper 3 bits 4501 with the treatment 4502 is described.

The autonomous exposure processing unit 4101 sets the value "001" (corresponding to "keep" of the action 4502) of the upper 3 bits 4501 of the lookup table 4500 as a reference value. Also, the autonomous exposure processing unit 4101 holds the setting value 4311 of the shift register for the first time, and the set value (previous output value) output from the selector 4103 in the previous frame after the second time.

When the high-order 3-bit signal is input from the SRAM 4100, the autonomous exposure processing section 4101 refers to the lookup table 4500 to identify the high-order 3 bits 4501, and reads out the corresponding action 4502. The autonomous exposure processing unit 4101 updates the previous output value with the read action 4502 .

Here, the previous output value is assumed to be "0011". If the upper 3 bits 4501 are "000", the action 4502 is "1 step up". In this case, the autonomous exposure processing unit 4101 increases the previous output value “0011” by one step to update it to “0100”, and outputs the updated setting value “0100” to the selector 4103 .

Also, if the upper 3 bits 4501 are "001", the action 4502 is "keep", that is, to maintain the status quo. In this case, the autonomous exposure processing unit 4101 outputs the previous output value “0011” to the selector 4103 . Also, if the upper 3 bits 4501 are, for example, "011", the action 4502 is "1 stage down". In this case, the autonomous exposure processing unit 4101 lowers the previous output value “0011” by one step to update it to “0010”, and outputs the updated setting value “0010” to the selector 4103 .

As in Application Example 1, it is important whether the pixel 201 is saturated or not, so the counter latch 502 need not output all 13 bits of the digital pixel signal to the autonomous exposure processing section 4101 . Also, since the lower 10 bits contain noise, it does not matter whether the pixel 201 is saturated or not.

Therefore, the autonomous exposure processing unit 4101 refers to the lookup table 4500 and executes the action 4502 of the exposure time 4302 with the upper 3-bit signal. As a result, the processing speed of the autonomous exposure processing unit 4101 can be increased.

In utilization example 2, the autonomous exposure processing unit 4101 executes the action 4502 of increasing or decreasing the exposure time 4312 by one step, so that the number of high-order bits to be handled is sufficient with 3 bits instead of 4 bits. Therefore, the transmission bit width from the counter latch 502 to the autonomous exposure processing unit 4101 can be reduced as compared with the first utilization example.

Also, the lookup table 4500 is an example, and the ranges of 1 step up, keep, and 1 step down may be expanded or reduced. Also, for example, the treatment 4502 of "1xx" of the upper 3 bits 4501 may be set to "2-step down". Also, any one of the values of action 4502 "one step up", "one step down" and "keep" may be excluded.

Next, Example 3 of increasing the speed of the autonomous exposure control inside the control block 400A will be described. In speed-up example 3 of autonomous exposure control inside control block 400A, unlike speed-up examples 1 and 2 described above, analog pixel signals from signal line 202 are output to autonomous exposure processing unit 4101 to perform autonomous exposure. It is an example of executing control.

FIG. 46 is a block diagram showing Example 3 of increasing the speed of autonomous exposure control inside the control block 400A. The autonomous exposure processing unit 4101 is connected to the signal line 202 of each pixel column of the pixel block 200 . The autonomous exposure processing section 4101 has a comparator 4601 , a 1-bit latch 4602 and a down counter 4603 .

FIG. 47 is a circuit diagram showing an example of comparator 4601. Referring to FIG. A comparator 4601 is a so-called CMOS inverter, and compares the voltage of the analog pixel signal with a voltage threshold. The smaller the charge accumulated in the photoelectric conversion unit 300, the higher the potential of the analog pixel signal flowing through the signal line 202 from the pixel 201 to the comparator 4601. When the voltage of the analog pixel signal exceeds the threshold voltage, the comparator 4601 outputs “0” to the 1-bit latch 4602 . The 1-bit latch 4602 holds "0".

As the charge accumulated in the photoelectric conversion unit 300 increases, the potential of the analog pixel signal from the pixel 201 flowing through the signal line 202 to the comparator 4601 becomes lower. When the voltage of the analog pixel signal becomes equal to or lower than the threshold voltage, the comparator 4601 outputs "1" to the 1-bit latch 4602 . The 1-bit latch 4602 holds “1” and outputs it to the down counter 4603 .

Returning to FIG. 46, down counter 4603 does not output a signal to selector 4103 until a 1-bit signal indicating “1” is input from 1-bit latch 4602 . As a result, the selector 4103 selects the set exposure value in the shift register 4102 and outputs it to the latch circuit 2321 . On the other hand, when the 1-bit signal indicating "1" is input from the 1-bit latch 4602, the down counter 4603 decreases the set value 4311, which is the set exposure value of the shift register 4102, by one step. For example, when the set exposure value is "0111" of the set value 4311, the shift register 4102 lowers "0111" by one step and outputs "0110" to the selector 4103 as the set exposure value. The selector 4103 selects the updated set value “0110” and outputs it to the latch circuit 2321 .

According to the utilization example of the signal line 202, the saturation of the pixel 201 is detected using the analog pixel signal before digital conversion, and the exposure time is autonomously shortened. Therefore, the autonomous exposure control is performed using the digital pixel signal. It is possible to speed up the processing as compared with the case.

Further, when a 1-bit signal of “0” is input to the 1-bit latch 4602 continuously a plurality of times, the 1-bit latch 4602 may output a 1-bit signal indicating “1” to the down counter 4603 . In this case, since the pixel 201 continues to be dark, the down counter 4603 may perform control to increase the set exposure value by one step.

[Exposure control by switching exposure values inside and outside control block 400]
Next, exposure control by switching exposure values inside and outside the control block 400 will be described with reference to FIGS. 48 to 51. FIG. Exposure control by switching exposure values in and out of control block 400 is performed by an external system.

FIG. 48 is an explanatory diagram showing an exposure control example 1 by switching the exposure values inside and outside the second semiconductor substrate 120 . Exposure control example 1 aims to improve the accuracy of exposure precision by reducing the exposure time difference (step) between adjacent pixel blocks 200 . An external system creates an exposure table 4810 for image data 4800 obtained from the pixel unit 101 . The exposure table 4810 is a table in which the TV value for each pixel block 200 is calculated. A TV value indicates the exposure time set for the pixel block 200 .

The external system detects a difference in TV value at a boundary composed of one or more pixel blocks arranged in the column direction (pixel block column) or one or more pixel blocks arranged in the row direction (pixel block row). Identify locations that exceed the threshold. For example, in an image region 4801 including a filament that emits light and its black background, like the image data 4800, the step of the TV value is equal to or greater than the threshold at the boundary, and noise increases.

For this reason, the external system identifies the pixel block columns or pixel block rows at the boundary and updates them so that the step of the TV value does not exceed the threshold. In FIG. 48, since the difference between the TV value of the second pixel block column 4812 from the left in the exposure table 4810 and the TV value of the third pixel block column 4813 is greater than or equal to the threshold value, the pixel block column 4812 and the pixel block column 4813 are the boundaries. Then, the TV value of the third pixel block column 4813 from the left is updated. For example, the external system averages the TV value of each pixel block column 4812 from the left and the TV value of each pixel block column 4814 from the left (fractions may be rounded down or rounded up). ) is set to the TV value of the pixel block column 4813 which is the third column from the left.

Note that the external system calculates the average value of the TV values of the first pixel block row 4811 from the left and the TV values of the third pixel block row 4813 from the left (fractions may be rounded down or rounded up). ) may be set to the TV value of the second pixel block column 4812 from the left.

The external system writes the updated TV value to the shift register 4102 as the set exposure value for the control block 400 in charge of the pixel block 200 with the updated TV value, and selects the selection signal for selecting the set exposure value from the shift register 4102. Output to 4103. As a result, it is possible to obtain image data with reduced noise at the boundary between light and dark.

FIG. 49 is an explanatory diagram showing an exposure control example 2 by switching the exposure values inside and outside the second semiconductor substrate 120 . Exposure control example 2 performs autonomous exposure control by the control block 400 when the phases of the emission frequency, movement frequency, or rotation frequency of a subject such as a light-emitting body, moving body, or rotating body do not match the sampling frequency of the imaging device 100. Stabilize exposure by switching from to exposure control by an external system.

If the emission frequency, movement frequency, or rotation frequency of the subject does not match the sampling frequency of the image sensor 100, the brightness of a certain pixel block 200 repeats brightness and darkness. Since the exposure value in the autonomous exposure processing unit is reflected with a delay of one frame, when the brightness of the pixel block 200 is “bright”, the exposure value is delayed by one frame and becomes a long-second exposure value. Overexposure occurs in the photographed image.

Also, when the luminance of the pixel block 200 is “dark”, the exposure value is set to a short-second exposure value with a delay of one frame, and the pixel block 200 causes blackout in the captured image. As described above, in the pixel block 200, the frequency of the subject and the phase of the exposure value do not match, so that blown-out highlights and blocked-up shadows alternately appear and continue to oscillate.

In such a case, the external system detects the repetition number or repetition time of blown-out highlights and blocked-up shadows for each pixel block 200, and selects the set exposure value from the shift register 4102 for the pixel block 200 in which oscillation is detected. A selection signal to select is output to the selector 4103 . Oscillation of blown-out highlights and blocked-up shadows is thereby avoided, and the exposure of the pixel block 200 is stabilized. After the exposure is stabilized, the external system may output a selection signal for selecting an exposure value from the autonomous exposure processing units 411 and 4101 to the selector 4103 .

FIG. 50 is an explanatory diagram showing Example 3 of exposure control by switching exposure values inside and outside the control block 400. In FIG. Exposure control example 3 optimizes exposure by setting for each pixel block 200 whether to apply autonomous exposure control in the control block 400 or exposure control by an external system.

The external system outputs a selection signal for selecting the exposure value obtained by the autonomous exposure processing unit 411 to the selector 4103 for the pixel block 200 (hereinafter referred to as the first pixel block 5001) in which the number of defective pixels is equal to or less than the allowable number. do. On the other hand, the external system receives a pixel block 200 (hereinafter referred to as a second pixel block 5002) in which the number of defective pixels is not less than the allowable number or a pixel block 200 (hereinafter referred to as a third pixel block 5003) including AF pixels that are partially shaded. ), a selection signal for selecting the set exposure value from the shift register 4102 is output to the selector 4103 .

Note that for a pixel block 200 in which a defective pixel is later identified after shipment and the first pixel block 5001 is changed to the second pixel block 5002, the external system controls the selector of the control block 400 in charge of the pixel block 200. 4103, a selection signal for selecting the set exposure value from the shift register 4102 is output.

For the second pixel block 5002 and the third pixel block 5003 whose number of defective pixels is known at the time of shipment, offset data is set in the autonomous exposure processing section 411 of the control block 400 . For the pixel block 200 provided with the offset data, the external system outputs a selection signal for selecting the exposure value obtained by the autonomous exposure processing section 411 to the selector 4103 .

Here, the offset data is a parameter for correcting the exposure value in the pixel block 200, and in the case of the second pixel block 5002, it is the position of the defective pixel. Thereby, the autonomous exposure processing unit 411 can exclude defective pixels in the preprocessing unit and calculate the maximum value or average value of the digital pixel signals.

In the case of the third pixel block 5003, the offset data are the positions and weights of AF pixels. Since a part of the light receiving area of the AF pixel is shielded from light, if the light shielding area is half of the original light receiving area of the AF pixel, the digital pixel signal from the AF pixel must be doubled. is.

Similarly, if the light-shielding area is ⅓ of the original light-receiving area of the AF pixel, the weight is 3 because the digital pixel signal from the AF pixel needs to be tripled. Thus, the weight is the light-receiving area of the pixel 201/the light-shielding area of the AF pixel. Also, for the third pixel block 5003 as well as for the second pixel block 5002, the offset data may be the position of the AF pixel. Then, the autonomous exposure processing unit 411 may exclude the AF pixels in the preprocessing unit 2311 and calculate the maximum value or average value of the digital pixel signals.

Note that for a pixel block 200 in which a defective pixel is later identified after shipment and the first pixel block 5001 is changed to the second pixel block 5002, the external system controls the control block 400 in charge of the pixel block 200. Offset data for defective pixels may be set in the exposure processing unit 411 .

In this way, it is possible to set which of the autonomous exposure control in the control block 400 and the exposure control by the external system is applied according to the degree of pixel loss in the pixel block 200, and to optimize the exposure for each pixel block 200. can be achieved.

<Method of reading exposure value for each control block 400>
Next, a method of reading the exposure value for each control block 400 will be described. When an image is generated by outputting the exposure value of each pixel block 200 to an external system, the external system outside the image sensor 100 generates a digital image of each pixel 201 of the pixel block 200 based on the exposure value of each pixel block 200. You need to demodulate (gain) the signal. In this case, the image pickup device 100 sets additional information including an image block ID and an exposure value to the digital image signal of each pixel 201 from the pixel block 200 (hereinafter referred to as the image signal of the pixel block 200), and sends it to the external system. will output.

When additional information is set in the image signal of the pixel block 200, the amount of data to be transmitted to the external system increases by the amount of additional information set, resulting in a decrease in communication speed and an increase in power consumption. In addition, as the size of the pixel block 200 becomes smaller (as the number of pixels in one pixel block 200 decreases) due to finer exposure control, the influence of a decrease in communication speed and an increase in power consumption increases. A method of reading an exposure value for each control block 400 for suppressing a decrease in communication speed and an increase in power consumption will be described below.

FIG. 51 is an explanatory diagram showing Example 1 of exposure value reading for each control block 400 . The pixel section 101 of the first semiconductor substrate 110 has an effective pixel area 5111 for receiving subject light and an optical black pixel area 5112 formed around the effective pixel area 5111 . The effective pixel area 5111 is composed of the plurality of pixel blocks 200 described above.

An optical black pixel region 5112 is a set of optical black pixels. An optical black pixel is a pixel 201 in which a light-receiving region in which the photoelectric conversion unit 300 can receive light is shielded. Since light does not enter the optical black pixels, the exposure time of the optical black pixels is uniquely determined by the incident time without depending on the amount of incident light. Also, the optical black pixel area 5112 is composed of a plurality of pixel blocks 200 like the effective pixel area 5111 . A pixel block 200 within the optical black pixel area 5112 is referred to as an OB pixel block 5120 .

The shift register 4102 of the exposure control unit 412 of the control block 400 (hereinafter referred to as the OB control block 5140) corresponding to one or more OB pixel blocks 5120 out of all the OB pixel blocks 5120 stores exposure time as a set exposure value. (For example, one of 1 ms, 2 ms, 4 ms, . . . , 100 ms) is set. OB control block 5140 is communicatively connected to control block 400 .

One or more reference pixels 5101 are provided in at least one pixel block 200 among all pixel blocks 200 in the effective pixel area 5111 . A reference pixel 5101 is a pixel 201 in which a light-receiving region capable of receiving light by the photoelectric conversion unit 300 is shielded, similarly to the optical black pixel. Since the reference pixel 5101 does not receive light as in the case of the optical black pixel, the exposure time of the optical black pixel is uniquely determined by the incident time without depending on the amount of incident light.

In pixel block 200 , each pixel 201 outputs a pixel signal to control block 400 . A preprocessing unit 2311 of the control block 400 calculates a statistical value (for example, an average value, a median value, a maximum value, or a minimum value; referred to as a reference pixel preprocessing result) of the pixel signal of the reference pixel 5101, and calculates an exposure value. Output to the calculation unit 2313 .

In each OB pixel block 5120 , each optical black pixel also outputs a pixel signal to OB control block 5140 . The preprocessing unit 2311 of each OB control block 5140 calculates a statistical value of the pixel signal of each optical black pixel (hereinafter referred to as black pixel preprocessing result).

The exposure value calculation unit 2313 of the control block 400 acquires the black pixel preprocessing result by the preprocessing unit 2311 of each OB control block 5140 . Then, the exposure value calculation unit 2313 of the control block 400 compares the reference pixel calculation result and each black pixel preprocessing result. The exposure value calculator 2313 of the control block 400 identifies the black pixel preprocessing result with the smallest difference from the reference pixel calculation result.

Then, the exposure value calculation unit 2313 of the control block 400 acquires the exposure value held by the OB control block 5140 from which the specified black pixel preprocessing result is calculated. The exposure value calculator 2313 of the control block 400 outputs the acquired exposure value to the exposure controller 412 .

Thus, by comparing the pixel signals from the reference pixel 5101 and the optical black pixel for each control block 400, it is possible to read the exposure value that is uniquely determined by the incident time without depending on the amount of incident light. . Also, the control block 400 includes the read exposure value in the digital pixel signal of each pixel 201 in the corresponding pixel block 200 and outputs the digital pixel signal to the external system. As a result, a decrease in communication speed and an increase in power consumption can be suppressed.

In addition, by arranging a plurality of reference pixels 5101 in one pixel block 200, even if the reference pixel 5101 has a pixel defect, it can be complemented with another reference pixel 5101. FIG. Also, the plurality of reference pixels 5101 may be arranged in different rows or different columns. This makes it possible to avoid pixel defects in the plurality of reference pixels 5101 arranged in the same row or the same column due to line defects in the pixel block 200 . Also, the plurality of reference pixels 5101 may be spaced apart. As a result, the reference pixel 5101 can be complemented with the digital pixel signals of its surrounding pixels.

FIG. 52 is an explanatory diagram showing Example 2 of reading the exposure value for each control block 400. As shown in FIG. Reading example 2 is an example in which the exposure value is read by the control block 400, unlike reading example 1 shown in FIG.

Pixel block 200 has one or more reference pixels 5202 . When a plurality of reference pixels 5202 are arranged, different exposure values (for example, Tv0 to Tv8) are set for each reference pixel 5202 . Reading example 2 is an example in which the exposure value of the pixel region 5200 excluding the reference pixel 5202 in the pixel block 200 is determined by the exposure value obtained for the reference pixel 5202 . Note that the reference pixel 5202 is not shielded from light unlike the reference pixel 5101 shown in FIG.

In the control block 400 , the autonomous exposure processing unit 411 acquires the digital pixel signal values S 0 to S 8 from the reference pixel 5202 and the digital pixel signal value SP of the target pixel region 5200 . The value SP of the digital pixel signal of the target pixel region 5200 is, for example, the statistical value of the digital pixel signals of all the pixels 201 within the target pixel region 5200 excluding the reference pixel 5202 .

FIG. 53 is a block diagram showing a detailed block configuration example of the control block 400 in Example 2 of reading the exposure value for each control block 400. As shown in FIG. In FIG. 53, the control block 400A will be described as an example, but the control block 400B can also be implemented in the control block 400B because a configuration similar to that of the signal processing section 402 can be placed in the signal processing section 1602. The control block 400A includes a signal processing unit 402 (a signal input unit 421, a signal conversion unit 422, and a signal output unit 423), an autonomous exposure processing unit 411, an exposure control unit 412, a pixel driving unit 413, and a setting unit. It has a part 5300 .

The setting unit 5300 generates and outputs a reset signal (TX2) for starting exposure at different reset timings for each of the reference pixels 5202 . Each of the reference pixels 5202 starts (or ends) exposure (accumulation in the photoelectric conversion unit 300) at the timing when the reset signal from the setting unit 5300 is input.

The autonomous exposure processing unit 411 specifies the value of the digital pixel signal of the reference pixel 5202 having the smallest difference from the value SP of the digital pixel signal of the target pixel region 5200 from S0 to S8. The autonomous exposure processing unit 411 sets the exposure value (for example, Tv0 to Tv8) set in the reference pixel 5202 that outputs the digital pixel signal of the specified value as the exposure value of the target pixel region 5200 .

Each pixel 201 in the target pixel region 5200 starts reset driving, for example exposure, according to the exposure value set by the autonomous exposure processing unit 411 as described above.

By reading the exposure value for each control block 400 in this way, the exposure value can be included in the digital pixel signal of each pixel 201 in the corresponding pixel block 200 and output to an external system. Therefore, a decrease in communication speed and an increase in power consumption can be suppressed.

Also, a plurality of reference pixels 5202 set to the same exposure value may be arranged in one pixel block 200 . As a result, even if the reference pixel 5202 has a pixel defect, it can be stored with another reference pixel 5202 . Also, multiple reference pixels 5202 may be arranged in different rows or different columns. This makes it possible to avoid pixel defects in a plurality of reference pixels 5202 arranged in the same row or the same column due to line defects in the pixel block 200 .

<Reduction of Color Misregistration in Autonomous Exposure Control for Each Control Block 400>
In the image pickup device 100, if the color of any one of the R pixels, G pixels, and B pixels is saturated, a color shift occurs when color imaging processing is performed after demosaicing. For example, even if the average value of the digital pixel signals of all the pixels 201 in the pixel block 200 is not saturated, the average value of any one of RGB single colors may be saturated. On the other hand, if saturation is detected separately for RGB single colors, the circuit size increases.

The imaging device 100 performs autonomous exposure control for each pixel block 200, but it is necessary to avoid image quality problems such as color shift. Here, an example of color shift reduction by the image sensor 100 that sets an appropriate exposure time so that each pixel block 200 does not saturate RGB colors will be described.

[Example 1 of reducing color misregistration]
FIG. 54 is a block diagram showing an internal configuration example of the preprocessing unit 2311 in example 1 of reducing color misregistration. The preprocessing section 2311 has a comparator 5401 and a latch circuit 5402 . The comparator 5401 compares the digital pixel signal from the pixel block 200 (hereinafter referred to as first pixel signal) and the digital pixel signal latched by the latch circuit 5402 (hereinafter referred to as second pixel signal).

The comparator 5401 compares the first pixel signal and the second pixel signal and outputs the pixel signal with the larger value to the latch circuit 5402 .

After the reset pulse from the controller 2312 resets the inside of the latch circuit 5402 , the overwrite storage of the digital pixel signal from the comparator 5401 is started. Before the input of the next reset pulse, the latch circuit 5402 receives a timing signal from the controller 2312 when all digital pixel signals for 200 pixels in one pixel block are input, and finally exposes the held digital pixel signals. Output to the value calculator 2313 .

The digital pixel signal output to the exposure value calculator 2313 is a digital pixel signal that takes the maximum value in the pixel block 200 for each frame. Thereby, the control block 400 can calculate an appropriate exposure value for the pixel block 200 in charge so that each color of RGB is not saturated for each frame. Therefore, color deviation in output image data from the imaging device 100 can be suppressed for each pixel block 200 .

[Color shift reduction example 2]
Color shift reduction example 2 is an example in which one or more white pixels are arranged in the pixel block 200 . A white pixel is a pixel 201 that has a transparent filter instead of a color filter 703 .

FIG. 55 is an explanatory diagram showing an example of a pixel block 200 in Example 2 of reducing color misregistration. In FIG. 55, R in the pixel 201 indicates an R (red) pixel, B indicates a B (blue) pixel, Ga and Gb indicate a G (green) pixel, and W indicates a white pixel. A pixel 201 whose left half is black is an AF pixel. Since the alphabet in the AF pixel is W, that pixel 201 is both an AF pixel and a white pixel. There are also pixel blocks 200 with no AF pixels.

The preprocessing unit 2311 discards the digital pixel signals of R pixels, B pixels, Ga pixels, and Gb pixels. When only one white pixel is arranged in the pixel block 200 , the preprocessing section 2311 outputs the digital pixel signal of the white pixel to the exposure value calculation section 2313 . When two or more white pixels are arranged in the pixel block 200 , the preprocessing unit 2311 calculates the maximum value or average value of the digital pixel signal values of the two or more white pixels, and outputs it to the exposure value calculation unit 2313 . do.

Since white pixels are not affected by color like R, B, Ga, and Gb pixels, the digital pixel signal of the white pixels is used for exposure control, thereby suppressing the saturation of the pixel block 200 with single RGB colors. can do.

Further, when AF pixels are included in the pixel block 200, by using the AF pixels also as white pixels, it is possible to reduce the number of replacements of RGB pixels with white pixels. Also, in the pixel block 200, a plurality of white pixels may be arranged discretely. Also in this case, the plurality of white pixels may be arranged in different rows or different columns. Thereby, it is possible to avoid pixel defects of a plurality of white pixels arranged in the same row or the same column due to a line defect in the pixel block 200 . Also, the plurality of white pixels may be spaced apart. This allows the white pixel to be complemented with the digital pixel signals of its surrounding pixels.

Also, the plurality of white pixels may be the pixels 201 whose sensitivity is adjusted in multiple steps. Specifically, for example, an ND filter or light shielding metal may be used for white pixels. If the sensitivity is adjusted with a light shielding metal, it may be set to the AF pixel. In this case, the width of the light shielding metal in the row direction may be set wider as the principal ray angle of the lens increases. This improves the phase difference detection accuracy of the AF pixels.

[Example 3 of reducing color misregistration]
Since the defective pixels in the pixel block 200 are saturated, the exposure time is set short when the preprocessing unit 2311 performs preprocessing using the digital pixel signals of the defective pixels. Therefore, in example 3 of reducing color misregistration, an example in which the preprocessing unit 2311 removes digital pixel signals of defective pixels will be described.

FIG. 56 is a block diagram showing an internal configuration example of the preprocessing unit 2311 in example 3 of reducing color misregistration. Assuming that the number of defective pixels assumed at the time of shipment is d (d is an integer equal to or greater than 1), the preprocessing unit 2311 serially connects (d+1) data holding units that hold digital pixel signals of defective pixels. FIG. 56 shows an example in which d=2, and has three stages of data holding units 5601, 5602, and 5603. FIG.

Data holding units 5601 , 5602 and 5603 have comparators 5611 , 5621 and 5631 and latch circuits 5612 , 5622 and 5632 .

In the data holding unit 5601, a comparator 5611 stores a digital pixel signal (hereinafter referred to as a first pixel signal) from the pixel block 200 and a signal latched by a latch circuit 5612 without distinguishing between R, G, and B pixels. A digital pixel signal (hereinafter referred to as a second pixel signal) is input.

The comparator 5611 compares the first pixel signal and the second pixel signal, and outputs the larger value of the pixel signal to the latch circuit 5612 . After the reset pulse from the controller 2312 resets the inside of the latch circuit 5612 , the overwrite storage of the digital pixel signal from the comparator 5611 is started. Before the input of the next reset pulse, the latch circuit 5402 receives a timing signal from the controller 2312 when all digital pixel signals for 200 pixels in one pixel block are input, and finally exposes the held digital pixel signals. Output to the value calculator 2313 .

That is, for a certain frame, when the digital pixel signals of all the pixels 201 in the pixel block 200 are input to the comparator 5611 as the first pixel signals, the digital pixel signal with the maximum value among the digital pixel signals of all the pixels 201 is It is held in latch circuit 5612 .

In the data holding portion 5602, the comparator 5621 and the latch circuit 5622 perform the same operations as the comparator 5611 and the latch circuit 5612 for the digital pixel signal not held in the latch circuit 5612.

As a result, when a digital pixel signal that is not held in the latch circuit 5612 in the pixel block 200 is input to the comparator 5621 as a first pixel signal for a certain frame, the digital pixel signal that is not held in the latch circuit 5612 is changed. Among them, the digital pixel signal with the maximum value is held in the latch circuit 5622 .

In the data holding unit 5603 as well, the comparator 5631 and the latch circuit 5632 perform the same operations as the comparator 5611 and the latch circuit 5612 for digital pixel signals not held by the latch circuits 5612 and 5622 .

As a result, when a digital pixel signal not held in the latch circuits 5612 and 5622 in the pixel block 200 is input to the comparator 5631 as a first pixel signal for a certain frame, the digital pixel signal is not held in the latch circuits 5612 and 5622. The digital pixel signal with the maximum value among the digital pixel signals is held in the latch circuit 5632 .

Among the digital pixel signal values of all the pixels 201 in the pixel block 200 for a certain frame, the maximum value is held in the latch circuit 5612, the second largest value is held in the latch circuit 5622, and the third largest value is held in the latch circuit 5622. It is held in latch circuit 5632 .

Therefore, when the preprocessing unit 2311 wants to output the maximum value excluding d (=2) defective pixels, it outputs the value of the digital pixel signal held in the latch circuit 5632 to the exposure value calculation unit 2313. .

Also, the output terminal of the comparator 5621 is switchably connected to the input/output terminal of the comparator 5631 and the average value calculation section 5600 via the switch 5610 . Switch 5610 is switch-controlled by controller 2312 . When the comparators 5621 and 5631 are connected by the switch 5610, the value of the digital pixel signal held in the latch circuit 5632 is output to the exposure value calculator 2313 as described above.

When the switch 5610 connects the comparator 5621 and the average value calculation section 5600, the average value calculation section 5600 calculates the average value of the digital pixel signals that are not held in the latch circuits 5612, 5622, and 5632, The calculated average value is output to the exposure value calculator 2313 .

As a result, preprocessing can be performed in consideration of the number of defective pixels d, and the digital pixel signals of the defective pixels can be removed. Therefore, color deviation in output image data from the imaging device 100 can be suppressed for each pixel block 200 .

[Example 4 of color shift reduction]
Color Misregistration Reduction Example 4 is a modification of Color Misregistration Reduction Example 3. FIG. In example 3 of reducing color shift, the circuit configuration of the preprocessing unit 2311 considers the number of defective pixels d at the time of shipment. This is a configuration example considering the number d.

FIG. 57 is a block diagram showing an internal configuration example of the imaging device 100 in example 4 of reducing color misregistration. In FIG. 57, control block 400a controls pixel block 200a, control block 400b controls pixel block 200b, and control block 400c controls pixel block 200c. The control blocks 400 a , 400 b , 400 c are communicatively connected on the second semiconductor substrate 120 .

The control blocks 400a, 400b and 400c respectively have autonomous exposure processing units 411a, 411b and 411c, exposure control units 412a, 412b and 412c, and storage units 5700a, 5700b and 5700c.

Here, it is assumed that the pixel blocks 200a and 200c have defective pixels equal to or less than the allowable number t (t is an integer equal to or greater than 0), and the pixel block 200b has defective pixels exceeding the allowable number. The allowable number t is a preset value. The storage units 5700a, 5700b and 5700c store the number of defective pixels of the pixel blocks 200a, 200b and 200c. The initial value of the number of defective pixels is a value at the time of shipment, and is set for each of the pixel blocks 200a, 200b, and 200c, but can be updated by calibration during use.

Since the pixel block 200b includes a number of defective pixels exceeding the allowable number t, the control block 400b does not calculate the exposure value from the digital pixel signal from the pixel block 200b, and either of the adjacent pixel blocks 200a, 200c acquires the exposure value calculated by the control block 400 of . For example, the control block 400b acquires the exposure value calculated by the control block 400 that controls the adjacent pixel block 200 with fewer defective pixels. In this way, by using the exposure values of the adjacent pixel blocks 200a and 200c whose number of defective pixels is equal to or less than the allowable number, it is possible to suppress the color fringing of the pixel block 200b.

Note that the adjacent pixel blocks 200 are the left and right pixel blocks 200a and 200c of the pixel block 200b in FIG. 57, but may include the upper and lower pixel blocks 200 (not shown). Alternatively, it may be an 8-pixel block surrounding the pixel block 200b.

Also, if the number of defective pixels in any of the adjacent pixel blocks 200 exceeds the allowable number t, the control block 400b selects the pixel block group that is the closest and has the allowable number t of defective pixels among the pixel blocks separated by two pixel blocks or more. The exposure value calculated by the control block 400 that controls the pixel block 200 described below may be acquired.

<Failure analysis of junction 610 between semiconductor substrates>
Next, defect analysis of bonding pads between semiconductor substrates will be described. As a method of avoiding the decrease in yield due to defective bonding of the junction 610 between the semiconductor substrates, there is a method of providing a plurality of junctions 610 for one signal path passing between the semiconductor substrates. However, it is difficult to detect whether each joint 610 is good or bad.

In this example, a control switch is provided for each junction 610 that joins the semiconductor substrates, and the failure analysis of the junction 610 between the semiconductor substrates is realized by switching the control switch to enable operation confirmation.

[Example of defect analysis of bonding pad 714 between semiconductor substrates in pixel drive signal line]
FIG. 58 is a circuit diagram showing an example of failure analysis of the bonding pad 714 between the semiconductor substrates in the pixel drive signal line. A plurality of pixels 201 in the row direction of the first semiconductor substrate 110 and the pixel drive section 413 of the second semiconductor substrate 120 are connected by pixel drive signal lines 5803 . A boundary surface 720 between the first semiconductor substrate 110 and the second semiconductor substrate 120 is provided with a plurality of bonding portions 610A and 610B.

Each of the joints 610A, 610B comprises a pair of joint pads 714a, 714b. Bond pads 714 a are provided on the first semiconductor substrate 110 and bond pads 714 b are provided on the second semiconductor substrate 120 . Pixel drive signal line 5803 has a signal path through junction 610A and a signal path through junction 610B.

A test circuit 5800 is provided between the two bonding pads 714 b and the pixel driver 413 on the second semiconductor substrate 120 . Test circuit 5800 has two switches 5801A and 5801B. Since the pixel control signal from the pixel driving section 413 has a large amplitude, the switches 5801A and 5801B are composed of CMOS switches. In addition, since the first semiconductor substrate 110 is constructed by a pixel-dedicated process using only NMOS, the switches 5801A and 5801B composed of CMOS switches are provided on the second semiconductor substrate 120. FIG.

The switch 5801A is provided between the pixel drive section 413 and the junction section 610A and is connected by the pixel drive signal line 5803 . The switch 5801B is provided between the pixel drive section 413 and the junction section 610B and connected by the pixel drive signal line 5803. FIG. Gate terminals of the switches 5801A and 5801B are connected to the pixel driving section 413 by switch control lines 5802, respectively.

When a control signal is input from the pixel drive section 413 to the gate terminal of the switch 5801A, the switch 5801A outputs the pixel drive signal from the pixel drive section 413 to the junction section 610A. When a control signal is input from the pixel drive section 413 to the gate terminal of the switch 5801B, the switch 5801B outputs the pixel drive signal from the pixel drive section 413 to the junction section 610B.

In the operation check before shipment, only the gate terminal of the switch 5801A out of the switches 5801A and 5801B is supplied with a control signal from the pixel driving section 413 through the switch control line 5802, and the pixel driving signal from the pixel driving section 413 is applied to the junction. It is checked whether it passes through 610A and reaches a plurality of pixels 201 in the row direction. Similarly, a control signal is applied only to the gate terminal of the switch 5801B from the pixel driving section 413 through the switch control line 5802, and the pixel driving signal from the pixel driving section 413 passes through the junction 610B to form a plurality of switches in the row direction. Check if the pixel 201 is reached.

If continuity is detected in at least one of the two signal paths passing through the junctions 610A and 610B of the pixel drive signal line 5803, it is determined that the junction between the pixel drive section 413 and the plurality of pixels 201 in the row direction is good. be.

[Example of defect analysis of bonding pad 714 between semiconductor substrates in signal line 202]
FIG. 59 is a circuit diagram showing a failure analysis example 1 of the bonding pad 714 between the semiconductor substrates in the signal line 202. As shown in FIG. The pixel 201 of the first semiconductor substrate 110 and the pixel driving section 413 of the second semiconductor substrate 120 are connected by the signal line 202 . The signal line 202 is shared by m pixels 201 in the column direction.

As in FIG. 58, a plurality of bonding portions 610A and 610B are provided on the interface 720 between the first semiconductor substrate 110 and the second semiconductor substrate 120. As shown in FIG. Each of the joints 610A, 610B comprises a pair of joint pads 714a, 714b. Bond pads 714 a are provided on the first semiconductor substrate 110 and bond pads 714 b are provided on the second semiconductor substrate 120 . Signal line 202 has a signal path through junction 610A and a signal path through junction 610B.

Test circuit 5800 is provided, for example, in signal input section 421 . Considering the symmetry of the pixel structure and the number of transistors, it is preferable to provide the test circuit 5800 on the second semiconductor substrate 120 . That is, when the test circuit 5800 is provided on the first semiconductor substrate 110, the layout of the pixel structure and the number of transistors between the pixel 201 closest to the second semiconductor substrate 120 and the other pixels 201 among the plurality of pixels 201 in the column direction are different. This is because the manufacturing yield is lowered due to the difference in the manufacturing yield.

The switch 5801A is provided between the pixel driving section 413 and the junction section 610A and connected by the signal line 202. FIG. The switch 5801B is provided between the pixel driving section 413 and the junction section 610B and connected by the signal line 202 . Gate terminals of the switches 5801A and 5801B are connected to the pixel driving section 413 by switch control lines 5802, respectively.

When a control signal is input from the pixel drive section 413 to the gate terminal of the switch 5801A, the switch 5801A outputs the analog pixel signal from the pixel 201 to the signal conversion section 422 via the junction 610A. When a control signal is input from the pixel drive section 413 to the gate terminal of the switch 5801B, the switch 5801B outputs the analog pixel signal from the pixel 201 to the signal conversion section 422 via the junction 610B.

In the operation check before shipment, only the gate terminal of the switch 5801A of the switches 5801A and 5801B is supplied with a control signal from the pixel driving section 413 through the switch control line 5802, and the analog pixel signal from the pixel 201 is applied to the junction section 610A. It is checked whether it passes through and reaches the signal converter 422 . Similarly, only the gate terminal of the switch 5801B is supplied with a control signal from the pixel drive section 413 through the switch control line 5802, and the analog pixel signal from the pixel 201 passes through the junction 610B and reaches the signal conversion section 422. Check whether

If continuity is detected in at least one of the two signal paths passing through the junctions 610A and 610B of the signal line 202, it is determined that the junction between the pixel 201 and the signal converter 422 is good.

FIG. 60 is a circuit diagram showing failure analysis example 2-1 of the bonding pad 714 between the semiconductor substrates in the signal line 202. As shown in FIG. In the failure analysis example 1 of FIG. 59, the test circuit 5800 is provided on the second semiconductor substrate 120, but in the failure analysis example 2-1 of FIG. This is effective when the circuit scale of the second semiconductor substrate 120 is increased. Specifically, for example, the first semiconductor substrate 110 has an FD shared pixel group 6000 . The FD shared pixel group 6000 shares the FD 303 and the pixel output unit 305 with a plurality of (four in FIG. 60) photoelectric conversion units 300 .

The pixel output section 305 has an amplifier section 351 and selection sections 352A and 352B, and constitutes a test circuit 5800. FIG. Selection units 352A and 352B serve as switches in test circuit 5800. FIG. The joint portion 610A connects between the selection portion 352A and the signal input portion 421 . The joint portion 610B connects between the selection portion 352B and the signal input portion 421 .

When the selection control signal φSEL is input to the gate terminal of the selection section 352A, the selection section 352A outputs analog pixel signals from the FD shared pixel group 6000 to the signal conversion section 422 via the junction section 610A. When the selection control signal φSEL is input to the gate terminal of the selection section 352B, the selection section 352B outputs analog pixel signals from the FD shared pixel group 6000 to the signal conversion section 422 via the junction 610B.

In the operation check before shipment, the selection control signal φSEL is applied only to the gate terminal of the selection section 352A of the selection sections 352A and 352B, and the analog pixel signal from the FD shared pixel group 6000 passes through the junction section 610A to the signal conversion section. Check if it reaches 422. Similarly, the selection control signal φSEL is applied only to the gate terminal of the selection section 352B, and it is confirmed whether the analog pixel signal from the FD shared pixel group 6000 reaches the signal conversion section 422 through the junction section 610B.

If continuity is detected in at least one of the two signal paths passing through the junctions 610A and 610B of the signal line 202, it is determined that the junction between the FD shared pixel group 6000 and the signal converter 422 is good.

FIG. 61 is a circuit diagram showing failure analysis example 2-2 of the bonding pad 714 between the semiconductor substrates in the signal line 202. As shown in FIG. In failure analysis example 2-1 in FIG. 60, the case of the FD shared pixel group 6000 has been described, but in failure analysis example 2-2 in FIG. In this case as well, if continuity is detected in at least one of the two signal paths passing through the junctions 610A and 610B of the signal line 202, it is determined that the junction between the pixel 201 and the signal converter 422 is good.

[Example of failure analysis of bonding pads between semiconductor substrates when signal paths are shared between multiple circuits]
FIG. 62 is a circuit diagram showing an example of failure analysis of bonding pads between semiconductor substrates when a signal path is shared between a plurality of circuits. FIG. 62 shows an example of failure analysis of bonding pads between semiconductor substrates 6200A and 6200B. If the semiconductor substrate 6200A is the first semiconductor substrate 110, the semiconductor substrate 6200B is the second semiconductor substrate 120, and if the semiconductor substrate 6200A is the second semiconductor substrate 120, the semiconductor substrate 6200B is the third semiconductor substrate .

The semiconductor substrate 6200A has circuits A1 and A2. If the semiconductor substrate 6200A is the first semiconductor substrate 110, the circuits A1 and A2 are the pixels 201, for example. If semiconductor substrate 6200A is second semiconductor substrate 120, circuits A1 and A2 are ADC 500, for example.

The semiconductor substrate 6200B has circuits B1 and B2. If semiconductor substrate 6200B is first semiconductor substrate 110, circuits B1 and B2 are ADC 500, for example. If the semiconductor substrate 6200B is the third semiconductor substrate 130, the circuits B1 and B2 are digital circuits in the data processing section 103, for example.

Bonding portions 6201P, 6201Q, 6202P, and 6202Q are provided on a boundary surface 6210 between the first semiconductor substrate 110 and the second semiconductor substrate 120 . Each of the joints 6201P, 6201Q, 6202P, 6202Q comprises a pair of joint pads 714a, 714b. Bond pads 714a are provided on semiconductor substrate 6200A, and bond pads 714b are provided on semiconductor substrate 6200B.

A test circuit 6220 is provided between the semiconductor substrates 6200A and 6200B with the interface 6210 therebetween. The test circuit 6220 consists of a first test circuit 6221 that performs defect analysis of the pair of bonding pads 714a and 714b between the circuits A1 and B1, and a second test circuit 6221 that performs defect analysis of the pair of bonding pads 714a and 714b between the circuits A2 and B2. It has a test circuit 6222 and a connection wiring 6223 that connects the first test circuit 6221 and the second test circuit 6222 .

The first test circuit 6221 includes switches SW1A1 and SW1B1 connected in series between circuits A1 and B1 via junction 6201P, and switches SW1A2 and SW1B2 connected in series via junction 6201Q between circuits A1 and B1. , are connected in parallel.

The second test circuit 6222 includes switches SW2A1 and SW2B1 connected in series through junction 6202P between circuits A2 and B2, and switches SW2A2 and SW2B2 connected in series through junction 6202Q between circuits A2 and B2. , are connected in parallel.

A connection wiring 6223 connects the switch SW1A2 of the first test circuit 6221 and the switch SW2A1 of the second test circuit 6222 on the semiconductor substrate 6200A, and connects the switch SW1B2 of the first test circuit 6221 and the switch SW1B2 of the second test circuit 6222 on the semiconductor substrate 6200B. It connects with the switch SW2B1.

In FIGS. 62 and 63, a route following circuit A1, switch SW1A1, junction 6201P, switch SW1B1, and circuit B1 is called a first wiring. A route following the circuit A1, the switch SW1A1, the junction 6201Q, the switch SW1B1, and the circuit B1 is called a second wiring. A route following the circuit A2, the switch SW2A1, the junction 6202P, the switch SW2B1, and the circuit B2 is called a third wiring. A route following the circuit A2, the switch SW2A2, the junction 6202Q, the switch SW2B2, and the circuit B2 is called a fourth wiring.

In the first test circuit 6221, the gates of the switches SW1A1 and SW1B1 are turned ON and the gates of the switches SW1A2 and SW1B2 are turned OFF to determine whether or not there is continuity between the circuits A1 and B1 of the first wiring. Failure analysis of section 6201P is performed.

Similarly, by turning ON the gates of the switches SW1A2 and SW1B2 and turning OFF the gates of the switches SW1A1 and SW1B1, the defect of the junction 6201Q as to whether or not there is continuity between the circuits A1 and B1 of the second wiring is detected. Analysis is performed.

In the second test circuit 6222, the gates of the switches SW2A1 and SW2B1 are turned ON and the gates of the switches SW2A2 and SW2B2 are turned OFF to determine whether or not there is continuity between the circuits A2 and B2 of the third wiring. Failure analysis of section 6202P is performed.

Similarly, by turning ON the gates of the switches SW2A2 and SW2B2 and turning OFF the gates of the switches SW2A1 and SW2B1, the defect of the junction 6202Q as to whether or not there is continuity between the circuits A2 and B2 of the fourth wiring is detected. Analysis is performed.

FIG. 63 is a circuit diagram showing a setting example after failure analysis of bonding pads between semiconductor substrates when a signal path is shared between a plurality of circuits. Assume that the defect analysis in FIG. 62 detects, for example, joint defects at joints 6202P and 6202Q. In this case, the third wiring and the fourth wiring in the second test circuit 6222 cannot transmit signals between the circuits A2 and B2. Therefore, in the first test circuit 6221, the switches SW1A1 and SW1B1 are turned ON to enable transmission through the first wiring 6301 between the circuits A1 and B1.

The first test circuit 6221 turns off the switches SW1A2 and SW1B2, the second test circuit 6222 turns on the switches SW2A1 and SW2B1 and turns off the switches SW2A2 and SW2B2, and the connection wiring 6223 turns off the switches SW3A and SW2B2. Turn on SW3B. This enables transmission between the circuits A2 and B2 through the detour route 6302 via the junction 6001Q that has passed the failure analysis. In this way, by using the path of the adjacent circuit, it is possible to avoid a conduction failure when the bonding pad 714 is defective.

[Example of failure analysis of bonding pads between semiconductor substrates when bonding parts are shared between multiple circuits]
FIG. 64 is a circuit diagram showing a defect analysis example 1 of a bonding pad between semiconductor substrates when a plurality of circuits share a bonding portion, and FIG. 65 shows a semiconductor substrate when a plurality of circuits share a bonding portion. FIG. 11 is a circuit diagram showing a defect analysis example 2 of a bonding pad between the two; 64 and 65 have the same circuit configuration, but different junctions are detected as defective. First, the circuit configurations of FIGS. 64 and 65 will be described.

The test circuit 6400 has switches SW1, SW2 and SW3 on the semiconductor substrate 6200A and switches SW4, SW5 and SW6 on the semiconductor substrate 6200B. Joints 6401 to 6403 are provided on the interface 6210 .

The switch SW1 switches between connection between the circuit A1 and the bonding pad 714a of the bonding portion 6401 and connection between another circuit (not shown) and the bonding pad 714a of the bonding portion 6401. FIG.

The switch SW2 switches between connection between the circuit A1 and the bonding pad 714a of the bonding portion 6403 and connection between the circuit A2 and the bonding pad 714a of the bonding portion 6403. FIG.

The switch SW3 switches between connection between the circuit A2 and the bonding pad 714a of the bonding portion 6402 and connection between another circuit (not shown) and the bonding pad 714a of the bonding portion 6402. FIG.
do.

The switch SW4 switches between connection between the circuit B1 and the bonding pad 714a of the bonding portion 6401 and connection between another circuit (not shown) and the bonding pad 714b of the bonding portion 6401. FIG.

The switch SW5 switches between connection between the circuit B1 and the bonding pad 714b of the bonding portion 6403 and connection between the circuit B2 and the bonding pad 714b of the bonding portion 6403. FIG.

The switch SW6 switches between connection between the circuit B2 and the bonding pad 714b of the bonding portion 6402 and connection between another circuit (not shown) and the bonding pad 714b of the bonding portion 6402. FIG.

In FIGS. 64 and 65, a route following circuit A1, switch SW1, junction 6401, switch SW4, and circuit B1 is called a first wiring. A route following the circuit A2, the switch SW3, the junction 6402, the switch SW6, and the circuit B2 is called a second wiring.

A route following the circuit A1, the switch SW2, the junction 6403, the switch SW5, and the circuit B1 is called a third wiring. A route following the circuit A1, the switch SW2, the junction 6403, the switch SW5, and the circuit B2 is called a fourth wiring.

A route following the circuit A2, the switch SW2, the junction 6403, the switch SW5, and the circuit B1 is called a fifth wiring. A route following the circuit A2, the switch SW2, the junction 6403, the switch SW5, and the circuit B2 is called a sixth wiring.

In FIG. 64, it is assumed that a bonding failure is detected at the bonding portion 6401 by failure analysis by the test circuit 6400 . In this case, the switches SW1 and SW4 are not connected, the switch SW2 connects the circuit A1 and the bonding pad 714a of the bonding portion 6403, and the switch SW5 connects the circuit B1 and the bonding pad 714b of the bonding portion 6403. forming a third wiring;

A second wiring is formed by connecting the circuit A2 and the bonding pad 714a of the bonding portion 6402 with the switch SW3, and connecting the circuit B2 and the bonding pad 714b of the bonding portion 6402 with the switch SW6.

As a result, signals are transmitted between the circuits A1 and B1 via the junction 6403 via the third wiring, and between the circuits A2 and B2 via the junction 6402 via the second wiring.

In FIG. 65, it is assumed that a bonding failure is detected at the bonding portion 6403 by failure analysis by the test circuit 6400 . In this case, the switches SW2 and SW5 are not connected, the switch SW1 connects the circuit A1 and the bonding pad 714a of the bonding portion 6401, and the switch SW4 connects the circuit B1 and the bonding pad 714b of the bonding portion 6401. A first wiring is formed.

A second wiring is formed by connecting the circuit A2 and the bonding pad 714a of the bonding portion 6402 with the switch SW3, and connecting the circuit B2 and the bonding pad 714b of the bonding portion 6402 with the switch SW6.

As a result, signal transmission is performed between the circuits A1 and B1 via the first wiring via the junction 6401, and signal transmission is performed via the second wiring via the junction 6403 between the circuits A2 and B2.

In this way, it is possible to detect defective joints of the joints 6401 to 6403 between the semiconductor substrates 6200A and 6200B, and to perform signal transmission using the joints that pass.

FIG. 66 is a block diagram showing a configuration example of an imaging device 6600 according to the embodiment. The imaging device 6600 includes an image sensor 100, a system control unit 6601, a driving unit 6602, a photometry unit 6603, a work memory 6604, a recording unit 6605, a display unit 6606, an operation unit 6608, and a driving unit 6614. , and a taking lens 6620 .

The photographing lens 6620 guides subject light beams incident along the optical axis OA to the image sensor 100 . The photographing lens 6620 is composed of a plurality of optical lens groups, and forms an image of subject light flux from a scene near its focal plane. The imaging lens 6620 may be an interchangeable lens that can be attached to and detached from the imaging device 6600 . Note that in FIG. 66, one virtual lens arranged near the pupil represents the photographing lens 6620 .

A driving unit 6614 drives a photographing lens 6620 . For example, the driving section 6614 moves the optical lens group of the photographing lens 6620 to change the focus position. Further, the driving section 6614 may drive the iris diaphragm in the photographing lens 6620 to control the light amount of the subject light flux incident on the imaging device 100 .

The drive unit 6602 has a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 100 according to instructions from the system control unit 6601 . Further, the operation unit 6608 receives instructions from the photographer using a release button or the like.

The image sensor 100 transfers the pixel signal to the image processing section 6611 of the system control section 6601 . An image processing unit 6611 generates image data by performing various image processing using the work memory 6604 as a workspace. For example, when generating image data in the JPEG file format, compression processing is performed after generating a color video signal from the signal obtained in the Bayer array. The generated image data is recorded in the recording unit 6605, converted into a display signal, and displayed on the display unit 6606 for a preset time.

A photometry unit 6603 detects the luminance distribution of a scene prior to a series of shooting sequences for generating image data. A photometry unit 6603 includes an AE sensor with about one million pixels, for example. A calculation unit 6612 of the system control unit 6601 receives the output of the photometry unit 6603 and calculates the brightness for each area of the scene.

A computing unit 6612 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The photometry unit 6603 may also be used by the image sensor 100 . Note that the calculation unit 6612 also executes various calculations for operating the imaging device 6600 . The drive unit 6602 may be partially or wholly mounted on the image sensor 100 . A part of the system control unit 6601 may be mounted on the imaging device 100 .

In addition, the present invention is not limited to the above contents, and may be arbitrarily combined. Other aspects conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

Reference Signs List 100, 100A, 100B image sensor 101 pixel section 102 control circuit section 103 data processing section 110 first semiconductor substrate 120 second semiconductor substrate 121 peripheral circuit section 130 third semiconductor substrate 200 pixel block 201 Pixel 202 Signal line 210 Pixel group 300 Photoelectric converter 301 Transfer unit 302 Discharge unit 304 Reset unit 305 Pixel output unit 306 Load current source 310 Readout unit 351 Amplifier 352 Selector 400 , 400A, 400B control block, 401 pixel control section, 402 signal transfer section, 411 autonomous exposure processing section, 412 exposure control section, 413 pixel drive section, 421 signal input section, 422 signal processing section, 423 signal output section

Claims (54)

a first semiconductor substrate having a plurality of pixels including photoelectric conversion units that convert light into electric charges;
a second semiconductor substrate having a control circuit section and a peripheral circuit section;
The control circuit unit
a first pixel control unit including a first exposure control circuit that controls an accumulation time for accumulating charges converted by the photoelectric conversion unit of the first pixel among the plurality of pixels;
a second pixel control unit including a second exposure control circuit that controls an accumulation time for accumulating charges converted by the photoelectric conversion unit of the second pixel among the plurality of pixels;
The peripheral circuit section
a first arithmetic circuit arranged outside the control circuit portion and performing arithmetic operation using the first signal read from the first pixel and outputting a first arithmetic result; a second arithmetic circuit that performs arithmetic using the second signal and outputs a second arithmetic result;
image sensor. The imaging device according to claim 1,
The pixel has a discharge section for discharging the charge of the photoelectric conversion section,
The first exposure control circuit controls the ejection portion of the first pixel based on the first calculation result,
The second exposure control circuit controls the ejection portion of the second pixel based on the second calculation result.
image sensor. The imaging device according to claim 1,
the first exposure control circuit controls timing for starting charge accumulation in the photoelectric conversion unit of the first pixel based on the first calculation result;
The second exposure control circuit controls timing to start accumulating charges in the photoelectric conversion unit of the second pixel based on the second calculation result.
image sensor. The imaging device according to claim 1,
The pixel has a transfer section that transfers the charge of the photoelectric conversion section,
The first exposure control circuit controls the transfer unit of the first pixel based on the first calculation result,
A said 2nd exposure control circuit is an image sensor which controls the said transfer part of a said 2nd pixel based on a said 2nd calculation result. The imaging device according to claim 1,
The first exposure control circuit controls timing for ending charge accumulation in the photoelectric conversion unit of the first pixel based on the first calculation result,
The second exposure control circuit controls timing for ending charge accumulation in the photoelectric conversion unit of the second pixel, based on the second calculation result.
image sensor. The imaging device according to claim 1,
The control circuit unit has a first conversion unit for converting the first signal into a digital signal and a second conversion unit for converting the second signal into a digital signal.
image sensor. The imaging device according to claim 6,
The control circuit section stores the first signal converted into a digital signal by the first conversion section and the second signal converted into a digital signal by the second conversion section. a second storage unit;
image sensor. The imaging device according to claim 1,
The peripheral circuit section has a first conversion section for converting the first signal into a digital signal, and a second conversion section for converting the second signal into a digital signal.
image sensor. The imaging device according to claim 1,
The first pixels and the second pixels are arranged in a column direction,
image sensor. The imaging device according to claim 9,
The first pixels are arranged in the same column as the second pixels,
image sensor. The imaging device according to claim 10,
The control circuit unit
a third pixel control unit including a third exposure control circuit that controls an accumulation time for accumulating charges in the photoelectric conversion unit of the third pixel among the plurality of pixels;
a fourth pixel control unit including a fourth exposure control circuit that controls an accumulation time for accumulating charges in the photoelectric conversion unit of the fourth pixel among the plurality of pixels;
The peripheral circuit section
a third arithmetic circuit arranged outside the control circuit portion and performing an arithmetic operation using the third signal read from the third pixel and outputting a third arithmetic result; a fourth arithmetic circuit that performs arithmetic using the fourth signal and outputs a fourth arithmetic result;
The third pixel and the fourth pixel are arranged in the column direction in a column different from that of the first pixel and the second pixel, and the third pixel is arranged in the same column as the fourth pixel. there is
image sensor. The imaging device according to claim 11,
The first pixel control unit and the second pixel control unit are arranged adjacent to each other in the row direction,
image sensor. The imaging device according to claim 8,
The peripheral circuit section has a digital signal processing circuit created by automatic placement and routing,
The first arithmetic circuit and the second arithmetic circuit are arranged between the digital signal processing circuit and the control circuit unit,
image sensor. The imaging device according to claim 2,
The pixel has a transfer section that transfers the charge of the photoelectric conversion section,
The first exposure control circuit controls the discharge section of the first pixel at the timing of transfer of the charge by the transfer section of the first pixel,
The second exposure control circuit controls the discharge section of the second pixel at the timing of transfer of the charge by the transfer section of the second pixel.
image sensor. The imaging device according to claim 14,
The first exposure control circuit controls the discharge unit of the first pixel at the timing of transfer of the charge by the transfer unit of the first pixel, and then controls the discharge unit of the first pixel based on the first calculation result. controlling the discharge unit;
The second exposure control circuit controls the discharge section of the second pixel at the timing of transfer of the charge by the transfer section of the second pixel, and then controls the discharge section of the second pixel based on the second calculation result. controlling the ejector;
image sensor. The imaging device according to claim 14,
The first exposure control circuit controls the transfer timing of the charge by the transfer unit of each first pixel of one of a plurality of first pixel groups including one or more first pixels. controlling the discharge section of the first pixel, and after the control, controlling the discharge section of the first pixel at the transfer timing of the charge by the transfer section of each first pixel of the remaining first pixel group; death,
The second exposure control circuit controls the transfer timing of the charge by the transfer unit of each second pixel of one of a plurality of second pixel groups including one or more second pixels. controlling the discharge section of the second pixel, and after the control, controlling the discharge section of the second pixel at the transfer timing of the charge by the transfer section of each second pixel of the remaining second pixel group; do,
image sensor. The imaging device according to claim 3,
The pixel has a transfer section that transfers the charge of the photoelectric conversion section,
The first exposure control circuit starts charge accumulation in the photoelectric conversion unit of the first pixel at the timing of transfer of the charge by the transfer unit of the first pixel,
The second exposure control circuit starts accumulating charge in the photoelectric conversion unit of the second pixel at the timing of charge transfer by the transfer unit of the second pixel.
image sensor. The imaging device according to claim 17,
The first exposure control circuit starts accumulating charges in the photoelectric conversion unit of the first pixel at the timing of transfer of the charge by the transfer unit of the first pixel, and then, based on the first calculation result, controlling the timing of starting charge accumulation in the photoelectric conversion unit of the first pixel;
The second exposure control circuit starts accumulating charge in the photoelectric conversion unit of the second pixel at the timing of transfer of the charge by the transfer unit of the second pixel, and then, based on the second calculation result, controlling the timing of starting charge accumulation in the photoelectric conversion unit of the second pixel;
image sensor. The imaging device according to claim 17,
The first exposure control circuit controls the transfer timing of the charge by the transfer unit of each first pixel of one of a plurality of first pixel groups including one or more first pixels. The photoelectric conversion unit of the first pixel starts accumulating electric charge, and after the start of accumulation, the transfer unit of each of the remaining first pixels of the first pixel group transfers the electric charge to the first pixel. start accumulating charges in the photoelectric conversion unit of
The second exposure control circuit controls the transfer timing of the charge by the transfer unit of each second pixel of one of a plurality of second pixel groups including one or more second pixels. The photoelectric conversion units of the second pixels start to accumulate electric charges, and after the start of the accumulation, the second pixels are transferred at the transfer timing of the electric charges by the transfer units of the remaining second pixels of the second pixel group. start accumulating charge in the photoelectric conversion unit of
image sensor. The imaging device according to claim 1,
The peripheral circuit unit outputs image data obtained by adding the first calculation result to the first signal and adding the second calculation result to the second signal.
image sensor. The imaging device according to claim 1,
The peripheral circuit unit inserts the first calculation result into the first signal, inserts the second calculation result into the second signal, and outputs the first signal and the second signal.
image sensor. The imaging device according to claim 1,
The first arithmetic circuit performs arithmetic using the first signal converted into a digital signal,
The second arithmetic circuit performs arithmetic using the second signal converted into a digital signal,
image sensor. The imaging device according to claim 22,
The control circuit section has a first conversion section for converting the first signal into a digital signal and a second conversion section for converting the second signal into a digital signal,
The first arithmetic circuit performs arithmetic using upper bits of the first signal converted into a digital signal by the first conversion unit,
The second arithmetic circuit performs arithmetic using upper bits of the second signal converted into a digital signal by the second conversion unit,
image sensor. 24. The imaging device according to claim 23,
The first arithmetic circuit performs arithmetic using the output first arithmetic result and the upper bits of the first signal,
The second arithmetic circuit performs arithmetic using the output second arithmetic result and the upper bits of the second signal.
image sensor. The imaging device according to claim 1,
The first arithmetic circuit is connected to the first pixel, converts the analog value of the first signal into a digital signal and performs arithmetic,
The second arithmetic circuit is connected to the second pixel, converts the analog value of the second signal into a digital signal, and performs an arithmetic operation.
image sensor. The imaging device according to claim 1,
A data processing unit is provided outside the control circuit unit,
the first arithmetic circuit performs arithmetic using a first signal group read from a first pixel group that is one or more of the first pixels, and outputs the first arithmetic result;
the second arithmetic circuit performs arithmetic using a second signal group read from a second pixel group, which is the one or more second pixels, and outputs the second arithmetic result;
The data processing unit
Based on the first calculation result for the first pixel group and the second calculation result for the second pixel group, the first calculation result is calculated outside the second semiconductor substrate. Replace with the first operation result for one pixel group,
image sensor. The imaging device according to claim 26,
The data processing unit is provided in the peripheral circuit unit,
image sensor. The imaging device according to claim 26,
Having a third semiconductor substrate having the data processing unit,
image sensor. The imaging device according to claim 1,
The first exposure control circuit has a first selection circuit that selects either one of the first calculation result and a set value from the outside of the second semiconductor substrate, and the first selection circuit When a specific pattern in which the calculation result is outside the predetermined range is repeated, the setting value is selected,
The second exposure control circuit has a second selection circuit that selects one of the second calculation result and the set value, and the second selection circuit selects one of the second calculation result and the specific pattern. if repeating, selecting said setting value;
image sensor. The imaging device according to claim 29,
Having a data processing unit that detects repetition of the specific pattern,
When the repetition of the specific pattern is detected in the first exposure control circuit, the data processing unit outputs a selection signal for selecting the set value to the first exposure control circuit, and outputs the selection signal to the second exposure control circuit. outputting a selection signal for selecting the set value to the second exposure control circuit when repetition of the specific pattern is detected for
image sensor. The imaging device according to claim 30,
The data processing unit is provided in the peripheral circuit unit,
image sensor. The imaging device according to claim 30,
Having a third semiconductor substrate having the data processing unit,
image sensor. The imaging device according to claim 1,
the first arithmetic circuit performs arithmetic using a first signal group read from a first pixel group that is one or more of the first pixels, and outputs the first arithmetic result;
The first exposure control circuit has a first selection circuit that selects either one of the first calculation result and a set value from the outside of the second semiconductor substrate, and the first selection circuit selecting one of the first calculation result and the set value based on the number of first defective pixels included in the pixel group;
the second arithmetic circuit performs arithmetic using a second signal group read from a second pixel group, which is the one or more second pixels, and outputs the second arithmetic result;
The second exposure control circuit has a second selection circuit that selects one of the second calculation result and the set value, and the second selection circuit selects a second defect included in the second pixel group. selecting one of the second calculation result and the set value based on the number of pixels;
image sensor. The imaging device according to claim 1,
The first arithmetic circuit is
a first pixel group including an optical black pixel signal read from an optical black pixel in an optical black pixel area among the plurality of pixels, and a first reference pixel for blocking subject light; performing calculation using the first reference signal read out from the first reference pixel,
The second arithmetic circuit is
Calculation using the optical black pixel signal and a second reference signal read from the second reference pixel in a second pixel group including the second pixel and a second reference pixel that shields subject light I do,
image sensor. The imaging device according to claim 1,
The first pixel control unit has a first setting unit that sets a charge accumulation timing by the photoelectric conversion unit of a first reference pixel existing in a first pixel group including the first pixel,
The first arithmetic circuit performs arithmetic on the first pixel using a first reference signal read from the first reference pixel at the accumulation timing set by the first setting unit,
The second pixel control unit has a second setting unit that sets a charge accumulation timing by the photoelectric conversion unit of a second reference pixel existing in a second pixel group including the second pixel,
The second arithmetic circuit performs arithmetic on the second pixel using a second reference signal read from the second reference pixel at the accumulation timing set by the second setting unit.
image sensor. The imaging device according to claim 35,
The first setting unit sets different accumulation timings for a plurality of the first reference pixels,
The first arithmetic circuit calculates any one of a plurality of first reference signals read from the plurality of first reference pixels according to the accumulation timing set by the first setting unit and the first reference pixel. performing calculations on a first pixel block including a plurality of the first reference pixels and the first pixels using the first signals from the first pixels other than
The second setting unit sets different accumulation timings for a plurality of the second reference pixels,
The second arithmetic circuit calculates any one of a plurality of second reference signals read from the plurality of second reference pixels according to the accumulation timing set by the second setting unit and the second reference pixel. performing calculations on a second pixel block including a plurality of the second reference pixels and the second pixels, using the second signals from the second pixels other than
image sensor. The imaging device according to claim 34 or 36,
a plurality of the first reference pixels are arranged in different rows or different columns in the first pixel group;
a plurality of the second reference pixels are arranged in different rows or different columns in the second pixel group;
image sensor. The imaging device according to claim 34 or 36,
a plurality of the first reference pixels are spaced apart from each other in the first pixel group;
a plurality of the second reference pixels are spaced apart in the second pixel group;
image sensor. The imaging device according to claim 1,
the first pixel and the second pixel are white pixels that receive subject light through a transparent filter;
The first arithmetic circuit is
Using the first signal read from the first pixel, perform an operation on a first pixel group including the first pixel;
The second arithmetic circuit is
Using the first signal read from the second pixel, perform an operation on a second pixel group including the second pixel;
image sensor. The imaging device according to claim 39,
The first pixel is an AF pixel having a light shielding portion that shields subject light and the transparent filter,
image sensor. The imaging device according to claim 1,
The first arithmetic circuit is
excluding first signals having values from a maximum value to a predetermined number in a first signal group read from each of the first pixels of a first pixel group including the first pixel; performing an operation on a first pixel group including the first pixel using the residual first signal;
The second arithmetic circuit is
excluding second signals having values ranging from the maximum value to a predetermined number in the second signal group read from each of the second pixels of the second pixel group including the second pixel; using the residual second signal to perform an operation on a first group of pixels including the second pixel;
image sensor. The imaging device according to claim 1,
The control circuit unit
A first storage section for storing a first number of defective pixels in a first pixel group including the first pixel, and a second storage section for storing a second number of defective pixels in a second pixel group including the second pixel. and
The first arithmetic circuit is
performing an operation using the first signal group read out from the first pixel group;
The first exposure control circuit,
If the number of first defective pixels stored in the first storage unit is equal to or less than a predetermined number, an accumulation time for accumulating charges in the photoelectric conversion unit of the first pixel is controlled based on the result of the first calculation. and controlling an accumulation time for accumulating charges in the photoelectric conversion unit of the first pixel based on the second calculation result when the number of the first defective pixels stored in the first storage unit is not equal to or less than a predetermined number. ,
image sensor. 43. The imaging device according to claim 42,
the first pixel group is arranged adjacent to the second pixel group;
image sensor. The imaging device according to claim 1,
wiring of a plurality of paths connecting between the first pixel of the first semiconductor substrate and a circuit of the second semiconductor substrate;
a plurality of junctions connecting each of the plurality of paths at a boundary between the first semiconductor substrate and the second semiconductor substrate;
a test circuit for detecting continuity between the first pixel of the first semiconductor substrate and circuitry of the second semiconductor substrate for each of the plurality of junctions;
An image sensor having 45. The imaging device according to claim 44,
The control circuit section has a first pixel drive section for driving the first pixels as a circuit of the second semiconductor substrate,
the wiring of the plurality of paths connects between the first pixel and the first pixel driving section;
The test circuit detects continuity between the first pixel and the first pixel driver for each of the plurality of junctions under the control of the first pixel driver.
image sensor. 45. The imaging device according to claim 44,
The control circuit section includes a first pixel driving section for driving the first pixels, and a first conversion section for converting the first signal into a digital signal as a circuit of the second semiconductor substrate,
the wiring of the plurality of paths connects between the first pixel and the first conversion unit;
The test circuit detects continuity between the first pixel and the first conversion unit for each of the plurality of junctions under the control of the first pixel drive unit.
image sensor. 45. The imaging device according to claim 44,
The control circuit section has a first conversion section for converting the first signal into a digital signal as a circuit of the second semiconductor substrate,
The test circuit includes:
comprising a plurality of selection units provided in the first pixel and configured to select and output the first signal for each of the plurality of paths;
The wiring of the plurality of paths connects between the plurality of selection units and the first conversion unit,
image sensor. 45. The imaging device according to claim 44,
The test circuit is provided on the first semiconductor substrate,
image sensor. 45. The imaging device according to claim 44,
The test circuit is provided on the second semiconductor substrate,
image sensor. The imaging device according to claim 1,
a third semiconductor substrate having a data processing unit for data processing the first signal and the second signal;
the first semiconductor substrate and the second semiconductor substrate are bonded together, the second semiconductor substrate and the third semiconductor substrate are bonded together,
a plurality of joints provided at a boundary between the two semiconductor substrates to be joined;
Between two bonded semiconductor substrates out of the first semiconductor substrate, the second semiconductor substrate and the third semiconductor substrate, the plurality of first circuits on one semiconductor substrate and second circuits on the other semiconductor substrate are formed in the plurality of semiconductor substrates. and the first wiring connected through the first bonding portion of the bonding portions, and the first circuit of the one semiconductor substrate and the second circuit of the other semiconductor substrate are connected to the second bonding portion of the plurality of bonding portions. a first test circuit that selects one of a second wiring connected via two junctions and detects continuity of the junction through which the selected path passes;
Between the two semiconductor substrates to be bonded, a third circuit for connecting a third circuit of one of the semiconductor substrates and a fourth circuit of the other semiconductor substrate through a third bonding portion among the plurality of bonding portions. and a fourth wiring that connects the third circuit of one of the semiconductor substrates and the fourth circuit of the other semiconductor substrate via a fourth junction among the plurality of junctions. a second test circuit that selects a route by wiring of and detects continuity of a junction through which the selected route passes;
The first test circuit and the second test circuit can be selectively connected on the one semiconductor substrate, and the first test circuit and the second test circuit can be selectively connected on the other semiconductor substrate. possible connecting wiring;
An image sensor having The imaging device according to claim 1,
a plurality of joints provided at a boundary between the first semiconductor substrate and the second semiconductor substrate;
Between the first semiconductor substrate and the second semiconductor substrate, a first circuit on one of the first semiconductor substrate and the second semiconductor substrate and a second circuit on the other semiconductor substrate are provided as the semiconductor substrate. a first wiring connected through a first joint of the plurality of joints, and a first circuit of the one semiconductor substrate and a second circuit of the other semiconductor substrate of the plurality of joints; a first test circuit that selects one of a second wiring connected via a second junction and detects continuity of the junction through which the selected path passes;
Between the first semiconductor substrate and the second semiconductor substrate, a third circuit of the one semiconductor substrate and a fourth circuit of the other semiconductor substrate are connected through a third joint portion among the plurality of joint portions. and a fourth wiring that connects the third circuit of the one semiconductor substrate and the fourth circuit of the other semiconductor substrate through the fourth junction among the plurality of junctions. and a second test circuit that selects a route by wiring and detects continuity of the junction through which the selected route passes;
The first test circuit and the second test circuit can be selectively connected on the one semiconductor substrate, and the first test circuit and the second test circuit can be selectively connected on the other semiconductor substrate. possible connecting wiring;
An image sensor having The imaging device according to claim 1,
a third semiconductor substrate having a data processing unit for data processing the first signal and the second signal;
the first semiconductor substrate and the second semiconductor substrate are bonded together, the second semiconductor substrate and the third semiconductor substrate are bonded together,
a plurality of joints provided at a boundary between the two semiconductor substrates to be joined;
Between two bonded semiconductor substrates out of the first semiconductor substrate, the second semiconductor substrate and the third semiconductor substrate, the plurality of first circuits on one semiconductor substrate and second circuits on the other semiconductor substrate are formed in the plurality of semiconductor substrates. a first wiring connected through the first bonding portion of the bonding portions, and a third circuit of the one semiconductor substrate and a fourth circuit of the other semiconductor substrate are connected to a second bonding portion of the plurality of bonding portions and the first circuit on one of the semiconductor substrates and the second circuit on the other semiconductor substrate are connected through a third junction among the plurality of junctions. a third wiring; a fourth wiring that connects the first circuit of one of the semiconductor substrates and the fourth circuit of the other semiconductor substrate through a third junction among the plurality of junctions; a fifth wiring that connects the third circuit on one semiconductor substrate and the second circuit on the other semiconductor substrate through the third junction; and the third circuit on the one semiconductor substrate and the other semiconductor substrate. and a sixth wiring connecting the fourth circuit of the semiconductor substrate through the third junction, and the conduction of the junction through which the selected path passes is detected. a test circuit;
An image sensor having The imaging device according to claim 1,
a plurality of joints provided at a boundary between the first semiconductor substrate and the second semiconductor substrate;
Between the first semiconductor substrate and the second semiconductor substrate, a first circuit on one of the first semiconductor substrate and the second semiconductor substrate and a second circuit on the other semiconductor substrate are provided as the semiconductor substrate. A first wiring connected via a first bonding portion of the plurality of bonding portions, and a third circuit of the one semiconductor substrate and a fourth circuit of the other semiconductor substrate are connected to a second wiring of the plurality of bonding portions. a second wiring connected through a joint portion, and a third joint portion among the plurality of joint portions for connecting the first circuit of the one semiconductor substrate and the second circuit of the other semiconductor substrate. a fourth wiring that connects the first circuit of one of the semiconductor substrates and the fourth circuit of the other semiconductor substrate through the third junction among the plurality of junctions; a fifth wiring that connects the third circuit of the one semiconductor substrate and the second circuit of the other semiconductor substrate through the third junction; and the third circuit of the one semiconductor substrate and the second circuit. A sixth wiring connecting the fourth circuit of the other semiconductor substrate via the third junction is selected, and conduction of the junction through which the selected path passes is detected. a test circuit that
An image sensor having An imaging device comprising the imaging device according to claim 1 .

Images