JP2023059562A - Error measuring device and error measuring method - Google Patents

Abstract

To allow the expected value of transmission time of a sequence pattern to be displayed.SOLUTION: An error measuring device 1 transmits a test signal with a known pattern to an object under measurement W, in a state in which the object under measurement W is shifted to a signal loopback state by a handshake of a sequence pattern with the object under measurement W based on a communication standard selected in advance, and measures an error of input data loop-backed and received from the object under measurement W in response to the transmission of the test signal. The error measuring device includes first calculation means 6a1 for calculating transmission time of a base pattern based on an encoding rule and a bit rate determined by the communication standard, the length of a base pattern in the sequence pattern, and the number of repetitions; and display control means 6b for controlling display of the transmission time of the base pattern calculated by the first calculation means 6a1.SELECTED DRAWING: Figure 1

Description

The present invention transmits a test signal of a known pattern to a device under test in a state in which the device under test is transitioned to a signal loop state by handshake of a sequence pattern between the device under test and the device under test based on a preselected communication standard. More specifically, the present invention relates to an error measuring apparatus and an error measuring method for measuring errors in input data received by being returned from a device under test along with transmission of a test signal.

For example, when testing a receiver as a device under test in communication standards for high-speed serial buses such as PCI Express and USB, an error measuring device disclosed in, for example, Patent Document 1 below is used. Sends a sequence pattern from to the receiver, performs a handshake that transitions the receiver to the test-only signal loopback state (Loopback.Active), inputs a known pattern for testing, and measures the error of the loopbacked signal. method is common.

By the way, in the error measuring device of Patent Document 1 below, the function of arbitrarily editing and transmitting a sequence pattern is useful. For example, when debugging a device under test, by creating various sequence patterns and investigating how the device under test changes state when receiving these patterns, all problems that occur in the device under test can be resolved. You can isolate the cause. In particular, by combining the arbitrary sequence pattern generation function of the error measuring device and the real-time oscilloscope, it is possible to greatly simplify the verification of the state transition of the device under test.

Also, when using the arbitrary sequence pattern generation function of the error measuring device and the real-time oscilloscope at the same time, the output signal of the device under test and the output signal of the error measuring device are simultaneously connected to the real-time oscilloscope and displayed as waveforms. It is efficient to observe how the state transition of the device under test is affected while adjusting the number of transmissions of each pattern output by .

Here, the sequence pattern to be transmitted to the device under test is generally set by the number of transmissions, but when debugging the device under test using a real-time oscilloscope, the transmission time is also displayed at the same time. and very convenient.

Japanese Patent Application Laid-Open No. 2020-127116

However, although the conventional error measuring device sets the number of transmissions of the sequence pattern to be transmitted to the device under test, it does not have a function of displaying the transmission time of the sequence pattern.

In the pattern generation of the test signal of the conventional error measuring device, the high-speed serial bus encodes the sequence pattern for each communication standard, and periodically generates a Skip Ordered Set (SKP OS) signal. It was not possible to derive an accurate transmission time by simple calculation from the number of transmissions because of the influence of the insertion, periodic insertion of EIEOS (Electrical Idle Exit Ordered Set), and the like.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an error measuring apparatus and an error measuring method capable of displaying an expected value of the transmission time of a sequence pattern.

In order to achieve the above object, an error measuring apparatus according to claim 1 of the present invention is a device under test W based on a preselected communication standard. error measuring device 1 for transmitting a test signal of a known pattern to the device under test in a state of transition to the state of , and measuring errors in input data received by being returned from the device under test as the test signal is transmitted. and
a first calculating means 6a1 for calculating the transmission time of the base pattern based on the encoding rule and bit rate determined by the communication standard, the length of the base pattern of the target state in the sequence pattern, and the number of repetitions;
and display control means 6b for controlling display of the transmission time of the base pattern calculated by the first calculation means.

The error measuring device according to claim 2 of the present invention is the error measuring device according to claim 1,
a second calculating means 6a2 for calculating an expected value of the transmission time of the insertion pattern based on the insertion pattern length and insertion frequency of the insertion pattern to be inserted into the base pattern;
The display control means 6b is characterized in that the expected value of the transmission time of the insertion pattern calculated by the second calculation means and the transmission time of the base pattern are added together to control the display.

The error measuring device according to claim 3 of the present invention is the error measuring device according to claim 2,
the communication standard is a high-speed serial bus standard;
The insertion pattern includes at least one of SKP OS (Skip Ordered Set) and EIEOS (Electrical Idle Exit Ordered Set).

The error measurement method according to claim 4 of the present invention is a state in which the device under test is transitioned to a signal return state by handshake of a sequence pattern with the device under test W based on a preselected communication standard. an error measurement method for transmitting a test signal having a known pattern to the device under test, and measuring an error in input data received by being returned from the device under test as the test signal is transmitted,
Based on the encoding rule and bit rate determined by the communication standard, the length of the base pattern of the target state in the sequence pattern, and the number of repetitions, the transmission time of the base pattern is and calculating
and a step of displaying and controlling the transmission time of the base pattern calculated by the first computing means.

The error measurement method according to claim 5 of the present invention is the error measurement method according to claim 4,
a step of calculating an expected value of the transmission time of the insertion pattern based on the insertion pattern length and the insertion frequency of the insertion pattern to be inserted into the base pattern by the second calculation means 6a2 provided in the error measurement device 1;
and a step of adding the expected value of the transmission time of the insertion pattern calculated by the second computing means and the transmission time of the base pattern and controlling the display.

The error measurement method according to claim 6 of the present invention is the error measurement method according to claim 5,
the communication standard is a high-speed serial bus standard;
The insertion pattern includes at least one of SKP OS (Skip Ordered Set) and EIEOS (Electrical Idle Exit Ordered Set).

According to the present invention, the user can calculate and display the expected value of the transmission time of the sequence pattern without being conscious of complicated calculations. can be debugged.

1 is a block configuration diagram of an error measuring device according to the present invention; FIG. FIG. 5 is a diagram showing an example of a pattern setting screen when performing a PCI Express standard test in the error measuring device according to the present invention; FIG. 4 is a diagram showing an example of a pattern setting screen when performing a USB standard test in the error measuring device according to the present invention; (a) A diagram showing an example of a SKP OS setting screen when performing a PCI Express standard test with the error measuring device according to the present invention, (b) SKP when performing a USB standard test with the error measuring device according to the present invention. It is a figure which shows an example of an OS setting screen. 4 is a flow chart showing a procedure for calculating an expected value of transmission time of a sequence pattern by the error measuring device according to the present invention; FIG. 6 is a flow chart showing a procedure for calculating the transmission time of the base pattern in FIG. 5; FIG. FIG. 6 is a flow chart showing a calculation procedure of an expected value of transmission time of SPK OS in FIG. 5; FIG. FIG. 6 is a flowchart showing a procedure for calculating an expected value of transmission time of EIEOS in FIG. 5; FIG.

EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated in detail, referring attached drawings.

The error rate measuring apparatus and error rate measuring method according to the present invention are tested by a sequence pattern in a standard test of a high-speed serial bus (hereinafter abbreviated as HSB) such as USB and PCI Express (hereinafter also referred to as PCIe). A test signal with a known pattern is sent to the DUT while the DUT is in a signal pattern loopback state (loopback). It measures the bit error rate.

The above sequence pattern is a pattern defined by the HSB communication standard, and is necessary for transitioning the device under test to a signal loopback state (loopback) via a predetermined state.

As shown in FIG. 1, an error measuring apparatus 1 of this embodiment is roughly configured including a setting operation section 2, a storage section 3, a measurement section 4, a display section 5 and a control section 6. FIG.

The setting operation unit 2 is operated by the user, and includes various soft keys, cursor keys, arrow keys, keys, switches, buttons, etc. provided on the apparatus main body.

The setting operation unit 2 includes setting and editing of sequence patterns on the display screen of the display unit 5 (pattern setting screen 11 in FIGS. 2 and 3, SKP OS setting screen 12 in FIGS. 4A and 4B). It is operated when performing various input settings, instructions to start or stop transmission of sequence patterns or test signals to the device under test W, instructions to start or stop measurement of the error rate of the device under test W, and the like.

The setting operation unit 2 can also use an external input device provided separately from the error measuring device 1 .

The storage unit 3 stores various types of sequence pattern information (sequence patterns defined by the HSB communication standard) based on the setting information on the pattern setting screen 11 in FIGS. 2 and 3 and the SKP OS setting screen 12 in FIGS. type, transmission order, transmission time, number of transmissions, etc.), known test signal information, and various information related to measurement conditions and measurement results of the error rate of the device under test W.

The measurement unit 4 includes a pattern generation unit 4a and an error detection unit 4b, and includes an HSB standard test of the device under test W under the control of the control unit 6 based on the setting information of the setting operation unit 2 and the information stored in the storage unit 3. Carry out various measurements.

The pattern generation unit 4a generates a sequence pattern based on setting information set on the pattern setting screen 11 shown in FIGS. 2 and 3 and the SKPOS setting screen 12 shown in FIGS. Generates a test signal of a known pattern for performing

The error detection section 4b causes the device under test W to transition to a signal pattern loopback state (loopback) according to the sequence pattern generated by the pattern generation section 4a. Errors in the input data returned from the object W to be measured are detected, and various measurements including the HSB standard test of the object W to be measured are performed.

The display unit 5 is composed of, for example, a liquid crystal display mounted on the main body of the apparatus. Under the control of the control unit 6, the display unit 5 displays a setting screen (pattern setting screen shown in FIG. 2 or FIG. Screen 11, SKP OS setting screen 12) of FIGS. display the results of various measurements based on the detection of errors in

Here, the pattern setting screen 11 in FIGS. 2 and 3 shows a state in which the "Pattern" tab at the top is pressed. On this pattern setting screen 11, when a desired communication standard to be set is selected from the pull-down menu of the input box of "Specification" ("PCIe4" is selected in FIG. 2, and "USB3.1 Gen2" is selected in FIG. 3). , each Block No. in the selected communication standard. "Break", "Pattern Type", "Bitrate", "Pattern", "Pattern Length", "Num or Time", "[num] or [μs]", "Time [ns]", "SKP Insertion , SKP Reset, EIEOSQ Insertion, EIEOSQ Interval [Pattern repeats], and EIEOSQ Reset.

Also, on the SKP OS setting screen 12 of FIGS. 4A and 4B, encoding rules ("8b10b" and "128b130b" in FIG. 4A, "8b10b" and "128b132b" in FIG. 4B) ON/OFF of Symbol Length and Interval Symbol Length×2 are set and input every time.

For example, in the encoding rule "128b130b" of the SKP OS setting screen 12 of FIG. It shows a state in which "OFF" is selected from the pull-down menu of the x2 input box.

The control unit 6 controls the measurement unit 4 based on the setting information of the setting operation unit 2 and the storage information of the storage unit 3, and performs overall control of each unit in order to perform various measurements of the object W to be measured. It includes calculation means 6a and display control means 6b.

The transmission time calculation means 6a calculates the expected value of the transmission time of the sequence pattern for each state (Block No.), and comprises a first calculation means 6a1 and a second calculation means 6a2. The first computing means 6a1 calculates the transmission time of the base pattern for each state based on the encoding rule and bit rate determined by the communication standard, the length of the base pattern in the sequence pattern, and the number of repetitions. Further, the second computing means 6a2 calculates an expected value of the transmission time of the insertion pattern for each state based on the insertion pattern length and insertion frequency of the insertion pattern to be inserted into the base pattern.

A method of calculating the expected value of the transmission time of the sequence pattern (the expected value of the transmission time of the base pattern and the expected value of the transmission time of the insertion pattern) calculated for each state will be described later in detail.

The display control means 6b controls the pattern setting screen 11 in FIGS. 2 and 3 and the SKP OS in FIG. The display section 5 is controlled to display the setting screen 12 .

Further, the display control means 6b displays the expected value of the transmission time of the sequence pattern for each state calculated by the transmission time calculation means 6a in "Time [ns]" of the pattern setting screen 11 shown in FIGS. to control the display unit 5.

Next, the outline of the calculation method of the expected value of the transmission time of the sequence pattern for each state by the error measuring device 1 will be described with reference to the flow chart of FIG.

First, two parameters (for example, “Block No.”: #28 in FIG. 2) to be calculated determined by the user setting selection standard (for example, “Specification” on the pattern setting screen 11 in FIG. 2: PCIe4) (for example, in FIG. 2 encoding specification “Pattern Type”: 128b130b, bit rate “Bitrate”: 16.0G) and the length of the base pattern of the state to be calculated in the sequence pattern created by the user (pattern length “Pattern Length” in FIG. 2: 128), the transmission time of the base pattern of the state to be calculated is calculated from the number of repetitions (repetition time) "Num or Time": Num and "[num] or [μs]: 200" in FIG. 2 (ST1).

Next, the expected value of the transmission time of the insertion pattern to be inserted into the base pattern as required is calculated. Specifically, when SKP OS is inserted into the base pattern as the insertion pattern, user-set parameters (SKP OS insertion ON/OFF, pattern length, insertion frequency, SKP OS Symbol×2: FIG. 2 or "SKP Insertion" on the pattern setting screen 11 of FIG. Calculate the expected value of the transmission time of the OS (ST2).

When EIEOS is inserted into the base pattern as an insertion pattern, user setting parameters related to EIEOS (ON/OFF of EIEOS insertion, insertion frequency: "EIEOSQ Insertion" on the pattern setting screen 11 of FIG. 2 and FIG. 3) , "EIEOSQ Interval [Pattern repeats]"), and the parameter (EIEOS Length) determined by the user setting selection standard ("Specification" on the pattern setting screen 11 in Figs. 2 and 3), the expected value of the EIEOS transmission time is calculated. (ST3). Note that when both SKP OS and EIEOS are inserted into the base pattern as insertion patterns, the order of calculation of ST2 and ST3 may be reversed.

Then, the transmission time of the base pattern obtained by the above calculation and the expected value of the transmission time of the insertion pattern calculated as necessary (expected value of transmission time of SKPOS, expected value of transmission time of EIEOS) are added. , the summed time is displayed as the expected value of the transmission time of the sequence pattern in "Time [ns]" of the pattern setting screen 11 shown in FIGS. 2 and 3 (ST4).

Next, details of each process of ST1 to ST3 in FIG. 5 will be described with reference to flow charts in FIGS. 6 to 8, showing specific numerical values when the selected standards are PCIe4 and USB3.1 Gen2.

First, as the processing of ST1 in FIG. 5, a method for calculating the transmission time of the base pattern in the sequence pattern will be described with reference to the flowchart in FIG.

[Calculation method of transmission time of base pattern in sequence pattern]
When calculating the transmission time of the base pattern in the sequence pattern of the state to be calculated, first, the bit rate of the state to be calculated is acquired from the communication standard selected by the user (ST21). For example, in the pattern setting screen 11 of FIG. 2, when calculating the transmission time of the base pattern in the sequence pattern of "Block No.": #28, select "PCIe4" from the pull-down menu of the hatched "Specification" input box 11a. is selected as the communication standard, 16 Gbps is obtained as the bit rate from the hatched "Bitrate" 11b of "Block No.": #28. In the pattern setting screen 11 of FIG. 3, when calculating the transmission time of the base pattern in the sequence pattern of "Block No.": #8, select " When "USB 3.1 Gen2" is selected as the communication standard, 10 Gbps is obtained as the bit rate.

Next, the transmission time per bit is calculated from the obtained bit rate (ST22). For example, when the selected standard is PCIe4, the acquired bit rate is 16 Gbps, so the transmission time per bit is calculated as 1/16 Gbps=6.25E ⁻¹¹ [sec]. Also, when the selected standard is USB 3.1 Gen2, the acquired bit rate is 10 Gbps, so the transmission time per bit is calculated as 1/10 Gbps=1E ⁻¹⁰ [sec].

Next, the ratio before and after encoding is calculated from the encoding rule (“Pattern Type” 11c in the pattern setting screen 11 of FIGS. 2 and 3) uniquely determined by the acquired bit rate (ST13). For example, when the selected standard is PCIe4, the ratio before and after encoding is calculated as 130/128=1.015625. Also, when the selected standard is USB 3.1 Gen2, the ratio before and after encoding is calculated as 132/128=1.03125.

Next, the number of bits per symbol is obtained from the encoding rule uniquely determined by the obtained bit rate (ST14). For example, when the selected standard is PCIe4, the number of bits per symbol is calculated as 128b130b→130 [bit]. Also, when the selected standard is USB 3.1 Gen2, the number of bits per symbol is calculated as 128b130b→132 [bit].

Next, the length of the pattern created by the user (“Pattern Length” 11d on the pattern setting screen 11 in FIGS. 2 and 3) is acquired (ST15). For example, when the selected standard is PCIe4 or USB3.1 Gen2, the length of the pattern created by the user: 128 [bits] is acquired from "Pattern Length" 11d of the pattern setting screen 11 of FIG. 2 or 3 .

Next, the number of transmissions of the pattern created by the user (“[num] or [μs]” 11e of the pattern setting screen 11 of FIG. 2 or 3) is obtained (ST16). For example, when the selected standard is PCIe4, the number of transmissions of the pattern created by the user: 200 [times] is obtained from "[num] or [μs]" 11e of the pattern setting screen 11 in FIG. When the selected standard is USB 3.1 Gen2, the number of transmissions of the pattern created by the user: 524228 [times] is obtained from "[num] or [μs]" 11e of the pattern setting screen 11 in FIG.

Next, the ratio before and after encoding obtained in ST13, ST15, and ST16, the pattern length, and the number of times of transmission are multiplied to calculate the total number of bits to be transmitted until block transition (ST17). For example, if the selected standard is PCIe4, the ratio before and after encoding: 1.015625, the pattern length: 128, and the number of transmissions: 200, so 1.015625 × 128 × 200 = 26000 [bit] is the total number of bits transmitted until block transition. Calculated as a number. Also, when the selected standard is USB 3.1 Gen2, the ratio before and after encoding: 1.03125, the pattern length: 128, and the number of transmissions: 524228, so 1.03125 x 128 x 524228 = 69198096 [bits] are transmitted before block transition. It is calculated as the total number of bits that

Next, the number of times of transmission per bit obtained in ST12 and ST17 is multiplied by the total number of bits to be transmitted until the block transition, and the total time to be transmitted until the block transition is calculated as the transmission time of the base pattern in the sequence pattern. (ST18). For example, when the selected standard is PCIe4, the number of transmissions per bit: 6.25E ⁻¹¹ , the total number of bits transmitted until block transition: 26000, so 6.25E ⁻¹¹ ×26000=1.625E ⁻⁰⁶ [sec] is calculated as the transmission time of the base pattern of "Block No.": #28 in the sequence pattern. Also, when the selected standard is USB 3.1 Gen2, the number of transmissions per bit: 1E ^-10 , the total number of bits transmitted until block transition: 69198096, so 1E ^-10 × 69198096 = 0.00691981 [sec] is the sequence "Block No." in the pattern: Calculated as the transmission time of the #8 base pattern.

Next, as the process of ST2 in FIG. 5, a method for calculating the expected value of the transmission time of SKP OS will be described with reference to the flowchart in FIG.

[Method of calculating expected value of transmission time of SKP OS]
When calculating the expected value of the SKP OS transmission time, the SKP settings of the user settings (insertion of SKP OS: ON/OFF, insertion pattern length, insertion frequency, SKP OS Symbol x 2) are first acquired (ST21). . For example, when the selected standard is PCIe4, SKP OS insertion: ON is acquired from "SKP Insertion" 11f of the pattern setting screen 11 of FIG. The insertion pattern length: 16, the insertion frequency: 375, and the SKP OS Symbol x 2: OFF are obtained from the "Interval" 12b and the "Symbol Length x 2" 12c. If the selected standard is USB 3.1 Gen2, SKP OS insertion: ON is obtained from "SKP Insertion" 11f on the pattern setting screen 11 in FIG. Length” 12a, “Interval” 12b, and “Symbol Length×2” 12c, the insertion pattern length: 16, the insertion frequency: 40, and the SKP OS Symbol×2: OFF are obtained.

Next, the SKP OS insertion interval is calculated by multiplying the SKP OS insertion frequency by the number of bits per symbol (ST22). For example, when the selected standard is PCIe4, the SKP OS insertion frequency is 375 and the number of bits per symbol is 130, so the SKP OS insertion interval is calculated as 375×130=48750 [bits]. When the selected standard is USB 3.1 Gen2, the SKP OS insertion frequency is 40 and the number of bits per symbol is 132, so the SKP OS insertion interval is calculated as 40×132=5280 [bits].

Next, the number of bits to be inserted by one SKP OS insertion is calculated from the SKP setting (ST23). For example, if the selected standard is PCIe4, the number of bits inserted by one SKP OS insertion is calculated as (16×8+4)=132 [bits]. Also, if the selected standard is USB 3.1 Gen2, the number of bits to be inserted in one SKP OS insertion is calculated as (16×8+4)=132 [bits].

Next, the average number of times of SKP OS inserted until block transition is calculated by dividing the total number of bits transmitted until block transition by the insertion interval of SKP OS (ST24). For example, if the selected standard is PCIe4, the total number of bits transmitted until block transition is 26000, and the SKP OS insertion interval is 48750, so the average number of times SKP OS is inserted before block transition is 26000/48750=0. .533333333 [times]. Also, when the selected standard is USB 3.1 Gen2, the total number of bits transmitted until block transition is 69198096, and the SKP OS insertion interval is 5280, so the average number of times SKP OS is inserted before block transition is 69198096. /5280=13105.7 [times].

Next, by multiplying the total number of bits to be transmitted until block transition by the insertion interval of SKP OS, the average number of bits of SKP OS to be inserted until block transition is calculated (ST25). For example, if the selected standard is PCIe4, the total number of bits transmitted until block transition is 132, and the SKP OS insertion interval is 0.533333333, so the average number of bits of SKP OS inserted before block transition is 132× It is calculated as 0.533333333=70.4 [bit]. Also, when the selected standard is USB 3.1 Gen2, the total number of bits transmitted until block transition is 132, and the SKP OS insertion interval is 13105.7, so the average bit of SKP OS inserted before block transition. The number is calculated as 132×13105.7=1729952 [bit].

Next, by multiplying the transmission time per bit by the average number of bits of the SKP OS inserted until the block transition, the average time to transmit the SKP OS until the block transition is calculated as the expected value of the transmission time of the SKP OS. Calculate (ST26). For example, if the selected standard is PCIe4, the transmission time per bit is 6.25E ⁻¹¹ , and the average number of bits of SKP OS inserted until block transition is 70.4, so the expected transmission time of SKP OS is 6. .25E ⁻¹¹ ×70.4=4.4E ⁻⁰⁹ [sec]. Also, if the selected standard is USB 3.1 Gen2, the transmission time per bit: 1E ^-10 and the average number of bits of SKP OS inserted until block transition: 1729952, so the expected value of the transmission time of SKP OS is 1E. It is calculated as ⁻¹⁰ ×1729952=0.00017299524 [sec].

Next, as the processing of ST3 in FIG. 5, a method for calculating the expected value of the EIEOS transmission time will be described with reference to the flowchart in FIG.

[Method for calculating expected value of EIEOS transmission time]
When calculating the expected value of the EIEOS transmission time, first, the EIEOS setting (ON/OFF of EIEOS insertion, insertion frequency) of the user setting is acquired (ST31). For example, when the selected standard is PCIe4, EIEOS insertion: ON and insertion frequency: 32 are obtained as EIEOS settings from "EIEOSQ Insertion" 11g and "EIEOSQ Interval [Pattern repeats]" 11h of the pattern setting screen 11 in FIG. If the selected standard is USB 3.1 Gen2, EIEOS insertion: ON and insertion frequency: 16384 are obtained as EIEOS settings from "EIEOSQ Insertion" 11g and "EIEOSQ Interval [Pattern repeats]" 11h of the pattern setting screen 11 in FIG. do.

Next, the number of bits per symbol is multiplied by the EIEOS insertion frequency to calculate the EIEOS insertion interval (ST32). For example, when the selected standard is PCIe4, the number of bits per symbol is 130, and the EIEOS insertion frequency is 32, so the EIEOS insertion interval is calculated as 130×32=4160 [bits]. Also, when the selected standard is USB 3.1 Gen2, the number of bits per symbol: 132 and the EIEOS insertion frequency: 16384, so the EIEOS insertion interval is calculated as 132×16384=2162688 [bits].

Next, EIEOS Length is acquired from the communication standard selected by the user (ST33). For example, if the selected standard is PCIe4, 130 [bit] is acquired as the EIEOS Length. Also, if the selected standard is USB 3.1 Gen2, 132 [bit] is acquired as the EIEOS Length.

Next, by dividing the EIEOS Length by the EIEOS insertion interval, the average number of EIEOS inserted until block transition is calculated (ST34). For example, when the selected standard is PCIe4, the EIEOS length is 26000 and the EIEOS insertion interval is 4160, so the average number of EIEOS insertions before block transition is calculated as 26000/4160=6.25 [times]. Also, when the selected standard is USB3.1 Gen2, the EIEOS length is 69198096, and the EIEOS insertion interval is 2162688. Therefore, the average number of times EIEOS is inserted before block transition is calculated as 69198096/2162688=31.99634 [times]. be done.

Next, EIEOS Length is multiplied by the average number of times of EIEOS inserted until block transition, and the average number of bits of EIEOS inserted until block transition is calculated (ST35). For example, if the selected standard is PCIe4, the EIEOS length is 130 and the average number of EIEOS bits inserted before block transition is 6.25, so the average number of EIEOS bits inserted before block transition is 130×6.25. =812.5 [bit]. Also, when the selected standard is USB 3.1 Gen2, the EIEOS length is 132 and the average number of EIEOS bits inserted before block transition is 31.99634, so the average number of EIEOS bits inserted before block transition is 132. It is calculated as x31.99634=4223.5166015625 [bit].

Next, by multiplying the transmission time per bit by the average number of bits of EIEOS inserted until block transition, the average time of EIEOS to be transmitted until block transition is calculated as the expected value of the transmission time of EIEOS (ST36). ). For example, when the selected standard is PCIe4, the transmission time per bit is 6.25E ⁻¹¹ , and the average number of EIEOS bits inserted until block transition is 812.5, so the expected value of the EIEOS transmission time is 6.25E ^{− .} It is calculated as ¹¹ ×812.5=5.08E ⁻⁰⁸ [sec]. Also, when the selected standard is USB 3.1 Gen2, the transmission time per bit: 1E ^-10 and the average number of bits of EIEOS inserted until block transition: 4223.5166015625, so the expected value of the transmission time of EIEOS is 1E ^{- .} It is calculated as ¹⁰ ×4223.5166015625=4.22E ⁻⁰⁷ [sec].

Then, the transmission time of the base pattern in the sequence pattern for each state obtained by the above calculation, the expected value of the transmission time of SKP OS, and the expected value of the transmission time of EIEOS are summed up to obtain the expected transmission time of the sequence pattern for each state. The value is displayed in "Time [ns]" 11i of the pattern setting screen 11 in FIGS.

For example, when the selected standard is PCIe4, the expected value of the transmission time of the sequence pattern of "Block No.": #28 is 1.625E ^-06 +4.4E ^-09 +5.08E ^-08 =1.68E ^-06 [sec] = 1,680 nsec, which is displayed in "Time [ns]" 11i indicated by a bold frame on the pattern setting screen 11 in Fig. 2 . Further, when the selected standard is USB 3.1 Gen2, the expected value of the transmission time of the sequence pattern of "Block No.": #8 is 0.00691981+0.00017299524+4.22E ⁻⁰⁷ =0.007093227 [sec]=7,093 , 227 nsec, which is displayed in "Time [ns]" 11i indicated by a bold frame on the pattern setting screen 11 in FIG.

Then, the user confirms the expected value of the transmission time of the sequence pattern for each state displayed in "Time [ns]" 11i of the pattern setting screen 11 of FIGS. The number of transmissions (transmission time) is adjusted according to the amount of deviation from the desired timing.

By the way, although PCI Express and USB, which are HSB communication standards, have been exemplified in the above embodiments, the present invention is not limited to this and can be applied to other communication standards. Also, although SKPS and EIEOS have been described as examples of insertion patterns to be inserted into the base pattern, insertion patterns corresponding to the selected communication standard may be used.

As described above, according to the present embodiment, the expected value of the transmission time of the sequence pattern can be calculated and displayed without the user being conscious of complicated calculations. can be used to debug the device under test. At this time, if the error measuring device and the device under test are connected to a real-time oscilloscope, timing adjustment can be easily performed between the pattern transmitted by the error measuring device and the pattern transmitted by the device under test. As a result, it is possible to easily and efficiently verify the state transition of the device under test, and to smoothly develop devices compatible with HSB.

Although the best mode of the error measuring device and the error measuring method according to the present invention has been described above, the present invention is not limited by the description and drawings according to this mode. In other words, it goes without saying that other forms, embodiments, operation techniques, etc. made by persons skilled in the art based on this form are all included in the scope of the present invention.

Reference Signs List 1 error measuring device 2 setting operation unit 3 storage unit 4 measurement unit 4a pattern generation unit 4b error detection unit 5 display unit 6 control unit 6a transmission time calculation means 6a1 first calculation means 6a2 second calculation means 6b display control means 11 Pattern setting screen 12 SKP OS setting screen W DUT

Claims (6)

Transmitting a test signal of a known pattern to the device under test (W) in a state in which the device under test (W) is transitioned to a signal loop state by handshake of a sequence pattern based on a communication standard selected in advance to the device under test. and an error measuring device (1) for measuring an error in input data received by being returned from the device under test in response to transmission of the test signal,
first computing means (6a1) for calculating the transmission time of the base pattern based on the encoding rule and bit rate determined by the communication standard, the length of the base pattern of the target state in the sequence pattern, and the number of repetitions;
and display control means (6b) for controlling display of the transmission time of the base pattern calculated by the first calculation means. a second calculation means (6a2) for calculating an expected value of the transmission time of the insertion pattern based on the insertion pattern length and insertion frequency of the insertion pattern to be inserted into the base pattern;
The display control means (6b) controls the display by summing the expected value of the transmission time of the insertion pattern calculated by the second calculation means and the transmission time of the base pattern. 2. An error measuring device according to claim 1. the communication standard is a high-speed serial bus standard;
3. The error measuring device according to claim 2, wherein said insertion pattern includes at least one of SKP OS (Skip Ordered Set) and EIEOS (Electrical Idle Exit Ordered Set). Transmitting a test signal of a known pattern to the device under test (W) in a state in which the device under test (W) is transitioned to a signal loop state by handshake of a sequence pattern based on a communication standard selected in advance to the device under test. and measuring an error in input data received by being returned from the device under test in response to transmission of the test signal, comprising:
a transmission time of the base pattern based on the encoding rule and bit rate determined by the communication standard, the length of the base pattern of the target state in the sequence pattern, and the number of repetitions; a step of calculating in (6a1);
and a step of displaying and controlling the transmission time of the base pattern calculated by the first computing means. A second calculation means (6a2) of the error measuring device (1) calculates an expected value of transmission time of the insertion pattern based on the insertion pattern length and insertion frequency of the insertion pattern to be inserted into the base pattern. and
5. The error according to claim 4, further comprising the step of adding the expected value of the transmission time of the insertion pattern calculated by the second computing means and the transmission time of the base pattern and performing display control. Measuring method. the communication standard is a high-speed serial bus standard;
6. The error measurement method according to claim 5, wherein said insertion pattern includes at least one of SKP OS (Skip Ordered Set) and EIEOS (Electrical Idle Exit Ordered Set).

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