JP2023047134A - Failure detection method and plasma processing apparatus - Google Patents

Abstract

To detect a failure of an impedance adjustment unit.SOLUTION: In a plasma processing apparatus that has a processing container partitioned into an antenna room and a processing room, and comprises: a metal window having a plurality of partial windows; an antenna generating inductive coupling plasma; an electrostatic chuck holding a substrate; and a bottom electrode supporting the electrostatic chuck, a failure detection method of an impedance adjustment unit between a plurality of partial windows including a plurality of capacitive elements existing between the plurality of partial windows and earth, and earth comprises the steps of: applying direct-current voltage to an attraction electrode of the electrostatic chuck; starting supply of source high-frequency power and/or bias high-frequency power; constantly supplying source high-frequency power and bias high-frequency power; measuring capacitive element voltage that is applied to each of the plurality of capacitive elements during performing processing of the substrate; and determining failures of a plurality of impedance adjustment units on the basis of a comparison result between the capacitive element voltage of the plurality of capacitive elements and the predetermined threshold value.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to failure detection methods and plasma processing apparatuses.

For example, Patent Literature 1 discloses an inductively coupled plasma processing apparatus that includes a processing chamber that accommodates a substrate to be processed and performs plasma processing, and a high-frequency antenna that forms an induced electric field in the processing chamber. In the inductively coupled plasma processing apparatus, a non-magnetic metal window is formed between the high-frequency antenna and the processing chamber and is insulated from the main body container that constitutes the processing chamber.

JP 2011-29584 A

The present disclosure provides a technique capable of detecting a failure of a component that adjusts impedance of a plasma processing apparatus.

According to one aspect of the present disclosure, a processing container, a metal window that divides the processing container into an antenna chamber and a processing chamber, has a plurality of partial windows, and high-frequency power for a source that is supplied to the antenna chamber an inductively coupled antenna for generating an inductively coupled plasma, an electrostatic chuck for electrostatically attracting a substrate to be processed in the processing chamber, and a lower electrode for supporting the electrostatic chuck and supplied with bias voltage high-frequency power. , a plasma processing apparatus comprising: a plurality of impedance adjustment units including a plurality of capacitive elements provided between the plurality of partial windows and a ground, and adjusting impedance in the plurality of partial windows; 3. A method for detecting a failure of the impedance adjustment unit of , comprising the steps of: applying a DC voltage to the electrostatic chuck; and starting to supply at least one of the high-frequency power for the source and the high-frequency power for the bias voltage. a step of steadily supplying the high-frequency power for the source and the high-frequency power for the bias voltage; a step of measuring a capacitive element voltage applied to each of the plurality of capacitive elements while the substrate to be processed is being processed; determining a failure of the plurality of impedance adjusters based on a comparison result between the capacitive element voltage of each of the capacitive elements and a predetermined threshold value.

According to one aspect, it is possible to detect a failure of a component that adjusts the impedance of the plasma processing apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS The cross-sectional schematic diagram which shows an example of the plasma processing apparatus which concerns on embodiment. The figure which shows an example of the impedance adjustment circuit which concerns on embodiment. FIG. 4 is a diagram showing an arrangement example of a plurality of partial windows and an impedance adjustment circuit according to the embodiment; The figure which shows the hardware constitutions of the control part which concerns on embodiment. The figure which shows the functional structure of the control part which concerns on embodiment. 4 is a flowchart showing a failure detection method according to the embodiment; FIG. 5 is a diagram showing an example of measurement results of capacitive element voltages according to the embodiment; An example of a table storing capacitive element voltage MAX values and determination results. 4 is a flowchart showing an abnormality determination method according to the embodiment;

Hereinafter, embodiments for carrying out the present disclosure will be described with reference to the drawings. In each drawing, the same components are denoted by the same reference numerals, and redundant description may be omitted.

[Plasma processing equipment]
A plasma processing apparatus according to an embodiment will be described with reference to FIGS. 1 to 3. FIG. FIG. 1 is a cross-sectional schematic diagram showing an example of a plasma processing apparatus 100 according to an embodiment. FIG. 2 is a diagram showing an example of the impedance adjustment circuit 18 according to the embodiment. FIG. 3 is a diagram showing an arrangement example of a plurality of partial windows and the impedance adjustment circuit 18 according to the embodiment.

The plasma processing apparatus 100 according to the embodiment is used, for example, for etching a metal film, an ITO film, an oxide film, etc. and ashing a resist film when forming a thin film transistor on a glass substrate for FPD (Flat Panel Display). Examples of FPDs include liquid crystal displays (LCDs), electroluminescence (EL) displays, plasma display panels (PDPs), and the like.

The plasma processing apparatus 100 has, for example, a rectangular tube-shaped airtight processing container 1 made of a conductive material such as aluminum whose inner wall surface is anodized (anodized). This processing container 1 is grounded by a grounding wire 1a. The processing container 1 is partitioned into an upper antenna chamber 3 and a lower processing chamber 4 by a metal window 2 which is insulated from the processing container 1 . The metal window 2 constitutes the ceiling wall of the processing chamber 4 in this example. The metal window 2 is made of, for example, a non-magnetic and conductive metal. An example of a metal in the present disclosure is aluminum or an alloy containing aluminum. The metal window 2 may be supported by the side wall of the processing vessel 1 or suspended from the ceiling of the antenna room 3 .

The antenna room 3 is provided with a gas supply pipe 20a penetrating vertically. The gas flow path 12 in the gas supply pipe 20a branches into a plurality of branch pipes (not shown), and is connected to partial windows 22a, 22b, and 22c of the metal window 2 divided by the insulator 6 into respective windows. Gas is supplied to the partial window. The partial windows 22 a , 22 b , 22 c are part of the partial windows of the metal window 2 and are also collectively called the partial windows 22 .

Each partial window 22 has a gas space (not shown) inside, and has a plurality of gas discharge ports on the surface facing the processing chamber 4 . supply. The gas supply pipe 20 a penetrates from the ceiling of the processing container 1 to the outside thereof and is connected to the processing gas supply section 20 . With such a configuration, when a substrate to be processed G (hereinafter also referred to as a substrate G) is plasma-processed, the processing gas supplied from the processing gas supply unit 20 is discharged into the processing chamber 4 through the gas supply pipe 20a. .

A radio frequency (RF) antenna 13 is arranged on the metal window 2 in the antenna room 3 so as to face the metal window 2 . The high-frequency antenna 13 is separated from the metal window 2 by a spacer 17 made of an insulating material. The high-frequency antenna 13 constitutes a spiral antenna. The metal window 2 is divided into, for example, 24 partial windows 22 below the spiral antenna (see FIG. 3). However, the number of partial windows 22 is not limited to this, and may be one or more, such as 40. The high-frequency antenna 13 is an example of an inductively coupled antenna that generates inductively coupled plasma by source high-frequency power supplied to the antenna chamber 3 .

During plasma processing, from the first high-frequency power supply 15, high-frequency power for the source (hereinafter also referred to as source RF power) with a frequency of 13.56 MHz, for example, for forming an induced electric field, is supplied to the matching box 14 and the feeding member 16. is supplied to the high-frequency antenna 13 via the Although not shown, the high-frequency antenna 13 of this example is configured concentrically with an outer ring-shaped antenna, an intermediate ring-shaped antenna, and an inner ring-shaped antenna. Antenna wires extend in the circumferential direction from the feeding portions 41 , 42 , 43 to form the three ring-shaped high-frequency antennas 13 . A capacitor (not shown) is connected to the end of each antenna line, and each antenna line is grounded via the capacitor. Each of the power supply units 41, 42, and 43 may be one, or two or more. An induced electric field is formed in the processing chamber 4 via the metal window 2 by the high-frequency antenna 13 supplied with the source RF power in this way, and plasma of the processing gas supplied in the processing chamber 4 is generated by this induced electric field. generated. Therefore, after the source RF power is supplied to the high-frequency antenna 13, the substrate G is plasma-processed by the generated plasma of the processing gas.

A stage ST facing the high-frequency antenna 13 with the metal window 2 interposed therebetween is provided in the lower part of the processing chamber 4 . The stage ST has a lower electrode 23 and an insulator frame 24 . The lower electrode 23 is made of a conductive material such as aluminum with an anodized surface. The substrate G is placed on an electrostatic chuck 48 arranged on the upper surface of the lower electrode 23 . An attraction electrode 49 is provided inside the electrostatic chuck 48 . The attraction electrode 49 is connected to a DC power source 47 via a feeder line 46 . By applying a DC voltage from the DC power supply 47 to the attraction electrode 49, the substrate G is held by the electrostatic chuck 48 by electrostatic attraction.

A lower electrode 23 is housed in an insulator frame 24 and supported on the bottom surface of the processing chamber 4 . A side wall 4a of the processing chamber 4 is provided with a loading/unloading port 27a for loading/unloading the substrate G and a gate valve 27 for opening and closing the port.

The lower electrode 23 is connected to a second high-frequency power supply 29 through a matching box 28 by a feeder line 25a provided inside a hollow post 25. As shown in FIG. The second high-frequency power supply 29 applies high-frequency power for bias voltage (hereinafter also referred to as bias RF power) with a frequency of 3.2 MHz, for example, to the lower electrode 23 during plasma processing. Ions in the plasma generated in the processing chamber 4 are effectively attracted to the substrate G by the bias RF power.

Furthermore, in order to control the temperature of the substrate G, a temperature control mechanism including a heating means such as a ceramic heater, a coolant channel, etc., and a temperature sensor are provided in the lower electrode 23 (both are not shown). ). Piping and wiring for these mechanisms and members are all led out of the processing chamber 1 through hollow struts 25 .

Between the stage ST and the side wall 4a of the processing chamber 4, a baffle plate 32 formed in an annular shape by a plurality of members is provided so as to surround the stage ST. Gas is passed through the hole into the exhaust space. An exhaust pipe 31 is provided at the bottom of the processing chamber 4 , and an exhaust device 30 including a vacuum pump and the like is connected through the exhaust pipe 31 . Gas in the processing chamber 4 is exhausted by the exhaust device 30, and the inside of the processing chamber 4 is controlled to a predetermined vacuum atmosphere (for example, 1.33 Pa). A He gas flow path (not shown) is provided in the lower electrode 23 , and He gas is supplied to the back surface of the substrate G placed on the lower electrode 23 through the He gas flow path.

Each component of the plasma processing apparatus 100 is connected to and controlled by a control unit 50 comprising a computer. A desired process is performed in the plasma processing apparatus 100 under the control of the controller 50 .

[Impedance adjustment circuit]
Impedance adjustment circuits 18a, 18b, and 18c are connected to the metal window 2 on the antenna room 3 side. Potential detectors C1, C2 and C3 are provided at the connecting portions connecting the impedance adjusting circuits 18a, 18b and 18c and the partial windows 22a, 22b and 22c. Thus, the potential detectors C1, C2, C3, . Potential detectors C1, C2, C3, . . . are also collectively referred to as potential detector VC.

The impedance adjustment circuits 18 a , 18 b , 18 c are an example of an impedance adjustment section that adjusts the impedance between the plurality of partial windows of the metal window 2 and the ground, and are also collectively called the impedance adjustment circuit 18 .

The impedance adjustment circuit 18 will be described with reference to FIGS. 2 and 3. FIG. FIG. 2 shows a cross section of one partial window 22 out of the plurality of partial windows of the metal window 2, and the impedance adjustment circuit 18 connected to the partial window 22. FIG.

As an example is shown in FIG. 3, the metal window 2 is divided into 24 partial windows 22 . These partial windows 22 are parts obtained by dividing the metal window 2 and are arranged adjacent to each other via the insulator 6 to form the metal window 2 . For example, each partial window may be suspended from the ceiling of the antenna room 3 by a supporting member (not shown) and fixed. In this example, the ceiling portion, which is the wall surface of the processing chamber 4 facing the lower electrode 23, that is, the overall shape of the metal window 2 is rectangular, and the inner peripheral area, the annular middle area, and the annular outer peripheral area at the center of this rectangle are formed. Divide into The inner peripheral area has four partial windows 22 obtained by dividing the rectangular inner peripheral area approximately diagonally. The four partial windows 22 in the inner peripheral area are composed of two mutually opposing triangles with short sides as bases and two mutually opposing trapezoids with long sides as bases. In addition, the intermediate area has a total of eight partial windows 22 obtained by dividing the annular intermediate area for each side and further dividing each side into two equal halves in the radial direction. In addition, the outer peripheral area has a total of 12 partial windows 22 obtained by dividing the annular outer peripheral area for each side and further dividing each side into three equal parts in the radial direction. In this embodiment, although not shown, the inner annular antenna is arranged to correspond to the inner peripheral area, the intermediate annular antenna to the intermediate area, and the outer annular antenna to the outer peripheral area.

Since each partial window 22 is arranged via the insulator 6, it is insulated from the processing container 1 and the partial windows 22 are also insulated from each other. Examples of materials for the insulator 6 are, for example, ceramics and polytetrafluoroethylene (PTFE).

2 and 3, one impedance adjusting circuit 18 is provided for each partial window 22a, 22b, 22c, . . . . That is, in this example, 24 impedance adjustment circuits 18 are connected to 24 partial windows 22 one-to-one. However, the present invention is not limited to this, and one impedance adjustment circuit 18 may be provided for a plurality of partial windows 22 . That is, the plurality of partial windows 22 can be partitioned into one or more areas, and each one or more areas can be connected to the impedance adjustment circuit. For example, the 24 partial windows 22 may connect one impedance adjustment circuit to each of the three areas of the inner peripheral area, the intermediate area, and the outer peripheral area.

As shown in FIG. 2, impedance adjustment circuit 18 includes a capacitive element 60 to adjust the impedance between partial window 22 and ground. The impedance adjustment circuit 18 is an R+C parallel circuit having a capacitive element 60 and a resistive element 61 . In this example, one capacitive element 60 and one resistive element 61 are connected in parallel with the capacitive element 60 for each partial window 22 . Capacitive element 60 is connected at one end to partial window 22 and at the other end to ground. A resistive element 61 is connected in parallel with the capacitive element 60 at one end to the partial window 22 and at the other end to ground.

The capacitive element 60 may be a variable capacitive element or a fixed capacitive element. However, by using the capacitive element 60 as a variable capacitive element, when bias RF power is applied to the lower electrode 23, the impedance between the metal window 2 functioning as an anode electrode and the ground (hereinafter also referred to as anode impedance) is reduced. can be variably adjusted, and the impedance can be adjusted with higher accuracy.

When the impedance adjustment circuit 18 is provided for each of multiple areas, the capacitive element 60 and the resistive element 61 may be connected to multiple partial windows 22 for each area. Note that the capacitive component C0 shown in FIG. 2 indicates a stray capacitance other than the capacitive component C due to the capacitive element 60, and is mainly between the metal window and another conductive member directly or indirectly connected to the ground. is the sum of the capacitive components brought about by the space of

The temperature of the metal window 2 is adjusted by allowing an insulating temperature control medium to flow through the flow path formed in the metal window 2 . Frictional electrification occurs when the insulating temperature control medium flows, electric charges are accumulated in the metal window 2, and the metal window 2 is charged up. Part of the electrons in the plasma may be accumulated in the metal window 2 and the metal window 2 may be charged up. It is important not to allow uncontrolled accumulation of charge on the metal window 2, because charging the metal window 2 will destabilize the plasma and affect the processing of the substrate G. FIG. Therefore, the impedance adjustment circuit 18 connects the resistance element 61 to the metal window 2 in parallel with the capacitance element 60 . As a result, the charge accumulated in the metal window 2 is discharged to the ground through the resistance element 61, so that the metal window 2 can be prevented from being charged up due to the uncontrollable charge, and plasma stability can be ensured.

The potential detectors VC (C1, C2, C3, . . . ) are installed near the impedance adjustment circuits 18a, 18b, 18c, . ). In the example of FIG. 1, the potential detectors C1, C2 and C3 are installed near the impedance adjustment circuits 18a, 18b and 18c. The potential detectors C1, C2, and C3 measure the potential difference generated by the transfer of charge occurring in each of the capacitive elements 60 of the impedance adjustment circuits 18a, 18b, and 18c during processing of the substrate G as the capacitive element voltage.

With such a configuration, high-frequency power for bias voltage is supplied to the lower electrode 23, the lower electrode 23 is used as a cathode electrode, the metal window 2 is used as an anode electrode that is a counter electrode facing the lower electrode 23, and the impedance adjustment circuit 18 is used as an anode electrode. Adjust impedance. As a result, a desired potential difference is generated between the metal window 2 and the plasma by the capacitance of the capacitive element 60, and cleaning can be performed by removing deposits of by-products adhering to the metal window 2 by plasma sputtering. . Further, when high-frequency power for bias voltage is supplied to the lower electrode 23, other parts in the processing container 1 can also function as anodes, but the metal window 2 is made to more positively function as an anode, so that the cathode electrode, that is, the lower electrode, is used. Strengthen the coupling with the electrode 23 . As a result, consumption of other parts in the processing vessel 1 due to plasma sputtering can be suppressed.

If the potential difference at the metal window 2 is too large, not only the by-products adhering to the metal window 2 are removed, but also the metal window 2 is consumed. become. Therefore, it is important to adjust the capacity of the capacitive element 60 within a range that can suppress excessive wear of the metal window 2 and other parts in the processing container 1 during cleaning while removing the by-products adhering to the metal window 2. is. As a result, it is possible to extend the life of each part and lengthen the maintenance cycle while suppressing particles.

[Configuration of control unit]
Next, the hardware configuration and functional configuration of the control unit 50 that controls the failure detection method of the impedance adjustment circuit 18, which will be described later, will be described with reference to FIGS. 4 and 5. FIG. FIG. 4 is a diagram showing the hardware configuration of the control unit 50 according to the embodiment. FIG. 5 is a diagram showing the functional configuration of the control unit 50 according to the embodiment.

The control unit 50 has a CPU (Central Processing Unit) 101, a ROM (Read Only Memory) 102, a RAM (Random Access Memory) 103, an I/O port 104, an operation panel 105, and a HDD 106 (Hard Disk Drive). Each section is connected by a bus B.

The CPU 101 controls various operations and various processes of the plasma processing apparatus 100 based on various programs read into the RAM 103 and recipes defining processing procedures for the substrate G such as etching, film formation, and cleaning. do. The processing of the substrate G (substrate processing) includes not only plasma processing of the substrate G, but also electrostatic chucking processing of applying a DC voltage to the chucking electrode 49 before plasma processing. The program includes a program that executes the failure detection method. The CPU 101 executes the failure detection method based on these programs read into the RAM 103 .

The ROM 102 is configured by an EEPROM (Electrically Erasable Programmable ROM), a flash memory, a hard disk, or the like, and is a storage medium for storing programs, recipes, and the like for the CPU 101 . The RAM 103 functions as a work area for the CPU 101 and the like.

The I/O port 104 acquires values of various sensors for detecting capacitive element voltage, temperature, pressure, gas flow rate, etc. from various sensors attached to the plasma processing apparatus 100 and transmits them to the CPU 101 . Also, the I/O port 104 outputs control signals output by the CPU 101 to each part of the plasma processing apparatus 100 . The I/O port 104 is also connected to an operation panel 105 for an operator (user) to operate the plasma processing apparatus 100 .

The HDD 106 is an auxiliary storage device and may store process recipes, programs, and the like. Further, the HDD 106 may store log information of measured values measured by various sensors.

A functional configuration of the control unit 50 shown in FIG. 5 will be described. The control unit 50 is connected by wire to the potential detector VC, that is, to 24 potential detectors C1 to C24. The control unit 50 has an acquisition unit 51 , an A/D conversion unit 52 , an abnormality detection determination unit 53 , an abnormality identification unit 54 , a display unit 55 , a process execution unit 56 and a storage unit 57 . The potential detector VC measures the capacitive element voltage while the substrate G is being processed. The potential detector VC may measure the capacitive element voltage across each of the plurality of capacitive elements 60 while the substrate G is subjected to processing consisting of a plurality of processing steps. The potential detector VC may measure the capacitive element voltage over one or more of a plurality of process steps in which the substrate G is processed.

The storage unit 57 stores a recipe in which a processing procedure for processing the substrate G is set. The storage unit 57 stores a table 57a (see FIG. 8) used in a failure detection method to be described later.

The process execution unit 56 processes the substrate G based on the recipe. The treatment includes electrostatic adsorption treatment, plasma treatment, and the like. While processing the substrate G, the process execution unit 56 applies a DC voltage to the attraction electrode 49 of the electrostatic chuck 48 to perform an electrostatic attraction process for attracting the substrate G to the electrostatic chuck 48, and the source RF power and the bias. RF power is supplied and the substrate G is subjected to plasma processing.

The obtaining unit 51 obtains the measured capacitive element voltage from the potential detector VC while the substrate G is being processed. For example, the acquisition unit 51 acquires the measured capacitive element voltage and the number (No.) of the impedance adjustment circuit 18 including the corresponding capacitive element 60 . The acquisition unit 51 obtains the measured capacitive element voltage, the number (No.) of the impedance adjustment circuit 18 including the corresponding capacitive element 60, and the processing step number (No.) of the processing step when the capacitive element voltage was measured. , may be obtained.

The A/D conversion unit 52 converts the analog signal of the capacitive element voltage acquired by the acquisition unit 51 into a digital signal. The abnormality detection determination unit 53 determines failure of each of the plurality of impedance adjustment circuits 18 based on the result of comparison between the digitally converted capacitive element voltage of each of the plurality of capacitive elements 60 and a predetermined threshold value.

Each of the plurality of capacitive elements 60 is in a short-circuited state when a failure occurs. At this time, the partial window 22 serving as the opposing electrode of the lower electrode 23 to which the bias RF power is supplied is substantially at the ground potential when viewed from the lower electrode due to the short-circuited capacitive element 60 . Therefore, when a DC voltage is applied to the electrostatic chuck 48 or the supply of at least one of the source RF power and the bias RF power is started, the potential of the partial window 22 does not fluctuate. There is no substantial potential difference across either end of the . Therefore, when the measured capacitive element voltage is below the threshold, it can be determined that the corresponding capacitive element 60 is short-circuited (failed).

The abnormality detection determination unit 53 determines at least the DC voltage application start time, the source RF power supply start time, the source RF power steady supply time, the bias RF power supply start time, the bias RF power steady supply time, and the DC power supply start time. A failure may be determined for each of the plurality of impedance adjustment circuits 18 based on the capacitive element voltage measured at one or two or more timings of the voltage application stop time.

For example, the abnormality detection determination unit 53 compares the capacitive element voltage and the threshold for each capacitive element 60 connected to each of the plurality of partial windows 22, and based on the comparison result for each capacitive element 60, each capacitive element 60 A failure may be determined for each impedance adjustment circuit 18 included.

If the capacitive element voltage measured over one or more of the plurality of processing steps does not exceed the threshold value, the abnormality detection determination unit 53 determines that the impedance adjustment circuit 18 including the corresponding capacitive element is faulty. may

The abnormality identifying unit 54 identifies the impedance adjustment circuit 18 including the capacitive element 60 whose capacitive element voltage does not exceed the threshold value or the partial window 22 connected to the impedance adjustment circuit 18 among the plurality of partial windows 22. good too. This makes it possible not only to detect a failure of the impedance adjustment circuit 18, but also to specify the failed portion.

The display unit 55 issues an alarm on the screen monitored by the operator when the processing of the substrate G is completed, and notifies the operator that an abnormality has occurred during the processing of the substrate G. FIG. In the case of an unmanned system that is not monitored by an operator, the determination flag of the faulty impedance adjustment circuit 18 in the table 57 a may be rewritten to abnormal and stored in the storage unit 57 .

Information specifying the failure of the impedance adjustment circuit 18 and the impedance adjustment circuit 18 or the partial window 22 determined as failure may be notified from the control unit 50 to the host computer 59 .

Acquisition unit 51 can be realized by I/O port 104 . The A/D conversion unit 52, the abnormality detection determination unit 53, the abnormality identification unit 54, and the process execution unit 56 can be realized by an A/D conversion circuit incorporated in the CPU 101 or CP101. The display unit 55 can be implemented by the operation panel 105 . Storage unit 57 can be realized by ROM 102 , RAM 103 and HDD 106 .

[Failure detection method]
Next, a failure detection method according to the embodiment will be described with reference to FIGS. 6 to 8. FIG. FIG. 6 is a flow chart showing a failure detection method according to the embodiment. FIG. 7 is a diagram illustrating an example of a measurement result of a capacitive element voltage according to the embodiment; FIG. 8 is an example of a table 57a storing capacitive element voltages (MAX values) and determination results used in the failure detection method of FIG.

The failure detection method of FIG. 6 is executed by the respective units of the control unit 50 . The failure detection method is started in parallel when the process execution unit 56 starts processing the substrate G. FIG. When the processing of the substrate G is started according to the recipe, the process execution unit 56 places the substrate G on the lower electrode 23 in the processing container 1 and prepares it in step S1. When the processing of the substrate G is started, each of the potential detectors VC (potential detectors C1, C2, C3, . Measure the capacitive element voltage near

Next, in step S<b>3 , the process execution unit 56 applies a DC voltage to the attraction electrode 49 of the electrostatic chuck 48 . Thereby, the substrate G is held by the electrostatic chuck 48 by electrostatic adsorption.

Next, in step S5, process execution unit 56 begins supplying source RF power and/or bias RF power. The supply of the source RF power and the bias RF power may be started at the same time or either may be started first, depending on the content of the substrate G to be processed. Next, in step S7, the process execution unit 56 plasmatizes the gas supplied from the processing gas supply unit 20 by the source RF power supplied to the antenna chamber 3, generates inductively coupled plasma, and plasma-processes the substrate G. conduct.

Next, in step S9, the acquisition unit 51 acquires the capacitive element voltage, which is the potential detection value measured by the potential detector VC. The obtaining unit 51 obtains 24 capacitive element voltages measured by the 24 potential detectors VC. In FIG. 6, step S9 is depicted as being executed simultaneously with or immediately after step S7 for convenience of illustration, but in reality, at least simultaneously with or before step S3, the capacitive element Starting to acquire voltage. The acquisition unit 51 continues to periodically or irregularly acquire the capacitive element voltages of the potential detectors VC provided near the impedance adjustment circuit 18 , that is, the capacitive element voltages of 24 .

Next, in step S11, the A/D conversion unit 52 converts the analog signal of the capacitive element voltage acquired by the acquisition unit 51 into a digital signal.

Next, in step S13, the abnormality detection determination unit 53 determines whether the capacitive element voltage after digital conversion is higher than the capacitive element voltage MAX value. The initial value of the capacitive element voltage MAX value (hereinafter also simply referred to as the MAX value) is set to 0 for each of the potential detectors VC. When the abnormality detection determination unit 53 determines that the capacitive element voltage is equal to or less than the MAX value, the process proceeds to step S17 skipping step S15. When the abnormality detection determination unit 53 determines that the capacitive element voltage is higher than the MAX value, it updates the MAX value to the value of the capacitive element voltage. As a result, the maximum value of the capacitive element voltage measured by the potential detector VC during substrate processing is stored in the storage unit 57 as the capacitive element voltage MAX value (see FIG. 8).

Next, in step S17, the abnormality detection determination unit 53 determines whether the processing steps have ended. When the abnormality detection determination section 53 determines that the processing steps have not been completed, the process returns to step S9, and repeats the processes of steps S9 to S15. As a result, the maximum value at that time is stored as the MAX value among the capacitive element voltages measured by the potential detector VC during substrate processing for each processing step.

When the abnormality detection determination unit 53 determines that the processing step has been completed, the process proceeds to step S19 and determines whether the processing of the substrate G has been completed. When the abnormality detection determination unit 53 determines that the processing of the substrate G has not been completed, the process returns to step S9, and the processing of steps S9 to S15 is repeated for the next processing step. As a result, the maximum value of the capacitive element voltage measured by the potential detector VC during substrate processing in the next processing step is stored in the capacitive element voltage MAX value of the next processing step.

When the abnormality detection determination unit 53 determines that the processing of the substrate G is finished, the process proceeds to step S21, the abnormality determination process shown in FIG. 9 is executed, and the present process is finished.

For example, in the example shown in FIG. 7, the processing of the substrate G consists of processing steps 1 and 2. FIG. In processing step 1, processing including plasma processing is performed, and in processing step 2, processing including static elimination processing for static elimination of the substrate G and the like is performed. The horizontal axis of FIG. 7 indicates the time from the start of substrate processing at 0 second, and the vertical axis (left) indicates each RF power (W) of source RF power and bias RF power and DC voltage (V). The vertical axis (right) in FIG. 7 indicates the capacitive element voltage (V) measured for each time shown on the horizontal axis.

In process step 1, at the start of substrate processing (0 second), the capacitive element voltage indicated by line e fluctuates when a DC voltage is supplied to the electrostatic chuck 48 as indicated by line d. This is because the capacitive element 60 is not short-circuited and is normal. Therefore, the potential detector VC detects the movement of charges charged in the capacitive element 60 due to the fluctuation of the DC voltage at the time of application of the DC voltage, and the capacitive element voltage It is a value measured as

At time _t1 , supply of source RF power shown on line a is started and source RF power is supplied until time _t4 . At time _t2 , the supply of bias RF power indicated by line b is started, and the bias RF power is also supplied until time _t4 . The potential detector VC detects variations in each of these RF powers at the time of supply of the source RF power and the time of supply of the bias RF power and at times t ₁ to t ₂ therebetween, and measures the capacitive element voltage indicated by line e. are doing.

Time t ₃ to time t ₄ correspond to the steady supply of source RF power indicated by line a and the steady supply of bias RF power indicated by line b. The potential detector VC measures the capacitive element voltage indicated by line e from time t ₃ to time t ₄ .

The potential detector VC outputs information including the processing step number (No.), the impedance adjustment circuit number (No.), and the measured capacitive element voltage, and the acquisition unit 51 acquires this information. As shown in FIG. 8, the storage unit 57 stores impedance adjustment circuit numbers (No.) for identifying each of the 24 impedance adjustment circuits 18 corresponding to the processing step numbers (No.), and the processing of FIG. The capacitive element voltage MAX value obtained by is stored.

In processing step 1 of FIG. 7, the capacitive element voltage (approximately 80 V) indicated by line e immediately after the start of substrate processing is stored in the capacitive element voltage MAX value.

Also for the capacitive element voltage measured in the processing step 2, the capacitive element voltage MAX value is stored in the storage unit 57 by executing the process of FIG. In process step 2, the potential detector VC detects the capacitance indicated by line e at time t ₅ when the application of the DC voltage supplied to the electrostatic chuck 48 is stopped, at time t ₆ when the supply of the source RF power is started, and when the source RF power is steadily supplied. Device voltage is measured.

In processing step 2 of FIG. 7, the capacitive element voltage indicated by line e at time _t5 when the application of the DC voltage is stopped is stored in the capacitive element voltage MAX value. The capacitive element voltage measured by the potential detector VC may have a negative value. Therefore, the capacitive element voltage used in the processing of FIG. 6 means the absolute value of the capacitive element voltage. That is, in processing step 2 of FIG. 7, the absolute value (approximately 40 V) of the capacitive element voltage at the supply stop time _t5 is stored as the capacitive element voltage MAX value.

It should be noted that it is not necessary to calculate the capacitive element voltage MAX value by dividing the processing steps 1 and 2 . At the end of the substrate processing, one capacitive element voltage MAX value may be calculated for each impedance adjustment circuit 18 and stored in the storage unit 57 .

In this way, the potential detector VC responds to transients with respect to the supply of the DC voltage, the source RF power, and the bias RF power supplied to the electrostatic chuck 48 by the movement of the charge charged on the capacitive element 60. The generated potential difference is output as the capacitive element voltage.

Therefore, when the capacitive element voltage MAX value is larger than a predetermined threshold value, it can be determined that the capacitive element 60 is not short-circuited and normal. On the other hand, when the capacitive element voltage MAX value is lower than the predetermined threshold value, it can be determined that the capacitive element 60 is short-circuited and abnormal. For example, although the threshold is not illustrated in FIG. 7, the threshold may be a value greater than 0 volts and several volts or less in consideration of noise and the like. Line f has a capacitive element voltage of 0 in processing steps 1 and 2 . In this case, the capacitive element 60 of the impedance adjustment circuit 18 (near the potential detector VC) corresponding to the measured potential detector VC is short-circuited and judged to be abnormal.

In the abnormality determination method described below, whether the capacitive element 60 (impedance adjustment circuit 18) is normal or abnormal is determined based on whether or not the capacitive element voltage changes in response to the transient phenomenon. The abnormality determination method is preferably executed after substrate processing as shown in FIG. 6, but may be executed each time each processing step is completed.

[Abnormality determination method]
FIG. 9 is a flow chart showing an abnormality determination method according to the embodiment. The abnormality determination method of FIG. 9 is started when called by step S21 of FIG. That is, when it is determined that the processing of the substrate G has ended, the execution of the abnormality determination method of FIG. 9 is started.

In step S<b>23 , the abnormality detection determination unit 53 determines whether the determination of all the impedance adjustment circuits 18 has been completed. When step S23 is executed for the first time, it is determined as "No", so the process proceeds to step S25, and the abnormality detection determination unit 53 determines that the undetermined capacitive element voltage MAX value of the impedance adjustment circuit 18 is equal to or higher than a predetermined threshold value. Determine if there is The capacitive element voltage MAX value here is the absolute value of the capacitive element voltage MAX value.

In step S25, when the abnormality detection determination unit 53 determines that the capacitive element voltage MAX value is equal to or greater than the predetermined threshold value, the process proceeds to step S27 and determines that the impedance adjustment circuit 18 is normal. The storage unit 57 stores "0" indicating normality in the determination flag corresponding to the impedance adjustment circuit 18 among the determination flags in the table 57a, and returns to step S23.

When the abnormality detection determination unit 53 determines in step S25 that the capacitive element voltage MAX value is lower than the predetermined threshold value, the process proceeds to step S29 and determines that the impedance adjustment circuit 18 is abnormal. The storage unit 57 stores "1" indicating abnormality in the determination flag corresponding to the impedance adjustment circuit 18 among the determination flags in the table 57a, and returns to step S23.

In step S23, the abnormality detection determination unit 53 repeats the processing of steps S25 to S29 until it determines that the determination of the capacitive element voltage MAX values corresponding to all the impedance adjustment circuits 18 has been completed. When the abnormality detection determination unit 53 determines in step S23 that the determination of all the impedance adjustment circuits 18 has been completed, the process proceeds to step S31 and extracts determination flags of all processing steps for each impedance adjustment circuit 18 .

Next, in step S<b>33 , the abnormality detection determination unit 53 determines whether the values of the determination flags of all the processing steps are all 1 for each impedance adjustment circuit 18 . The abnormality detection determination unit 53 may refer to the table 57 a of the storage unit 57 to determine whether the all determination flag is 1 for each impedance adjustment circuit 18 . When the abnormality detection determination unit 53 determines that the all determination flag is 1, the process proceeds to step S37, determines that the impedance adjustment circuit 18 is abnormal, and specifies the part where the abnormality is found. As the part where the abnormality is found, the number of the impedance adjustment circuit 18 whose determination flag is "1" may be specified, or the partial window 22 attached to the impedance adjustment circuit 18 whose determination flag is "1" may be specified. may A processing step number may be specified together with these pieces of information.

Next, in step S39, the abnormality detection determination part 53 notifies abnormality, and terminates this process. As an example of notification of abnormality, the abnormality detection determination unit 53 notifies the host computer 59 of the abnormality of the impedance adjustment circuit 18 and the information of the partial window 22 in which the abnormality is detected. As another example of notification of abnormality, the display unit 55 issues an alarm on the screen monitored by the operator to notify the operator. In the case of an unmanned system that is not monitored by an operator, the abnormality detection determination unit 53 may transmit the table 57a to the host computer 59 or other equipment and notify the failure.

In step S33, when the abnormality detection determination unit 53 determines that at least one of the determination flags of all the processing steps for each impedance adjustment circuit 18 is 0, the process proceeds to step S35, and the impedance adjustment circuit 18 is determined to be normal. It makes a decision and terminates this process.

In the abnormality determination method described above, it is determined that the impedance adjustment circuit 18 is abnormal only when the determination flag indicates abnormality in all the processing steps, but the present invention is not limited to this. An impedance adjustment unit 18 including a capacitive element whose capacitive element voltage measured over one or more of the plurality of processing steps did not exceed the threshold value may be determined as a failure. For example, in substrate processing that includes a plurality of processing steps, when the determination flag indicates an abnormality in one processing step, the corresponding impedance adjustment circuit 18 may be determined to be abnormal.

As described above, according to the failure detection method and the plasma processing apparatus of this embodiment, failure of the impedance adjustment circuit 18 of the plasma processing apparatus 100 can be detected. In addition, the failed impedance adjustment circuit 18 or the partial window 22 in which the failed impedance adjustment circuit 18 is provided can be identified.

For example, three transients, starting to apply DC voltage, starting to supply source RF power, and starting to supply bias RF power, and two RF steady supplies: steady supply of source RF power, steady supply of bias RF power, and DC voltage. If the voltage detector VC detects the potential difference generated in the capacitive element 60 in response to one of the stop of the application of , and the capacitive element voltage is measured, an erroneous judgment may occur in the determination of normality and abnormality. However, in the failure detection method described above, in the example of processing step 1 in FIG. A potential detector VC detects the potential difference generated in the capacitive element 60 in response to the phenomenon and two RF constant supplies, ie, the constant supply of the source RF power and the constant supply of the bias RF power, to measure the capacitive element voltage. In the example of processing step 2 in FIG. 7, the voltage detector VC detects the potential difference generated in the capacitive element 60 in response to two transient phenomena, ie, the stoppage of the DC voltage supplied to the electrostatic chuck and the start of the supply of the source RF power. and measure the capacitive element voltage. Therefore, according to the failure detection method and abnormality determination method of this embodiment, two or more transient phenomena of at least one of the DC voltage and a plurality of RF powers are detected by the potential detector VC, and the capacitive element voltage is measured. Thereby, the failure of the impedance adjustment circuit 18 can be detected with high accuracy.

The failure detection method and the plasma processing apparatus according to the embodiments disclosed this time should be considered as examples and not restrictive in all respects. Embodiments can be modified and improved in various ways without departing from the scope and spirit of the appended claims. The items described in the above multiple embodiments can take other configurations within a consistent range, and can be combined within a consistent range.

Targets to be plasma-processed by the plasma processing apparatus 100 of the present disclosure include, for example, a substrate G to be processed G6 of 1.5 m × 1.85 m and a rectangular substrate G to be processed of other dimensions. Various members such as disk-shaped wafers can be used without limitation.

1 Processing Container 2 Metal Window 3 Antenna Chamber 4 Processing Chamber 6 Insulator 13 High Frequency Antenna 15 First High Frequency Power Supply 16 Feeding Member 18 Impedance Adjustment Circuit 20 Processing Gas Supply Part 22 Partial Window 23 Lower Electrode 29 Second High Frequency Power Supply 30 Exhaust Apparatus 32 Baffle plate 60 Capacitive element 61 Resistive element G Substrates to be processed C1, C2, C3 Potential detector ST Stage

Claims (7)

a processing container; a metal window that divides the processing container into an antenna chamber and a processing chamber; a metal window having a plurality of partial windows; and a plasma processing apparatus comprising: an electrostatic chuck that electrostatically attracts a substrate to be processed in the processing chamber; and a lower electrode that supports the electrostatic chuck and is supplied with bias voltage high-frequency power,
a plurality of impedance adjustment units including a plurality of capacitive elements provided between the plurality of partial windows and ground, and adjusting impedance between the plurality of partial windows and ground;
A method for detecting a failure of the plurality of impedance adjustment units, comprising:
applying a DC voltage to the electrostatic chuck;
starting to supply at least one of the high-frequency power for the source and the high-frequency power for the bias voltage;
a step of steadily supplying the high-frequency power for the source and the high-frequency power for the bias voltage;
measuring a capacitive element voltage applied to each of the plurality of capacitive elements while the substrate to be processed is processed;
a step of determining a failure of the plurality of impedance adjustment units based on a comparison result between the capacitive element voltage of each of the plurality of capacitive elements and a predetermined threshold;
A failure detection method comprising: each of the plurality of capacitive elements is in a short-circuited state at the time of failure,
In the step of determining the failure, an impedance adjustment unit including a capacitive element whose capacitive element voltage does not exceed the threshold is determined to be a failure.
The failure detection method according to claim 1. The step of measuring the capacitive element voltage includes measuring the capacitive element voltage applied to each of the plurality of capacitive elements while the substrate to be processed is subjected to a process consisting of a plurality of processing steps;
In the step of determining the failure, an impedance adjustment unit including a capacitive element in which the capacitive element voltage measured over one or more of the plurality of processing steps does not exceed the threshold value is determined to be a failure.
The failure detection method according to claim 2. The step of judging the failure includes at least the time of starting the application of the DC voltage, the time of starting the supply of the high frequency power for the source, the time of the steady supply of the high frequency power for the source, the time of starting the supply of the high frequency power for the bias voltage, and the time of starting the supply of the high frequency power for the bias voltage. Determining failure of the plurality of impedance adjustment units based on the capacitive element voltage measured at one or more of the time when the bias voltage high-frequency power is steadily supplied and when the application of the DC voltage is stopped. do,
The failure detection method according to any one of claims 1 to 3. The step of determining the failure includes comparing the capacitive element voltage with the threshold value for each of the capacitive elements connected to each of the plurality of partial windows, and based on the comparison result for each capacitive element, the capacitive element Determining a failure for each of the impedance adjustment units included;
The failure detection method according to any one of claims 1 to 4. identifying, among the plurality of partial windows, a partial window connected to the capacitive element for which the capacitive element voltage did not exceed the threshold;
The failure detection method according to any one of claims 1 to 5. a processing container; a metal window that divides the processing container into an antenna chamber and a processing chamber; a metal window having a plurality of partial windows; an electrostatic chuck that electrostatically attracts the substrate to be processed in the processing chamber; a lower electrode that supports the electrostatic chuck and is supplied with bias voltage high-frequency power; and the plurality of partial windows and a ground. a plurality of impedance adjustment units that include a plurality of capacitive elements provided therebetween and adjust impedance between the plurality of partial windows and ground; and a control unit;
The control unit
applying a DC voltage to the electrostatic chuck;
starting to supply at least one of the high-frequency power for the source and the high-frequency power for the bias voltage;
a step of steadily supplying the high-frequency power for the source and the high-frequency power for the bias voltage;
measuring a capacitive element voltage applied to each of the plurality of capacitive elements while the substrate to be processed is processed;
a step of determining a failure of the plurality of impedance adjustment units based on a comparison result between the capacitive element voltage of each of the plurality of capacitive elements and a predetermined threshold;
Plasma processing equipment that controls

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