JP2023039050A - Switching control circuit and power supply circuit - Google Patents

Abstract

To provide a switching control circuit capable of accurately detecting a state of a load, and a power supply circuit.SOLUTION: A switching control circuit includes: a transformer including a primary coil and a secondary coil; a first and a second transistors for controlling a current of the primary coil; and a resonance circuit including the primary coil and a first capacitor, and controls switching of a first and a second transistors of a power supply circuit that generates an output voltage of a target level on a secondary side. The switching control circuit includes: an averaging circuit for averaging a first voltage Vis according to a resonance current flowing in a first period in the power supply circuit in a cycle based on a setting signal to output it as a second voltage Vca indicating a load current flowing in a load of the power supply circuit; a setting circuit for outputting a setting signal N for increasing a cycle when the load current increases based on the second voltage; and a drive signal output circuit for outputting drive signals Vdr1 and Vdr2 for driving the first and the second transistors based on a feedback voltage according to the output voltage, the second voltage, and the setting signal.SELECTED DRAWING: Figure 2

Description

The present invention relates to switching control circuits and power supply circuits.

A switching control circuit that controls an LLC current resonance type converter may include a load detection circuit that detects the state of the load based on the resonance current (for example, Patent Documents 1 and 2).

Japanese Patent No. 6229804 JP 2019-193447 A

By the way, the load detection circuit described above generates a detection voltage representing the state of the load based on the resonance current. Also, in general, the load detection circuit amplifies the resonance current with a predetermined gain to generate a detection voltage. Therefore, when the gain is large, the detected voltage may be saturated. On the other hand, if the gain is reduced, it may become difficult to detect the detection voltage when the resonance current is small.

SUMMARY OF THE INVENTION An object of the present invention is to provide a switching control circuit capable of accurately detecting the state of a load.

A switching control circuit according to the present invention for solving the above-described problems includes a transformer including a primary coil and a secondary coil, first and second transistors for controlling the current of the primary coil, the primary coil and the secondary coil. a resonant circuit including a capacitor, and a switching control circuit for controlling switching of the first and second transistors of a power supply circuit for generating an output voltage of a target level on a secondary side, wherein the first transistor in the power supply circuit comprises: an averaging circuit for averaging a first voltage corresponding to a resonant current flowing for a period with a period based on a set signal and outputting a second voltage indicating a load current flowing in a load of the power supply circuit; a setting circuit for outputting the setting signal for lengthening the cycle based on the second voltage; a feedback voltage corresponding to the output voltage; a feedback voltage corresponding to the output voltage; and a drive signal output circuit that outputs a drive signal for driving the second transistor.

A power supply circuit according to the present invention for solving the above-described problems includes a transformer including a primary coil and a secondary coil, first and second transistors for controlling the current of the primary coil, the primary coil and the first A power supply circuit for generating an output voltage of a target level on a secondary side, comprising: a resonance circuit including a capacitor; and a switching control circuit for controlling switching of the first and second transistors, wherein the switching control circuit comprises: an averaging circuit for averaging a first voltage corresponding to a resonance current flowing in the power supply circuit for a first period with a period based on a setting signal and outputting a second voltage indicating a load current flowing in a load of the power supply circuit; a setting circuit for outputting the setting signal for lengthening the cycle when the load current increases based on the second voltage; a feedback voltage corresponding to the output voltage; the second voltage; and the setting signal. a drive signal output circuit for outputting a drive signal for driving the first and second transistors according to the first and second transistors.

According to the present invention, it is possible to provide a switching control circuit that can accurately detect the state of a load.

1 is a diagram showing an example of a switching power supply circuit 10a; FIG. It is a figure which shows an example of control IC40a. 6 is a diagram showing an example of a setting circuit 62; FIG. 6 is a diagram showing an example of an averaging circuit 65; FIG. 8 is a flow chart showing an example of an operation of an output circuit 84; 4 is a diagram showing an example of operation of a control circuit 91; FIG. 4 is a diagram showing the relationship between voltage Vca and voltage Vis in the control IC 40a; FIG. FIG. 10 is a diagram showing the relationship between the thinning number N, the voltage Vca, and the signal Vload; 4 is a diagram showing an example of drive signals Vdr1 and Vdr2 when the load 11 is in a heavy load state; FIG. 4 is a diagram showing an example of drive signals Vdr1 and Vdr2 when the load 11 is in a light load state; FIG. FIG. 10 is a diagram showing an example of the operation of the control IC 40a when N=0 (gain of 1.0); FIG. 10 is a diagram showing an example of the operation of the control IC 40a when N=1 (gain of 0.5); FIG. 10 is a diagram showing the relationship between the voltage Vca and the voltage Vis in the control IC 40a when a modification of the setting circuit 62 is used; FIG. 10 is a diagram showing the relationship between the voltage Vca and the voltage Vis in the control IC 40a when a modification of the setting circuit 62 is used; FIG. 10 is a diagram showing the relationship between the voltage Vca and the voltage Vis in the control IC 40a when a modification of the setting circuit 62 is used; 6 is a diagram showing an example of an averaging circuit 67; FIG. 3 is a diagram showing an example of a switching power supply circuit 10b; FIG. It is a figure which shows an example of control IC40b.

At least the following matters will become apparent from the descriptions of this specification and the accompanying drawings.

=====This Embodiment=====
<<<outline of switching power supply circuit 10a>>>
FIG. 1 is a diagram showing an example of the configuration of a switching power supply circuit 10a that is an embodiment of the present invention. The switching power supply circuit 10a is an LLC current resonance type power supply circuit that generates an output voltage Vout of a target level in a load 11 from a predetermined input voltage Vin.

The switching power supply circuit 10a includes capacitors 20, 21, 22, 32, a resistor 23, NMOS transistors 24, 25, a transformer 26, a control block 27, diodes 30, 31, a constant voltage circuit 33, and a light emitting diode 34. be.

The capacitor 20 stabilizes the voltage between the power supply line to which the input voltage Vin is applied and the ground line on the ground side, and removes noise and the like. Note that the input voltage Vin is a DC voltage of a predetermined level. The capacitor 21 is a so-called resonant capacitor that forms a resonant circuit together with leakage inductance between the primary coil L1 and the secondary coils L2 and L3. Note that the capacitor 21 corresponds to the "first capacitor".

The capacitor 22 and the resistor 23 form a detection circuit that divides and detects the resonance current Icr flowing through the capacitor 21 .

Also, the resistor 23 generates a voltage Vis based on a current obtained by shunting the resonance current Icr. Therefore, the voltage Vis becomes a voltage corresponding to the resonance current Icr. The resonance current Icr when the resonance current Icr flows in the direction of the arrow shown in FIG. 1 is referred to as a positive resonance current Icr, and the voltage Vis in this case is assumed to be a positive voltage. Also, when the resonance current Icr flows in the direction of the arrow, that is, when the resonance current Icr flows in the order of the primary coil L1, the capacitor 22, and the resistor 23, the direction of the resonance current Icr is positive. Also, when the resonance current Icr flows in the direction opposite to the direction of the arrow, that is, when the resonance current Icr flows in the order of the resistor 23, the capacitor 22, and the primary coil L1, the direction of the resonance current Icr is negative.

The NMOS transistor 24 is a high-side power transistor, and the NMOS transistor 25 is a low-side power transistor. Specifically, the NMOS transistors 24 and 25 are connected in series between a node to which the input voltage Vin is applied and a node to which the ground voltage is applied. In this embodiment, the NMOS transistors 24 and 25 are used as switching elements, but PMOS transistors and bipolar transistors may be used, for example. The NMOS transistor 24 corresponds to the "first transistor", and the NMOS transistor 25 corresponds to the "second transistor".

The transformer 26 includes a primary coil L1, secondary coils L2 and L3, and an auxiliary coil La. The primary coil L1, the secondary coils L2 and L3, and the auxiliary coil La are insulated. In the transformer 26, voltages are generated in the secondary coils L2 and L3 on the secondary side and the auxiliary coil La in accordance with the change in the voltage across the primary coil L1 on the primary side.

One end of the primary coil L 1 is connected to the source of the NMOS transistor 24 and the drain of the NMOS transistor 25 , and the other end is connected to the source of the NMOS transistor 25 via the capacitor 21 .

Therefore, when the NMOS transistors 24 and 25 start switching, the voltages of the secondary coils L2 and L3 and the auxiliary coil La change. The primary coil L1 and the secondary coils L2 and L3 are electromagnetically coupled with different polarities, and the primary coil L1 and the auxiliary coil La are electromagnetically coupled with the same polarity.

The control block 27 is a circuit block for controlling switching of the NMOS transistors 24 and 25, and will be detailed later.

Diodes 30, 31 rectify the voltages of secondary coils L2, L3, and capacitor 32 smoothes the rectified voltages. As a result, a smoothed output voltage Vout is generated across the capacitor 32 . Note that the output voltage Vout becomes a DC voltage of the target level.

The constant voltage circuit 33 is a circuit that generates a constant DC voltage, and is configured using, for example, a shunt regulator.

The light emitting diode 34 is an element that emits light having an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 33, and constitutes a photocoupler together with a phototransistor 52, which will be described later. In this embodiment, the intensity of the light from the light emitting diode 34 increases as the level of the output voltage Vout increases.

<<<control block 27>>>
Control block 27 includes control IC 40 a , diode 50 , capacitors 51 , 53 , 54 , phototransistor 52 and resistor 55 . The control IC 40a corresponds to a "switching control circuit".

The control IC 40a is an integrated circuit that controls switching of the NMOS transistors 24 and 25, and has terminals VCC, GND, FB, IS, CA, HO, LO and VS.

A terminal VCC is a terminal to which a power supply voltage Vcc is applied for operating the control IC 40a. A terminal VCC is connected to the cathode of a diode 50 and a capacitor 51 having one end grounded. Then, the capacitor 51 is charged with the voltage from the auxiliary coil La of the transformer 26 and becomes the voltage Vcc. The control IC 40a is activated by applying a divided voltage of an input voltage Vin obtained by rectifying an AC input via a terminal (not shown), and after being activated, operates based on the power supply voltage Vcc.

A terminal GND is a terminal to which a ground voltage is applied, and is connected to, for example, a housing of a device in which the switching power supply circuit 10a is provided.

A terminal FB is a terminal for generating a feedback voltage Vfb corresponding to the output voltage Vout, and is connected to a phototransistor 52 and a capacitor 53 . The phototransistor 52 causes a bias current I1 having a magnitude corresponding to the intensity of the light from the light emitting diode 34 to flow from the terminal FB to the ground, and the capacitor 53 removes noise between the terminal FB and the ground. provided in Therefore, the phototransistor 52 operates as a transistor that generates a sink current.

A terminal IS is a terminal for detecting the current value of the resonance current of the primary coil L1. Here, a voltage corresponding to the current value of the resonance current of the primary coil L1 is generated at the node to which the capacitor 22 and the resistor 23 are connected. Therefore, a voltage Vis corresponding to the current value of the resonance current of the primary coil L1 is applied to the terminal IS. Note that the voltage Vis corresponds to the "first voltage".

A terminal CA is a terminal to which a voltage Vca generated based on the resonance current of the primary coil L1 and corresponding to the input power of the switching power supply circuit 10a is applied. Although details will be described later, a capacitor 54 and a resistor 55 are connected to the terminal CA. Also, the voltage Vca corresponds to the "second voltage", and the capacitor 54 corresponds to the "second capacitor".

A terminal HO is a terminal to which a driving signal Vdr1 for driving the NMOS transistor 24 is output, and the gate of the NMOS transistor 24 is connected.

A terminal LO is a terminal to which a driving signal Vdr2 for driving the NMOS transistor 25 is output, and the gate of the NMOS transistor 25 is connected.

A terminal VS is a terminal to which a voltage of a connection node to which the source terminal of the NMOS transistor 24 and the drain terminal of the NMOS transistor 25 are connected is applied. When transistor 25 is turned on, ground voltage is applied. Note that the terminal VS corresponds to the "first terminal".

The potential of the voltage Vs of the terminal VS is the reference potential of the output voltage of a bootstrap circuit (not shown) for turning on the NMOS transistor 24 when the input voltage Vin is applied to the terminal VS.

<<<details of the control IC 40a>>>
FIG. 2 is a diagram showing an example of the control IC 40a. The control IC 40a is an integrated circuit that switches the NMOS transistors 24 and 25 based on the magnitude of the resonance current Icr. The control IC 40 a includes resistors 60 , 63 and 64 , a drive signal output circuit 61 , a setting circuit 62 , an averaging circuit 65 and an overload detection circuit 66 . Note that the terminal VCC is omitted here for convenience.

== Resistance 60 ==
Resistor 60 generates feedback voltage Vfb based on bias current I1 from phototransistor 52 . A predetermined voltage Vdd is applied to one end of the resistor 60, and the other end is connected to the terminal FB. Therefore, if the resistance value of the resistor 60 is "R", the feedback voltage Vfb generated at the terminal FB is expressed by Equation (1).

Vfb=Vdd−R×I1 (1)
As described above, in this embodiment, the current value of the bias current I1 increases as the output voltage Vout increases. Therefore, when the output voltage Vout increases, the feedback voltage Vfb decreases.

==Drive signal output circuit 61==
The drive signal output circuit 61 outputs drive signals Vdr1 and Vdr2 for driving the NMOS transistors 24 and 25, respectively. Specifically, the drive signal output circuit 61 outputs the drive signals Vdr1 and Vdr2 based on the feedback voltage Vfb, the voltage Vca, and the thinning number N, which will be described later. The drive signal output circuit 61 includes an oscillation circuit 70 , a detection circuit 71 and a drive circuit 72 .

=== Oscillation circuit 70 ===
The oscillation circuit 70 is a voltage-controlled oscillation circuit that outputs an oscillation signal Vosc for switching the NMOS transistors 24 and 25 to the drive circuit 72 based on the input feedback voltage Vfb. The transmission signal Vosc is, for example, a signal whose high level (hereinafter referred to as "H" level) duty ratio is 50%. Note that the oscillator circuit 70 outputs the oscillation signal Vosc with a high frequency when the level of the voltage Vfb becomes low. Note that the oscillation signal Vosc corresponds to a "second oscillation signal".

=== Detection circuit 71 ===
The detection circuit 71 outputs a signal Vload indicating the state of the load 11 to the drive circuit 72 and the overload detection circuit (OLP) 66 based on the voltage Vca and the thinning number N. FIG. The signal Vload is a signal representing a digital value of several bits converted from the voltage Vca converted into a digital value by an analog/digital converter (not shown) and the thinning number N.

Further, the details of the detection circuit 71 and the details of the relationship between the voltage Vca, the thinning number N, and the signal Vload will be described later.

===Drive Circuit 72===
The drive circuit 72 drives the NMOS transistors 24 and 25 based on the transmission signal Vosc and the signal Vload from the detection circuit 71 . The details of the drive circuit 72 will be described later.

== Setting circuit 62 ==
The setting circuit 62 outputs a thinning number N that controls the rate of increase (or gain) of the voltage Vca with respect to the voltage Vis based on the voltage Vca. Specifically, the setting circuit 62 causes the averaging circuit 65, which will be described later, to average the voltage Vis in a cycle (hereinafter referred to as a cycle TA) based on the thinning number N and output it as a voltage Vca. When the load current Iout increases and the voltage Vca rises, the setting circuit 62 increases the thinning number N so as to lengthen the period TA. On the other hand, when the load current Iout decreases and the voltage Vca decreases, the setting circuit 62 decreases the thinning number N so as to shorten the period TA.

The setting circuit 62 includes comparators 80 and 82, reference voltage circuits 81 and 83, and an output circuit 84, as shown in FIG. Comparators 80 and 82 are comparators that compare the level of voltage Vca with predetermined level Vca_h or predetermined level Vca_l, and output circuit 84, which will be described later, sets thinning number N based on the comparison result.

===comparators 80, 82===
When the amplitude of the voltage Vis increases and the level of the voltage Vca exceeds the predetermined level Vca_h, the comparator 80 outputs a comparison result of "H" level. On the other hand, when the level of the voltage Vca is lower than the predetermined level Vca_h, the comparator 80 outputs a comparison result of "L" level. The predetermined level Vca_h is output by a reference voltage circuit 81 that operates based on the power supply voltage Vdd.

Further, when the amplitude of the voltage Vis decreases and the level of the voltage Vca becomes lower than the predetermined level Vca_l, the comparator 82 outputs a comparison result of "H" level. On the other hand, when the level of the voltage Vca is higher than the predetermined level Vca_l, the comparator 82 outputs a comparison result of "L" level. The predetermined level Vca_l is output by a reference voltage circuit 83 that operates based on the power supply voltage Vdd. Also, in the present embodiment, the predetermined level Vca_l is a level (eg, 2.5 V) that is half the predetermined level Vca_h (eg, 5 V).

Further, the comparator 80 corresponds to the "first comparison circuit", and the comparator 82 corresponds to the "second comparison circuit". Further, the predetermined level Vca_h corresponds to the "first reference voltage", and the predetermined level Vca_l corresponds to the "second reference voltage". The reference voltage circuit 81 corresponds to the "first reference voltage output circuit", and the reference voltage circuit 83 corresponds to the "second reference voltage output circuit".

=== Output circuit 84 ===
The output circuit 84 is an up/down counter that changes the count value based on the comparison results of the comparators 80 and 82 and outputs the result as the thinning number N. FIG. Specifically, when the comparator 80 outputs a comparison result of "H" level, the output circuit 84 increments the thinning number N. On the other hand, when the comparator 82 outputs the "H" level comparison result, the output circuit 84 decrements the thinning number N. However, when the thinning number N is 0, the output circuit 84 does not decrement the thinning number N even if the comparator 82 outputs an "H" level comparison result.

Although the details will be described later, when the thinning number N is incremented, the cycle (cycle TA) averaged by the averaging circuit 65 is doubled. On the other hand, when the thinning number N is decremented, the cycle (cycle TA) averaged by the averaging circuit 65 is halved. Note that the thinning number N corresponds to a "setting signal".

== resistors 63, 64 ==
Returning to FIG. 2, the resistors 63 and 64 divide the voltage Vs to generate the voltage Vs_div at the connection point. When the NMOS transistor 24 is turned on and the NMOS transistor 25 is turned off, the voltage Vs becomes the input voltage Vin, and when the NMOS transistor 24 is turned off and the NMOS transistor 25 is turned on, the voltage Vs becomes the ground voltage. That is, depending on whether the NMOS transistors 24 and 25 are turned on or off, the voltage Vs becomes either the input voltage Vin or the ground voltage. Accordingly, the voltage Vs_div changes between the voltage corresponding to the input voltage Vin and the ground voltage by turning on/off the NMOS transistors 24 and 25 .

== Averaging circuit 65 ==
The averaging circuit 65 averages the voltage Vis at a timing corresponding to the voltage Vs_div and outputs the voltage Vca. Specifically, the averaging circuit 65 averages the positive voltage Vis generated when the resonance current Icr flows in the positive direction at a period TA based on the timing corresponding to the voltage Vs_div and the thinning number N. . Then, the averaging circuit 65 outputs the averaged voltage as the voltage Vca indicating the load current Iout.

The averaging circuit 65 includes a comparator 90, a control circuit 91, and a charging/discharging circuit 92, as shown in FIG.

===Comparator 90===
The comparator 90 is a circuit that outputs a signal clk that changes like the voltage Vs that changes between the input voltage Vin and the ground voltage. Specifically, when the NMOS transistor 24 is turned on and the voltage Vs_div is higher than the reference voltage Vref, the comparator 90 outputs the "H" level signal clk. On the other hand, when the NMOS transistor 25 is turned on and the voltage Vs_div is lower than the reference voltage Vref, the comparator 90 outputs the "L" level signal clk.

Further, as described above, when the NMOS transistor 24 is turned on, the resonance current Icr flows in the positive direction, and when the NMOS transistor 25 is turned on, the resonance current Icr flows in the negative direction. Therefore, when the resonance current Icr flows in the positive direction, the signal clk becomes "H" level, and when the resonance current Icr flows in the negative direction, the signal clk becomes "L" level. The comparator 90 corresponds to the "oscillation signal output circuit", and the signal clk corresponds to the "first oscillation signal".

The period during which the "H" level signal clk is output corresponds to the "first period", and the period during which the "L" level signal clk is output corresponds to the "second period".

===control circuit 91====
The control circuit 91 outputs the signal sw_ctrl based on the thinning number N and the signal clk. Specifically, the control circuit 91 thins out the "H" level signal included in the signal clk based on the thinning number N corresponding to the voltage Vca, and outputs the thinned out signal as the signal sw_ctrl.

In other words, the control circuit 91 shortens or extends the cycle in which the control signal sw_ctrl is at the "H" level, based on the thinning number N. FIG. Further, the signal sw_ctrl controls the rate of increase of the voltage Vca with respect to the voltage Vis when the charging/discharging circuit 92, which will be described later, generates the voltage Vca.

How the control circuit 91 outputs the signal sw_ctrl based on the thinning number N will be described later. Note that the control circuit 91 corresponds to a "control signal output circuit", and the signal sw_ctrl corresponds to a "control signal". The "H" level corresponds to the "first logic level", and the "L" level corresponds to the "second logic level".

=== Charge/Discharge Circuit 92 ===
The charging/discharging circuit 92 averages the voltage Vis corresponding to the resonance current of the primary coil L1 detected at the terminal IS by the capacitor 54 connected to the terminal CA, and outputs it as the voltage Vca indicating the load current Iout.

Note that the charge/discharge circuit 92 averages the voltage Vis based on the positive resonance current Icr based on the signal sw_ctrl from the control circuit 91 .

Specifically, the charge/discharge circuit 92 switches the voltage of the node A to the voltage Vis of the terminal IS or the ground voltage based on the signal sw_ctrl. Then, the charging/discharging circuit 92 charges or discharges the capacitor 54 connected to the terminal CA via the resistor 103, and outputs the voltage Vca.

The current value of the resonance current Icr of the primary coil L1 increases according to the input power of the switching power supply circuit 10a. Also, the input power of the switching power supply circuit 10 a increases according to the power consumed by the load 11 . Therefore, the voltage Vca increases as the load 11 becomes heavier (that is, as the load current Iout of the load 11 increases).

The charge/discharge circuit 92 includes switches 100 and 102 , an inverter 101 and a resistor 103 .

The switch 100 is an element that is turned on when the control circuit 91 outputs the "H" level signal sw_ctrl. When switch 100 is turned on, voltage Va at node A to which switches 100 and 102 are connected becomes voltage Vis at terminal IS.

The switch 102 is an element that is turned on when the control circuit 91 outputs the "L" level signal sw_ctrl and the inverter 101 outputs the "H" level signal. Then, when the switch 102 is turned on, the voltage Va of the node A becomes the ground voltage.

A resistor 103 is connected between node A and terminal CA, and together with capacitor 54 connected to terminal CA, resistor 103 constitutes an RC integration circuit that operates with a "time constant τ". Assuming that the resistance value of the resistor 103 is R1 and the capacitance value of the capacitor 54 is C1, "time constant τ"=R1×C1. The “time constant τ” is assumed to be sufficiently longer than the period of the drive signals Vdr1 and Vdr2 that drive the NMOS transistors 24 and 25. FIG.

Therefore, when the control circuit 91 outputs the “H” level signal sw_ctrl, the charging/discharging circuit 92 charges the capacitor 54 via the resistor 103 with the voltage Vis based on the positive resonance current Icr corresponding to the power consumption of the load 11. do.

On the other hand, when the control circuit 91 outputs the "L" level signal sw_ctrl, the charging/discharging circuit 92 discharges the capacitor 54 via the resistor 103 with the ground voltage.

Thereby, the charging/discharging circuit 92 can average the voltage Vis and output the voltage Vca indicating the load current Iout.

Also, resistors 55 and 103 form a voltage dividing circuit. Therefore, when the resistance value of the resistor 55 is large, the voltage applied to the capacitor 54 becomes large, and as a result, the rate of increase of the voltage Vca with respect to the voltage Vis becomes large.

On the other hand, when the resistance value of the resistor 55 is small, the voltage applied to the capacitor 54 is relatively small compared to when the resistance value of the resistor 55 is large. become smaller. Note that the resistor 55 may not be connected to the terminal CA.

<<Operation of Output Circuit 84 and Averaging Circuit 65>>
FIG. 5 is a flow chart showing an example of the operation of the output circuit 84. As shown in FIG. FIG. 6 is a diagram for explaining what kind of signal sw_ctrl is output by the control circuit 91 according to the thinning number N. As shown in FIG. In FIG. 5, first, when the control IC 40a is activated, the output circuit 84 sets the thinning number N to 0 (S100).

When the thinning number N is 0, the control circuit 91 outputs the signal sw_ctrl as shown in FIG. 6A. Specifically, when the thinning number N is 0, the control circuit 91 outputs the signal clk as the signal sw_ctrl.

At this time, the rate of increase of the voltage Vca with respect to the voltage Vis becomes the rate of increase determined by the resistor 55, and this rate of increase is assumed to be a gain of 1.0 times. Then, the output circuit 84 increases the gain by 1.0 as shown in FIG. 7 until the level of the voltage Vca reaches the predetermined level Vca_h.

When the gain is 1.0 times, the charge/discharge circuit 92 of FIG. 4 applies the voltage Vis to the terminal CA each time the resonance current Icr flows in the positive direction. Therefore, as the voltage Vis increases, the voltage Vca increases at an increasing rate determined by the resistor 55 as shown in FIG.

Then, as shown in FIG. 5, the comparator 80 compares whether the level of the voltage Vca is lower than the predetermined level Vca_h (S110).

When the comparator 80 indicates that the level of the voltage Vca is lower than the predetermined level Vca_h (S110: Yes), the output circuit 84 leaves the thinning number N at zero.

On the other hand, when the comparator 80 indicates that the level of the voltage Vca is higher than the predetermined level Vca_h (S110: No), the output circuit 84 sets the thinning number N to 1 (S120).

When the thinning number N is 1, the control circuit 91 outputs the signal sw_ctrl as shown in FIG. 6B. Specifically, when the thinning number N is 1, the control circuit 91 thins out the "H" level signal contained in the signal clk once while the "H" level signal clk is input twice. , outputs the “H” level signal sw_ctrl once. Therefore, the period TA is twice as long as the period when the thinning number N is zero.

At this time, the rate of increase of the voltage Vca with respect to the voltage Vis is half the rate of increase determined by the resistor 55, and this rate of increase is assumed to be a gain of 0.5 times. That is, the gain is determined according to the period TA. Then, the output circuit 84 increases the gain by 0.5 as shown in FIG. 7 until the level of the voltage Vca reaches the predetermined level Vca_h.

When the gain is 0.5 times, the charge/discharge circuit 92 of FIG. 4 applies the voltage Vis to the terminal CA each time the resonance current Icr flows twice in the positive direction. Therefore, as the voltage Vis increases, the voltage Vca increases at an increase rate 1/2 times the increase rate determined by the resistor 55 as shown in FIG.

In this case, the period TA is double that when the thinning number N is 0, so the level of the voltage Vca drops to the predetermined level Vca_l as shown in FIG. This is because the period TA is doubled and the number of times the positive voltage Vis is averaged over a predetermined period is halved.

Then, as shown in FIG. 5, comparators 80 and 82 compare whether the level of voltage Vca is lower than predetermined level Vca_h and higher than predetermined level Vca_l (S130).

When the comparators 80 and 82 indicate that the level of the voltage Vca is lower than the predetermined level Vca_h and higher than the predetermined level Vca_l (S130: Yes), the output circuit 84 leaves the thinning number N at one.

When the comparator 82 indicates that the level of the voltage Vca is lower than the predetermined level Vca_l, the output circuit 84 sets the thinning number N to 0 (S100).

In this case, the period TA is 1/2 that when the thinning number N is 1, so the level of the voltage Vca rises to the predetermined level Vca_h as shown in FIG. This is because the period TA is halved and the number of times the positive voltage Vis is averaged during a given period is doubled.

Then, when the thinning number N becomes 0 (that is, the gain is 1.0 times), the charging/discharging circuit 92 of FIG. 4 applies the voltage Vis to the terminal CA each time the resonance current Icr flows in the positive direction. Therefore, as the voltage Vis increases, the voltage Vca increases at an increasing rate determined by the resistor 55 . Then, compared to the increase rate when the thinning number N is 1 (that is, the gain is 0.5 times), the increase rate is , the rate of increase doubles as shown in FIG.

Further, as shown in FIG. 5, when the comparator 80 indicates that the level of the voltage Vca is higher than the predetermined level Vca_h, the output circuit 84 sets the thinning number N to 2 (S140).

Then, when the thinning number N is 2, the control circuit 91 outputs the signal sw_ctrl as shown in (C) of FIG. Specifically, when the thinning number N is 2, the control circuit 91 thins out the "H" level signal included in the signal clk three times while the "H" level signal clk is input four times. , outputs the “H” level signal sw_ctrl once. Therefore, the period TA is twice as long as the period when the thinning number N is one.

At this time, the rate of increase of the voltage Vca with respect to the voltage Vis is 1/4 of the rate of increase determined by the resistor 55, and this rate of increase is assumed to be a gain of 0.25 times. Then, the output circuit 84 increases the gain by 0.25 as shown in FIG. 7 until the level of the voltage Vca reaches the predetermined level Vca_h.

When the gain is 0.25 times, the charging/discharging circuit 92 of FIG. 4 applies the voltage Vis to the terminal CA each time the resonance current Icr flows in the positive direction four times. Therefore, as the voltage Vis increases, the voltage Vca increases at an increase rate 1/4 times the increase rate determined by the resistor 55 as shown in FIG.

Then, as shown in FIG. 5, the comparator 82 compares whether the level of the voltage Vca is higher than the predetermined level Vca_l (S150).

When the comparator 82 indicates that the level of the voltage Vca is higher than the predetermined level Vca_l (S150: Yes), the output circuit 84 leaves the thinning number N at two.

When the comparator 82 indicates that the level of the voltage Vca is lower than the predetermined level Vca_l (S150: No), the output circuit 84 sets the thinning number N to 1 (S120).

In this case, the period TA is 1/2 that when the thinning number N is 2, so the level of the voltage Vca rises to the predetermined level Vca_h as shown in FIG.

=== Detection circuit 71 ===
Returning to FIG. 2, as described above, the detection circuit 71 outputs the signal Vload indicating the state of the load 11 to the drive circuit 72 and the overload detection circuit (OLP) 66 based on the voltage Vca and the thinning number N. do.

Specifically, the detection circuit 71 detects the state of the load 11 based on the voltage Vca that changes based on the thinning number N and the thinning number N, and sends it to the drive circuit 72 and the overload detection circuit 66 as a signal Vload. Output.

Note that the signal Vload is a signal indicating a digital value of several bits as described above, and as shown in FIG. is a signal. That is, the signal Vload is a signal obtained by converting the voltage Vca whose rate of increase with respect to the voltage Vis changes depending on the thinning number N into a voltage value (indicated by a dashed line, for example) whose rate of increase with respect to the voltage Vis is constant.

Further, when the load 11 is in a heavy load state, the detection circuit 71 outputs a signal Vload indicating that the load 11 is in a heavy load state. On the other hand, when the load 11 is in a light load state, the detection circuit 71 outputs a signal Vload indicating that the load 11 is in a light load state. Note that the signal Vload corresponds to the "detection result".

Note that “the state of the load 11 is a heavy load” refers to, for example, a case where the current value of the load current Iout flowing through the load 11 is equal to or greater than a predetermined value (eg, 1 A). Further, "the state of the load 11 is light load" refers to, for example, the case where the current value of the load current Iout flowing through the load 11 is smaller than a predetermined value (eg, 1 A). Further, "the state of the load 11 is no load" refers to the case where the current value of the load current Iout flowing through the load 11 is extremely small or 0 (zero) A. Also, although the current value of the load current Iout for determining whether the state of the load 11 is heavy load or light load is, for example, 1 A, this current value can be set variously. This setting can be variously changed by setting a digital threshold value for discriminating the signal Vload by the drive circuit 72 that receives the signal Vload. The drive circuit 72 uses the signal Vload to determine whether the load is heavy or light.

===Drive Circuit 72===
Drive circuit 72 drives NMOS transistors 24 and 25 in FIG. Specifically, the drive circuit 72 causes the drive signals Vdr1 and Vdr2 to alternately go to the "H" level as shown in FIG. NMOS transistors 24 and 25 are switched in a continuous switching operation such that In this case, the drive circuit 72 does not stop the switching operation intermittently.

Further, the drive circuit 72 performs continuous switching operation and intermittent switching operation as shown in FIG. The NMOS transistors 24 and 25 are switched so that the stopping operation is repeated.

9 and 10, the drive circuit 72 is shown to output the drive signals Vdr1 and Vdr2 which are generated at a duty ratio of 50% according to the transmission signal Vosc and which alternately become "H" level. there is However, in practice, the drive circuit 72 has a dead time and outputs the drive signals Vdr1 and Vdr2 which are generated at a duty ratio of about 50% according to the transmission signal Vosc and which alternately become "H" level. In FIG. 10, the drive signals Vdrv1 and Vdrv2 have the same number of pulses during the switching operation, but this is merely an example, and the number of pulses may be different.

Here, the "dead time" means, for example, the period from when the "H" level driving signal Vdr1 becomes low level (hereinafter referred to as "L" level) to when the driving signal Vdr2 becomes "H" level. , and is a period during which both the drive signals Vdr1 and Vdr2 are at the "L" level.

== Overload Detection Circuit (OLP) 66 ==
An overload detection circuit (OLP) 66 detects (that is, determines) whether or not the load 11 is overloaded based on the signal Vload from the detection circuit 71 . Specifically, the overload detection circuit 66 detects that the load 11 is overloaded based on the fact that the value of the signal Vload indicating the state of the load 11, that is, the value of the load current Iout is equal to or greater than a predetermined value. detect that there is Various thresholds may be set for detecting whether the load 11 is overloaded. This setting can be variously changed by setting a digital threshold value for determining the signal Vload by the overload detection circuit 66 that receives the signal Vload. Whether or not there is an overload is determined by the overload detection circuit 66 using the signal Vload.

When detecting that the load 11 is overloaded, the overload detection circuit 66 outputs a signal olp to the drive circuit 72 to turn off the NMOS transistors 24 and 25 . Note that the overload detection circuit 66 corresponds to a "determination circuit".

<<Operation of control IC 40a>>
==When the thinning number N is 0==
FIG. 11 is a diagram showing an example of the operation of the control IC 40a when the thinning number N is zero.

At time t0, the drive circuit 72 of the control IC 40a outputs the "L" level drive signal Vdr2, and the NMOS transistor 25 is turned off.

After that, the negative resonance current Icr causes the voltage Vs of the terminal VS to rise and become half the input voltage Vin at time t1. Accordingly, the resistors 63 and 64 in FIG. 2 generate a voltage Vs_div corresponding to the voltage Vs, and the comparator 90 in FIG. 4 outputs the "H" level signal clk. Also, since the thinning number N is 0, the control circuit 91 outputs the signal clk as the signal sw_ctrl.

At this time, the switch 100 in FIG. 4 is turned on based on the "H" level signal sw_ctrl, and the voltage Va of the node A becomes the voltage Vis.

At time t2 when the dead time has elapsed from time t0, the drive circuit 72 outputs the "H" level drive signal Vdr1, and the NMOS transistor 24 is turned on. Then, the voltage Vis corresponding to the resonance current Icr flowing in the positive direction becomes positive.

At time t3 after the drive circuit 72 outputs the "L" level drive signal Vdr1, the positive resonance current Icr causes the voltage Vs of the terminal VS to drop to half the input voltage Vin. Accordingly, resistors 63 and 64 in FIG. 2 generate voltage Vs_div corresponding to voltage Vs, and comparator 90 in FIG. 4 outputs signal clk of "L" level.

At this time, the switch 102 in FIG. 4 is turned on based on the "L" level signal sw_ctrl, and the voltage Va of the node A becomes the ground voltage. After time t4, the same operation is repeated. Therefore, period TA is a period from time t1 to time t4, and charging/discharging circuit 92 outputs voltage Vca based on voltage Vis. As a result, as described above, the voltage Vca is output with a gain of 1.0 times the magnitude of the voltage Vis.

==When the thinning number N is 1==
FIG. 12 is a diagram showing an example of the operation of the control IC 40a when the thinning number N is one.

The operation from time t10 to time t13 is the same as the operation from time t0 to time t3 in FIG. Note that the voltage Vis is assumed to be twice the voltage in the case of FIG.

At time t14, the negative resonance current Icr causes the voltage Vs of the terminal VS to rise to half the input voltage Vin. Accordingly, the resistors 63 and 64 in FIG. 2 generate a voltage Vs_div corresponding to the voltage Vs, and the comparator 90 in FIG. 4 outputs the "H" level signal clk. However, since the thinning number N is 1, the control circuit 91 does not output the signal clk as the signal sw_ctrl. Therefore, the voltage Va of node A remains at the ground voltage.

At time t15 after the drive circuit 72 of the control IC 40a outputs the "L" level drive signal Vdr1, the positive resonance current Icr causes the voltage Vs of the terminal VS to drop to half the input voltage Vin. . Accordingly, resistors 63 and 64 in FIG. 2 generate voltage Vs_div corresponding to voltage Vs, and comparator 90 in FIG. 4 outputs signal clk of "L" level.

At this time, the switch 102 in FIG. 4 is turned on based on the "L" level signal sw_ctrl, and the voltage Va of the node A remains at the ground voltage. After time t16, the same operation is repeated. Therefore, period TA is a period from time t11 to time t16, and charging/discharging circuit 92 outputs voltage Vca based on voltage Vis. As a result, as described above, the voltage Vca is output with a gain of 0.5 times the magnitude of the voltage Vis.

<<Modified Example of Setting Circuit 62>>
In the above-described embodiment, the period TA is doubled each time the level of the voltage Vca exceeds the predetermined level Vca_h and the thinning number N is incremented. By doubling the period TA, the level of the voltage Vca becomes a predetermined level Vca_l that is half the level of the predetermined level Vca_h.

In such a case, if the voltage Vca is affected by noise and fluctuates, the thinning number N may be incremented or decremented frequently. Therefore, in order to suppress the influence of noise, a predetermined level Vca_l_delta lower than the predetermined level Vca_l may be used instead of the predetermined level Vca_l. As a modified example of the setting circuit 62, the operation of the setting circuit 62 when using the predetermined level Vca_l_delta will be described below.

13 to 15 are diagrams showing the relationship between the voltage Vca and the voltage Vis in the control IC 40a when the modification of the setting circuit 62 is used.

Specifically, in the setting circuit 62 shown in FIG. 3, the reference voltage circuit 83 outputs half the predetermined level Vca_h (eg, 5V) as the predetermined level Vca_l (eg, 2.5V). However, in a modification of the setting circuit 62, the reference voltage circuit 83 outputs a level lower than half the predetermined level Vca_h as the predetermined level Vca_l_delta (eg, 2.4V).

How the control IC 40a outputs the voltage Vca in such a case will be described below. 13 shows the operation when the state of the load 11 changes from no load to heavy load, and FIG. 14 shows the operation when the state of the load 11 changes from heavy load to no load. Moreover, FIG. 15 is the figure drawn combining FIG. 13 and FIG.

First, a case where the state of the load 11 changes from no load to heavy load will be described with reference to FIG. When the voltage Vis increases while the setting circuit 62 is outputting the thinning number N of "0", the averaging circuit 65 outputs a gradually increasing voltage Vca. Then, the setting circuit 62 outputs the thinning number N of "0" until the level of the voltage Vca reaches the predetermined level Vca_h.

After that, when the voltage Vis further increases, the averaging circuit 65 outputs an even larger voltage Vca. Therefore, the setting circuit 62 outputs the thinning number N of "1". As a result, the level of voltage Vca drops to a predetermined level Vca_l.

Then, the setting circuit 62 increases the thinning number N as the voltage Vis increases. Each time the thinning number N increases, the level of the voltage Vca decreases to a predetermined level Vca_l.

Next, a case where the state of the load 11 changes from heavy load to no load will be described with reference to FIG. If the voltage Vis decreases while the setting circuit 62 is outputting the thinning number N of, for example, "2", the averaging circuit 65 outputs a gradually decreasing voltage Vca. Then, the setting circuit 62 outputs the thinning number N of "2" until the level of the voltage Vca reaches the predetermined level Vca_l_delta.

After that, when the voltage Vis further decreases, the averaging circuit 65 outputs an even smaller voltage Vca. Therefore, the setting circuit 62 outputs the thinning number N of "1". As a result, the level of voltage Vca rises to level Vca_x below predetermined level Vca_h.

Then, as the voltage Vis decreases, the setting circuit 62 decreases the thinning number N. Each time the thinning number N decreases, the level of the voltage Vca rises to the level Vca_x below the predetermined level Vca_h. As a result, the setting circuit 62 does not output the original thinning number N again immediately after switching the thinning number N. FIG. Therefore, the setting circuit 62 does not frequently repeat the increment or decrement of the thinning number N, and the influence of noise on the voltage Vca is suppressed.

As shown in FIG. 15, in the modification of the setting circuit 62, when the voltage Vis increases, that is, when the state of the load 11 becomes heavy, and the level of the voltage Vca reaches a predetermined level Vca_h, the thinning number N varies. Then, when the thinning number N changes, the level of the voltage Vca drops to a predetermined level Vca_l.

On the other hand, as shown in FIG. 15, when the voltage Vis decreases, that is, when the load 11 becomes light, the thinning number N changes when the level of the voltage Vca reaches a predetermined level Vca_l_delta. Then, when the thinning number N changes, the level of the voltage Vca rises to the level Vca_x.

From the above, the level of the voltage Vca when the thinning number N changes and the level to which the voltage Vca reaches when the thinning number N changes are different when the state of the load 11 goes to heavy load and to light load. It varies from time to time. Therefore, even if the voltage Vis fluctuates due to noise, it is possible to prevent the thinning number N from frequently fluctuating and the voltage Vca from similarly fluctuating.

<<Modified Example of Averaging Circuit 65>>
FIG. 16 is a diagram showing an example of an averaging circuit 67 that is a modification of the averaging circuit 65. As shown in FIG. In addition, in FIG. 16, the same reference numerals are given to the same objects as in FIG.

The averaging circuit 67 further includes a level shift circuit (LS) 110 , a bias circuit (BIAS) 111 and a buffer circuit 112 . The level shift circuit 110 is provided between the terminal IS and the switch 100, and shifts the level of the voltage Va that changes around 0V (zero volt).

The level shift circuit 110 shifts the voltage Vis so that the center level of the voltage Vis becomes a predetermined level. Here, the "predetermined level" is, for example, a level (Vdd/2=2.5V) that is half the power supply voltage Vdd (eg, 5V).

Also, the level shift circuit 110 is, for example, a voltage dividing circuit in which the power supply voltage Vdd is applied to the high voltage side and the voltage Vis is applied to the low voltage side.

The bias circuit 111 is provided between the terminal GND and the switch 102 and applies a predetermined voltage (for example, 1 V) to the level of the ground voltage. Also, the bias circuit 111 is, for example, a voltage source that generates a predetermined voltage.

Buffer circuit 112 amplifies voltage Va at node A and outputs it as voltage Vca through resistor 103 . Also, the buffer circuit 112 is, for example, an arithmetic circuit including a plurality of operational amplifiers. Thereby, the averaging circuit 67 can average based on the voltage from the level shift circuit 110 corresponding to the voltage Vis and the predetermined voltage from the bias circuit 111, and can output the level of the voltage Vca within a desired range.

===== Other Embodiments =====
<<<outline of switching power supply circuit 10b>>>
FIG. 17 is a diagram showing an example of a switching power supply circuit 10b that is a modification of the switching power supply circuit 10a. In FIG. 17, the same reference numerals are assigned to the same objects as in FIG. Therefore, identical objects will not be described.

The switching power supply circuit 10b further includes resistors 56 and 57 that divide the voltage generated in the auxiliary winding La. A voltage Vvw is generated at the connection point of the resistors 56 and 57 . The control IC 40b further includes a terminal VW, and the voltage Vvw is applied to the terminal VW of the control IC 40b. The control IC 40b uses the voltage Vvw applied to the terminal VW to suppress so-called out-of-resonance.

Here, the primary coil L1 and the auxiliary coil La are electromagnetically coupled with the same polarity. Therefore, when the positive resonance current Icr flows through the primary coil L1, the voltage generated in the auxiliary coil La is a positive voltage. As a result, when the NMOS transistor 24 is turned on and the voltage Vs becomes the input voltage Vin, the auxiliary coil La also generates a positive voltage. Therefore, the voltage Vvw changes with the same polarity and phase as the voltage Vs.

<<<details of the control IC 40b>>>
FIG. 18 is a diagram showing an example of the control IC 40b. In FIG. 18, the same reference numerals are given to the same objects as in FIG. The same object will not be described again.

Averaging circuit 65 of FIG. 18 uses voltage Vvw instead of voltage Vs to generate signal sw_ctrl. Other circuits of the control IC 40b operate similarly to the circuits of the control IC 40a. Thereby, the control IC 40b can use the voltage Vvw instead of the voltage Vs to realize the same operation as the control IC 40a. Note that the terminal VW corresponds to the "second terminal".

===Summary===
The switching power supply circuit 10a of the present embodiment has been described above. The control IC 40 a includes an averaging circuit 65 , a setting circuit 62 and a drive signal output circuit 61 . The control IC 40a changes the rate of increase of the voltage Vca as the voltage Vis increases, that is, as the load current Iout increases. Since the control IC 40a outputs the voltage Vca at the highest rate of increase when the load 11 is in a state of no load, the control IC 40a can accurately detect the state of the load 11 even when the voltage Vis is small. Become. Therefore, the control IC 40a can accurately detect the state of the load.

The setting circuit 62 also includes comparators 80 and 82 and an output circuit 84 . Thereby, the control IC 40a can determine the thinning number N according to the change of the voltage Vca, and can change the rate of increase of the voltage Vca.

Further, the output circuit 84 outputs the thinning number N so as to change the period TA based on the voltage Vca. Thereby, the control IC 40a can change the rate of increase of the voltage Vca based on the voltage Vca.

The setting circuit 62 further includes reference voltage circuits 81 and 83 . Thereby, the control IC 40a can change the thinning number N with high accuracy.

Also, the output circuit 84 is an up/down counter. As a result, the output circuit 84 can output the thinning number N with a simple circuit.

The averaging circuit 65 also includes a comparator 90 , a control circuit 91 , and a charging/discharging circuit 92 . By generating the signal sw_ctrl based on the thinning number N, the averaging circuit 65 can change the cycle TA and change the rate of increase of the voltage Vca.

The control IC 40a also has a terminal VS. The averaging circuit 65 of the control IC 40a generates the signal sw_ctrl based on the voltage Vs, thereby outputting the voltage Vca from the positive voltage Vis.

The control IC 40b also has a terminal VW for receiving voltage from the auxiliary coil La. Based on the voltage Vvw, the averaging circuit 65 of the control IC 40b can output the voltage Vca from the voltage Vis, which is a positive voltage, similarly to the averaging circuit 65 of the control IC 40a.

The drive signal output circuit 61 also includes an oscillation circuit 70 , a detection circuit 71 , and a drive circuit 72 . The detection circuit 71 outputs a signal Vload based on the thinning number N and the voltage Vca. Thereby, the drive circuit 72 can switch the NMOS transistors 24 and 25 according to the state of the load 11 .

The control IC 40 a also includes an overload detection circuit 66 . When the overload detection circuit 66 outputs a signal olp indicating that the load 11 is overloaded, the drive circuit 72 turns off the NMOS transistors 24 and 25 . Thereby, the control IC 40 a can protect the load 11 .

The above-described embodiments are intended to facilitate understanding of the present invention, and are not intended to limit and interpret the present invention. Further, the present invention can be modified and improved without departing from its spirit, and it goes without saying that the present invention includes equivalents thereof.

10a, 10b switching power supply circuit 11 loads 20, 21, 22, 32, 51, 53, 54 capacitors 23, 55 to 57, 60, 63, 64, 103 resistors 24, 25 NMOS transistor 26 transformer 27 control blocks 30, 31, 50 diode 33 constant voltage circuit 34 light emitting diode 52 phototransistor 61 drive signal output circuit 62 setting circuit 65 averaging circuit 66 overload detection circuit 67 averaging circuit 70 oscillation circuit 71 detection circuit 72 drive circuits 80, 82, 90 comparator 81, 83 reference voltage circuit 84 output circuit 91 control circuit 92 charge/discharge circuit 100, 102 switch 101 inverter 110 level shift circuit 111 bias circuit 112 buffer circuit

Claims (11)

a transformer including a primary coil and a secondary coil; first and second transistors for controlling the current in the primary coil; and a resonant circuit including the primary coil and a first capacitor. A switching control circuit for controlling switching of the first and second transistors of a power supply circuit that generates on the secondary side,
an averaging circuit for averaging a first voltage corresponding to a resonance current flowing in the power supply circuit for a first period with a period based on a setting signal and outputting a second voltage indicating a load current flowing in a load of the power supply circuit;
a setting circuit that outputs the setting signal for lengthening the cycle when the load current increases based on the second voltage;
a drive signal output circuit that outputs a drive signal for driving the first and second transistors based on the feedback voltage corresponding to the output voltage, the second voltage, and the setting signal;
a switching control circuit including; A switching control circuit according to claim 1, wherein
The setting circuit is
a first comparison circuit that compares the second voltage and a first reference voltage;
a second comparison circuit that compares the second voltage with a second reference voltage that is lower than the first reference voltage;
an output circuit that outputs the setting signal that lengthens the period when the second voltage reaches the first reference voltage, and outputs the setting signal that shortens the period when the second voltage reaches the second reference voltage; ,
a switching control circuit including; A switching control circuit according to claim 2, wherein
The output circuit is
When the second voltage reaches the first reference voltage, outputting the setting signal which doubles the period, and when the second voltage reaches the second reference voltage, outputs the setting signal which halves the period. which outputs
switching control circuit. A switching control circuit according to claim 3, wherein
a first reference voltage output circuit that outputs the first reference voltage;
a second reference voltage output circuit that outputs the second reference voltage at a level lower than half the level of the first reference voltage;
a switching control circuit including; The switching control circuit according to any one of claims 2 to 4,
The output circuit is
An up-down counter that changes a count value indicating the cycle and outputs the count value as the setting signal when the second voltage becomes the first reference voltage or the second voltage becomes the second reference voltage. is
switching control circuit. The switching control circuit according to any one of claims 1 to 5,
The averaging circuit is
an oscillation signal output circuit that outputs a first oscillation signal whose logic level changes between the first period and the second period;
a control signal output circuit for outputting a control signal having a first logic level in the first period based on the first oscillation signal and the setting signal at the cycle;
based on the control signal at the first logic level, charging a second capacitor with the first voltage that produces the second voltage; and discharging the second capacitor based on the control signal at the second logic level. a charging and discharging circuit;
a switching control circuit including; A switching control circuit according to claim 6,
The switching control circuit is an integrated circuit having a first terminal connected to a connection node between the first transistor and the second transistor,
The oscillation signal output circuit outputs the first oscillation signal based on the voltage of the first terminal.
switching control circuit. A switching control circuit according to claim 6,
the transformer includes an auxiliary coil electromagnetically coupled to the primary coil or the secondary coil;
The switching control circuit is an integrated circuit having a second terminal to which the voltage from the auxiliary coil is applied,
The oscillation signal output circuit outputs the first oscillation signal based on the voltage of the second terminal.
switching control circuit. The switching control circuit according to any one of claims 1 to 8,
The drive signal output circuit is
an oscillation circuit that outputs a second oscillation signal having a frequency corresponding to the feedback voltage;
a detection circuit that detects the state of the load based on the second voltage and the setting signal;
a drive circuit that drives the first and second transistors based on the detection result of the detection circuit and the second oscillation signal;
a switching control circuit including; A switching control circuit according to claim 9,
a determination circuit that determines whether the load current is equal to or greater than a predetermined value based on the detection result of the detection circuit;
The drive circuit is
turning off the first and second transistors when the determination circuit determines that the load current is equal to or greater than the predetermined value;
switching control circuit. a transformer including a primary coil and a secondary coil;
first and second transistors for controlling current in the primary coil;
a resonant circuit including the primary coil and a first capacitor;
a switching control circuit that controls switching of the first and second transistors;
A power supply circuit for generating a target level output voltage on the secondary side, comprising:
The switching control circuit is
an averaging circuit for averaging a first voltage corresponding to a resonance current flowing in the power supply circuit for a first period with a period based on a setting signal and outputting a second voltage indicating a load current flowing in a load of the power supply circuit;
a setting circuit that outputs the setting signal for lengthening the cycle when the load current increases based on the second voltage;
a drive signal output circuit that outputs a drive signal for driving the first and second transistors based on the feedback voltage corresponding to the output voltage, the second voltage, and the setting signal;
Power supply circuit including.

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