JP2023022856A - Wiring board and manufacturing method of wiring board - Google Patents

Wiring board and manufacturing method of wiring board Download PDF

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JP2023022856A
JP2023022856A JP2021127881A JP2021127881A JP2023022856A JP 2023022856 A JP2023022856 A JP 2023022856A JP 2021127881 A JP2021127881 A JP 2021127881A JP 2021127881 A JP2021127881 A JP 2021127881A JP 2023022856 A JP2023022856 A JP 2023022856A
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conductive member
wiring board
photosensitive resin
resin layer
layer
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貴志 藤田
Takashi Fujita
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Toppan Inc
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Toppan Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate

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  • Manufacturing Of Printed Wiring (AREA)

Abstract

To provide a wiring board which has a structure that prevents disconnection between connection terminals even when the stress acts in the thickness direction of a semiconductor device and provide a manufacturing method thereof.SOLUTION: A wiring board 1 comprises: an inner layer wiring board 100; an outer layer wiring board 105; and a wiring external electrode 10. The wiring external electrode 10 comprises: a first conductive member 11; and a second conductive member 12. The first conductive member 11 comprises: a portion where an upper surface and a side surface are covered by the second conductive member 12 (hereinafter referred to as a pad part 112); and a portion which protrudes from the outer layer wiring board 105 and where the side surface is not covered by the second conductive member 12 (hereinafter referred to as a post part 111). A bottom surface of the pad part has a first protruding shape surface 114 that is wider than an upper surface of the post part, and a bottom surface of the portion covering the side surface of the pad part 112 of the second conductive member 12 has a second protruding shape surface 115 that expands in connection with the first protruding shape surface 114.SELECTED DRAWING: Figure 1

Description

本発明は、配線基板及び配線基板の製造方法に関する。 The present invention relates to a wiring board and a method for manufacturing the wiring board.

最近、電子産業の発達につれて、電子部品の高性能化、高機能化、小型化が要求されており、これによって、ＳＩＰ（System In Package）、３Ｄパッケージなどの表面実装部品基板においても、高集積化、薄型化、微細回路パターン化の要求が急増している。 Recently, with the development of the electronic industry, there is a demand for high performance, high functionality and miniaturization of electronic components. Demands for thinning, thinning, and fine circuit patterning are rapidly increasing.

特に、電子部品の基板への表面実装技術において、半導体チップをマザーボードと連結しなければならないため、フリップチップボンディング方式が多く用いられている。 In particular, in the technology of surface mounting electronic components onto a substrate, a flip chip bonding method is often used because a semiconductor chip must be connected to a mother board.

フリップチップボンディング方式は、半導体チップに、金、はんだあるいはその他の金属などの素材で数十μｍないし数百μｍの外部接続端子（すなわち、バンプ）を形成し、バンプの形成された半導体素子を覆して（flip）、表面が基板側に向かうように実装させるものである。更に半導体チップの微細化大型化に伴いＦＣＢＧＡ（Flip Chip-Ball Grid Array）用配線基板を介して半導体素子をマザーボードと連結する方式が採用されている。 In the flip-chip bonding method, external connection terminals (ie, bumps) with a thickness of several tens to several hundreds of microns are formed on a semiconductor chip using a material such as gold, solder, or other metal, and the semiconductor element with the bumps is overturned. It is mounted so that the front surface faces the substrate side by flipping it. Furthermore, as semiconductor chips become finer and larger, a method of connecting a semiconductor element to a mother board via a wiring board for FCBGA (Flip Chip-Ball Grid Array) has been adopted.

フリップチップボンディング方式は、半導体素子の外部接続端子の狭ピッチ化に対応するために、Ｃｕポストなどのメタルポストを使用した構造に発展している。Ｃｕポストの利用は半導体素子とＦＣＢＧＡ基板との距離を確保することによって、隣あうメタルポスト間のショートの解消による狭ピッチ化の対応する構成として注目をあびている。 The flip-chip bonding method has evolved into a structure using metal posts such as Cu posts in order to cope with the narrower pitch of external connection terminals of semiconductor elements. The use of Cu posts is attracting attention as a configuration for narrowing the pitch by eliminating shorts between adjacent metal posts by securing the distance between the semiconductor element and the FCBGA substrate.

例えば特許文献１、２では、半導体素子側と接続する配線基板の構造として、メタルポストを形成し、その上にはんだバンプを形成する構成が開示されている。 For example, Patent Literatures 1 and 2 disclose a configuration in which metal posts are formed and solder bumps are formed thereon as a structure of a wiring board connected to a semiconductor element.

特許第５０１１３２９号公報Japanese Patent No. 5011329 特開２０２０－１８８１３９号公報JP 2020-188139 A

半導体装置では接続信頼性が重要であるが、ＦＣＢＧＡ用配線基板と半導体チップでは線膨張係数が異なるため、温度変化によって接続端子部の弱い部分に応力が集中し、負荷が累積することで半導体装置の故障が引き起こされる。 Connection reliability is important in semiconductor devices, but since the coefficient of linear expansion differs between the FCBGA wiring board and the semiconductor chip, stress concentrates on the weak portions of the connection terminals due to temperature changes. failure is caused.

特許文献１、２の構造では、こうした接続端子部での応力集中に起因する損傷に対する対策について開示はない。また従来、ＦＣＢＧＡ用配線基板と半導体チップと間にアンダーフィルとばれる樹脂で封止するなど、基板の長さ方向の応力に対して緩和する方法が開発されてきたが、接続端子の狭ピッチ化に伴い半導体装置の厚さ方向に働く応力による接続端子間の剥離が問題となっている。 The structures of Patent Documents 1 and 2 do not disclose countermeasures against damage caused by such stress concentration at the connection terminal portion. Conventionally, a method of relieving the stress in the longitudinal direction of the substrate has been developed, such as sealing the space between the wiring substrate for FCBGA and the semiconductor chip with a resin called underfill. Along with this, peeling between connection terminals due to stress acting in the thickness direction of the semiconductor device has become a problem.

そこで本発明は、半導体装置の厚さ方向に応力が働く場合でも、接続端子間の剥離を防止する構造を有する配線基板及びその製造方法を提供することを目的とする。 SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a wiring board having a structure that prevents separation between connection terminals even when stress acts in the thickness direction of a semiconductor device, and a method of manufacturing the wiring board.

前記の課題を解決するために、代表的な本発明の配線基板の一つは、内層配線基板と、外層配線基板と、配線外部電極を備えており、前記配線外部電極は、第１導電性部材と第２導電性部材を備え、前記第１導電性部材は、前記第２導電性部材に上面と側面を覆われている部分（以下、「パッド部」という。）と、前記外層配線基板から突出し前記第２導電性部材に側面を覆われていない部分（以下、「ポスト部」という。）を有し、前記パッド部の底面は前記ポスト部の上面より広い第１突出形状面を有し、前記第２導電性部材の前記パッド部の側面を覆う部分の底面は前記第１突出形状面につながって広がる第２突出形状面を有している、配線基板である。 In order to solve the above-mentioned problems, one representative wiring board of the present invention includes an inner layer wiring board, an outer layer wiring board, and a wiring external electrode, and the wiring external electrode has a first conductivity. a member and a second conductive member, wherein the first conductive member includes a portion (hereinafter referred to as a “pad portion”) whose upper and side surfaces are covered with the second conductive member; and the outer layer wiring board. and the bottom surface of the pad portion has a first projecting shape surface that is wider than the top surface of the post portion. and a bottom surface of a portion of the second conductive member covering the side surface of the pad section has a second protruding surface extending from the first protruding surface.

本発明によれば、配線基板において、半導体装置の厚さ方向に応力が働く場合でも、接続端子間の剥離を防止することができる。
前記した以外の課題、構成および効果は、以下の実施をするための形態における説明により明らかにされる。 According to the present invention, it is possible to prevent separation between connection terminals even when stress acts on the wiring board in the thickness direction of the semiconductor device.
Problems, configurations, and effects other than those described above will be clarified by the description in the following embodiments.

図１は、本発明の配線基板１を用いた半導体装置４００を示す断面図である。FIG. 1 is a sectional view showing a semiconductor device 400 using the wiring board 1 of the present invention. 図２Ａは、配線外部電極１０の断面図である。FIG. 2A is a cross-sectional view of the wiring external electrode 10. FIG. 図２Ｂは、配線外部電極１０の中心線Z-Z‘軸からX軸正方向の断面を拡大した模式図である。FIG. 2B is a schematic diagram showing an enlarged cross section of the wiring external electrode 10 in the X-axis positive direction from the center line Z-Z' axis. 図３Ａは、内層配線基板１００と外層配線基板１０５を備えた基板の断面図である。FIG. 3A is a cross-sectional view of a substrate including an inner layer wiring board 100 and an outer layer wiring board 105. FIG. 図３Ｂは、シード層２０１を形成した基板の断面図である。FIG. 3B is a cross-sectional view of the substrate with the seed layer 201 formed thereon. 図３Ｃは、シード層２０１を感光性樹脂層２０２で被覆した基板の断面図である。FIG. 3C is a cross-sectional view of a substrate having a seed layer 201 covered with a photosensitive resin layer 202. FIG. 図３Ｄは、感光性樹脂層２０２の開口部にＣｕポストを形成した基板の断面図である。FIG. 3D is a cross-sectional view of a substrate having Cu posts formed in the openings of the photosensitive resin layer 202. FIG. 図３Ｅは、感光性樹脂層２０２とＣｕポストの間に間隙５０を形成した基板の断面図である。FIG. 3E is a cross-sectional view of the substrate with the gap 50 formed between the photosensitive resin layer 202 and the Cu post. 図３Ｆは、開口部１０６の中のＣｕポストの上にはんだを形成した基板の断面図である。FIG. 3F is a cross-sectional view of the substrate with solder formed on the Cu posts in the openings 106. FIG. 図３Ｇは、感光性樹脂層２０２をはく離した後の基板の断面図である。FIG. 3G is a cross-sectional view of the substrate after the photosensitive resin layer 202 is stripped. 図３Ｈは、シード層２０１をエッチング除去した後の基板の断面図である。FIG. 3H is a cross-sectional view of the substrate after seed layer 201 is etched away. 図３Ｉは、はんだを加圧プレスし平坦化処理した後の基板の断面図である。FIG. 3I is a cross-sectional view of the substrate after the solder has been pressure pressed and planarized.

以下、図面を参照して、本発明の実施形態について説明する。なお、この実施形態により本発明が限定されるものではない。また、図面の記載において、同一部分には同一の符号を付して示している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the present invention is not limited by this embodiment. Moreover, in the description of the drawings, the same parts are denoted by the same reference numerals.

本開示においては、方向を示すために、図面上に表記されたＸ軸、Ｙ軸、Ｚ軸に示す方向を用いることがある。 In the present disclosure, the directions indicated by the X-axis, Y-axis, and Z-axis on the drawings may be used to indicate directions.

本開示において、「上面」とは、積層する向きに直交する面の上側を意味する。逆に「底面」とは、積層する向きに直交する面の下側を意味する。「側面」とは、上面と底面に挟まれた外周の面を意味する。また、「断面」とは、特に断りのない限りＸＺ平面における断面を意味する。 In the present disclosure, the “upper surface” means the upper side of the surface orthogonal to the stacking direction. Conversely, the “bottom surface” means the lower side of the surface orthogonal to the stacking direction. "Side surface" means an outer peripheral surface sandwiched between the top surface and the bottom surface. In addition, "cross section" means a cross section on the XZ plane unless otherwise specified.

本開示において、特に断りのない限り、「上」はZ軸の正方向、「厚さ」「高さ」はＺ方向の長さを意味する。 In the present disclosure, unless otherwise specified, "top" means the positive direction of the Z-axis, and "thickness" and "height" mean the length in the Z direction.

本開示において、「層上」「基板上」というときは、特に断りのない限り、層や基板などの上面または底面に直接または介在物を介して接する状態を意味する。 In the present disclosure, the terms “on a layer” and “on a substrate” refer to a state of being in contact with the top surface or bottom surface of a layer, substrate, or the like directly or via an intervening material, unless otherwise specified.

本開示において「接続する」とは、２つの対象物の間に電流が流れるように連結することを意味しており、２つの対象物が直接接触してもよいし、２つの対象物の間に介在物が存在していてもよい。 In the present disclosure, "connect" means to connect two objects so that an electric current flows between them, and the two objects may be in direct contact or Inclusions may be present in

図１は、本発明の配線基板１を用いた半導体装置４００を示す断面図である。
半導体装置４００は、半導体素子３００が半導体素子３００側の素子外部電極３０１を介して本発明の配線基板１と接続しており、両者の間隙をアンダーフィル１０７にて充填した構造を有する。 FIG. 1 is a sectional view showing a semiconductor device 400 using the wiring board 1 of the present invention.
A semiconductor device 400 has a structure in which a semiconductor element 300 is connected to the wiring substrate 1 of the present invention through element external electrodes 301 on the semiconductor element 300 side, and the gap between the two is filled with an underfill 107 .

配線基板１は、内層配線基板１００、外層配線基板１０５、および配線外部電極１０を備える。 The wiring board 1 includes an inner layer wiring board 100 , an outer layer wiring board 105 , and wiring external electrodes 10 .

内層配線基板１００は、１層以上の内層絶縁層１０１と、前記内層絶縁層１０１上に設けられた１層以上の配線層１０３と、前記内層絶縁層１０１を貫通し複数の前記配線層１０３間を電気的に接続する内層ビア１０４からなる内層配線パターン１０２から構成される。 The inner layer wiring substrate 100 includes one or more inner insulating layers 101, one or more wiring layers 103 provided on the inner insulating layer 101, and a plurality of wiring layers 103 that penetrate through the inner insulating layer 101. It is composed of an inner-layer wiring pattern 102 consisting of inner-layer vias 104 electrically connecting the .

外層配線基板１０５は、前記内層配線基板１００上に設けられる。外層配線基板１０５には、内層配線パターン１０２の一部が露出するように開口部が設けられる。 The outer layer wiring board 105 is provided on the inner layer wiring board 100 . The outer layer wiring board 105 is provided with an opening so that a part of the inner layer wiring pattern 102 is exposed.

配線外部電極１０は、外層配線基板１０５の開口部を介して内層配線パターン１０３と接続し、かつ半導体素子３００と素子外部電極３０１を介して接続している。 The wiring external electrodes 10 are connected to the internal layer wiring pattern 103 through the openings of the external layer wiring substrate 105 and are connected to the semiconductor element 300 through the element external electrodes 301 .

図２Ａは、配線外部電極１０の断面図である。配線外部電極１０は、第１導電性部材１１と第２導電性部材１２からなる。第1導電性部材はビア部１１０、ポスト部１１１，およびパッド部１１２からなる。配線外部電極１０はZ-Z’軸を中心線とする回転対象の形状を有するとして説明するが、必ずしも回転対象に限られる必要はない。 FIG. 2A is a cross-sectional view of the wiring external electrode 10. FIG. The wiring external electrode 10 is composed of a first conductive member 11 and a second conductive member 12 . The first conductive member comprises a via portion 110 , a post portion 111 and a pad portion 112 . Although the wiring external electrode 10 is described as having a rotationally symmetrical shape with the Z-Z' axis as the center line, it is not necessarily limited to a rotationally symmetrical shape.

ビア部１１０は、外層配線基板１０５に設けられた前記開口部に第１導電性部材が充填され形成される部分で略円柱状である。形状は特に限定されないが、ＸＹ平面での径はポスト部１１１の径より小さく、底面から上面に広がるテーパー状に形成されている。 The via portion 110 is formed by filling the opening provided in the outer layer wiring board 105 with the first conductive member and has a substantially columnar shape. Although the shape is not particularly limited, the diameter on the XY plane is smaller than the diameter of the post portion 111, and it is formed in a tapered shape that spreads from the bottom surface to the top surface.

ポスト部１１１は、ビア部１１０の上に位置し、外部配線基板から突出し、第２導電性部材１２に側面を覆われていない。ビア部の上に位置する。略円柱状の形状をとる。 The post portion 111 is positioned on the via portion 110 , protrudes from the external wiring board, and has a side surface not covered with the second conductive member 12 . Located above the via. It has a substantially cylindrical shape.

パッド部１１２は、ポスト部１１１の上に位置し、第２導電性部材１２に上面と側面を覆われている。パッド部１１２の底面の径はポスト部１１１の上面の径より大きい。略円柱状の形状をとるが、上面から底面へ広がるテーパー形状も含む。 The pad portion 112 is positioned on the post portion 111 and covered with the second conductive member 12 on the upper surface and the side surface. The diameter of the bottom surface of the pad portion 112 is larger than the diameter of the top surface of the post portion 111 . Although it has a substantially cylindrical shape, it also includes a tapered shape that spreads from the top surface to the bottom surface.

図２Ｂは、配線外部電極１０の中心線Z-Z‘軸からＸ軸正方向の断面を拡大した模式図である。
配線外部電極１０は、全体としてみると第1導電性部材１１のパッド部１１２と第２導電性部材１２が釘の頭のようにポスト部１１１から突出しており、ポスト部１１１の上面より広い突出形状面１１３がＸＹ平面上に広がって形成される。 FIG. 2B is a schematic diagram showing an enlarged cross section of the wiring external electrode 10 in the positive direction of the X-axis from the center line ZZ'-axis.
In the wiring external electrode 10 as a whole, the pad portion 112 of the first conductive member 11 and the second conductive member 12 protrude from the post portion 111 like the head of a nail. A shape surface 113 is formed extending on the XY plane.

さらに本実施形態では、前記突出形状面１１３は、パッド部１１２の底面が形成する第１突出形状面１１４と、パッド部１１２の側面を覆う第２導電性部材１２の底面が形成し、第１突出形状面１１４とつながり広がる第２突出形状面１１５とから構成される。
配線外部電極１０が回転対象の形状をとる場合、第１，第２突出形状面はリング形状をとる。 Further, in the present embodiment, the protruding surface 113 is formed by the first protruding surface 114 formed by the bottom surface of the pad section 112 and the bottom surface of the second conductive member 12 covering the side surface of the pad section 112. It is composed of a protruding shaped surface 114 and a second protruding shaped surface 115 which is connected and spreads.
When the wiring external electrode 10 has a rotationally symmetrical shape, the first and second protruding faces have a ring shape.

例としてパッド部１１２の半径Ａ１は接続する半導体素子の大きさによるが、ほぼ２５μｍもしくはそれ以上の大きさを有し、Ｚ方向の長さＨ２は４～７μｍの値を有する。第１突出形状面１１４における、リング形状の半径方向の幅の長さΔＡ（Ａ１－Ａ２）は０．５～３μｍ（好ましくは１～３μｍ）の値を有する。ポスト部１１１のＺ方向の長さＨ１は６～８μｍの値を有する。 As an example, the radius A1 of the pad portion 112 is approximately 25 μm or more depending on the size of the semiconductor element to be connected, and the length H2 in the Z direction has a value of 4 to 7 μm. The radial width ΔA (A1−A2) of the ring shape in the first projecting shape surface 114 has a value of 0.5 to 3 μm (preferably 1 to 3 μm). The Z-direction length H1 of the post portion 111 has a value of 6 to 8 μm.

第２導電性部材１２は、パッド部１１２の半径Ａ１と同じ半径をもつ球体の体積の５０～１５０％（好ましくは５０～１００％）の体積のはんだ部材から後述の製造方法で形成する。パッド部１１２に積層される第２導電性部材１２の厚さ（Ｌ）は前記はんだ部材の体積により決まる値を有する。さらに本実施形態では、第２導電性部材１２による第２突出形状面１１５における、リング形状の半径方向の幅の長さΔＦは例として１．２～７μｍの値を有する。 The second conductive member 12 is formed from a solder member having a volume of 50 to 150% (preferably 50 to 100%) of the volume of a sphere having the same radius as the radius A1 of the pad portion 112 by the manufacturing method described later. The thickness (L) of the second conductive member 12 laminated on the pad portion 112 has a value determined by the volume of the solder member. Furthermore, in the present embodiment, the radial width ΔF of the ring shape on the second projecting surface 115 formed by the second conductive member 12 has a value of 1.2 to 7 μm, for example.

＜作用・効果＞
本実施形態では、Ｚ方向にひずみ応力がかかった場合でも、配線外部電極１０が突出形状面１１３を有することによるアンカー効果により、剥がれを防止することができる。さらに突出形状面１１３はＸＹ平面上の複数方向に突出していることから、多方面の応力ひずみに対してはがれにくい効果を発揮することができる。 <Action/effect>
In the present embodiment, even when a strain stress is applied in the Z direction, peeling can be prevented by the anchor effect of the wiring external electrode 10 having the projecting surface 113 . Furthermore, since the protruding surface 113 protrudes in a plurality of directions on the XY plane, it is possible to exert an effect of being difficult to peel off against stress strain in many directions.

さらに本実施形態では、突出形状面１１３は、第１導電性部材１１により形成される第１突出形状面１１４と第２導電性部材１２により形成される第２突出形状面１１５との２種類の突出形状面で構成していることから、いずれか一方の突出形状面のみの場合に比べ、アンカー効果が一層向上し、ひずみ応力に対し剥がれにくくすることができる。 Furthermore, in the present embodiment, the protruding surface 113 is of two types: a first protruding surface 114 formed by the first conductive member 11 and a second protruding surface 115 formed by the second conductive member 12. Since it is composed of protruding shaped surfaces, the anchoring effect is further improved compared to the case where only one of the protruding shaped surfaces is used, and it is possible to make it difficult to peel off against strain stress.

上述のように第２導電性部材１２は、パッド部１１２の半径Ａ１と同じ半径をもつ球体の体積の５０～１５０％（好ましくは５０～１００％）の体積のはんだ部材から形成されている。このことにより、複数の第１導電性部材１１の間でＺ方向の高さにばらつきを生じた場合でも、ばらつきを吸収できるだけの厚さ（Ｌ）をもたせ、対向する半導体素子３００側の素子外部電極３０１との接続不良を生じないようにすることができる。 As described above, the second conductive member 12 is formed of a solder member having a volume of 50 to 150% (preferably 50 to 100%) of the volume of a sphere having the same radius as the radius A1 of the pad portion 112. FIG. As a result, even if there is a variation in height in the Z direction among the plurality of first conductive members 11, the thickness (L) is sufficient to absorb the variation. A connection failure with the electrode 301 can be prevented.

またはんだ部材の量を適正に抑えることで、半導体素子３００と配線基板１を連結する際に、素子外部電極３０１と第１導電性部材１１との間で潰され横にはみ出したはんだ部材が、近接する他の外部電極との間で繋がりショート不良が発生することを回避することもできる。 Alternatively, by appropriately suppressing the amount of the solder member, when the semiconductor element 300 and the wiring board 1 are connected, the solder member that is crushed between the element external electrode 301 and the first conductive member 11 and protrudes sideways is It is also possible to avoid the occurrence of short-circuit failure due to connection with other adjacent external electrodes.

＜材料＞
第１導電性部材１１には例えば銅を使用する。電解めっき法により形成することが可能である。 <Material>
For example, copper is used for the first conductive member 11 . It can be formed by an electrolytic plating method.

第２導電性部材１２には、例えばはんだを使用する。はんだペースト印刷法や、電解めっき法、はんだボール搭載法により形成することが可能である。はんだにはＳｎ、Ａｇ、Ｃｕ、Ｐｂ、Ｉｎ、Ｓｂ、Ｂｉの内いずれか２種以上の合金組成が使用可能である。はんだが溶融する温度でのリフロ―処理によりドーム形状のはんだバンプを得ることができ、プレス処理を追加することで先端が平坦な形状のはんだバンプを得ることができる。 Solder, for example, is used for the second conductive member 12 . It can be formed by a solder paste printing method, an electroplating method, or a solder ball mounting method. An alloy composition of two or more of Sn, Ag, Cu, Pb, In, Sb, and Bi can be used for solder. Dome-shaped solder bumps can be obtained by reflow processing at a temperature at which solder melts, and solder bumps with flat tips can be obtained by adding press processing.

第１導電性部材１１がＣｕで、第２導電性部材１２がはんだである場合、加熱溶融にてはんだとＣｕの界面に例えばCu6Sn5合金やCu3Sn合金などの合金層を形成することで、半導体素子３００実装時の加熱でも合金層が溶融せず、接合信頼性を向上させることが可能となる。 When the first conductive member 11 is Cu and the second conductive member 12 is solder, an alloy layer such as a Cu6Sn5 alloy or a Cu3Sn alloy is formed at the interface between the solder and Cu by heating and melting to form a semiconductor element. The alloy layer does not melt even when heated during 300 mounting, and the bonding reliability can be improved.

[配線基板の製造方法]
次に本発明の配線基板の製造方法について説明する。図３Ａ～図３Ｉは、本発明の実施形態にかかる配線基板１を製造する各工程における、基板の断面図である。以下の説明において、上述の実施形態と同一又は同等の構成要素については同一の符号を付し、その説明を簡略又は省略する。 [Method for manufacturing wiring board]
Next, a method for manufacturing a wiring board according to the present invention will be described. 3A to 3I are cross-sectional views of the substrate in each step of manufacturing the wiring substrate 1 according to the embodiment of the present invention. In the following description, the same reference numerals are given to components that are the same as or equivalent to those of the above-described embodiment, and the description thereof will be simplified or omitted.

各製造工程の説明において、第１導電性部材１１はＣｕポスト、第２導電性部材１２ははんだと言うことがあるが、これら実施例に限定されるものではなく、特に断りのない限りその工程における状態のものを意味する。 In the description of each manufacturing process, it may be said that the first conductive member 11 is a Cu post and the second conductive member 12 is a solder, but they are not limited to these examples, and unless otherwise specified, the process means the state in

製造方法は、この例に限定されず、同様の形状を得られれば、製造方法は自由に選択することが可能である。また、配線外部電極１０が３つの例を図示しているが、電極の数はこれに限られるものでないことは言うまでもない。 The manufacturing method is not limited to this example, and any manufacturing method can be freely selected as long as a similar shape can be obtained. Also, although an example in which there are three wiring external electrodes 10 is illustrated, it goes without saying that the number of electrodes is not limited to this.

図３Ａは、内層配線基板１００と外層配線基板１０５を備えた基板の断面図である。内層配線基板１００は、複数の内層絶縁層１０１と、内層絶縁層１０１上に形成される複数の配線層１０３と、内層絶縁層１０１を貫通して複数の配線層間を電気的に接続する内層ビア１０４とから構成される。外層配線基板１０５には、内層配線パターン１０２の最外層の一部が露出する様に開口部をもつ。 FIG. 3A is a cross-sectional view of a substrate including an inner layer wiring board 100 and an outer layer wiring board 105. FIG. The inner layer wiring board 100 includes a plurality of inner layer insulating layers 101, a plurality of wiring layers 103 formed on the inner layer insulating layers 101, and inner layer vias penetrating the inner layer insulating layer 101 and electrically connecting the plurality of wiring layers. 104. The outer layer wiring board 105 has an opening so that a part of the outermost layer of the inner layer wiring pattern 102 is exposed.

図３Ｂは、シード層２０１を形成した基板の断面図である。シード層２０１は無電解めっき膜ないしスパッタ膜により形成される。シード層２０１は第１導電性部材の電解めっきの給電層として作用する。無電解めっき膜は例えばＣｕ、Ｐｄ、Ａｌ、Ｓｎ、Ｎｉ，Ｃｒなどの金属が使用可能である。
スパッタ膜では、Ｃｕ、Ｎｉ，Ａｌ，Ｔｉ，Ｃｒ，Ｍｏ，Ｗ，Ｔａ，Ａｕ，Ｉｒ，Ｒｕ，Ｐｄ，Ｐｔ，ＡｌＳｉ，ＡｌＳｉＣｕ，ＡｉＣｕ，ＮＩＦｅ、ＩＴＯ，ＩＺＯ，ＡＺＯ，ＺｎＯ，ＰＺＴ，ＴｉＮ，Ｃｕ3Ｎ4、Ｃｕ合金や、これらを複数組み合わせたものを使用することができる。
本実施形態では、電気特性、製造の容易性の観点およびコスト面を考慮して、無電解銅めっきを使用する。無電解銅めっきの膜厚は、電解めっきの給電層として１μｍ以下とするのが好ましい。 FIG. 3B is a cross-sectional view of the substrate with the seed layer 201 formed thereon. The seed layer 201 is formed of an electroless plated film or a sputtered film. The seed layer 201 acts as a power supply layer for electrolytic plating of the first conductive member. Metals such as Cu, Pd, Al, Sn, Ni, and Cr can be used for the electroless plated film.
Sputtered films include Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AiCu, NIFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, Cu alloys, or combinations of these may be used.
In this embodiment, electroless copper plating is used in consideration of electrical properties, ease of manufacture, and cost. The film thickness of the electroless copper plating is preferably 1 μm or less as a power feeding layer for electrolytic plating.

図３Ｃは、シード層２０１を感光性樹脂層２０２で被覆した基板の断面図である。配線外部電極１０を形成する位置に感光性樹脂層２０２の開口部１０６を形成する。当該開口部１０６に、第１導電性部材１１と第２導電性部材１２を形成するために、感光性樹脂層２０２は数十μｍの厚さが必要である。前記開口部１０６は略円柱状であるが、上部に行くほど広くなるテーパ状のものも含む。
感光性樹脂層２０２は液状レジストやフォルム状に形成されたドライフィルムレジストを使用することができる。ネガ型レジストやポジ型レジストの何れも使用することができる。本実施形態ではアクリル系のネガ型ドライフィルムレジストを使用する。 FIG. 3C is a cross-sectional view of a substrate having a seed layer 201 covered with a photosensitive resin layer 202. FIG. An opening 106 is formed in the photosensitive resin layer 202 at the position where the wiring external electrode 10 is to be formed. In order to form the first conductive member 11 and the second conductive member 12 in the opening 106, the photosensitive resin layer 202 needs to have a thickness of several tens of μm. The opening 106 has a substantially cylindrical shape, but it also includes a tapered shape that widens toward the top.
For the photosensitive resin layer 202, a liquid resist or a form-shaped dry film resist can be used. Either a negative resist or a positive resist can be used. In this embodiment, an acrylic negative type dry film resist is used.

図３Ｄは、感光性樹脂層２０２の開口部１０６にＣｕポストを形成した基板の断面図である。Ｃｕポストは銅を主成分とする金属からなり電解銅めっきにて形成される。 FIG. 3D is a cross-sectional view of a substrate having Cu posts formed in the openings 106 of the photosensitive resin layer 202. FIG. The Cu post is made of a metal containing copper as a main component and is formed by electrolytic copper plating.

図３Ｅは、感光性樹脂層２０２とＣｕポストの間に間隙５０を形成した基板の断面図である。
前記感光性樹脂層２０２の開口部１０６に形成したＣｕポストの上に表面処理層を保護層として形成することができる。表面処理層は、ニッケル、パラジウム、金、スズの何れかの金属の１層ないし複数層で構成し、形成方法としては、電解めっき法や無電解めっき法が使用可能である。表面処理層を円滑に形成する目的で、前記開口部１０６から露出するＣｕポストの表面に前処理エッチングを行い表面の状態を整える。前処理エッチングのエッチング液として例えば過酸化水素と硫酸の混合液を使用することができる。 FIG. 3E is a cross-sectional view of the substrate with the gap 50 formed between the photosensitive resin layer 202 and the Cu post.
A surface treatment layer can be formed as a protective layer on the Cu posts formed in the openings 106 of the photosensitive resin layer 202 . The surface treatment layer is composed of one or more layers of metal such as nickel, palladium, gold, or tin, and can be formed by electroplating or electroless plating. For the purpose of smoothly forming the surface treatment layer, pretreatment etching is performed on the surface of the Cu post exposed from the opening 106 to condition the surface. For example, a mixed solution of hydrogen peroxide and sulfuric acid can be used as an etchant for pretreatment etching.

このとき、前処理エッチングのエッチング液がＣｕポストの表面のみならず、前記感光性樹脂層２０２の開口部１０６壁面との間にも浸み込むことで、感光性樹脂層２０２とＣｕポストの間に間隙５０が形成されることを見出した。間隙５０の大きさはエッチング時間などにより調整できるが、例えばＸ方向に０．２～２．０μｍの長さでＺ方向に４～７μｍの大きさを形成することができる。 At this time, the etchant for the pretreatment etching penetrates not only into the surface of the Cu post but also into the wall surface of the opening 106 of the photosensitive resin layer 202, thereby forming a gap between the photosensitive resin layer 202 and the Cu post. It has been found that a gap 50 is formed in the The size of the gap 50 can be adjusted by the etching time or the like. For example, the gap 50 can be formed to have a length of 0.2 to 2.0 μm in the X direction and a size of 4 to 7 μm in the Z direction.

図３Ｆは、開口部１０６の中のＣｕポストの上にはんだを形成した基板の断面図である。本実施形態で、はんだの形成方法は、はんだペーストをスキージで開口部に充填するペースト印刷法、電解めっきにてはんだを析出させる電解めっき法、またははんだボールを搭載するボール搭載法などである。 FIG. 3F is a cross-sectional view of the substrate with solder formed on the Cu posts in the openings 106. FIG. In the present embodiment, the solder is formed by a paste printing method in which solder paste is filled into openings with a squeegee, an electrolytic plating method in which solder is deposited by electrolytic plating, or a ball mounting method in which solder balls are mounted.

ペースト印刷法では、感光性樹脂層２０２の開口部１０６をマスクパターンとして使用し、感光性樹脂層２０２の上に置いたはんだペーストをスキージでかいて、前記開口部１０６に押し込むことで充填することができる。
電解めっき法では、Ｃｕポストを形成する際に使用したシード層２０１より給電し、はんだを析出することができる。 In the paste printing method, the openings 106 of the photosensitive resin layer 202 are used as a mask pattern, and the solder paste placed on the photosensitive resin layer 202 is drawn with a squeegee and pressed into the openings 106 for filling. can.
In the electroplating method, power is supplied from the seed layer 201 used when forming the Cu posts, and solder can be deposited.

何れの方法でも、前記感光性樹脂層２０２の開口部１０６の高さより、はんだが積層された後の全体の高さを低く形成することで、最終的に製造される配線外部電極１０の高さを制御することが可能となる。 In either method, the height of the wiring external electrode 10 finally manufactured is lowered by forming the overall height after the solder is laminated lower than the height of the opening 106 of the photosensitive resin layer 202. can be controlled.

ボール搭載法では、感光性樹脂層２０２の開口部１０６にフラックスを充填させ、さらにはんだボールを振り込むことではんだを形成することができる。この方法では、はんだ量がはんだボールの体積で決まるため、ばらつきの少ないはんだを形成することができる。 In the ball mounting method, the solder can be formed by filling the openings 106 of the photosensitive resin layer 202 with flux, and then sprinkling solder balls. With this method, the amount of solder is determined by the volume of the solder ball, so solder can be formed with little variation.

次いで、感光性樹脂層２０２の開口部１０６に充填したはんだを、はんだの組成に応じた温度で加熱溶融処理する。溶融したはんだは表面張力によりドーム形状になる。
はんだの溶融温度はその材料組成により変化する。本実施形態では、Ｓｎ―３．０Ａｇ－０．５Ｃｕの合金材料を使用し、加熱温度は２５４℃にて制御した。 Next, the solder filling the openings 106 of the photosensitive resin layer 202 is heated and melted at a temperature corresponding to the composition of the solder. The molten solder takes on a dome shape due to surface tension.
The melting temperature of solder varies with its material composition. In this embodiment, an alloy material of Sn-3.0Ag-0.5Cu was used, and the heating temperature was controlled at 254.degree.

このとき感光性樹脂層２０２として、はんだを加熱溶融する温度で収縮変形する材料を選択することで、感光性樹脂層２０２とＣｕポストの間に間隙５１が形成される。本実施形態では例えば１～５μｍの間隙５１が形成される。 At this time, a gap 51 is formed between the photosensitive resin layer 202 and the Cu post by selecting a material that shrinks and deforms at the temperature at which the solder is heated and melted for the photosensitive resin layer 202 . In this embodiment, a gap 51 of 1 to 5 μm, for example, is formed.

表面処理層形成時の前処理エッチングによる間隙５０、感光性樹脂層２０２熱収縮による間隙５１のいずれか、もしくは両方を利用することで、はんだを溶融する工程で、感光性樹脂層２０２とＣｕポストとの間隙にはんだが入り込み、Ｃｕポストの側面の一部にはんだを形成することが可能となる。 By using either or both of the gap 50 due to pretreatment etching at the time of forming the surface treatment layer and the gap 51 due to heat shrinkage of the photosensitive resin layer 202, the photosensitive resin layer 202 and the Cu post can be separated from each other in the process of melting the solder. Solder enters into the gap between and, and solder can be formed on a part of the side surface of the Cu post.

図３Ｇは、感光性樹脂層２０２をはく離した後の基板の断面図である。感光性樹脂層２０２を剥離液にて剥離し、Ｃｕポストとはんだの積層体を露出する構造を得る。
剥離液としては特に規定しないが、感光性樹脂層２０２を剥離可能で、Ｃｕポストやはんだへのダメージの少ない液体を選択すればよい。例えば、アルカリ系のアミン系の水溶液や水酸化ナトリウム水溶液が使用可能である。 FIG. 3G is a cross-sectional view of the substrate after the photosensitive resin layer 202 is stripped. The photosensitive resin layer 202 is peeled off with a peeling solution to obtain a structure in which the laminated body of the Cu post and the solder is exposed.
Although the peeling liquid is not particularly specified, a liquid that can peel the photosensitive resin layer 202 and causes less damage to the Cu posts and solder may be selected. For example, an alkaline amine-based aqueous solution or a sodium hydroxide aqueous solution can be used.

図３Ｈは、シード層２０１をエッチング除去した後の基板の断面図である。シード層２０１をエッチングする際、エッチング液にＣｕを選択的にエッチング可能な材料を選択することで、Ｃｕポストの側面のうち、はんだに対し露出している部分もエッチングすることができる。一方、はんだで覆われている部分では、はんだがマスクとなりエッチングされないため、図２Ｂの第１突出形状面１１４（Ｘ方向の長さΔＡ）を形成することができる。 FIG. 3H is a cross-sectional view of the substrate after seed layer 201 is etched away. When the seed layer 201 is etched, by selecting a material that can selectively etch Cu as an etchant, it is possible to etch the portions of the side surfaces of the Cu posts that are exposed to the solder. On the other hand, since solder serves as a mask and is not etched in a portion covered with solder, the first projecting shaped surface 114 (length ΔA in the X direction) of FIG. 2B can be formed.

Ｃｕを選択的にエッチングするエッチング液として、例えば(a)硫酸過水、(b)リン酸、モノエタノールアミン、過水、(c)銅錯体、アンモニア、(d)アミン化合物、有機酸、のいずれかの溶液を使用することができる。エッチング量は、エッチング液の材料やエッチング時間などで調整されるが、最終的に第１導電性部材のパッド部突出形状面のΔＡが0.5～３μm（好ましくは1～３μm）となるようにエッチング量を調整する。 Etching solutions for selectively etching Cu include, for example, (a) sulfuric acid/hydrogen peroxide, (b) phosphoric acid, monoethanolamine, hydrogen peroxide, (c) copper complexes, ammonia, (d) amine compounds, and organic acids. Either solution can be used. The amount of etching is adjusted depending on the material of the etchant, the etching time, etc., but the final etching is performed so that the ΔA of the protruding surface of the pad portion of the first conductive member is 0.5 to 3 μm (preferably 1 to 3 μm). Adjust quantity.

図３Ｉは、はんだを加圧プレスし平坦化処理した後の基板の断面図である。Ｃｕポストとはんだの積層体を加圧プレスすることで、第２導電性部材１２となるはんだの先端が平坦となる。必須工程ではないが、半導体素子３００を実装時の位置ずれを低減することが可能となる。 FIG. 3I is a cross-sectional view of the substrate after the solder has been pressure pressed and planarized. By pressing the laminated body of the Cu post and the solder, the tip of the solder that becomes the second conductive member 12 is flattened. Although it is not an essential step, it is possible to reduce misalignment during mounting of the semiconductor element 300 .

このようにして得た配線基板１と、半導体素子３００を素子外部電極３０１を介して実装し、アンダーフィル１０７を充填し、図１に示す半導体装置４００が完成する。 The wiring board 1 thus obtained and the semiconductor element 300 are mounted via the element external electrodes 301, and the underfill 107 is filled to complete the semiconductor device 400 shown in FIG.

以上、本発明の実施の形態について説明したが、本発明は、上述した実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更が可能である。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present invention.

１・・・配線基板、１０・・・配線外部電極、１１・・・第１導電性部材、
１２・・・第２導電性部材、５０・・・間隙、５１・・・間隙、
１００・・・内層配線基板、１０１・・・内層絶縁層、
１０２・・・内層配線パターン、１０３・・・配線層、１０４・・・内層ビア、
１０５・・・外層配線基板、１０６・・・開口部、１０７・・・アンダーフィル、
１１０・・・ビア部、１１１・・・ポスト部、１１２・・・パッド部、
１１３・・・突出形状面、１１４・・・第１突出形状面、１１５・・・第２突出形状面、２０１・・・シード層、２０２・・・感光性樹脂層、３００・・・半導体素子、
３０１・・・素子外部電極、４００・・・半導体装置 DESCRIPTION OF SYMBOLS 1... Wiring board, 10... Wiring external electrode, 11... First conductive member,
12... second conductive member, 50... gap, 51... gap,
100... inner layer wiring board, 101... inner layer insulating layer,
102... inner layer wiring pattern, 103... wiring layer, 104... inner layer via,
105... outer layer wiring board, 106... opening, 107... underfill,
110: Via portion, 111: Post portion, 112: Pad portion,
DESCRIPTION OF SYMBOLS 113... Protruding shape surface 114... 1st protruding shape surface 115... Second protruding shape surface 201... Seed layer 202... Photosensitive resin layer 300... Semiconductor element ,
301... element external electrode, 400... semiconductor device

Claims (8)

内層配線基板と、外層配線基板と、配線外部電極を備える配線基板において、
前記配線外部電極は、第１導電性部材と第２導電性部材を備え、
前記第１導電性部材は、前記第２導電性部材に上面と側面を覆われている部分（以下、「パッド部」という。）と、前記外層配線基板から突出し前記第２導電性部材に側面を覆われていない部分（以下、「ポスト部」という。）を有し、
前記パッド部の底面は前記ポスト部の上面より広い第１突出形状面を有し、前記第２導電性部材の前記パッド部の側面を覆う部分の底面は前記第１突出形状面につながって広がる第２突出形状面を有している、配線基板。 A wiring board comprising an inner layer wiring board, an outer layer wiring board, and a wiring external electrode,
The wiring external electrode comprises a first conductive member and a second conductive member,
The first conductive member has a portion (hereinafter referred to as a “pad portion”) whose upper surface and side surfaces are covered with the second conductive member, and a portion that protrudes from the outer layer wiring board and has side surfaces that are covered with the second conductive member. has a portion that is not covered (hereinafter referred to as “post portion”),
The bottom surface of the pad portion has a first protruding shape surface wider than the top surface of the post portion, and the bottom surface of the portion of the second conductive member covering the side surface of the pad portion is connected to the first protruding shape surface and spreads. A wiring board having a second projecting shaped surface. 前記配線外部電極は中心軸に対し回転対象形状をとり、
前記第１突出形状面、および前記第２突出形状面はリング形状をとる、請求項１に記載の配線基板。 The wiring external electrode has a rotationally symmetrical shape with respect to the central axis,
2. The wiring board according to claim 1, wherein said first projecting surface and said second projecting surface are ring-shaped. 前記第１突出形状面において、前記リング形状の半径方向の幅の長さが０．５～３μmの範囲にある、請求項２に記載の配線基板。 3. The wiring board according to claim 2, wherein the radial width of the ring shape is in the range of 0.5 to 3 μm on the first projecting surface. 前記第２突出形状面において、前記リング形状の半径方向の幅の長さが１．２～７μmの範囲にある、請求項２または３に記載の配線基板。 4. The wiring board according to claim 2, wherein the radial width of the ring shape is in the range of 1.2 to 7 μm on the second projecting surface. 前記第１導電性部材が銅からなることを特徴とする請求項１～４のいずれかに記載の配線基板。 5. The wiring board according to claim 1, wherein said first conductive member is made of copper. 前記第２導電性部材がスズ、銀、銅、鉛、ビスマス、インジウム、アンチモンの何れかの金属の1つないし複数からなることを特徴とする請求項１～５のいずれかに記載の配線基板。 6. The wiring board according to claim 1, wherein said second conductive member is made of one or more of tin, silver, copper, lead, bismuth, indium and antimony. . 前記配線基板の製造方法が、
（１）前記外層配線基板にシード層を形成する工程と、
（２）前記シード層を感光性樹脂層にて被覆し、前記配線外部電極を形成する位置に前記感光性樹脂層の開口部を設ける工程と、
（３）前記感光性樹脂層の開口部に前記第１導電性部材を形成する工程と、
（４）前記感光性樹脂層の開口部に前記第２導電性部材を充填する工程と、
（５）前記第２導電性部材の溶融温度で熱処理し、前記第１導電性部材の上面、および側面の一部を前記第2導電性部材で覆う工程と、
（６）前記感光性樹脂層を剥離し、前記第１導電性部材と前記第２導電性部材を露出する工程と、
（７）前記シード層と前記第１導電性部材とを選択的にエッチングするエッチング液でエッチング処理する工程、
を有する、請求項１～６に記載の配線基板の製造方法。 The method for manufacturing the wiring board comprises:
(1) forming a seed layer on the outer wiring board;
(2) covering the seed layer with a photosensitive resin layer and providing an opening in the photosensitive resin layer at a position where the wiring external electrode is to be formed;
(3) forming the first conductive member in the opening of the photosensitive resin layer;
(4) filling the opening of the photosensitive resin layer with the second conductive member;
(5) heat-treating at the melting temperature of the second conductive member to cover the upper surface and part of the side surface of the first conductive member with the second conductive member;
(6) peeling the photosensitive resin layer to expose the first conductive member and the second conductive member;
(7) etching with an etchant that selectively etches the seed layer and the first conductive member;
The method for manufacturing a wiring board according to any one of claims 1 to 6, having 前記感光性樹脂層の開口部に前記第２導電性部材を充填する工程の前に、前記感光性樹脂層の開口部に形成された前記第１導電性部材の表面に前処理エッチングを行う、請求項７に記載の配線基板の製造方法。 Before the step of filling the opening of the photosensitive resin layer with the second conductive member, pretreatment etching is performed on the surface of the first conductive member formed in the opening of the photosensitive resin layer. The method of manufacturing the wiring board according to claim 7 .
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