JP2023012133A - Circuit module and electronic device - Google Patents

Abstract

To reduce signal transmission loss.SOLUTION: A circuit module 100 includes a slave substrate 101 having a signal line 11 and a master substrate 102 fixed to the slave substrate 101. The signal line 11 has a signal pattern 111, which is a conductor pattern, the signal pattern 111 facing a main surface 1191 of the master substrate 102 and arranged on a main surface 1171 of the slave substrate 101. The master substrate 102 has a conductor plane 15 arranged on the main surface 1191 so as to face the signal pattern 111 with spacing.SELECTED DRAWING: Figure 2

Description

The present invention relates to signal transmission technology.

In general, when performing digital signal communication between two semiconductor elements, a signal line is used as a signal transmission line. A signal line is formed on a substrate such as a printed wiring board, and two semiconductor elements are mounted on the substrate. In order to suppress signal crosstalk between signal lines, signal lines are generally placed adjacent to a ground layer or a power supply layer via an insulating layer on a substrate. Patent Document 1 discloses a printed wiring board in which a conductor layer having signal lines is arranged adjacent to a ground layer or a power supply layer.

JP 2007-213375 A

2. Description of the Related Art As electronic devices become more sophisticated, signal transmission speeds tend to increase. As the speed of signals increases, the problem of increased signal attenuation has become conspicuous. If the amount of signal attenuation increases in the signal line, the signal waveform is distorted in the process of propagating the signal wave through the signal line, and there is a risk of malfunction in the semiconductor element on the signal receiving side.

An object of the present invention is to reduce signal transmission loss.

A circuit module of the present invention includes a first substrate having a signal line, and a second substrate fixed to the first substrate, the signal line facing a second surface of the second substrate. A first substrate has a signal pattern arranged on a first surface thereof, and the second substrate has a conductor plane arranged on the second surface so as to face the signal pattern with a gap therebetween. Characterized by

According to the present invention, signal transmission loss is reduced.

1 is an explanatory diagram of a digital camera according to an embodiment; FIG. (a) is a plan view of the circuit module according to the embodiment. (b) is a cross-sectional view of the circuit module according to the embodiment. 3 is a cross-sectional view of the circuit module taken along line III-III in FIG. 2(b); FIG. (a) and (b) are sectional views of a circuit module of a modification. (a) and (b) are sectional views of a circuit module of a modification. 4 is a graph of Example 1 and Comparative Example 1; 4 is a graph of Example 2; (a) is a cross-sectional view of a circuit module of a comparative example. (b) is a cross-sectional view of the circuit module taken along line VIIIB-VIIIB shown in (a).

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram of a digital camera 600 according to an embodiment. A digital camera 600 is an interchangeable-lens digital camera and includes a camera body 601 . The camera body 601 is an example of electronic equipment. A camera body 601 is detachable with a lens unit (lens barrel) 602 including lenses. Note that the lens unit and the camera body may be integrated to form an electronic device.

The camera body 601 includes a housing 611 , a circuit module 100 and a circuit module 200 . The circuit module 100 and the circuit module 200 are housed inside the housing 611 . A battery (not shown) is accommodated inside the housing 611 . The circuit module 100 and the circuit module 200 are connected by a flexible printed wiring board 300 .

The circuit module 200 is an imaging module in this embodiment. The circuit module 200 includes a printed wiring board 201 and an image sensor 202 mounted on the printed wiring board 201 . The image sensor 202 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor. The image sensor 202 has a function of converting light incident through the lens unit 602 into an electrical signal.

The circuit module 100 is an image processing module in this embodiment. The circuit module 100 has a mother board 102 , a circuit unit 110 mounted on the mother board 102 , and a power supply unit 130 mounted on the mother board 102 . The power supply unit 130 converts a voltage supplied from a battery (not shown) into a predetermined power supply voltage V0 and applies it to the circuit unit 110, thereby supplying the circuit unit 110 with the power necessary for the operation of each part of the circuit unit 110. This is the power supply circuit that supplies the power. The power supply voltage V0 is a DC voltage.

FIG. 2(a) is a plan view of the circuit module 100 according to the embodiment. FIG. 2B is a cross-sectional view of the circuit module 100 according to the embodiment. FIG. 3 is a cross-sectional view of the circuit module 100 taken along line III-III in FIG. 2(b).

The circuit unit 110 includes a child board 101 , a logic LSI (Large Scale Integration) 103 mounted on the child board 101 , and two memory ICs (Integrated Circuits) 104 mounted on the child board 101 . The logic LSI 103 is an example of a first semiconductor element. Memory IC 104 is an example of a second semiconductor element. Further, the child board 101 is an example of a first board, and the parent board 102 is an example of a second board. The number of memory ICs 104, that is, the number of second semiconductor elements is two in this embodiment, but may be one or three or more.

The logic LSI 103 is an element that performs image processing. Specifically, the logic LSI 103 has a function of acquiring an electrical signal representing image data from the image sensor 202, correcting the acquired electrical signal, and generating corrected image data. The logic LSI 103 also functions as a memory controller that controls the memory IC 104 . The memory IC 104 is a memory element capable of storing data such as image data, and can store data transmitted from the logic LSI 103 under the control of the logic LSI 103 .

Signals that can be communicated between the logic LSI 103 and each memory IC 104 are digital signals such as data signals, address signals, command signals, and clock signals. In this embodiment, the digital signal is a single-ended signal. The digital signal transmission speed is 200 Mbps or higher, preferably 2 Gbps or higher, and more preferably 5 Gbps or higher. When the transmission speed of the digital signal is 2 Gbps, the frequency of the fundamental wave of the digital signal is 1 GHz, the triple harmonic is 3 GHz, and the fifth harmonic is 5 GHz. Thus, the higher the transmission speed of the digital signal, the higher the frequency of the signal wave component contained in the digital signal.

The logic LSI 103 and each memory IC 104 operate when the power supply unit 130 applies a power supply voltage V0, for example, a DC voltage of 1.1V. Note that the power supply unit 130 may be mounted on the daughter board 101 instead of the mother board 102 or may be mounted on a board other than the mother board 102 and the daughter board 101 . In other words, the power supply unit 130 only needs to be able to supply power to the logic LSI 103 and each memory IC 104 and is arranged inside the housing 611 .

In this embodiment, development efficiency is improved by unitizing the logic LSI 103 and the memory IC 104 . Also, the logic LSI 103 and the memory IC 104 are arranged close to each other so as to reduce transmission loss of digital signals. As a result, the size of the circuit unit 110 is also reduced.

In this embodiment, the child board 101 is a rigid board. The substrate of the child substrate 101 may be any substrate such as a semiconductor substrate such as silicon, a ceramic substrate, or a glass epoxy substrate, but the glass epoxy substrate is preferable from the viewpoint of cost and ease of procurement. A glass epoxy substrate is a substrate obtained by impregnating a glass cloth with an epoxy resin. In this embodiment, the child board 101 is a rigid printed wiring board using an insulating base material as the base material.

In this embodiment, the parent substrate 102 is a rigid substrate. The base material of the mother board 102 may be any substrate such as a semiconductor substrate such as silicon, a ceramic substrate, or a glass epoxy substrate, but a glass epoxy substrate is preferable from the viewpoint of cost and ease of procurement. In this embodiment, the mother board 102 is a rigid printed wiring board using an insulating base material as the base material.

The child board 101 has an insulating base material 117 that is an example of a first insulator part, and a conductor part arranged inside or outside the insulating base material 117 . The insulating base material 117 has a major surface 1171 that is an example of a first surface and a major surface 1172 that is an example of a third surface and is opposite to the major surface 1171 . The main surface 1171 is the surface facing the mother substrate 102 . The logic LSI 103 and each memory IC 104 are mounted on the main surface 1172 .

The mother board 102 has an insulating base material 119 that is an example of a second insulator part, and a conductor part arranged inside or outside the insulating base material 119 . The insulating base material 119 has a major surface 1191 that is an example of a second surface and a major surface 1192 that is an example of a fourth surface and is opposite to the major surface 1191 . The main surface 1191 is the surface facing the circuit unit 110 , that is, the child board 101 . Circuit unit 110 is mounted on main surface 1191 . The child board 101 is smaller than the parent board 102 in plan view, that is, in the Z direction perpendicular to the main surface 1191 .

In this embodiment, the circuit unit 110 is mounted on the mother board 102 so that the main surface 1171 and the main surface 1191 face each other. Since the logic LSI 103 and each memory IC 104 are not present between the main surfaces 1171 and 1191, the distance between the main surfaces 1171 and 1191 can be narrowed.

The logic LSI 103 is electrically and mechanically connected to the child board 101 through a plurality of connection terminals 106 . Specifically, the logic LSI 103 is connected to a plurality of pads arranged on the main surface 1172 of the daughter board 101 with a plurality of connection terminals 106 . Thus, the plurality of connection terminals 106 are arranged between the logic LSI 103 and the main surface 1172 and used to fix the logic LSI 103 to the child board 101 .

Each memory IC 104 is electrically and mechanically connected to the sub-board 101 through a plurality of connection terminals 107 . Specifically, each memory IC 104 is connected to a plurality of pads arranged on the main surface 1172 of the daughter board 101 with a plurality of connection terminals 107 . Thus, the plurality of connection terminals 107 are arranged between the corresponding memory ICs 104 and the main surface 1172 and are used to fix the corresponding memory ICs 104 to the child board 101 .

The child board 101 is electrically and mechanically connected to the parent board 102 with a plurality of connection terminals 108 . Specifically, a plurality of pads arranged on main surface 1171 of child board 101 and a plurality of pads arranged on main surface 1191 of parent board 102 are connected by a plurality of connection terminals 108 . Thus, the plurality of connection terminals 108 are arranged between the main surface 1171 and the main surface 1191 and are used to secure the daughter board 101 to the mother board 102 . Each connection terminal 106, 107, 108 contains a bonding material such as solder.

The child board 101 has at least two conductor layers, two conductor layers 1011 and 1012 in this embodiment. Conductor layer 1011 is an example of a first conductor layer. The conductor layer 1012 is an example of a second conductor layer. The conductor layers 1011, 1012 are layers on which conductive conductor patterns, ie metal foils, are arranged. Each conductor layer 1011, 1012 is a surface layer. That is, conductor layer 1011 is defined on major surface 1171 and conductor layer 1012 is defined on major surface 1172 . That is, the child board 101 preferably has at least two surface layers, and may have an inner layer (conductor layer) in addition to the two surface layers. In this embodiment, the conductor layer 1012 is a conductor layer adjacent to the conductor layer 1011 with the insulating material (dielectric material) of the insulating base material 117 interposed therebetween. Conductor layer 1011 is covered with solder-resist film 118 , which is a first solder-resist film disposed on main surface 1171 , except for portions connected to connection terminals 108 . A solder-resist film 118 may be disposed on a portion of the conductor layer 1011 where there is no conductor pattern.

Mother board 102 may have at least one conductor layer. The mother board 102 preferably has two conductor layers or less, and has two conductor layers 1021 and 1022 in this embodiment. The conductor layers 1021, 1022 are layers on which conductive conductor patterns, ie metal foils, are arranged. Each conductor layer 1021, 1022 is a surface layer. That is, conductor layer 1021 is defined on major surface 1191 and conductor layer 1022 is defined on major surface 1192 . That is, the mother substrate 102 preferably has at least a surface layer on the main surface 1191 side, and may have a surface layer on the main surface 1192 side and/or an inner layer (conductor layer) in addition to the surface layer on the main surface 1191 side. . Conductor layer 1021 is covered with solder-resist film 120, which is a second solder-resist film disposed on main surface 1191, except for portions connected to connection terminals 108. FIG. A solder-resist film 120 may be disposed on a portion of the conductor layer 1021 where there is no conductor pattern.

The conductor layer 1022 may be omitted. In this case, the mother substrate 102 is a substrate having only one conductor layer 1021 as at least one conductor layer.

The child board 101 has a plurality of signal lines 11 respectively corresponding to the two memory ICs 104 . For example, the logic LSI 103 and each memory IC 104 are electrically connected by 40 to 50 signal lines 11 . Each signal line 11 is made of a metal such as copper, that is, a conductor.

The plurality of connection terminals 106 includes a power terminal 1061 , a ground terminal 1062 and a plurality of transmission terminals 1063 . Although only one power supply terminal 1061 and one ground terminal 1062 are shown in FIG. 2B, there may be a plurality of each.

The plurality of connection terminals 107 includes a power terminal 1071 , a ground terminal 1072 and a plurality of reception terminals 1073 . Although only one power supply terminal 1071 and one ground terminal 1072 are illustrated in FIG. 2B, there may be a plurality of each.

The logic LSI 103 operates by applying a power supply voltage V0 between the power supply terminal 1061 and the ground terminal 1062 via the line L0 of the circuit module 100, that is, the power supply line L1 and the ground line L2. The memory IC 104 operates by applying a power supply voltage V0 between the power supply terminal 1071 and the ground terminal 1072 through the line L0, that is, the power supply line L1 and the ground line L2. The line L0 is made of a metal such as copper, that is, a conductor. The line L0 includes a power line L1 having a power potential V1 and a ground line L2 having a ground potential V2. Here, the potential difference (V1−V2) between the power supply potential V1 and the ground potential V2 is the power supply voltage V0, which is the operating voltage of the logic LSI 103 and the memory IC 104. FIG.

Each transmission terminal 1063 is a terminal for transmitting a digital signal. Each receiving terminal 1073 is a terminal for receiving a digital signal. Each signal line 11 is electrically connected to the corresponding transmission terminal 1063 of the logic LSI 103 and the corresponding reception terminal 1073 of the memory IC 104 . As a result, digital signals can be transmitted between the logic LSI 103 and each memory IC 104 via each signal line 11 .

A plurality of signal lines 11 corresponding to each memory IC 104 are arranged in parallel with a space therebetween, as shown in FIG. 2(a). From the viewpoint of miniaturization of the circuit unit 110, that is, miniaturization of the circuit module 100, it is preferable that the distance between the plurality of signal lines 11 is as narrow as possible. At that time, in order to reduce crosstalk between the plurality of signal lines 11, it is preferable that the signal lines 11 are close to a reference line with a stable potential and little potential fluctuation, such as the ground line L2 or the power line L1.

Here, a circuit module of a comparative example will be described. FIG. 8A is a cross-sectional view of a circuit module 100X of a comparative example. FIG. 8(b) is a cross-sectional view of the circuit module 100X along line VIIIB-VIIIB shown in FIG. 8(a). The circuit module 100X has a logic LSI 103X, a memory IC 104X, and a substrate 102X on which the logic LSI 103X and the memory IC 104X are mounted. The board 102X is a rigid printed wiring board having three or more conductor layers, for example, a board having six conductor layers.

The logic LSI 103X is connected to the substrate 102X through a plurality of connection terminals 106X, and the memory IC 104X is connected to the substrate 102X through a plurality of connection terminals 107X. The multiple connection terminals 106X include a transmission terminal 1063X for transmitting signals, a power supply terminal 1061X, and a ground terminal 1062X. The multiple connection terminals 107X include a reception terminal 1073X for receiving signals, a power supply terminal 1071X, and a ground terminal 1072X.

Among the six conductor layers of the substrate 102X, from the surface layer on which the logic LSI 103X and the memory IC 104X are mounted, the first to sixth conductor layers are arranged in order toward the opposite surface layer. The six conductor layers are spaced apart in the Z direction via the insulator of the insulating base material 119X. A power terminal 1061X of the logic LSI 103X and a power terminal 1071X of the memory IC 104X are connected by a conductor pattern L1X arranged on the first conductor layer. The ground terminal 1062X of the logic LSI 103X and the ground terminal 1072X of the memory IC 104X are connected by wiring including the conductor pattern L2X arranged on the third conductor layer of the substrate 102X. A transmission terminal 1063X of the logic LSI 103X and a reception terminal 1073X of the memory IC 104X are connected by a signal line including the signal pattern 111X arranged on the second conductor layer. Therefore, the signal pattern 111X is sandwiched between the conductor patterns L1X and L2X via an insulator. Various conductor patterns 116X are also arranged on each of the fourth to sixth conductor layers. A solder resist film 120X is formed on the conductor pattern L1X.

The insulating base material 119X is made of an insulator (dielectric) having a dielectric constant higher than that of the solder resist film 120X, such as glass epoxy. The signal pattern 111X is arranged adjacent to the conductor patterns L1X and L2X via the insulating material (dielectric material) of the insulating base material 119X. This suppresses crosstalk of digital signals propagating through the signal pattern 111X. Since the signal pattern 111X is arranged to face the conductor patterns L1X and L2X via a dielectric material with a high dielectric constant, the dielectric loss due to the dielectric material of the insulating base material 119X increases as the speed of digital signals increases. and the digital signal is distorted. In particular, the amount of attenuation of harmonic components in the digital signal, such as the third harmonic component and the fifth harmonic component, increases. Among the third harmonic component and the fifth harmonic component, the attenuation amount of the fifth harmonic component is particularly large. When the transmission speed of the digital signal is 200 Mbps or higher, the distortion of the digital signal becomes large, and when the transmission speed of the digital signal is 2 Gbps or higher, the distortion of the digital signal becomes significant. In particular, when the transmission speed of the digital signal is 5 Gbps or higher, the distortion of the digital signal becomes more pronounced. Here, for example, when the transmission speed of a digital signal is 2 Gbps, the frequency of the 3rd harmonic is 3 GHz and the frequency of the 5th harmonic is 5 GHz with respect to the frequency of the fundamental wave of the digital signal of 1 GHz. Therefore, the attenuation amount is large in the high frequency band of 3 GHz or higher, and the attenuation amount is particularly large in the high frequency band of 5 GHz or higher.

In this embodiment, signal line 11 includes signal pattern 111 disposed on major surface 1171 , ie, conductor layer 1011 . The signal pattern 111 is a strip-shaped conductor pattern. In addition, the signal line 11 includes a signal via 112 extending in the Z direction connecting the transmitting terminal 1063 and the signal pattern 111, and a signal via 113 extending in the Z direction connecting the receiving terminal 1073 and the signal pattern 111. include. The signal pattern 111 is composed of a conductor pattern, that is, a metal foil such as copper foil. Each signal via 112, 113 is a via conductor. A conductor pattern 121 is arranged on the conductor layer 1012 .

The mother board 102 also has a conductor plane 15 arranged on the main surface 1191 , ie, on the conductor layer 1021 . The conductor plane 15 is also made of metal foil such as copper foil. The conductor plane 15 is a solid conductor pattern. A conductor pattern 122 is arranged on the conductor layer 1022 . The signal pattern 111 and the conductor plane 15 are opposed to each other with an interval D1 in the Z direction so as not to be short-circuited. The conductor plane 15 is part of the line L0 used to apply the power supply voltage V0 to the logic LSI 103 and memory IC 104. FIG.

In this embodiment, the conductor plane 15 is a part of the ground line L2 of the line L0, which has the ground potential V2. Since the signal pattern 111 and the conductor plane 15 are arranged on the main surfaces 1171 and 1191 facing each other, the signal pattern 111 and the conductor plane 15 are close to each other. That is, the signal pattern 111 and the conductor plane 15 face each other. Therefore, a return current for the signal current flowing through the signal pattern 111 easily flows through the conductor plane 15, and crosstalk between the signal lines 11 is suppressed. Moreover, even in the signal line 11 through which high-speed digital signals propagate, a stable characteristic impedance can be realized.

Also, the dielectric loss is proportional to the dielectric constant of the dielectric between the signal line and the ground line (or power line). In this embodiment, the insulating material (dielectric material) of the insulating substrates 117 and 119 does not exist between the signal pattern 111 and the conductor plane 15 . Therefore, the dielectric loss due to the insulating bases 117 and 119 is reduced, and the distortion of the digital signal propagating through the signal line 11, that is, the transmission loss of the digital signal is reduced. In particular, since the attenuation amount of the harmonic components of the digital signal in the high frequency band is reduced, the transmission loss of the digital signal is reduced.

The Z-direction spacing D1 between the signal pattern 111 and the conductor plane 15 is preferably narrower than the Z-direction spacing D2 between the adjacent conductor layers 1011 and 1012 on the child board 101 . As a result, the electric field coupling between the signal pattern 111 and the conductor plane 15 is strengthened, the dielectric loss is more effectively reduced, and the distortion of the digital signal propagating through the signal line 11, that is, the transmission loss of the digital signal is effectively reduced. be. Also, local variation in the characteristic impedance of the signal pattern 111 is reduced, and the characteristic impedance can be stabilized at a desired value, eg, 60Ω. In addition, there is an effect that the mechanical strength of the sub-board 101 is increased. Thus, in this embodiment, a desired value of characteristic impedance can be achieved with the two-layer sub-board 101, which is effective for cost reduction. Also, the parent substrate 102 can be a two-layer substrate or a single-sided substrate to achieve a desired value of characteristic impedance.

Here, between the signal pattern 111 and the conductor plane 15, there are solder resist films 118, 120 having a dielectric constant lower than that of the insulating substrates 117, 119. FIG. For example, the insulating substrates 117 and 119 have a dielectric constant of 4.3, and the solder resist films 118 and 120 have a dielectric constant of 3.0. Since the dielectric constants of the solder resist films 118 and 120 that protect the signal pattern 111 and the conductor plane 15 are lower than the dielectric constants of the insulating substrates 117 and 119, the dielectric loss is reduced and the transmission loss of the digital signal is reduced. be done.

Also, an air gap D3 is preferably provided between the signal pattern 111 and the conductor plane 15 . This is because the relative dielectric constant of air is lower than the relative dielectric constant of the insulating substrates 117 and 119 and the relative dielectric constant of the solder resist films 118 and 120 . Air has a dielectric constant of 1.0. The air gap D3 is the distance in the Z direction between the solder-resist film 118 and the solder-resist film 120 in this embodiment. The presence of the air gap D3 effectively reduces the dielectric loss and effectively reduces the transmission loss of the digital signal.

All of the signal patterns 111 of each signal line 11 are positioned within a region surrounded by the outline of the conductor plane 15 when viewed in the Z direction, as shown in FIG. 2(a). As a result, signal crosstalk can be effectively suppressed. Further, all of the signal lines 11 are positioned within a region surrounded by the outline of the conductor plane 15 when viewed in the Z direction, as shown in FIG. 2(a). This makes it possible to more effectively suppress signal crosstalk.

Although it is preferable that the conductor plane 15 is set to the ground potential V2, it is not limited to this. The potential of the conductor plane 15 may be a potential for determining the amplitude of the digital signal (electrical signal) transmitted by the logic LSI 103 and may be a potential with little fluctuation, for example, it may be the power supply potential V1.

Here, the signal pattern 111 has a conductor surface 1111 facing the conductor plane 15 and a conductor surface 1112 opposite to the conductor surface 1111 and in contact with the main surface 1171 of the insulating base material 117 . Also, the conductor plane 15 has a conductor surface 151 facing the signal pattern 111 and a conductor surface 152 opposite to the conductor surface 151 and in contact with the principal surface 1191 of the insulating base material 119 . The conductor surface 1111 is an example of a first conductor surface, and the conductor surface 1112 is an example of a second conductor surface. The conductor surface 151 is an example of a third conductor surface, and the conductor surface 152 is an example of a fourth conductor surface.

In the present embodiment, in order to prevent separation between the insulating base material 117 and the signal pattern 111, that is, to bring the insulating base material 117 and the signal pattern 111 into close contact, the main surface 1171 of the insulating base material 117 and the conductor of the signal pattern 111 are separated from each other. The surface 1112 is a rough surface. By roughening the surfaces 1171 and 1112, the insulating base material 117 and the signal pattern 111 are fixed by an anchor effect.

Similarly, in order to prevent separation between the insulating base material 119 and the conductor plane 15, that is, to bring the insulating base material 119 and the conductor plane 15 into close contact, the principal surface 1191 of the insulating base material 119 and the conductor surface 152 of the conductor plane 15 are separated. and has a rough surface. By roughening the surfaces 1191 and 152, the insulating base material 119 and the conductor plane 15 are fixed by an anchor effect.

As the speed of digital signals increases, the signal current tends to concentrate on the surface of the signal pattern 111 due to the skin effect. In particular, among the signal currents, the higher the frequency component, the more likely it is to concentrate on the thin portion near the surface of the signal pattern 111 . For example, the 3rd and 5th harmonic components flow closer to the surface than the fundamental component, and the 5th harmonic component flows closer to the surface than the 3rd harmonic component. The higher the transmission speed of the digital signal, that is, the higher the frequency of the fundamental wave of the digital signal, the more pronounced the skin effect.

In this embodiment, since the signal pattern 111 faces the conductor plane 15 , the signal current tends to concentrate on the conductor face 1111 facing the conductor plane 15 among the conductor faces 1111 and 1112 of the signal pattern 111 . In this embodiment, the surface roughness of conductor surface 1111 is smaller than the surface roughness of conductor surface 1112 . Here, since the conductor surface 1112 is in contact with the main surface 1171, the surface roughness of the conductor surface 1112 and the surface roughness of the main surface 1171 are the same. That is, the surface roughness of conductor surface 1111 is smaller than the surface roughness of main surface 1171 . The surface roughness of the conductor surface 1111 is preferably 0.005 μm or more and 0.05 μm or less in arithmetic mean roughness Ra, and the surface roughness of the conductor surface 1112, that is, the surface roughness of the main surface 1171, is 0.5 μm or more and 5 μm or less. is preferred. In this way, the signal current is more likely to concentrate on the smooth conductor surface 1111 rather than the rough conductor surface 1112, so that the resistance loss of the signal current and the attenuation of the signal current are reduced. This makes it easier for the signal current to flow through the signal pattern 111, thereby reducing signal transmission loss.

A return current flows through the conductor plane 15 in the direction opposite to the direction in which the signal current flows. In this embodiment, since the conductor plane 15 faces the signal pattern 111 , the return current tends to concentrate on the conductor face 151 facing the signal pattern 111 among the conductor faces 151 and 152 of the conductor plane 15 . In this embodiment, the surface roughness of conductor surface 151 is smaller than the surface roughness of conductor surface 152 . Here, since the conductor surface 152 is in contact with the main surface 1191, the surface roughness of the conductor surface 152 and the surface roughness of the main surface 1191 are the same. That is, the surface roughness of conductor surface 151 is smaller than the surface roughness of principal surface 1191 . The surface roughness of the conductor surface 151 is preferably 0.005 μm or more and 0.05 μm or less in arithmetic mean roughness Ra, and the surface roughness of the conductor surface 152, that is, the surface roughness of the main surface 1191, is 0.5 μm or more and 5 μm or less. is preferred. In this way, the return current tends to concentrate on the smooth conductor surface 151 instead of the rough conductor surface 152, so that the resistance loss of the return current is reduced and the attenuation of the return current is reduced. This makes it easier for the return current to flow through the conductor plane 15, and as a result, the signal current also flows smoothly, reducing signal transmission loss. The conductor surface 1111 and the conductor surface 151 can be made smooth by plating metal on the surface of the metal foil.

[Modification]
In the above embodiment, the case where the air gap D3 exists, that is, D3>0, has been described, but the present invention is not limited to this. For example, as shown in FIG. 4A, the air gap D3 may be extremely small or may not exist. In these cases, it is possible to omit only one of the solder resist films 118 and 120 .

Moreover, if the air gap D3 exists, the solder resist film 120 may be omitted and the conductor plane 15 may be exposed to the air as shown in FIG. 4(b). Further, if the air gap D3 exists, the signal pattern 111 may be exposed to the air by omitting the solder resist film 118 as shown in FIG. 5(a). If the air gap D3 exists, both the solder resist films 118 and 120 may be omitted, and the signal pattern 111 and conductor plane 15 may be exposed to the air, as shown in FIG. 5(b).

(Example)
The signal transmission characteristics of the circuit module 100 of the embodiment and the circuit module 100X of the comparative example were obtained by computer simulation.

(Example 1)
The circuit module 100 used in Example 1 corresponds to the circuit module 100 of the above embodiment. The material of the conductor was mainly copper. Each of the signal pattern 111 and the conductor plane 15 is made of copper foil with a plated surface. The wiring width of the signal pattern 111 was set to 125 μm. The thickness of each solder resist film 118, 120 was set to 20 μm. The interval D1 was set to 20 μm.

As a suitable method for realizing the distance D1=20 μm, paste cream solder is applied to either the child substrate 101 or the mother substrate 102 by screen printing or the like, and then the child substrate 101 is placed on the mother substrate 102. place. Then, it can be realized by heating in a reflow furnace to melt the cream solder and then cooling to solidify the melted solder. However, the connection method is not limited to solder joint. In the case of soldering, it is preferable that the pitch of the connection terminals 108 is wider than the pitch of the terminals of the logic LSI 103 and the pitch of the terminals of the memory IC 104 on the child board 101 from the viewpoint of mounting reliability.

The insulating material of the insulating base materials 117 and 119 is a composite material in which glass fibers are impregnated with an epoxy resin. The relative dielectric constant of the insulating substrates 117 and 119 is 4.3, and the relative dielectric constant of the solder resist films 118 and 120 is 3.0. In the above configuration, the characteristic impedance of the signal pattern 111 was 60Ω.

(Comparative example 1)
The circuit module 100X used in Comparative Example 1 corresponds to the circuit module 100X of the comparative example. The material of the conductor was mainly copper. The insulating base material 119X is a composite material in which glass fibers are impregnated with an epoxy resin. The dielectric constant of the insulating base material 119X was set to 4.3.

The thickness of the copper foil of the signal pattern 111X, conductor pattern L2X, etc. was set to 18 μm. Since the conductor pattern L1X is a layer exposed to air, its surface is plated. Therefore, the thickness of the conductor pattern L1X is set to 43 μm, which is thicker than the signal pattern 111X and the conductor pattern L2X. The interval between the signal pattern 111X and the conductor pattern L1X was set to 200 μm, and the interval between the signal pattern 111X and the conductor pattern L2X was set to 400 μm. The wiring width of the signal pattern 111X was set to 125 μm. In the above embodiment, the characteristic impedance of the signal pattern 111X was 60Ω.

(Simulation results of Example 1 and Comparative Example 1)
6 is a graph showing transmission characteristics of Example 1 and Comparative Example 1. FIG. In FIG. 6, the vertical axis is the transmission characteristic and the horizontal axis is the frequency. The wiring length of each of the signal patterns 111 and 111X was set to 100 mm. The graph shown in FIG. 6 is a graph showing simulation results of transmission characteristics of the signal patterns 111 and 111X at frequencies from 1 MHz to 20 GHz. In FIG. 6, reference numeral 301 denotes transmission characteristics of Example 1, and reference numeral 302 denotes transmission characteristics of Comparative Example 1. In FIG. HyperLynx of Siemens EDA Japan Co., Ltd. was used as a simulator.

The transmission characteristic indicates, in voltage ratio, how much the sine-wave electric signal applied to the input ends of the signal patterns 111 and 111X is transmitted (propagated) to the output ends. The denominator of the voltage ratio is the voltage at the input and the numerator of the voltage ratio is the voltage at the output.

At 5 GHz, the transmission characteristic 302 of Comparative Example 1 was -2.87 dB, and the amplitude of the sine wave was attenuated by about 30%. On the other hand, the transmission characteristic 301 of Example 1 is -0.36 dB, and the amplitude of the sine wave is attenuated by about 4%. From the above results, according to the signal pattern 111 of Example 1, the transmission characteristics of the signal wave are greatly improved as compared with the signal pattern 111X of Comparative Example 1. FIG. That is, in signal transmission at 2 Gbps, in the signal pattern 111X of Comparative Example 1, the signal component of 5 GHz, which is a five-fold harmonic of the fundamental wave, is attenuated by about 30%. be. On the other hand, in the signal pattern 111 of the first embodiment, the attenuation of the signal component of 5 GHz, which is the five-fold harmonic of the fundamental wave, is about 4%. Therefore, in the first embodiment, high-speed transmission of digital signals can be realized.

The transmission characteristic 301 as shown in FIG. 6 is considered to be because the dielectric loss tangent between the signal pattern 111 and the conductor plane 15, that is, the dielectric loss, is small in the structure of the circuit module 100 of the first embodiment.

In addition, although the signal pattern 111X of the comparative example 1 is sandwiched between the conductor patterns L1X and L2X, in order to increase the strength of the substrate 102X having three or more layers by the anchor effect, the signal pattern 111X included in the substrate 102X, etc. The surface of the copper foil of is roughened. Since the surface of the copper foil is roughened, the resistance loss due to the skin effect increases, and the attenuation of the sine wave is considered to be large. On the other hand, in the signal pattern 111 of the first embodiment, the conductor surface 1111 of the signal pattern 111 and the conductor surface 151 of the conductor plane 15 facing the conductor surface 1111 are plated with copper to form smooth surfaces. The flatness of each conductor surface 1111, 151 is good, so the resistance loss due to the skin effect is small, and the attenuation of signal waves can be suppressed.

In FIG. 6, the difference between transmission characteristics 301 and 302 at 20 GHz is greater than the difference between transmission characteristics 301 and 302 at 5 GHz. Thus, the difference between the transmission characteristics 301 and 302 increases as the transmission speed of the digital signal increases. That is, in the first embodiment, the higher the transmission speed of the digital signal, the higher the effect of reducing the amount of attenuation of the digital signal.

(Example 2)
7 is a graph showing simulation results of Example 2. FIG. In Example 2, the characteristic impedance of the signal pattern 111 was simulated when the interval D1, the width w of the signal pattern 111, and the thickness hr of the solder resist films 118 and 120 were changed in the configuration of Example 1. FIG.

Impedance matching is also important to ensure the quality of digital signals in high-speed transmission. Considering the reduction of signal wave reflection in the memory IC 104 and the signal via 113, the characteristic impedance of the signal pattern 111 is preferably 40Ω or more and 80Ω or less, more preferably 60Ω.

From the graph shown in FIG. 7, it is preferable that the interval D1 be 8 μm or more and 130 μm or less in order to keep the characteristic impedance of the signal pattern 111 within the range of 40Ω or more and 80Ω or less. In order to set the characteristic impedance of the signal pattern 111 to 60Ω, the interval D1 is preferably 12 μm or more and 70 μm or less. In this case, the width w of the signal pattern 111 is preferably 25 μm or more and 150 μm or less.

Thus, by bringing the signal pattern 111 and the conductor plane 15 close to each other, the impedance of the signal line 11 can be matched with the impedance of the input terminals of the logic LSI 1103 and the memory IC 104 even if the width w of the signal pattern 111 is narrow. . Therefore, while wiring the signal patterns 111 at high density, the crosstalk between the signal lines 11 is suppressed, and the transmission loss in the high frequency band can be reduced.

The present invention is not limited to the embodiments described above, and many modifications are possible within the technical concept of the present invention. Moreover, the effects described in the embodiments are merely enumerations of the most suitable effects resulting from the present invention, and the effects of the present invention are not limited to those described in the embodiments.

Further, in the above-described embodiments, a case where the circuit unit of the present invention is applied to an imaging device such as a digital camera as an electronic device has been described, but the present invention is not limited to this. The electronic unit of the present invention can also be applied to image forming apparatuses such as printers, copiers, facsimiles, and multifunction machines having these functions as electronic equipment.

Also, in the above-described embodiment, the case where the child board 101 and the parent board 102 are fixed by soldering has been described, but the present invention is not limited to this. For example, it may be fixed by a fixing jig (not shown).

Also, in the above-described embodiment, the case where the logic LSI 103 and the memory IC 014 are mounted on the sub-board 101 has been described, but the present invention is not limited to this. For example, another board may be mounted on the child board 101, and the logic LSI 103 and the memory IC 014 may be mounted on the other board.

DESCRIPTION OF SYMBOLS 11... Signal line, 15... Conductor plane, 100... Circuit module, 101... Child board (first board), 102... Parent board (second board), 111... Signal pattern

Claims (20)

a first substrate having a signal line;
comprising the first substrate and a fixed second substrate;
the signal line has a signal pattern arranged on the first surface of the first substrate facing the second surface of the second substrate;
The second substrate has a conductor plane arranged on the second surface so as to face the signal pattern with a gap therebetween.
A circuit module characterized by: The signal pattern has a first conductor surface facing the conductor plane and a second conductor surface facing the first conductor surface,
the surface roughness of the first conductor surface is smaller than the surface roughness of the second conductor surface;
2. The circuit module according to claim 1, wherein: The conductor plane has a third conductor surface facing the signal pattern and a fourth conductor surface facing the third conductor surface,
the surface roughness of the third conductor surface is smaller than the surface roughness of the fourth conductor surface;
3. The circuit module according to claim 1, wherein: Further comprising a first semiconductor element and a second semiconductor element mounted on a third surface opposite to the first surface of the first substrate and performing digital signal communication via the signal line,
4. The circuit module according to claim 1, wherein: the first semiconductor element includes a transmission terminal electrically connected to the signal line and transmitting the digital signal;
The second semiconductor element is electrically connected to the signal line and includes a receiving terminal for receiving the digital signal,
5. The circuit module according to claim 4, wherein: wherein the second semiconductor device is a memory device;
6. The circuit module according to claim 4 or 5, characterized in that: The conductor plane is part of a line used to apply a power supply voltage to the first semiconductor element and the second semiconductor element,
7. The circuit module according to any one of claims 4 to 6, characterized in that: the conductor plane is at ground potential;
8. The circuit module according to claim 7, wherein: The distance between the signal pattern and the conductor plane is the distance between the first conductor layer on which the signal pattern is arranged and the second conductor layer adjacent to the first conductor layer with an insulator interposed therebetween. narrower than the interval
9. The circuit module according to any one of claims 1 to 8, characterized in that: The distance between the signal pattern and the conductor plane is 8 μm or more and 130 μm or less.
10. The circuit module according to any one of claims 1 to 9, characterized in that: The distance between the signal pattern and the conductor plane is 12 μm or more and 70 μm or less.
10. The circuit module according to any one of claims 1 to 9, characterized in that: The signal pattern has a width of 25 μm or more and 150 μm or less.
12. The circuit module according to claim 1, wherein: At least one of the first substrate and the second substrate is a rigid substrate,
13. The circuit module according to any one of claims 1 to 12, characterized in that: The rigid board is a printed wiring board,
14. The circuit module according to claim 13, wherein: The first substrate has a first insulator portion, and a first solder resist film arranged to cover the signal pattern and having a relative dielectric constant lower than that of the first insulator portion.
15. The circuit module according to any one of claims 1 to 14, characterized in that: The second substrate has a second insulator portion, and a second solder resist film arranged to cover the conductor plane and having a relative dielectric constant lower than that of the second insulator portion.
16. The circuit module according to any one of claims 1 to 15, characterized in that: The number of conductor layers of the first substrate is two,
17. The circuit module according to any one of claims 1 to 16, characterized in that: The number of conductor layers of the second substrate is two or less,
18. The circuit module according to any one of claims 1 to 17, characterized in that: there is an air gap between the signal pattern and the conductor plane;
19. The circuit module according to any one of claims 1 to 18, characterized in that: a housing;
20. The circuit module according to any one of claims 1 to 19, arranged inside the housing;
electronic equipment.

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