JP2023010215A - semiconductor chip - Google Patents

Abstract

To provide a semiconductor chip capable of reducing its manufacturing cost.SOLUTION: A semiconductor chip 10 includes a substrate 23 and an epitaxial layer 24, and has a rectangular shape when viewed in a thickness direction. The semiconductor chip 10 includes an operation layer region 25 and a chip outer periphery region 26. When a length of the semiconductor chip 10 in a crystal plane orientation <11-20> is set to a length A1 and the maximum length of the operation layer region 25 in the direction of the crystal plane orientation <11-20> is set to a length A2, and also when a length of the semiconductor chip 10 in a direction orthogonal to the direction of the crystal plane orientation <11-20> is set to a length B1 and the maximum length of the operation layer region 25 in the direction orthogonal to the direction of the crystal plane orientation <11-20> is set to a length B2, a difference value obtained by subtracting the length A2 from the length A1 and a difference value obtained by subtracting the length B2 from the length B1 are different.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to semiconductor chips.

2. Description of the Related Art A semiconductor device manufacturing method is known in which a device portion is formed on a substrate made of silicon carbide and the device portion is separated (see, for example, Patent Document 1). According to Patent Document 1, trench grooves are formed in a substrate along the shape of an electrode film, and device portions are separated along the trench grooves.

JP 2009-206221 A

2. Description of the Related Art In manufacturing semiconductor chips, it is required to improve so-called yield and reduce manufacturing costs. Therefore, one object is to provide a semiconductor chip that can be manufactured at a reduced cost.

A semiconductor chip according to the present disclosure includes a substrate made of SiC and including a first main surface having an off angle of 4° or less, and an epitaxial layer formed on the first main surface, wherein It is rectangular in shape. The semiconductor chip has, when viewed in the thickness direction of the semiconductor chip, an operating layer region including an active region arranged in the central region of the semiconductor chip and a field stop region arranged on the outer peripheral side of the active region, and an operating layer region. a chip perimeter region surrounding and disposed along an outer edge of the semiconductor chip. The outer edge of the field stop region includes four sides each arranged along the outer edge of the semiconductor chip and forming the outer edge of the active layer region. _The length of the semiconductor chip in the direction of crystal plane orientation <11-20> is defined as length A1, the maximum length of the active layer region in the direction of crystal plane orientation <11-20> is defined as length _A2 , and the crystal plane The length of the semiconductor chip in the direction perpendicular to the <11-20> direction of the crystal plane orientation is defined as length _B1 , and the maximum length of the active layer region in the direction perpendicular to the direction of crystal plane orientation <11-20> is defined as length. B2, the value of the difference obtained by _subtracting the length _A2 from the length A1 is different from the value of the difference obtained by _subtracting the length _B2 from the length _B1 .

According to the above semiconductor chip, the manufacturing cost can be reduced.

FIG. 1 is a schematic cross-sectional view when a part of the semiconductor chip according to the first embodiment is cut. 2 is a schematic plan view showing a part of the semiconductor chip shown in FIG. 1. FIG. FIG. 3 is a schematic cross-sectional view showing part of the semiconductor chip shown in FIG. FIG. 4 is a view of the disk-shaped substrate in the thickness direction showing the state where the operating layer region is formed in the first embodiment. FIG. 5 is a schematic plan view of a semiconductor chip according to Embodiment 2. FIG. FIG. 6 is a view of the disk-shaped substrate in the thickness direction showing the state where the operating layer region is formed in the second embodiment.

[Description of Embodiments of the Present Disclosure]
First, the embodiments of the present disclosure are listed and described. A semiconductor chip according to the present disclosure includes a substrate made of SiC and including a first main surface having an off angle of 4° or less, and an epitaxial layer formed on the first main surface. It looks like a rectangle. The semiconductor chip has, when viewed in the thickness direction of the semiconductor chip, an operating layer region including an active region arranged in the central region of the semiconductor chip and a field stop region arranged on the outer peripheral side of the active region, and an operating layer region. a chip perimeter region surrounding and disposed along an outer edge of the semiconductor chip. The outer edge of the field stop region includes four sides each arranged along the outer edge of the semiconductor chip and forming the outer edge of the active layer region. _The length of the semiconductor chip in the direction of crystal plane orientation <11-20> is defined as length A1, the maximum length of the active layer region in the direction of crystal plane orientation <11-20> is defined as length _A2 , and the crystal plane The length of the semiconductor chip in the direction perpendicular to the <11-20> direction of the crystal plane orientation is defined as length _B1 , and the maximum length of the active layer region in the direction perpendicular to the direction of crystal plane orientation <11-20> is defined as length. B2, the value of the difference obtained by _subtracting the length _A2 from the length A1 is different from the value of the difference obtained by _subtracting the length _B2 from the length _B1 .

The semiconductor chip has a rectangular shape, and when viewed in the thickness direction of the semiconductor chip, an active layer region including an active region arranged in the central region of the semiconductor chip and a field stop region arranged on the outer peripheral side of the active region. and a chip perimeter region surrounding the active layer region and disposed along the outer edge of the semiconductor chip. Such a semiconductor chip, for example, uses a disk-shaped substrate (wafer), forms a device portion using an epitaxial layer grown on the substrate as an active region, and then dices the substrate into individual pieces. It is manufactured by A plurality of semiconductor chips can be obtained from one substrate. Considering the individualization of each semiconductor chip, the substrate is provided with a dicing area including a cutting allowance arranged between the semiconductor chips. That is, when viewed in the thickness direction of the substrate, the substrate on which the epitaxial layer is formed has a plurality of operating layer regions arranged at intervals, and a chip peripheral region arranged on the outer peripheral side of each operating layer region. and a dicing area arranged on the outer peripheral side of each chip outer peripheral area.

Here, defects may be included during the crystal growth of the epitaxial layer formed on the substrate. If a region that operates as a device section contains crystal defects, there is a risk that the crystal defects will become a current path. As a result, a breakdown voltage defect of the semiconductor chip is caused. From the viewpoint of ensuring the reliability of ensuring the reliable operation of the semiconductor chip, such a semiconductor chip becomes a defective product.

The number of semiconductor chips that can be obtained from one substrate is limited. Therefore, if the number of defective semiconductor chips obtained from a single substrate cannot be reduced and a large number of good semiconductor chips with high reliability cannot be obtained, the yield will be poor. As a result, the manufacturing cost cannot be reduced.

A semiconductor chip including a semiconductor layer made of SiC (silicon carbide) as an operating layer is sometimes required from the viewpoint of improving withstand voltage. Here, the present inventors compared epitaxial crystal growth using a substrate made of Si (silicon) when performing epitaxial crystal growth using a substrate made of SiC in a semiconductor chip. As a result, they paid attention to the fact that crystal defects are likely to occur during crystal growth. In manufacturing a semiconductor chip using a substrate made of SiC, the following points were found. That is, when epitaxial crystal growth is performed on a substrate made of SiC, the direction in which crystal defects grow starting from the main surface of the substrate is elongated in the direction of the crystal plane orientation <11-20>. . Focusing on the crystal defect originating from the main surface of the substrate, the crystal defect extends longer in the direction of the <11-20> crystal plane orientation than in the direction perpendicular to the direction of the <11-20> crystal plane orientation. bottom. Then, the present inventors made intensive studies to suppress the occurrence of defective products caused by crystal defects in the operating layer region as much as possible, and completed the present invention.

According to the semiconductor chip of the present disclosure, the length of the semiconductor chip in the direction of crystal plane orientation <11-20> is defined as length A1, and the maximum length of the _active layer region in the direction of crystal plane orientation <11-20> is With a length A of ₂ , the length of the semiconductor chip in the direction perpendicular to the direction of the crystal plane orientation <11-20> is assumed to be a length B ₁ , and the operating layer in the direction perpendicular to the direction of the crystal plane orientation <11-20> _Assuming that the maximum length of the region is length B2, the value of the difference obtained by subtracting the length _A2 from the length A1 is different from the value of the difference obtained by _subtracting the length _B2 from the length _B1 . Since the growth direction of crystal defects is the direction of the crystal plane orientation <11-20>, by configuring in this way, the value of the difference obtained by subtracting the length A ₂ from the length A ₁ and the value of the difference obtained by subtracting the length A 2 from the length B ₁ Compared to the case where the value of the difference after subtracting the length B2 is the same, the probability that crystal defects _are included in the active layer region during epitaxial crystal growth can be reduced. That is, the idea of the present inventors is to locate many crystal defects generated during epitaxial crystal growth in the chip outer peripheral region and the dicing region, which do not affect the operation of the semiconductor chip. Therefore, among a plurality of semiconductor chips obtained from one substrate, it is possible to reduce the number of semiconductor chips that are defective due to breakdown voltage failure. As a result, the manufacturing cost can be reduced.

_In the above semiconductor chip, if the thickness of the epitaxial layer is the thickness T1 in the cross section of the semiconductor chip cut in the thickness direction, the value of the difference obtained by _subtracting the length _A2 from the length A1 is the thickness T It may be larger than the value obtained by dividing ₁ by the tangent of the off angle of the substrate. _The thickness T1 of the epitaxial layer is defined according to the breakdown voltage required for the semiconductor chip. By doing so, the value of the difference obtained by _subtracting the length _A2 from the length A1 is appropriately set according to the thickness _T1 of the epitaxial layer, thereby further reducing the probability that the crystal defect is included in the operating layer region. can be made Therefore, it is possible to more appropriately reduce the manufacturing cost.

In the above semiconductor chip, the off angle may be 4°. Since such a semiconductor chip has good productivity, it is possible to further reduce the manufacturing cost.

In the above semiconductor chip, the thickness T1 may be ₄ μm or more and 30 μm or less. By doing so, it is possible to sufficiently secure the breakdown voltage required for the semiconductor chip, and to avoid the area of the active layer region occupying the chip area from becoming excessively small when using the semiconductor chip according to the present disclosure. , it is possible to provide a semiconductor chip with low resistance when conducting.

_In the above semiconductor chip, the value of the difference obtained by subtracting the length _A2 from the length A1 may be greater _than the value of the difference obtained by subtracting the length B2 from the length _B1 . By doing so, many crystal defects can be arranged between the respective operating layer regions of the semiconductor chips which are spaced apart in the direction of the crystal plane orientation <11-20>. It is possible to reduce the probability that a semiconductor chip that is included in the region and has a breakdown voltage defect is manufactured. Therefore, the yield of semiconductor chips can be improved, and the manufacturing cost can be further reduced.

In the above semiconductor chip, the value of the difference obtained by subtracting the length _A2 from the length A1 may be 0.2 _mm or more. _The value of the difference obtained by subtracting the length B2 from the length _B1 may be 0.1 mm or more. By defining each length in this manner, the manufacturing cost can be reliably reduced.

In the above semiconductor chip, the value of the difference obtained by subtracting the length _A2 from the length A1 may be 0.5 _mm or more. _The value of the difference obtained by subtracting the length B2 from the length _B1 may be 0.1 mm or more. By defining each length in this manner, the manufacturing cost can be reduced more reliably.

_In the above semiconductor chip, the value of the difference obtained by subtracting the length _A2 from the length A1 may be smaller _than the value of the difference obtained by subtracting the length B2 from the length _B1 . By doing so, many crystal defects can be arranged between the active layer regions of the semiconductor chip which are spaced apart in the direction orthogonal to the direction of the crystal plane orientation <11-20>. It is possible to reduce the probability that a semiconductor chip that is included in the operating layer region and has a breakdown voltage defect is manufactured. Therefore, the yield of semiconductor chips can be improved, and the manufacturing cost can be further reduced.

In the above semiconductor chip, the value of the difference obtained by subtracting the length _A2 from the length A1 may be 0.1 _mm or more. _The value of the difference obtained by subtracting the length B2 from the length _B1 may be 0.2 mm or more. By defining each length in this manner, the manufacturing cost can be reliably reduced.

In the above semiconductor chip, the value of the difference obtained by subtracting the length _A2 from the length A1 may be 0.2 _mm or more. _The value of the difference obtained by subtracting the length B2 from the length _B1 may be 0.3 mm or more. By defining each length in this manner, the manufacturing cost can be reliably reduced.

In the above semiconductor chip, the value of the difference obtained by subtracting the length _A2 from the length A1 may be 0.1 _mm or more. _The value of the difference obtained by subtracting the length B2 from the length _B1 may be 0.5 mm or more. By defining each length in this manner, the manufacturing cost can be reduced more reliably.

[Details of the embodiment of the present disclosure]
Next, one embodiment of the semiconductor chip of the present disclosure will be described with reference to the drawings. In the following drawings, the same reference numerals are given to the same or corresponding parts, and the description thereof will not be repeated.

(Embodiment 1)
A configuration of the semiconductor chip according to the first embodiment of the present disclosure will be described. FIG. 1 is a schematic cross-sectional view when a part of the semiconductor chip according to the first embodiment is cut. FIG. 1 schematically shows part of a semiconductor chip. 2 is a schematic plan view showing a part of the semiconductor chip shown in FIG. 1. FIG. FIG. 3 is a schematic cross-sectional view showing part of the semiconductor chip shown in FIG. In FIGS. 1, 2 and 3, the direction indicated by the arrow X and its opposite direction indicate the crystal plane orientation <11-20>, which will be described later. The direction indicated by the arrow Y and its opposite direction indicate the direction perpendicular to the direction of the crystal plane orientation <11-20>. The direction indicated by the arrow Z and its opposite direction indicate the thickness direction of the semiconductor chip. In addition, in FIG. 3, crystal defects are schematically illustrated from the viewpoint of facilitating understanding.

1, 2 and 3, semiconductor chip 20 according to the first embodiment is included in a semiconductor device such as a power module, for example. The semiconductor chip 20 includes a first electrode 11 and a second electrode 12, also called back electrode. Both the first electrode 11 and the second electrode 12 are made of Al (aluminum), for example. The semiconductor chip 20 is used as, for example, a transistor chip or a diode chip. When the semiconductor chip 20 is a transistor chip, the first electrode 11 becomes a source electrode or a gate electrode, and the second electrode 12 becomes a drain electrode. When the semiconductor chip 20 is a diode chip, the first electrode 11 becomes an anode electrode and the second electrode 12 becomes a cathode electrode.

The semiconductor chip 20 includes a semiconductor layer made of SiC as an operating layer. The semiconductor chip 20 is a wide bandgap semiconductor chip. A wide bandgap semiconductor chip refers to a semiconductor chip having, as an operating layer, a semiconductor layer made of a material having a bandgap larger than that of silicon. Such a wide bandgap semiconductor chip has a high dielectric breakdown voltage, that is, a high withstand voltage. Moreover, since the resistance of the drift layer can be reduced, the on-resistance can be reduced.

The semiconductor chip 20 has a rectangular shape when viewed in the thickness direction. When viewed in the thickness direction of the semiconductor chip 20, the outer edge 21 of the semiconductor chip 20 includes four sides 22a, 22b, 22c and 22d. Each of the sides 22a, 22b, 22c, and 22d is composed of a line segment. The sides 22a and 22b are arranged parallel to each other with a gap in the X direction, and form a pair facing each other. The sides 22c and 22d are arranged parallel to each other with a gap in the Y direction, that is, in a direction orthogonal to the X direction, forming a pair of opposing sides. Each side 22a, 22b, 22c, 22d is directly connected.

The semiconductor chip 20 includes a substrate 23 including a first main surface 23a with an off angle of 4° or less, and an epitaxial layer 24 formed on the first main surface 23a. The epitaxial layer 24 is formed by epitaxial crystal growth on the first major surface 23 a of the substrate 23 . In this embodiment, the off angle indicated by the angle θ in FIG. 3 is 4°. The off angle of the first main surface 23a is preferably greater than 0° and equal to or less than 4°. _The thickness of epitaxial layer 24 is also indicated by thickness T1. _The thickness of substrate 23 is indicated by thickness T2. The thickness of the semiconductor chip 20 excluding the first electrode 11 and the second electrode ₁₂ is indicated by thickness T3. Here, the thickness T2 of the epitaxial layer 24 is defined according to the withstand voltage required for the semiconductor chip ₂₀ . Specifically, when the breakdown voltage required for the semiconductor chip ₂₀ is 1200 V, the thickness T2 is set to 10 μm or more. Moreover, when the breakdown voltage required for the semiconductor chip ₂₀ is 3300 V, the thickness T2 is set to 30 μm or more. In this embodiment, the thickness T1 is set to ₄ μm or more and 30 μm or less. Note that the thickness T1 may be ₅ μm or more and 30 μm or less.

The semiconductor chip 20 includes an operating layer area 25 and a chip peripheral area 26 . The operating layer region 25 includes an active region 27 arranged in the central region of the semiconductor chip 20, a termination region arranged on the outer peripheral side of the active region 27 and including guard ring regions 28a, 28b, and 28c, and an active region 27. a field stop region 29 located on the outer peripheral side and on the outer peripheral side of the termination region.

Guard ring region 28 a is arranged at a position close to active region 27 and provided so as to surround active region 27 . Guard ring region 28b is provided to surround guard ring region 28a. The guard ring region 28c is arranged at a position close to the field stop region 29 and provided so as to surround the guard ring region 28b. The guard ring regions 28 a , 28 b , 28 c are spaced apart from each other toward the outer edge 21 of the semiconductor chip 20 . The guard ring regions 28a, 28b, and 28c are, for example, p-type semiconductor regions.

Field stop region 29 is provided to surround guard ring region 28c. The field stop region 29 is an n-type semiconductor region. The outer edge 31 of field stop region 29 constitutes the outer edge 31 of active layer region 25 . The field stop region 29 is, for example, an n-type semiconductor region.

When viewed in the thickness direction of the semiconductor chip 20, the outer edge 31 of the field stop region 29 includes four sides 32a, 32b, 32c and 32d. Each of the sides 32a, 32b, 32c, 32d is composed of a line segment. The sides 32a and 32b are arranged parallel to each other with a gap in the X direction, and form a pair facing each other. The sides 32c and 32d are spaced apart in the Y direction in parallel to form a pair of opposing sides. Each side 22a, 22b, 22c, 22d is connected via an arc portion.

The semiconductor chip 20 described above uses a disk-shaped substrate, forms a device portion using a part of an epitaxial layer grown on the substrate as an active region, and then separates the substrate by dicing. Manufactured by FIG. 4 is a view of the disk-shaped substrate in the thickness direction showing the state where the operating layer region is formed in the first embodiment. In FIG. 4, a portion including the active layer region 25 is shown in an enlarged form in the region surrounded by the dashed line.

Referring to FIG. 4, disc-shaped substrate 23 is partially provided with notch 34 in order to clarify its orientation. The substrate 23 on which the epitaxial layer is formed has a plurality of operating layer regions 25 arranged at intervals when viewed in the thickness direction of the substrate 23 and chips arranged on the outer peripheral side of each operating layer region 25 . It includes an outer peripheral region 26 and a dicing region 35 arranged on the outer peripheral side of each chip outer peripheral region 26 . A plurality of active layer regions 25 are formed so as to be spaced apart in the X direction and the Y direction, respectively. From the viewpoint of facilitating separation of the semiconductor chips 20 into individual pieces, for example, the dicing regions 35 are arranged in a grid pattern. In other words, on the substrate 23, the operating layer regions 25 having the same structure are periodically formed in the X direction and the Y direction.

Crystal defects may occur during epitaxial crystal growth. Referring to FIG. 3, the direction in which crystal defect 37 grows from first main surface 23a of substrate 23 as starting point 36 is elongated in the <11-20> crystal plane orientation direction. Then, regarding the crystal defect 37 originating from the first main surface 23a of the substrate 23, the crystal defect occurs in the direction of the crystal plane orientation <11-20> rather than in the direction perpendicular to the direction of the crystal plane orientation <11-20>. 37 is elongated. That is, the crystal defects 37 grow together with the epitaxial crystal growth and reach the surface 24 a of the epitaxial layer 24 . That is, the termination 38 of the crystal defect 37 appears on the surface 24 a of the epitaxial layer 24 . When viewed in the thickness direction of the semiconductor chip 20, the X _- direction length of the crystal defect 37 is indicated by the length D1. Length D ₁ results from thickness T ₁ of epitaxial layer 24 . In the present embodiment, the off-angle θ is 4°, so the length D1 of the crystal defect 37 is obtained by dividing the thickness T1 by the tangent (tan) of the off _- angle ₄ ° of the substrate. When the thickness T1 is ₁₀ μm, the length D1 of the crystal defect 37 is ₁₄₃ μm. Also, when the thickness _T1 is 30 μm, the length _D1 of the crystal defect 37 is 429 μm. In many cases, the crystal defect 37 has an isosceles triangle shape with the starting point 36 as the vertex when viewed in the thickness direction of the semiconductor chip 20 . _In this case, for example, if the length D1 in the X direction is 0.15 μm, the length in the Y direction perpendicular to the X direction is 0.05 μm.

Here, the length of the semiconductor chip 20 in the X direction, which is the direction of the <11-20> crystal plane orientation, is _defined as length A1. Length A1 is the length between _side 22a and side 22b. Let length _A2 be the maximum length of the active layer region 25 in the X direction, which is the direction of the crystal plane orientation <11-20>. Length _A2 is the length between side 32a and side 32b. The length of the semiconductor chip 20 in the Y direction, which is the direction perpendicular to the crystal plane orientation <11-20>, is defined as length _B1 . Length _B1 is the length between side 22c and side 22d. The maximum length of the active layer region ₂₅ in the Y direction, which is the direction orthogonal to the <11-20> crystal plane orientation, is defined as length B2. Length B2 is the length between _side 32c and side 32d. _The value of the difference obtained by subtracting the length _A2 from the length A1 is the length obtained by adding the length _m1 between the sides 22a and 32a and the length _m2 between the sides 22b and 32b. (length m ₁ +length m ₂ ). _The value of the difference obtained by subtracting the length B2 from the length _B1 is the _sum of the length n1 between the sides 22c and 32c and the length _n2 between the sides 22d and 32d. (length n ₁ +length n ₂ ).

In the semiconductor chip 20 according to the present disclosure, the difference (length A ₁ - length A ₂ ) obtained by subtracting the length A ₂ from the length A ₁ and the difference obtained by subtracting the length B ₂ from the length B ₁ ( length B ₁ - length B ₂ ). _In this embodiment, the value of the difference obtained by subtracting the length _A2 from the length A1 is greater _than the value of the difference obtained by subtracting the length B2 from the length _B1 . In the semiconductor chip 20 according to the present disclosure, the Y-direction length B2 of the operating layer region 25 is longer _than the X-direction length _A2 . In this embodiment, the value of the difference obtained by subtracting the length _A2 from the length A1 is 0.5 _mm or more. _The value of the difference obtained by subtracting the length B2 from the length _B1 is 0.1 mm or more. Specifically, the value of the difference obtained by subtracting the length _A2 from the length A1 is 0.5 _mm . Also, the value of the difference obtained by subtracting the length B2 from the length _B1 is 0.1 _mm .

The direction in which the crystal defects 37 grow is longer in the <11-20> direction of the crystal plane orientation, which is the step flow growth direction. That is, it becomes longer in the X direction. Then, regarding the crystal defect 37 originating from the first main surface 23a of the substrate 23, the crystal defect occurs in the direction of the crystal plane orientation <11-20> rather than in the direction perpendicular to the direction of the crystal plane orientation <11-20>. lengthens. Therefore, with this configuration, the value of the difference obtained by subtracting the length _A2 from the length A1 and the value of the difference obtained by subtracting the length _B2 from the length _{B1 are} the same. Therefore, if a crystal defect 37 exists between the respective active layer regions 25 of the semiconductor chips 20 that are spaced apart in the direction of the crystal plane orientation <11-20>, the crystal defect 37 exists within the active layer region 25. can be reduced. That is, many crystal defects 37 generated during epitaxial crystal growth can be arranged in the chip outer peripheral region 26 and the dicing region 35 which do not affect the operation of the semiconductor chip 20 . In this way, among the plurality of semiconductor chips 20 obtained from one substrate 23, the number of semiconductor chips 20 that are defective due to breakdown voltage failure can be reduced. As a result, the manufacturing cost can be reduced.

_In this embodiment, the value of the difference obtained by subtracting the length _A2 from the length A1 is greater _than the value of the difference obtained by subtracting the length B2 from the length _B1 . Therefore, many crystal defects 37 can be arranged between the respective operating layer regions 25 of the semiconductor chips 20 which are arranged with a gap in the direction of the crystal plane orientation <11-20>, and the crystal defects 37 can be arranged in the operating layer region. 25 can be reduced. Therefore, it is possible to reduce the probability of manufacturing a semiconductor chip with a defective withstand voltage, improve the yield of the semiconductor chip, and further reduce the manufacturing cost.

In this embodiment, the value of the difference obtained by subtracting the length _A2 from the length A1 is 0.5 _mm or more. Also, the value of the difference obtained by subtracting the length B2 from the length _B1 is 0.1 mm or _more . By defining each length in this manner, the manufacturing cost can be reduced more reliably.

In addition, in _a cross section of the semiconductor chip 20 cut in the thickness direction, the value of the difference obtained by subtracting the length _A2 from the length A1 is larger _than the value obtained by dividing the thickness T1 by the tangent of the off angle of the substrate 23. Largely configured. Therefore, the value of the difference obtained by subtracting the length _A2 from the length A1 should be appropriately _adjusted according to the thickness T1 of the epitaxial layer 24 to further reduce the probability that the crystal defect 37 is included in the _active layer region 25. can be done. Therefore, it is possible to more appropriately reduce the manufacturing cost.

In this embodiment, the off angle is 4°. Therefore, such a semiconductor chip 20 has good productivity, so that the manufacturing cost can be further reduced.

In this embodiment, the thickness T1 is ₄ μm or more and 30 μm or less. Therefore, the breakdown voltage required for the semiconductor chip 20 can be sufficiently ensured, and when the semiconductor chip 20 according to the present disclosure is used, excessive reduction in the area of the operating layer region 25 in the chip area can be avoided. A semiconductor chip 20 with low time resistance can be provided.

In the above embodiment, the value of the difference obtained by subtracting the length _A2 from the length A1 may be 0.2 _mm or more. _The value of the difference obtained by subtracting the length B2 from the length _B1 may be 0.1 mm or more. By defining each length in this manner, the manufacturing cost can be reliably reduced.

(Embodiment 2)
Next, Embodiment 2, which is another embodiment, will be described. FIG. 5 is a schematic plan view of a semiconductor chip according to Embodiment 2. FIG. FIG. 6 is a view of the disk-shaped substrate in the thickness direction showing the state where the operating layer region is formed in the second embodiment. The semiconductor chip of the _second embodiment differs from the _first embodiment in that the value of the difference obtained by subtracting the length _A2 from the length A1 is smaller than the value of the difference obtained by subtracting the length B2 from the length _B1 . is different from the case of

₅ and 6, in the semiconductor chip according to the _second embodiment, the value of the difference obtained by subtracting the length _A2 from the length A1 is the difference obtained by subtracting the length B2 from the length _B1 . less than value. By doing so, many crystal defects 37 can be arranged between the active layer regions 25 of the semiconductor chip 20 which are arranged at intervals in the direction orthogonal to the direction of the crystal plane orientation <11-20>. It is possible to reduce the probability of manufacturing a semiconductor chip 20 that includes crystal defects 37 in the operating layer region 25 and has a breakdown voltage defect. Therefore, it is possible to improve the yield of the semiconductor chip 20 and further reduce the manufacturing cost.

In this embodiment, the value of the difference obtained by subtracting the length _A2 from the length A1 is 0.1 _mm or more. _The value of the difference obtained by subtracting the length B2 from the length _B1 is 0.5 mm or more. Specifically, the value of the difference obtained by subtracting the length _A2 from the length A1 is 0.1 _mm . _The value of the difference obtained by subtracting the length B2 from the length _B1 is 0.5 mm. By defining each length in this manner, the manufacturing cost can be reduced more reliably.

In the above embodiment, the value of the difference obtained by subtracting the length _A2 from the length A1 may be 0.1 _mm or more. _The value of the difference obtained by subtracting the length B2 from the length _B1 may be 0.2 mm or more. By defining each length in this manner, the manufacturing cost can be reliably reduced. Further, in the above embodiment, the value of the difference obtained by subtracting the length _A2 from the length A1 may be 0.2 _mm or more. _The value of the difference obtained by subtracting the length B2 from the length _B1 may be 0.3 mm or more. By defining each length in this manner, the manufacturing cost can be reliably reduced.

It should be understood that the embodiments disclosed this time are illustrative in all respects and are not restrictive in any aspect. The scope of the present invention is defined by the scope of the claims rather than the above description, and is intended to include all modifications within the meaning and range of equivalents of the scope of the claims.

The semiconductor chip of the present disclosure can be applied particularly advantageously when reduction in manufacturing cost is required.

11 First electrode 12 Second electrode 20 Semiconductor chip 21, 31 Outer edge 22a, 22b, 22c, 22d, 32a, 32b, 32c, 32d Side 23 Substrate 23a First major surface 24 Epitaxial layer 24a Surface 25 Active layer region 26 Chip peripheral region 27 Active regions 28a, 28b, 28c Guard ring region 29 Field stop region 34 Notch 35 Dicing region 36 Starting _point 37 Crystal defect ₃₈ Ending A1, _A2 , _B1 , B2, D1, _m1 , _{m 2} , n ₁ , n ₂ Length T ₁ , T ₂ , T ₃ Thickness θ Angle

Claims (11)

A semiconductor having a rectangular shape when viewed in a thickness direction, comprising a substrate made of SiC and including a first main surface having an off angle of 4° or less, and an epitaxial layer formed on the first main surface. is a chip
Seen in the thickness direction of the semiconductor chip,
an active layer region including an active region arranged in a central region of the semiconductor chip and a field stop region arranged on the outer peripheral side of the active region;
a chip peripheral region surrounding the operating layer region and arranged along the outer edge of the semiconductor chip;
the outer edge of the field stop region includes four sides respectively arranged along the outer edge of the semiconductor chip and forming the outer edge of the operating layer region;
_The length of the semiconductor chip in the direction of crystal plane orientation <11-20> is defined as length A1,
The maximum length of the operating layer region in the direction of the crystal plane orientation <11-20> is defined as length _A2 ,
A length _B1 is a length of the semiconductor chip in a direction orthogonal to the direction of the crystal plane orientation <11-20>,
Assuming that the maximum length of the _active layer region in the direction orthogonal to the direction of the crystal plane orientation <11-20> is length B2,
_A semiconductor chip, wherein a difference value obtained by subtracting the length _A2 from the length A1 is different from _a difference value obtained by subtracting the length B2 from the length _B1 . In a cross section obtained by cutting the semiconductor chip in the thickness direction,
_Assuming that the thickness of the epitaxial layer is thickness T1, the value of the difference obtained by _subtracting the length _A2 from the length A1 is the value obtained by dividing the thickness T1 by the _tangent of the off angle of the substrate. 2. The semiconductor chip of claim 1, wherein the semiconductor chip is also large. 3. The semiconductor chip according to claim 2, wherein said off angle is 4[deg.]. The semiconductor chip according to any one of claims ₁ to 3, wherein said thickness T1 is 4 µm or more and 30 µm or less. 5. Any of claims ₁ to 4, wherein the difference between the length A1 minus the length _A2 is greater _than the difference between the length _B1 minus the length B2. 2. The semiconductor chip according to item 1. The value of the difference obtained by subtracting the length _A2 from the length A1 is 0.2 _mm or more,
6. The semiconductor chip according to claim ₅ , wherein a difference value obtained by subtracting said length B2 from said length _B1 is 0.1 mm or more. The value of the difference obtained by subtracting the length _A2 from the length A1 is 0.5 _mm or more,
6. The semiconductor chip according to claim ₅ , wherein a difference value obtained by subtracting said length B2 from said length _B1 is 0.1 mm or more. 5. Any of claims ₁ to 4, wherein the difference between the length A1 minus the length _A2 is less _than the difference between the length _B1 minus the length B2. 2. The semiconductor chip according to item 1. The value of the difference obtained by subtracting the length _A2 from the length A1 is 0.1 _mm or more,
9. The semiconductor chip according to claim 8, wherein a difference value obtained by subtracting said length B2 from said length _B1 is 0.2 _mm or more. The value of the difference obtained by subtracting the length _A2 from the length A1 is 0.2 _mm or more,
9. The semiconductor chip according to claim 8, wherein a difference value obtained by subtracting said length B2 from said length _B1 is 0.3 _mm or more. The value of the difference obtained by subtracting the length _A2 from the length A1 is 0.1 _mm or more,
9. The semiconductor chip according to claim 8, wherein a difference value obtained by subtracting said length B2 from said length _B1 is 0.5 mm or _more .

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