JP2022545715A - Bank configurable power modes - Google Patents

Abstract

Methods, systems, and devices for bank configurable power modes are described. Aspects include operating a memory device having multiple memory banks in a first mode. While operating in the first mode, the memory device may receive commands to transition to a second mode having a lower power consumption level than the first mode. The memory device places a first subset of memory banks into a first low power mode operating at a first power consumption level and places a second subset of memory banks at a lower power consumption level than the first power consumption level. The second mode may be transitioned to by switching to a second low power mode operating at a second power consumption level that may be better. In some cases, the memory device may switch a first subset of memory banks out of a first low power mode while maintaining a second subset of memory banks in a low power mode.

Description

This patent application claims priority to U.S. Patent Application No. 16/551,581 by Mirichigni et al. , assigned to the assignee of the present application and is expressly incorporated herein by reference in its entirety.

The following relates generally to systems including at least one memory device, and more specifically to bank configurable power modes.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is accumulated by programming different states of the memory device. Binary devices, for example, most often store one of two states often indicated by a logic one or a logic zero. Other devices may store more than two states. To access the stored information, a component of the device can read or sense at least one stored state within the memory device. To store information, components of the device may write or program states into the memory device.

Magnetic hard disk, Random Access Memory (RAM), Read Only Memory (ROM), Dynamic RAM (DRAM), Synchronous Dynamic RAM (SDRAM), Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM), Resistive RAM ( There are various types of memory devices, including RRAM), flash memory, phase change memory (PCM), and the like. Memory devices can be volatile or non-volatile. Non-volatile memories, such as FeRAM, can maintain their stored logic states for long periods of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. FeRAM may be capable of achieving densities similar to volatile memory, but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices.

Memory device improvements generally include increased memory cell density, increased read/write speed, increased reliability, increased data retention, reduced power consumption, or improved manufacturing processes, among other metrics. obtain. A solution to improve power consumption in memory devices would be desirable.

An example system that supports bank configurable power modes according to examples as disclosed herein is described. An example of a memory die that supports bank configurable power modes in accordance with examples as disclosed herein is described. 1 illustrates an example memory device state diagram that supports bank configurable power modes in accordance with examples as disclosed herein. 6 illustrates an example command mode state diagram that supports bank configurable power modes in accordance with examples as disclosed herein. 6 illustrates an example command mode state diagram that supports bank configurable power modes in accordance with examples as disclosed herein. 6 illustrates an example command mode state diagram that supports bank configurable power modes in accordance with examples as disclosed herein. An example process flow for supporting bank configurable power modes according to examples as disclosed herein is described. 4 illustrates an example power mode bitmap for a memory device that supports bank configurable power modes in accordance with examples as disclosed herein. 4 illustrates an example power mode bitmap for a memory device that supports bank configurable power modes in accordance with examples as disclosed herein. 4 illustrates an example power mode bitmap for a memory device that supports bank configurable power modes in accordance with examples as disclosed herein. 4 illustrates an example power mode bitmap for a memory device that supports bank configurable power modes in accordance with examples as disclosed herein. 4 illustrates an example power mode bitmap for a memory device that supports bank configurable power modes in accordance with examples as disclosed herein. 4 illustrates an example power mode bitmap for a memory device that supports bank configurable power modes in accordance with examples as disclosed herein. 4 illustrates an example power mode bitmap for a memory device that supports bank configurable power modes in accordance with examples as disclosed herein. 4 illustrates an example power mode bitmap for a memory device that supports bank configurable power modes in accordance with examples as disclosed herein. 4 illustrates an example power mode bitmap for a memory device that supports bank configurable power modes in accordance with examples as disclosed herein. 1 illustrates an example command mode state diagram that supports bank configurable power modes in accordance with examples as disclosed herein. An example power level consumption profile for a memory device supporting a bank configurable power mode in accordance with examples as disclosed herein will now be described. FIG. 2 illustrates a block diagram of a memory device supporting bank configurable power modes according to examples as disclosed herein. 4 shows a flow chart describing one or more methods of supporting bank configurable power modes according to examples as disclosed herein. 4 shows a flow chart describing one or more methods of supporting bank configurable power modes according to examples as disclosed herein. 4 shows a flow chart describing one or more methods of supporting bank configurable power modes according to examples as disclosed herein. 4 shows a flow chart describing one or more methods of supporting bank configurable power modes according to examples as disclosed herein.

Some memory devices may operate in one or more low power modes, in which the memory device may disable or alter the operation of circuitry supporting memory cells to reduce power consumption. For example, a FeRAM device may transition from an idle state to a low power state that consumes less power than an idle state based on deactivating some amount of circuitry. In a low power state, the memory device may not be able to perform access operations (e.g., read operations, write operations, etc.) on the memory cells of the memory device, or may enter an active state in which such operations may be performed. It may not be possible to transition directly (eg, when in a low power state, the memory device may have to transition first to an idle state and then to an active state). In some cases, FeRAM devices may support different low power states associated with different reduced levels of current consumption (eg, associated with different amounts of deactivated circuitry).

Similarly, a DRAM device may also transition its memory banks from an idle state to a low power state, which may include powering down one or more circuit components to reduce current consumption in the DRAM device. In some cases, a DRAM may remain in self-refresh mode while powering down other components used to perform access operations (read operations, write operations, etc.).

Transitioning a memory device from a low power mode to an active mode (eg, idle mode and then active mode) can take a certain amount of time. For example, a memory device may need to perform one or more procedures to activate circuits that were deactivated while in a low power state in order to access memory cells. In some cases, low power modes that consume less current (ie, use less energy, more circuits are deactivated) may take longer to transition to idle or active modes.

Some memory devices (eg, some FeRAM and DRAM devices) can control low power modes at the device or die level. That is, when transitioning to a low power mode, the circuitry for the device or the entire die may change operating modes to use less power. Thus, transitioning the memory device or die from a low power mode to an idle mode to activate at least a portion of the memory array (e.g., a bank of the memory array) when the memory device receives a command to perform an operation on the memory array. There may be latency associated with subsequent transitions to modes. Furthermore, although the entire memory device may be switched into or out of low power mode, access operations (eg, read, write, etc.) may be performed only on active portions of the memory array. As a result, the memory die achieves an overall reduction in power consumption (e.g., reduction in power usage from operating in low power mode is associated with transitioning the die to and from low power mode). It may only switch to low power mode if it will remain in the low power mode for a minimum period of time, such as for a period of time long enough to be greater than the power loss. Thus, the memory die may realize less power savings than desired due to the losses associated with switching the device or the entire die to and from low power modes. Additionally, memory devices or dies may operate less frequently in low power modes due to the latency required to wake up the entire device or die, further increasing power consumption.

Memory devices achieve greater power savings (e.g., lower current consumption) by operating different portions of the memory device or die therein (e.g., different portions of a single memory array) in different power modes. can. For example, a first portion of the memory device or die may operate in a first power mode and a second portion of the memory device or die may operate in a second power mode. The first power mode may be an active mode, or a low power mode that may be accessed with shorter latency (eg, faster wakeup time) than other low power modes. Such low power modes with relatively shorter latencies may be referred to as power down (PD) modes. The memory device may operate the second portion of the memory in a second low power mode compared to the PD mode, and the second low power mode may be accessed with longer latency. A low power mode with relatively long latency may be referred to as a deep sleep (DS) mode. In some cases, a memory device may support multiple DS modes, each with different amounts of power consumption (e.g., different amounts of circuitry deactivated for portions of the memory device in DS mode). Correspondingly, different portions of the memory device can be in different DS modes at the same time. In some cases, a memory device may switch a first portion of memory from PD mode to idle or active mode while maintaining a second portion of memory in DS mode (and vice versa). ). In this regard, memory devices increase power savings by operating different portions of the device in different power modes and, in some cases, transitioning only a portion of the memory cells to active mode to perform access operations. can be realized. Accordingly, the memory device may reduce losses due to transitioning into and out of low power modes, and may operate in one or more low power modes more frequently and for longer periods of time.

Aspects taught herein include using power mode bitmaps to indicate portions (e.g., memory banks) that operate in various low power modes (e.g., PD and DS power modes). The power mode bitmap may be written to one or more registers (eg, mode registers) or other storage within the memory device. Additionally or alternatively, a memory device may be configured via one or more commands to switch different portions (eg, different memory banks) into one or more low power modes. In some cases, when a memory device receives a command to enter a low power mode, the memory device may use power to determine which portions of the memory device should operate in which low power mode. You can access the mode bitmap. Further, while operating in one or more low power modes, the memory device may activate or activate one or more portions from the low power mode while maintaining other portions of the memory device in the low power mode. You can switch to idle mode. In some cases, memory devices may control low power modes at the bank level. Thus, the memory device can switch different banks between active mode, idle mode, and one or more different low power modes.

Operating different portions of the memory device in different low power modes can result in a reduction in overall current consumption. For example, a memory device may switch some portions of its memory more frequently and for longer periods of time in a low power mode, such as DS mode, compared to a memory device that switches the entire memory device into and out of low power mode. It may be possible to operate Additionally, the memory device may operate portions of the memory device in PD mode, which may switch to idle or active mode more quickly to service commands received by the memory device, to reduce latency.

In some cases, memory devices operate some memory banks in PD mode and other memory banks in one or more DS modes, including when the same or a limited number of banks are accessed repeatedly. Benefit from working. For example, these frequently accessed banks may operate in PD mode, which supports switching them to idle/active mode more quickly to perform one or more access operations. obtain. Therefore, these banks can realize a slight increase in power savings by switching between PD mode and idle/active mode. In addition, the memory device may achieve greater reductions in power usage by operating other memory banks in one or more DS modes, leaving these DS banks idle as access operations are focused on the PD banks. / It may not be necessary to switch to active mode. Thus, the overall current usage (e.g., due to both PD mode and DS mode) for the memory device is reduced compared to systems that switch the memory device or the entire die between active and low power modes. obtain. In some cases, operating additional memory banks in DS mode to increase power savings may reduce the bandwidth for access operations due to longer access times associated with portions of memory devices operating in DS mode. width can be reduced. The amount of memory banks operating in each of PD and DS modes can be varied to balance power savings and bandwidth. Additionally, in some cases, memory controllers (internal or external to the memory device) may be associated with a memory controller based on power consumption considerations (e.g., to support the increased use of DS mode for other memory banks). Data for one or more applications may be allocated across one or more memory banks (by concentrating data in a relatively small number of memories). These and other advantages can be appreciated by those skilled in the art.

The disclosed mechanisms are first described in the context of a memory system and memory die, as described with reference to FIGS. 1-2. The disclosed mechanisms are described in the context of memory device state diagrams, process flows, power mode bitmaps, and power level consumption diagrams, as described with reference to FIGS. 3-10. These and other features of the disclosure are further illustrated by and with reference to apparatus diagrams and flow charts for bank configurable power modes, as described with reference to FIGS. 11-15.

FIG. 1 illustrates an example system 100 that utilizes one or more memory devices according to examples as disclosed herein. System 100 may include external memory controller 105 , memory device 110 , and multiple channels 115 coupling external memory controller 105 with memory device 110 . System 100 may include one or more memory devices, but for ease of explanation, one or more memory devices may be described as a single memory device 110 .

System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, or graphics processing devices. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, laptop computer, tablet computer, smart phone, mobile phone, wearable device, Internet connected device, or the like. Memory device 110 may be a component of a system configured to store data for one or more other components of system 100 . In some examples, system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

At least a portion of system 100 may be an example of a host device. Such host devices may be computing devices, mobile computing devices, wireless devices, graphics processing devices, computers, laptop computers, tablet computers, smartphones, mobile phones, wearable devices, Internet-connected devices, or any other fixed or It can be an example of a device that uses memory to execute a process, such as a portable electronic device. In some cases, host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 105 . In some cases, external memory controller 105 may be referred to as a host or host device. In some examples, system 100 is a graphics card.

In some cases, memory device 110 is an independent device or component configured to communicate with other components of system 100 and to provide physical memory addresses/spaces potentially used or referenced by system 100. could be. In some examples, memory device 110 may be configurable to work with at least one or more different types of system 100 . Signaling between the components of system 100 and memory device 110 depends on the modulation scheme for modulating the signal, different pin designs for communicating the signal, separate packaging of system 100 and memory device 110, system 100 and memory device 110. It may be operable to support clock signaling and synchronization with device 110, timing conventions, and/or other factors.

Memory device 110 may be configured to store data for components of system 100 . In some cases, memory device 110 may act as a slave-type device to system 100 (eg, executing in response to commands provided by system 100 through external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 may include two or more memory dies 160 (eg, memory chips) to support a desired or specified capacity for data storage. A memory device 110 that includes more than one memory die may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

System 100 may further include processor 120 , basic input/output system (BIOS) component 125 , one or more peripheral components 130 , and input/output (I/O) controller 135 . Components of system 100 may electronically communicate with each other using bus 140 .

Processor 120 may be configured to control at least a portion of system 100 . Processor 120 can be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. , or a combination of these types of components. In such cases, processor 120 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), or a system-on-chip (SoC), among other examples.

BIOS component 125 may be a software component, including BIOS that operates as firmware that may initialize and execute various hardware components of system 100 . BIOS component 125 may also manage data flow between processor 120 and various components of system 100, such as peripheral components 130, I/O controller 135, and the like. BIOS component 125 may include programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

Peripheral component 130 may be any input or output device or interface for such a device that may be integrated into or with system 100 . Examples include disk controllers, audio controllers, graphics controllers, Ethernet controllers, modems, universal serial bus (USB) controllers, serial or parallel ports, or peripheral card slots such as peripheral component interconnect (PCI) or dedicated graphics ports. can be Peripheral component 130 may be any other component understood by those skilled in the art as a peripheral.

I/O controller 135 may manage data communications between processor 120 and peripheral components 130 , input devices 145 , or output devices 150 . I/O controller 135 may manage peripherals that are not integrated into or with system 100 . In some cases, I/O controller 135 may represent a physical connection or port to an external peripheral component.

Inputs 145 may represent devices or signals external to system 100 that provide information, signals, or data to system 100 or components thereof. This may include a user interface, or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or may be managed by I/O controller 135 .

Output 150 may represent a device or signal external to system 100 configured to receive an output from anywhere within system 100 or its components. Examples of output 150 may include a display, audio speakers, a printed device, or another processor on a printed circuit board, or the like. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or may be managed by I/O controller 135 .

Memory device 110 may include device memory controller 155 and one or more memory dies 160 . Each memory die 160 includes a local memory controller 165 (eg, local memory controller 165-a, local memory controller 165-b, and/or local memory controller 165-N) and a memory array 170 (eg, memory array 170-a, memory array 170-b, and/or memory array 170-N). Memory array 170 may be a collection (eg, grid) of memory cells, each memory cell configured to store at least one bit of digital data. The organization of memory array 170 and/or memory cells is described in more detail with reference to FIG.

Memory device 110 may be an example of a two-dimensional (2D) array of memory cells, or an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die 160 . A 3D memory device may include more than one memory die 160 (eg, memory die 160-a, memory die 160-b, and/or any amount of memory die 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other or may be adjacent to each other. In some cases, memory die 160-N within a 3D memory device may be referred to as decks, levels, layers, or dies. 3D memory devices can be stacked in any amount (e.g., 2 high, 3 high, 4 high, 5 high, 6 high, 7 high, 8 high) It may include memory die 160-N. This may increase the amount of memory cells that can be placed on the substrate compared to a single 2D memory device, which in turn may reduce manufacturing costs or increase the performance of the memory array, or it can be both. In some 3D memory devices, different decks share at least one common access line, such that several decks may share at least one of wordlines, digitlines, and/or platelines. obtain.

Device memory controller 155 may include circuits or components configured to control the operation of memory device 110 . Accordingly, device memory controller 155 may include hardware, firmware, and software that enable memory device 110 to implement commands, receive, transmit, and receive commands, data, or control information related to memory device 110 . or can be configured to do so. Device memory controller 155 may be configured to communicate with external memory controller 105 , one or more memory dies 160 , or processor 120 . In some cases, memory device 110 may receive data and/or commands from external memory controller 105 . For example, memory device 110 may write commands that indicate that memory device 110 is to store certain data on behalf of a component of system 100 (eg, processor 120), or if memory device 110 is stored within memory die 160. A read command may be received that indicates to provide certain data to a component of system 100 (eg, processor 120). In some cases, device memory controller 155 may work in conjunction with local memory controller 165 of memory die 160 to control operations of memory device 110 as described herein. Examples of components included within device memory controller 155 and/or local memory controller 165 are a receiver for demodulating signals received from external memory controller 105 , a receiver for modulating signals for transmission to external memory controller 105 . It may include decoders, logic, decoders, amplifiers, filters, or the like.

A local memory controller 165 (eg, local to memory die 160 ) may be configured to control the operation of memory die 160 . Also, local memory controller 165 may be configured to communicate (eg, receive and transmit data and/or commands) with device memory controller 155 . Local memory controller 165 may support device memory controller 155 to control the operation of memory device 110 as described herein. In some cases, memory device 110 does not include device memory controller 155, and local memory controller 165 or external memory controller 105 may perform various functions described herein. Thus, local memory controller 165 may be configured to communicate with device memory controller 155 , other local memory controllers 165 , or directly with external memory controller 105 or processor 120 .

External memory controller 105 may be configured to enable communication of information, data, and/or commands between components of system 100 (eg, processor 120 ) and memory device 110 . External memory controller 105 may act as a liaison between the components of system 100 and memory devices 110 such that the components of system 100 need not know the operational details of the memory devices. Components of system 100 may submit requests (eg, read commands or write commands) to external memory controller 105 that external memory controller 105 satisfies. External memory controller 105 may redirect or convert communications exchanged between components of system 100 and memory device 110 . In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

In some cases, external memory controller 105 or other components of system 100 or their functionality described herein may be implemented by processor 120 . For example, external memory controller 105 may be hardware, firmware, or software implemented by processor 120 or other components of system 100, or some combination thereof. Although external memory controller 105 is depicted as being external to memory device 110 , in some cases external memory controller 105 , or its functionality described herein, may be implemented by memory device 110 . For example, external memory controller 105 may be hardware, firmware, or software implemented by device memory controller 155 or one or more local memory controllers 165, or some combination thereof. In some cases, external memory controller 105 is implemented by processor 120 and memory device 110 such that a portion of external memory controller 105 is implemented by processor 120 and another portion is implemented by device memory controller 155 or local memory controller 165 . can be distributed over Similarly, in some cases one or more of the functions described herein for device memory controller 155 or local memory controller 165 may in some cases may be implemented by the external memory controller 105).

Components of system 100 may exchange information with memory device 110 using multiple channels 115 . In some examples, channel 115 may enable communication between external memory controller 105 and memory device 110 . Each channel 115 may include one or more signal paths or transmission media (eg, conductors) between terminals associated with components of system 100 . For example, channel 115 may include a first terminal that includes one or more pins or pads on external memory controller 105 and one or more pins or pads on memory device 110 . A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to function as part of a channel. In some cases, the terminal pins or pads may be part of the channel 115 signal path. Additional signal paths may be coupled with the terminals of the channels for routing signals within the components of system 100 . For example, memory device 110 includes signal paths (e.g., memory die 170) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170). signal paths internal to memory device 110 or components thereof, such as internal to 160).

Channel 115 (and associated signal paths and terminals) may be dedicated to communicating a particular type of information. In some cases, channel 115 may be an aggregated channel and thus include multiple individual channels. For example, data channel 190 may be x4 (eg, including 4 signal paths), x8 (eg, including 8 signal paths), and x16 (eg, including 16 signal paths), and so on. Signals communicated over the channel may use a double data rate (DDR) timing scheme. For example, some symbols of the signal may be recorded on rising edges of the clock signal and other symbols of the signal may be recorded on falling edges of the clock signal. Signals communicated over the channel may use single data rate (SDR) signaling. For example, one symbol of the signal may be recorded every clock cycle.

In some cases, channel 115 may include one or more command and address (CA) channels 186 . CA channel 186 may be configured to communicate commands, including control information (eg, address information) associated with the commands, between external memory controller 105 and memory device 110 . For example, CA channel 186 may contain a read command with the address of the desired data. In some cases, CA channel 186 may be recorded on the rising edge of the clock signal and/or the falling edge of the clock signal. In some cases, CA channel 186 may include any amount of signal paths (eg, eight or nine signal paths) for decoding address and command data.

In some cases, channel 115 may include one or more clock signal (CK) channels 188 . CK channel 188 may be configured to communicate one or more common clock signals between external memory controller 105 and memory device 110 . Each clock signal may be configured to oscillate between high and low states to coordinate the actions of external memory controller 105 and memory device 110 . In some cases, the clock signals may be differential outputs (eg, CK_t and CK_c signals), and the signal path of CK channel 188 may be configured accordingly. In some cases, the clock signal may be single ended. CK channel 188 may include any amount of signal paths. In some cases, clock signal CK (eg, CK_t and CK_c signals) may provide a timing reference for command and addressing operations for memory device 110 or other system-wide operations for memory device 110 . Clock signal CK may therefore be referred to variously as control clock signal CK, command clock signal CK, or system clock signal CK. System clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

In some cases, channel 115 may include one or more data (DQ) channels 190 . Data channel 190 may be configured to communicate data and/or control information between external memory controller 105 and memory device 110 . For example, data channel 190 may communicate information written (eg, bi-directional) to memory device 110 or information read from memory device 110 .

In some cases, channel 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any amount of signal paths.

Channel 115 may couple external memory controller 105 with memory device 110 using a variety of different architectures. Examples of various architectures may include buses, point-to-point connections, crossbars, high density interposers such as silicon interposers, or channels formed in organic substrates, or some combination thereof. For example, in some cases the signal path may at least partially include a high density interposer such as a silicon interposer or a glass interposer.

Signals communicated over channel 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate signals communicated between external memory controller 105 and memory device 110 . A binary symbol modulation scheme may be an example of an M-ary modulation scheme where M equals two. Each symbol of the binary symbol modulation scheme can be configured to represent one bit of digital data (eg, the symbol can represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, and/or pulse amplitude modulation (PAM) with two symbols (eg, PAM2), etc. Not limited.

Memory device 110 may receive one or more commands to operate one or more portions of memory device 110 in a low power mode. For example, memory device 110 may receive a command to write power bitmap data to one or more mode registers of memory device 110 (eg, via CA channel 186). The power bitmap data may point to a first portion (eg, one or more memory banks) of memory device 110 operating in a first low power mode, such as PD mode. The power bitmap data may also point to a second portion of memory device 110 operating in a second low power mode associated with a lower power consumption level than the first mode, such as DS mode. Memory device 110 may receive the power bitmap data and write it to one or more mode registers.

Memory device 110 receives the command to enter the low power mode and accesses the power bitmap data stored on the mode register. Additionally or alternatively, memory device 110 may receive one or more commands specifying information that may otherwise be written to the mode register. Memory device 110 may switch a first portion of memory device 110 to PD mode and may switch a second portion of memory device 110 to DS mode. While operating the first and second portions in their respective low power modes, the memory device 110 issues a command to switch the first portion out of PD mode, e.g., into idle mode or active mode. (e.g., memory device 110 may receive commands to selectively switch only the portion in PD mode to idle mode or active mode, leaving only the portion in DS mode to remain in DS mode). ). Memory device 110 may bring a first portion of memory device 110 out of PD mode while continuing to operate a second portion in DS mode. Memory device 110 may perform one or more operations in a first portion of memory device 110 . For example, memory device 110 may perform a read or write operation on a bank associated with the first portion of memory device 110 . In some cases, memory device 110 may receive a command to return the first portion to low power mode and transition the first portion to PD mode.

FIG. 2 illustrates an example memory die 200 according to examples as disclosed herein. Memory die 200 may be an example of memory die 160 described with reference to FIG. In some cases, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205 programmable to store different logic states. Each memory cell 205 may be programmable to store more than one state. For example, memory cell 205 may be configured to store one bit of information (eg, logic 0 or logic 1) at a time. In some cases, a single memory cell 205 (eg, a multilevel memory cell) is configured to store multiple bits of information (eg, logic 00, logic 01, logic 10, or logic 11) at a time. obtain.

Memory cells 205 may store states (eg, polarization states or dielectric charges) that represent digital data. In the FeRAM architecture, memory cells 205 may include capacitors containing ferroelectric materials for storing charge and/or polarization representing programmable states. In a DRAM architecture, memory cell 205 may include a capacitor containing dielectric material for storing charge representing a programmable state.

Operations such as reading and writing may be performed on memory cells 205 by activating or selecting access lines such as word lines 210 , digit lines 215 and/or plate lines 220 . In some cases, digit lines 215 may also be referred to as bit lines. References to access lines, word lines, digit lines, plate lines, or the like are interchangeable without loss of understanding and operation. Activating or selecting a word line 210, digit line 215, or plate line 220 may involve applying a voltage to the respective line.

Memory die 200 may include access lines (eg, wordlines 210, digitlines 215, and platelines 220) arranged in a grid-like pattern. Memory cells 205 may be located at the intersections of word lines 210 , digit lines 215 , and/or plate lines 220 . By biasing wordline 210, digitline 215, and plateline 220 (e.g., applying a voltage to wordline 210, digitline 215, or plateline 220), a single memory cell 205 can Can be accessed at intersections.

Accessing memory cells 205 can be controlled through row decoder 225 , column decoder 230 , and plate driver 235 . For example, row decoder 225 may receive a row address from local memory controller 265 and activate word line 210 based on the received row address. Column decoder 230 receives a column address from local memory controller 265 and activates digit lines 215 based on the received column address. Plate driver 235 may receive a plate address from local memory controller 265 and activate plate line 220 based on the received plate address. For example, memory die 200 includes a plurality of wordlines 210 labeled WL_1 through WL_M, a plurality of digitlines 215 labeled DL_1 through DL_N, and a plurality of platelines labeled PL_1 through PL_P. , where M, N, and P depend on the size of the memory array. Thus, by activating word line 210, digit line 215, and plate line 220, eg, WL_1, DL_3, and PL_1, memory cell 205 at their intersection can be accessed. The intersection of word lines 210 and digit lines 215 in either a two-dimensional or three-dimensional configuration may be referred to as the address of memory cell 205 . In some cases, the intersection of word lines 210 , digit lines 215 and plate lines 220 may be referred to as the address of memory cell 205 .

Memory cell 205 may include a logic storage component such as capacitor 240 and a switching component 245 . Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled with switching component 245 and a second node of capacitor 240 may be coupled with plate line 220 . Switching component 245 may be an example of a transistor or any other type of switch device that selectively establishes or de-establishes electronic communication between two components.

Selecting or deselecting memory cell 205 may be accomplished by activating or deactivating switching component 245 . Capacitor 240 may be in electronic communication with digit line 215 using switching component 245 . For example, capacitor 240 may be isolated from digit line 215 when switching component 245 is deactivated, and capacitor 240 may be coupled to digit line 215 when switching component 245 is activated. In some cases, switching component 245 is a transistor whose operation is controlled by applying a voltage to the gate of the transistor, the voltage difference between the gate of the transistor and the source of the transistor being greater than the threshold voltage of the transistor. is too large or too small. In some cases, switching component 245 may be a p-type transistor or an n-type transistor. Word line 210 may be in electronic communication with the gate of switching component 245 and may activate/deactivate switching component 245 based on the voltage applied to word line 210 .

Word lines 210 may be conductive lines in electronic communication with memory cells 205 that are used to perform access operations on memory cells 205 . In some architectures, word line 210 may be in electronic communication with the gate of switching component 245 of memory cell 205 and may be configured to control switching component 245 of the memory cell. In some architectures, word line 210 may be in electronic communication with the capacitor node of memory cell 205, and memory cell 205 may not include switching components.

Digit lines 215 may be conductive lines that connect memory cells 205 with sense components 250 . In some architectures, memory cell 205 may be selectively coupled to digit line 215 during a portion of an access operation. For example, word line 210 and switching component 245 of memory cell 205 may be configured to selectively couple and/or isolate capacitor 240 of memory cell 205 and digit line 215 . In some architectures, memory cell 205 may be in electronic communication (eg, continuously) with digit line 215 .

Plate lines 220 may be conductive lines in electronic communication with memory cells 205 that are used to perform access operations on memory cells 205 . The plate line 220 may be in electronic communication with a capacitor 240 node (eg, cell bottom). Plate line 220 may be configured to cooperate with digit line 215 to bias capacitor 240 during access operations of memory cell 205 .

Sense component 250 may be configured to determine the state (eg, polarization state or charge) stored on capacitor 240 of memory cell 205 and to determine the logic state of memory cell 205 based on the sensed state. . The charge stored by memory cell 205 may be very small in some cases. Accordingly, sense component 250 may include one or more sense amplifiers for amplifying the signal output of memory cell 205 . The sense amplifier may detect small changes in charge on digit line 215 during a read operation and produce a signal corresponding to either logic 0 or logic 1 based on the detected charge. During a read operation, capacitor 240 of memory cell 205 may output a signal (eg, discharge charge) on its corresponding digit line 215 . The signal may change the voltage on digit line 215 . Sense component 250 may be configured to compare a signal received from memory cell 205 via digit line 215 to a reference signal 255 (eg, a reference voltage). Sense component 250 may determine the stored state of memory cell 205 based on the comparison. For example, in binary signaling, if digit line 215 has a higher voltage than reference signal 255, sense component 250 may determine that the stored state of memory cell 205 is a logic one and digit line 215 is at reference signal 255. 255, sense component 250 may determine that the stored state of memory cell 205 is a logic zero. Sense component 250 may include various transistors or amplifiers for detecting and amplifying signal differences. The detected logic state of memory cell 205 may be provided as an output of sense component 250 (e.g., to input/output 260), device memory controller 155, etc. (e.g., directly or using local memory controller 265). , the detected logic state may be indicated to another component of memory device 110 , including memory die 200 . In some cases, sense component 250 may be in electronic communication with row decoder 225 , column decoder 230 , and/or plate driver 235 .

Local memory controller 265 may control the operation of memory cells 205 through various components (eg, row decoder 225, column decoder 230, plate driver 235, and sense component 250). Local memory controller 265 may be an example of local memory controller 165 described with reference to FIG. In some cases, one or more of row decoder 225 , column decoder 230 , plate driver 235 , and sense component 250 may be co-located with local memory controller 265 . Local memory controller 265 receives one or more commands and/or data from external memory controller 105 (or device memory controller 155 described with reference to FIG. 1) and sends commands and/or data to memory die 200 . converting into information that can be used; performing one or more operations on memory die 200; It may be configured to communicate data to the controller 155). The local memory controller 265 may generate row, column, and plateline address signals to activate the target wordline 210 , the target digitline 215 , and the target plateline 220 . Local memory controller 265 may also generate and control various voltages or currents used during operation of memory die 200 . In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied and may be different for various operations discussed in the operation of memory die 200 .

In some cases, local memory controller 265 may be configured to perform write operations (eg, programming operations) on one or more memory cells 205 of memory die 200 . During a write operation, memory cells 205 of memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. Local memory controller 265 may identify the memory cell 205 on which to perform the write operation. The local memory controller 265 may identify the target word line 210, the target digit line 215, and/or the target plate line 220 in electronic communication with the target memory cell 205 (eg, the address of the target memory cell 205). . To access a target memory cell 205, the local memory controller 265 may use the target word line 210, target digit line 215, and/or target plate line 220 (e.g., word line 210, digit line 215, or can be activated by applying a voltage to the plate line 220). Local memory controller 265 places a particular signal (eg, voltage) on digit line 215 and a particular signal on plate line 220 during a write operation to store a particular state in capacitor 240 of memory cell 205 . (eg voltage) may be applied, the particular state indicating the desired logic state.

In some cases, local memory controller 265 may be configured to perform read operations (eg, sensing operations) on one or more memory cells 205 of memory die 200 . During a read operation, the logic states stored within memory cells 205 of memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. Local memory controller 265 may identify the memory cell 205 on which to perform the read operation. The local memory controller 265 may identify the target word line 210, the target digit line 215, and/or the target plate line 220 in electronic communication with the target memory cell 205 (eg, the address of the target memory cell 205). . To access a target memory cell 205, the local memory controller 265 may use the target word line 210, target digit line 215, and/or target plate line 220 (e.g., word line 210, digit line 215, or can be activated by applying a voltage to the plate line 220). The target memory cell 205 may transfer a signal to the sense component 250 in response to biasing the access line. Sense component 250 may amplify the signal. Local memory controller 265 may activate sense component 250 (eg, latch sense component), thereby comparing the signal received from memory cell 205 to reference signal 255 . Based on the comparison, sense component 250 may determine the logic state stored on memory cell 205 . Local memory controller 265 may communicate the logic state stored on memory cell 205 to external memory controller 105 (or a device memory controller) as part of a read operation.

In some memory architectures, accessing memory cell 205 may degrade or destroy the logic state stored within memory cell 205 . For example, a read operation performed on a ferroelectric memory cell can corrupt the logic state stored in the ferroelectric capacitor. In another example, a read operation implemented in a DRAM architecture may partially or fully discharge the capacitor of the memory cell of interest. Local memory controller 265 may perform a rewrite or refresh operation to return the memory cells to their original logic state. Local memory controller 265 may rewrite the logic state to the target memory cell after a read operation. In some cases, a rewrite operation can be considered part of a read operation. Also, activating a single access line, such as word line 210, may disturb states stored in several memory cells in electronic communication with that access line. Accordingly, a rewrite or refresh operation may be performed on one or more memory cells that may not have been accessed.

FIG. 3 illustrates an example memory device state diagram 300 that supports bank configurable power modes according to examples as disclosed herein. The mechanism of memory device state diagram 300 may be a memory device (eg, memory device 110, memory die 160, or memory die 200 described with reference to FIGS. 1-2) or memory device state diagram 300 described with reference to FIGS. It may be implemented by one or more components of a memory device such as device controller 155 , local memory controller 165 , or local memory controller 265 . Memory device state diagram 300 may describe different states or modes of operation that may be transitioned between one or more portions (eg, one or more banks) of a memory device. In some cases, some functions of the memory device (e.g., read operations, write operations, refresh operations, etc.) may be performed when the relevant portion (e.g., bank) of the memory device is in a particular state or mode (e.g., active mode). It can only be run if it is running.

Among other states, a memory device (eg, under the direction of one or more controllers for the memory device, such as external memory controller 105, device memory controller 155, or local memory controller 165, or combinations thereof) may be in an idle state. 305 or active state 310. In the idle state 305, there may be no memory cells accessible. In active state 310, at least a portion of the memory device (e.g., a bank, a row within a bank) may be activated to allow access operations (e.g., read, write, or refresh operations). obtain. The memory device may switch between idle mode 305 and active mode 310 based on receiving one or more commands. For example, a memory device may operate in idle mode 305 and switch to active mode 310 based on receiving a command (eg, an activate command for a memory bank) from a host device. An activate command may transition the device to an activate mode 306, which may power up one or more components of the memory device. The memory device may automatically transition from activated mode 306 to active mode 310 once the components of the memory device are powered up. In some cases, the memory device may operate in active mode 310 and switch to idle mode 305 . For example, a memory device may receive a command to switch to idle mode while operating in active mode 310 and may perform one or more procedures to transition to idle mode 305 . In some cases (eg, DRAM memory devices), the memory device may receive a precharge command and transition to precharge mode 312 . From precharge mode 312, the memory device may automatically transition to idle mode 305, eg, after completing one or more precharge operations. The memory device may switch from the idle state 305 to any of the first set of operational modes and from the active state 310 to any of the second set of modes.

In some cases, from the idle mode 305, the controller may switch the memory device to operate in one of multiple low power modes 315,320. For example, the memory device may transition to a first low power mode 315 (eg, power down-0), which may be referred to as a power down (PD) mode. When operating in PD mode 315 , the memory device may consume less current than when operating in idle mode 305 or active mode 310 . In some examples, PD mode 315 may be associated with the highest amount of current consumption among the low power modes 315 , 320 and may have the shortest exit time to return to idle mode 305 . In another example, the memory device transitions to a second set of low power modes 320 (eg, power down-1, power down-2, power down-3), which may be referred to as deep sleep (DS) modes 320. obtain. When operating in DS mode 320 , the memory device may consume less current (and deactivate more components) than when operating in PD mode 315 . A first DS mode 320-a may have the highest current consumption among DS modes 320 and may be referred to as a first DS level. The second DS mode 320-b may have less current consumption (and deactivate more components) than the first DS mode 320-a and may be referred to as a second DS level. A third DS mode 320-c may have the lowest current consumption (and the most deactivated components) among the DS modes 320 and may be referred to as the third DS level. In some examples, first DS mode 320-a may have a later end time (eg, time to switch to idle state 305 or active state 310) than PD mode 315, but DS mode 320-a It can have the fastest finish time of all. The second DS mode 320-b may have a later end time than the first DS mode 320-a and may have a faster end time than the third DS mode 320-c. It should be appreciated that any number of PD or DS modes are possible.

In some examples, when a memory device exits DS mode 320 , the device may first transition to a different low power mode such as PD mode 315 or refresh mode before switching to idle mode 305 . For example, if the memory device operates in the first DS mode 320-a and receives a command to exit the low power mode, the memory device may first switch to PD mode 315 before switching to idle mode 305. . In examples involving DRAM memory devices, PD mode 315 may involve performing a self-refresh operation before switching to idle mode 305 . In some examples, when the memory device exits DS mode 320 or PD mode 315, it enters an idle mode, an active mode, or another low power mode (e.g., from one DS mode 320 to another DS mode 320; (from PD mode 315 to another PD mode 315, from DS mode 320 to PD mode 315, or from PD mode 315 to DS mode 320).

In some cases, from active mode 310 the controller may switch the memory device to operate in active power down mode 325 or access mode 330 . In active power down mode 325, current consumption may be higher than in low power modes 315,320. For example, at least some circuitry within the memory device that is deactivated while the memory device is in one of the low power modes 315, 320 may be activated while the memory device is in the active power down mode 325. can remain. When the memory bank is in access mode 330, the memory device performs one or more access operations (e.g., read, write, etc.) on the memory cells of the activated portion of the memory device (e.g., activated memory bank). ) can be implemented.

In some cases, different portions of the memory device may operate in different modes, as described herein. For example, a memory device may operate in a first mode, such as idle mode 305 . The controller causes a first portion of the memory device to operate in a first low power mode, such as PD mode 315, and a second portion of the memory device to operate in a second low power mode, such as DS mode 320. can be switched to In some cases, the controller may subsequently switch the first portion from PD mode 315 to idle mode 305 or active mode 310 while maintaining the second portion in DS mode. The controller may also subsequently return the first portion from idle 305 or active mode 310 to a low power mode, such as PD mode 315, while maintaining the second portion in DS mode.

In some cases, the controller may switch operating modes of the memory device at the bank level. For example, one or more banks of memory devices may be independently switched between different operating modes. In some examples, a first bank or set of banks may be switched to operate in PD mode 315 (eg, from idle mode 305), while a second bank or set of banks may be switched to DS mode 320. (eg, from idle mode 305). In other examples, additional sets of banks may operate independently in other or the same modes. For example, a first set of banks can be switched to PD mode 315 and a second set of banks can also be switched to PD mode 315 . In some cases, the first set of banks may be switched out of PD mode 315 while maintaining the second set of banks in PD mode 315 (or DS mode 320). In a further example, the third set of banks can operate in different modes, such as DS mode 320 . Thus, the memory device can dynamically and independently switch different banks or bank groups between different operating modes. Although the concepts may in some cases be described with reference to one or more memory banks for purposes of example and clarity, memory devices may be similar to those described herein with respect to memory banks. It should be appreciated that the method may switch the memory device or other portion of the die between different modes of operation.

FIG. 4A illustrates an example command mode state diagram 401 that supports bank configurable power modes according to examples as disclosed herein. The mechanism of command mode state diagram 401 may be a memory device (eg, memory device 110, memory die 160, or memory die 200 described with reference to FIGS. 1-2) or a memory device described with reference to FIGS. It may be implemented by one or more components of a memory device such as device controller 155 , local memory controller 165 , or local memory controller 265 . Command mode state diagram 400 is an example of idle mode 405, which may be an example of idle mode 305 described with reference to FIG. 3, and low power mode 320 (eg, DS mode) described with reference to FIG. One or more commands 425, 426 used to switch the memory device to and from low power mode 415 may be described. In some cases, a mode register write (MRW) command 430 may be used to write data to one or more mode registers of the memory device.

A memory device may be configured via one or more commands to switch different portions of the memory device between different modes. In some examples, data indicating assignment of different portions (eg, memory banks) of a memory device to different low power modes may be stored in a mode register. A mode register write (MRW) command 430 may switch the memory device to MRW mode 420 . For example, a memory device may operate in idle mode 405 and receive MRW commands 430 . In response, the memory device may switch from idle mode 405 to MRW mode 420, and while in MRW mode 420, the memory device writes data to the mode register indicating the allocation of different memory banks to different low power modes. obtain. The memory device may return from MRW mode 420 to idle mode 405 when the write to the mode register data is complete. In some examples, switching from MRW mode 420 to idle mode may be automatic (eg, upon completion of writing data to the mode register).

A power down transition (PDE) command may be used to switch the memory device to low power mode 415 . For example, a memory device may operate in idle mode 405 and receive PDE command 425-a. In response, the memory device may switch from idle mode 405 to low power mode 415 (eg, DS mode), which causes different portions of the memory device to transition to different low power modes (eg, the first transition to a first DS level and a second set of banks transition to a second DS level). In some cases, assignment of a first portion of the memory device to a first low power mode 415 (e.g., a first DS level) and a second portion of the memory device to a second low power mode 415 (e.g., a first DS level). For example, the assignment to the second DS level) may be based on data stored in the mode register. Different portions of the memory device may operate in their respective low power modes until receiving one or more exit power down (PDX) commands.

In some cases, a memory device may receive an exit command 426 (eg, PDX_ALL) to switch all memory banks out of low power mode 415 . For example, exit all command 426 may be configured to indicate that all banks operating in low power mode 415 (eg, DS mode) are switched to idle mode 405 . A memory bank operating in DS mode may switch to idle mode 405 within the DS end time, which may be longer than the PD end time. In some cases, the end time may alternatively be referred to as the wakeup time.

FIG. 4B illustrates an example command mode state diagram 402 that supports bank configurable power modes according to examples as disclosed herein. The mechanism of command mode state diagram 402 may be a memory device (eg, memory device 110, memory die 160, or memory die 200 described with reference to FIGS. 1-2) or a memory device described with reference to FIGS. It may be implemented by one or more components of a memory device such as device controller 155 , local memory controller 165 , or local memory controller 265 . Command mode state diagram 402 is an example of idle mode 405, which may be an example of idle mode 305 described with reference to FIG. 3, and low power mode 315 (eg, PD mode) described with reference to FIG. One or more commands 425, 427 used to switch the memory device to and from low power mode 417 may be described. In some cases, MRW command 430 may be used to write data to one or more mode registers of a memory device, as described herein.

A power down transition (PDE) command may be used to switch the memory device to a low power mode 417 (eg, PD mode). For example, a memory device may operate in idle mode 405 and receive PDE commands 425 . In response, the memory device may switch from idle mode 405 to low power mode 417 (eg, PD mode). In some cases, PDE command 425 may include aspects of PDE command 425 described with reference to FIG. 4A. For example, PDE command 425 may switch from idle mode 405 to one or more low power modes 415, 417, which may cause different portions of the memory device to transition to different low power modes (e.g., the first set of banks). transitions to PD and a second set of banks transitions to DS mode). In some cases, assignment of a first portion of the memory device to a first low power mode 415 (eg, DS mode) and a second portion of the memory device to a second low power mode 417 (eg, PD mode). mode) may be based on data stored in the mode register. Different portions of the memory device may operate in their respective low power modes until receiving one or more exit power down (PDX) commands.

In some cases, the memory device may receive a first selective exit command 427 (eg, PDX_SEL) that instructs the memory device to switch a portion of the memory device out of low power mode 417 . For example, selective exit command 427 may be configured to indicate that all memory banks operating in PD mode 417 are switched to idle mode 405 while keeping memory banks operating in DS mode 415. . A memory bank operating in PD mode may switch to idle mode 405 within the expiration time associated with PD mode.

In some cases, the memory device may receive a second exit command 427 (eg, PDX_ALL) to switch all memory banks out of low power mode 417 . Exit all command 427 may be configured to indicate that all memory banks operating in low power mode 415 (eg, PD mode, DS mode, etc.) are switched to idle mode 405 . A memory bank operating in PD mode can switch to idle mode 405 within the PD end time, a memory bank operating in DS mode can switch to idle mode 405 within the DS end time, and the DS end time is It may be longer than the PD end time. In some cases, the end time may alternatively be referred to as the wakeup time.

FIG. 4C illustrates an example command mode state diagram 403 that supports bank configurable power modes according to examples as disclosed herein. The mechanism of command mode state diagram 403 may be a memory device (eg, memory device 110, memory die 160, or memory die 200 described with reference to FIGS. 1-2) or a memory device described with reference to FIGS. It may be implemented by one or more components of a memory device such as controller 155, local memory controller 165, or local memory controller 265. Command mode state diagram 403 illustrates active mode 410, which may be an example of active mode 310 described with reference to FIG. 3, and low power mode 419, which may be an example of active power down 325 described with reference to FIG. One or more commands 425, 427 used to switch memory devices between may be described. In some cases, MRW command 430 may be used to write data to one or more mode registers of a memory device, as described herein.

In some cases, the memory device may transition directly between active mode 410 and low power mode 419 . If the memory device switches directly between active mode 410 and low power mode 419, the memory device may transition to active PD mode (eg, active power down 325 described with reference to FIG. 3) and switch to DS mode. It may not be possible to migrate. For example, if a memory device operates in active mode 410 and receives a PDE command 425, the memory device may be configured to switch one or more memory banks to active PD mode.

FIG. 5 illustrates an example process flow 500 that supports bank configurable power modes according to examples as disclosed herein. Process flow 500 may be implemented by a memory device (eg, memory device 110, memory die 160, or memory die 200 described with reference to FIGS. 1-2), or memory device controller 155 described with reference to FIGS. It may be implemented by one or more components of a memory device such as local memory controller 165 or local memory controller 265 . Process flow 500 is one of command and address (CA) bus 505 and data (DQ) bus 510, etc., which may be examples of CA channel 186, DQ channel 190, or other channel 115 described with reference to FIG. Command signals transmitted over the above channels may be described. Process flow 500 may also describe PD mode 515 and DS mode 520 that may be indicated when a subset of memory banks are operating in PD mode and/or DS mode as described herein. Process flow 500 may describe command sequences for switching different subsets of memory banks between different modes (eg, idle mode, active mode, PD mode, or DS mode).

First, a host device or memory device may determine to transition one or more memory banks to a low power mode. This can be triggered by a variety of factors, including expected periods of inactivity in memory banks, inactivity time thresholds, host device commands, or power constraints/thresholds. In some cases, a memory device may store data on one or more mode registers that indicate assignment of different memory banks to different low power modes. In some cases, the memory device may accumulate this data in a mode register before deciding to enter a low power mode. For example, a memory device may write data upon power-up or based on receiving commands from a host device. In other cases, the memory device may store this data in the mode register after determining to enter the low power mode. For example, in response to receiving a command to enter a low power mode, or in response to a command from the host device.

The memory device may receive MRW command 525 via CA bus 505, which may be an example of MRW command 430 described with reference to FIG. In response to receiving the MRW command 525, the memory device may write power mode data (PMD) 530 to one or more mode registers that indicate the assignment of different memory banks to different low power modes. In some cases, PMD 530 may include one or more power mode bitmaps, which are further described in connection with FIGS. 6-8. In some examples, a memory device may receive PMD 530 over DQ bus 510 or other channel (eg, CA bus 505) and write PMD 530 to one or more mode registers of the memory device.

A determination may be made to transition to a low power mode, and the memory device may receive PDE command 535 over CA bus 505, which may be an example of PDE command 425-a described with reference to FIG. The memory device may access the mode register to determine to which low power mode the first set of memory banks should be switched. That is, the memory device may use the data stored in the mode register to determine whether to switch the first set of memory banks to PD mode or DS mode. In response to receiving the PDE command 535 and determining that the first set of memory banks should be switched to PD mode, the memory device switches the first set of memory banks to PD mode 540 and the A second set may switch to DS mode 545, which may be examples of the PD and DS modes described herein. The first and second sets of memory banks may continue to operate in separate PD and DS modes until the memory device receives one or more additional commands.

While operating in low power mode, the host device (or memory device) may determine to perform one or more operations on a subset of memory banks in low power mode. The memory device may receive PDX_SEL command 550 via CA bus 505, which may be an example of PDX_SEL command 425-b described with reference to FIG. In response to receiving the PDX_SEL command 550, the memory device may switch the first set of memory banks from PD mode 540 to idle mode or active mode. A first set of memory banks may exit PD mode within a first period of time, which may be referred to as the PD exit time. In some examples, the PD end time may be earlier than the DS end time. In some examples, the memory device performs one or more operations, such as one or more access operations (eg, read, write) while maintaining the second set of memory banks in DS mode. It can be implemented in a first set of banks. Thus, while a first set of memory banks operates in a higher power consumption mode, a second set of memory banks may continue to operate in a lower power consumption mode.

After performing the operation on the first set of memory banks, the host device (or memory device) may determine to return the first set of memory banks to low power mode. In some cases, the first set of banks will be switched to PD mode which will allow access to these banks within a short end time (PD end time) compared to the DS banks. In other cases, the first set of banks may be switched to DS mode, which may reduce their power consumption compared to PD mode, but lengthen their expiration time. The memory device may receive the PDE command 555 via the CA bus 505 and access the mode register to determine to which low power mode the first set of memory banks should be switched. That is, the memory device may use the data stored in the mode register to determine whether to switch the first set of memory banks to PD mode or DS mode. In response to receiving PDE command 555 and determining that the first set of memory banks should be switched to PD mode, the memory device may switch the first set of memory banks back to PD mode 560 .

Another decision can then be made to switch the memory bank out of low power mode. In some cases, the first set of memory banks may be switched out of PD mode independently of the second set of memory banks in DS mode, as described above. In some cases, the second set of memory banks can be switched out of DS mode independently. In some cases, both the first and second sets of memory banks can be switched from PD and DS modes using a single command (eg, PDX_ALL). In one example, the memory device may receive a PDX_SEL command 565 and switch the first set of memory banks out of PD mode. The first set of memory banks may transition to idle mode or active mode within the PD expiration time. Additionally or alternatively, the memory device may receive a PDX_ALL command 570 to switch the second set of memory banks out of DS mode. A second set of memory banks may transition to idle mode or active mode within the DS expiration time, which may be longer than the PD expiration time. Therefore, even if a single PDX_ALL command is received and the memory device initiates a switching procedure for both sets of memory banks at the same time, the first set of memory banks will be switched over to the second set of memory banks. It can be accessed in faster time than the set.

The foregoing description of process flow 500 in the context of a first set of memory banks and a second set of memory banks is general to transitioning portions of memory devices to and from different low power modes. are presented to illustrate the general concept. Accordingly, this description applies these concepts to other memory device hierarchies, such as larger numbers of memory banks, different groups or memory banks, memory dies, memory arrays, or other groups of memory cells, or combinations thereof. is not intended to be limiting.

6A-6C illustrate an example of power mode data supporting bank configurable power modes according to examples as disclosed herein. The power mode data may include a set of bank mask variables 605 (which may collectively include bank masks) and a set of bank group mask variables 610 (which may collectively include bank group masks), which in some cases are , may be written to one or more registers of the memory device. Based on bank mask variable 605 and bank group mask variable 610, memory device may determine the low power mode in which different memory banks 615 operate (eg, in response to a PDE command). For example, different memory banks 615 may be switched to different low power modes (eg, PD mode and DS mode for various DS levels as described herein) based on corresponding power mode data. Bank mask variable 605 and bank group mask variable 610 may be correlated with a particular memory bank 615 of a memory device based on a mapping between one or more mode register fields and memory bank 615 .

FIG. 6A illustrates an example power mode assignment 601 for a set of memory banks 615 based on corresponding bank mask variables 605 and bank group mask variables 610 . FIG. 6B illustrates an example bitmap format 602 for writing corresponding bank masks and bank group masks to one or more mode registers. FIG. 6C shows the bits containing the corresponding bank mask variable 605 and bank group mask variable 610 (pointing to the power mode assignment 601 described in FIG. 6A) as written to the mode register according to the bitmap format 602 described in FIG. 6B. An example of map data 603 will be described. The power mode data described in FIGS. 6A-6C may be stored in a memory device (eg, memory device 110, memory die 160, or memory die 200 described with reference to FIGS. 1-2) or may be utilized in accordance with the techniques described herein by one or more components of a memory device such as memory device controller 155, local memory controller 165, or local memory controller 265 described above.

FIG. 6A illustrates an example power mode assignment 601 for a set of memory banks 615 based on corresponding bank mask variables 605 and bank group mask variables 610 . For example, the low power mode assigned to each memory bank 615 may be indicated by (and thus determined based on) one or more of the corresponding bank mask variable 605 and the corresponding bank group mask variable 610 . In some cases, for a given memory bank 615, the corresponding bank group mask 610 variable determines whether (i) the memory bank 615 should operate in a first low power mode (e.g., the corresponding bank group mask 610 If the variable is a first logical value such as "0", the memory bank may operate in DS mode), or (ii) the memory bank should operate in the power mode specified by the second corresponding variable. (eg, if the corresponding bank group mask variable 610 is a second logical value such as "1", the corresponding bank mask variable 605 determines whether the memory bank should operate in PD mode or DS mode). can be evaluated to do).

6A, each column of memory banks 615 may correspond to a group of memory banks associated with the same bank group mask variable 610, each row of memory banks 615 is the bank number (index) within the group of memory banks; As such, it can be associated with a corresponding bank mask variable 605 . Thus, each bank group mask variable 610 can be associated with a corresponding column of memory bank 615 and each bank mask variable 605 can be associated with a corresponding row of memory bank 615 . Any number of groups of memory banks 615, each containing any number of memory banks 615, may be used, and memory banks 615 and their groups may be arranged in physical columns and rows as depicted in FIG. 6A. It should be understood that they need not be ordered.

As shown in the example of FIG. 6A, a first group of memory banks 615 may be associated with bank group mask variable 610-a (BG0) and a second group of memory banks 615 may be associated with bank group mask variable 610-a (BG0). b (BG1), a third group of memory banks 615 may be associated with bank group mask variables 610-c (BG2), and a fourth group of memory banks 615 may be associated with bank group mask variables 610-c (BG2). d(BG3). A second group of memory banks 615 may all be assigned DS mode based on setting BG1 to "0". The first, third, and fourth groups of memory banks 615 are assigned low power modes based on the corresponding bank mask variables 605 based on setting BG0, BG2, and BG3 to "1". can be Within each of the first, third, and fourth groups of memory banks 615, memory banks 615 in rows with corresponding bank mask variables 605 set to "0" may be assigned DS mode, and corresponding The PD mode may be assigned to memory banks 615 in rows whose corresponding bank mask variable 605 is "1".

Bank mask variable 605 and bank group mask variable 610 may alternatively be separate bivariate sequences in which the two variables collectively point to an assigned low power mode (e.g., based on a combination of variables in the bivariate sequence). It can be considered, described, or evaluated as pointing to each memory bank 615 . For example, the first variable in the two-variable sequence can be the corresponding Bank Group Mask variable 610 and the second variable in the two-variable sequence can be the corresponding Bank Mask variable 605 . Thus, in some cases, memory banks 615 associated with 00, 01, or 10 sequences may be assigned a first low power mode (eg, DS mode), and memory banks 615 associated with 11 sequences may may be assigned a second low power mode (eg, PD mode). Each memory bank 615 may be associated with a corresponding bank mask variable 605 and a corresponding bank group mask variable 610 (eg, based on mapping to fields of the mode register).

As an illustrative example, the first memory bank 615-a contains a value (eg, BG3=1) for the first variable according to the fourth bank group mask variable 610-d and the first bank mask variable A value (eg, B0=1) for the second variable according to 605-a may be assigned. Thus, the two-variable sequence for first memory bank 615-a is 11, which indicates that PD mode is assigned to first memory bank 615-a (eg, switched to PD mode in response to a PDE command). ). The second memory bank 615-b contains the value for the first variable (eg, BG3=1) according to the fourth bank group mask 610-d and the value for the first variable according to the fifth bank mask variable 605-e. A value (eg, B4=0) for the second variable may be assigned. Therefore, the two-variable sequence for the second memory bank 615-b is 01, which indicates that the second memory bank 615-b is assigned to DS mode (eg, switched to DS mode in response to a PDE command). ).

FIG. 6B illustrates an example bitmap format 602 for writing a bank mask variable 605 (eg, as a bank mask) and a bank group mask variable 610 (eg, as a bank group mask) to separate mode registers. do. The bank mask variable 605 and bank group mask variable 610 are associated with specific addresses (fields, bit positions) within the mode register so that the memory device can correlate values stored within the mode register to specific memory banks 615 . can be associated. In some cases, the bitmap format 602 also provides a format for storing data that indicates the DS level (of multiple possible DS levels) at which the memory device should switch the memory bank 615 assigned DS mode. can contain. For example, data pointing to a DS level may transfer a memory bank assigned DS mode to a first, second, or third DS level (eg, DS level 320-a, DS level 320-a, as described with reference to FIG. 3). It may indicate whether to switch to level 320-b or DS level 320-c).

In some cases, the PMD may contain a first set of values (B0-B7) each written to a particular register field (eg, one of fields 0-7). First register entry 620 (eg, PMD[0]). The memory device may be configured to identify that the value in first register entry 620 corresponds to bank mask variable 605 . The memory device may also be configured to identify that each register field (0-7) in the first register entry corresponds to a particular bank mask 605 value. For example, register field 0 contains the value of B0, register field 1 contains the value of B1, and so on. Thus, the memory device may access the PMD data containing the first register entry 620 and the value of the bank mask variable 605 for each memory bank 615 (or additionally or alternatively, the value of the second variable in the two-variable sequence). value).

The PMD may also include a second register entry 625 (eg, PMD[1]) that may include a second set of values (BG0-BG3) each written to a particular register field (eg, 0-7). . The memory device may be configured to identify that the value in second register entry 625 corresponds to bank group mask variable 610 . The memory device may also be configured to identify which register fields (0-3) in the second register entry correspond to a particular bank group mask 610 value. For example, register field 0 contains the value of BG0, register field 1 contains the value of BG1, and so on. Thus, the memory device may access the PMD containing the second register entry 625 and the value of the bank group mask variable 610 for each memory bank 615 (or additionally or alternatively, the value of the first variable in the two-variable sequence). value) can be determined.

The memory device stores a corresponding bank group mask variable 610 and a corresponding bank mask variable 605 (e.g., first and second variables) stored within the PMD (e.g., as discussed in connection with FIG. 6A). and the mapping configured between those variables and memory banks 615, each memory bank 615 may identify a low power mode (eg, PD mode or DS mode) to which it should be switched.

In some cases, the third mode register may contain a DS sequence, which may contain an indication of the DS level at which the memory device should switch DS memory banks 615 . This may be an option if the memory device supports multiple DS levels, such as DS level 320 described with reference to FIG. For example, a first DS level (eg, 320-a) may be associated with a first DS sequence (eg, 01) and a second DS level (eg, 320-b) may be associated with a second DS sequence. (eg, 10), and a third DS level may be associated with a third DS sequence (eg, 11). To identify the DS level, a third register entry 630 may contain a set of values corresponding to one of the DS sequences. Therefore, the PMD has a third register entry 630 (eg, PMD [2]). The memory device may be configured to identify values in the third register entry 630 as corresponding to different DS sequences. For example, the first value of the DS sequence may be associated with register field 0, and the second value of the DS sequence may be associated with register field 1. Accordingly, the memory device may access the PMD containing the particular DS level associated with the DS memory bank.

FIG. 6C illustrates an example bitmap value 603 stored in the mode register according to the exemplary bitmap format 602 illustrated in FIG. 6B, which may point to the exemplary power mode assignment 601 illustrated in FIG. 6A. . For example, the first register entry 620 (1, 1, 1, 1, 0, 0, 0, 0) is the value of the exemplary bank mask variables 605 (B0=1, B1=1, B2=1, B3 =1, B4=0, B5=0, B6=0, B7=0), and the second register entry 626 (1,0,1,1) corresponds to the value of the exemplary bank group mask 610 ( BG0=1, BG1=0, BG2=1, BG3=1). Therefore, the memory device accesses the mode register and identifies the stored bitmap value, thereby determining which memory bank 615 (along with which DS level to use for the memory bank 615 to which DS mode is assigned). ) to determine which low power mode to switch to.

The example presented in FIG. 6 provides an example of a mapping that groups multiple memory banks together for the purpose of assigning variable sequences. Such methods may allow fewer variables (eg, 12 mode register values) to assign low power modes to a larger number of banks (eg, 32 banks). In some cases, such as larger memory arrays, this method stores a relatively small number of variables in the mode register while still allowing flexibility in assigning different low power modes to different subsets of memory banks 615. can provide a solution for Examples presented in FIGS. 7 and 8 illustrate methods for individually assigning each memory bank 615 to a different low power mode (eg, either PD mode or DS mode) and each memory bank 615 to which DS mode is assigned. are further individually assigned to particular DS levels (eg, DS level 320). Thus, these methods may provide finer-grained control over the low-power modes assigned to each memory bank 615, but may accumulate a larger amount of variables in one or more mode registers. In some cases, the methods of FIGS. 6-8 may be combined, modified, or otherwise adapted to provide different methods of assigning different low power modes to different memory banks. obtain. Varying amounts of data (e.g., varying numbers of bits in a mode register) can be used in memory banks or other parts of a memory device, with tradeoffs between granularity and flexibility of control and associated overhead. It should be understood that it may be dedicated to indicating low power mode assignments to . It should further be appreciated that register entries as described herein may be accumulated in any number of mode registers.

7A-7C illustrate an example power mode bitmap 703 that supports bank configurable power modes according to examples as disclosed herein. The power mode bitmap 703 may include writing PMDs to one or more mode registers of the memory device, which indicate assignment of different memory banks to different low power modes. In the example of FIG. 7, the power mode bitmap 703 may contain unique values for each memory bank of the memory device. A first value (eg, 0) may be associated with a first low power mode (eg, PD mode) and a second value (eg, 1) may be associated with a second low power mode (eg, DS mode). ). Accordingly, each memory bank can be assigned to either PD mode or DS mode based on the mode register value associated with each memory bank. In some cases, power mode bitmap 703 may include DS level data for assigning one of a plurality of different DS levels to memory banks in DS mode.

FIG. 7A illustrates an example memory bank assignment 701 that associates each memory bank 715 with a low power mode. Each memory bank 715 can be associated with a bank mask address 705 and a bank group mask address 710 . For example, the first memory bank 715-a may have unique addresses corresponding to the first bank mask address 705-a (B0) and the fourth bank group mask address 710-d (BG3). That is, the first memory bank 715-a may be associated with a unique address BG3_B0. As another example, the second memory bank 715-b has a second unique address corresponding to the second bank mask address 705-e (B4) and the second bank group mask address 710-d (BG3). can have Accordingly, the second memory bank 715-b may be associated with a unique address BG3_B4. Each memory bank of a memory device may be associated with a unique address. A unique address may be used to associate each memory bank with a different mode register value used to indicate a low power mode for each memory bank.

FIG. 7B illustrates memory bank associations 702 that correlate each unique memory bank address to a specific field within a mode register that can be used to store a value that indicates a low power mode for the corresponding memory bank. For example, the first register entry 720 (PMD[0]) may contain unique register fields for each memory bank in the first memory bank group mask 710-a (BG0). Further, the first register field (0) may be associated with a unique bank address BG0_B0 such that each memory bank within the first bank group mask 710-a (BG0) is assigned to a different register field; Two register fields (1) may be associated with a unique bank address BG0_B1. In some examples, each register entry 725, 730, and 735 (PMD[1], PMD[2], and PMD[3]) contains a unique register field for each memory bank within their respective group. can contain. Accordingly, a memory device may be configured to associate different mode register locations with different memory banks.

In some cases, memory bank association 702 may include a fifth register entry 740 (PMD[4]) that may be used to store a value that indicates the DS level for memory banks assigned to DS mode. In some cases, a single DS level may be designated by a value stored in fourth register entry 740, which may be an example of the DS level discussed in connection with FIG.

FIG. 7C illustrates an example of a power mode bitmap 703 stored in a mode register corresponding to the allocation of memory banks to low power modes illustrated in FIG. 7A. For example, the first register entries 720 (eg, 0, 1, 0, 0, 1, 1, 1, 1) each correspond to a different memory bank within the first bank group mask 710-a (BG0). . The second register entries 725 (eg, 0, 1, 0, 1, 0, 0, 1, 0) each correspond to a different memory bank within the second bank group mask 710-b (BG1). A third register entry 730 and a fourth register entry 735 have values corresponding to different memory banks in the third bank group mask 710-c (BG2) and the fourth bank group mask 710-d (BG3), respectively. respectively. The memory device may be configured to associate a first mode register value (eg, 0) with a first low power mode and a second register value (eg, 1) with a second low power mode. In the illustrated example, a first register value of 0 is associated with DS mode and a second register value of 1 is associated with PD mode. In this regard, the memory device may be configured to access power mode bitmap 703 and determine the low power mode for each memory bank. In some cases, a memory device may access fifth register entry 740 to determine in which DS power mode (eg, DS level) a memory bank in DS mode should operate. For example, a first set of values (eg, 0,1) may correspond to a first DS level, a second set of values (1,0) may correspond to a second DS level, and A third set may correspond to a third DS level.

8A-8C illustrate an example power mode bitmap 803 that supports bank configurable power modes according to examples as disclosed herein. The power mode bitmap 803 may include writing PMDs to one or more mode registers of the memory device, which indicate assignment of different memory banks to different low power modes. In some cases, the power mode bitmap may also indicate different DS levels for each memory bank to which DS mode is assigned. In the example of FIG. 8, power mode bitmap 803 may include two mode register fields for each memory bank of the memory device. The values stored in the two mode register fields may uniquely point to one or more different low power modes. For example, if (i) the two fields associated with the memory bank store 00 sequences, the memory bank may be assigned PD mode, and (ii) if the two fields store 01s, the memory bank has If a DS mode of DS level 1 may be assigned and (iii) two fields store 10, then the memory bank may be assigned a DS mode of DS level 2 and (iv) two fields store 11. In that case, the memory bank may be assigned a DS mode of DS level 3. Thus, each memory bank can be individually assigned a low power mode and DS level based on two fields in the mode register associated with each memory bank.

FIG. 8A illustrates an example memory bank assignment 801 that associates each memory bank 815 with a low power mode and a DS level for DS memory banks. Each memory bank may be associated with a unique bank address as described in connection with FIG. Also, each memory bank may be associated with a DS level that may be used for memory banks assigned to DS mode. For example, first memory bank 815-a may have a first unique bank corresponding to PD mode. As another example, the second memory bank 815-b may have a second unique bank address corresponding to DS mode and DS level two.

FIG. 8B illustrates a memory bank association 802 that correlates each unique bank address to a specific low power mode field and DS level field by correlating each memory bank to two fields in the mode register. For example, a first register entry (PMD[0]) may include a first register field (eg, BG0_B0_0) and a second register field (eg, BG0_B0_1) that correlate to each memory bank. A combination of the first register field and the second register field may be used to distinguish between different low power modes. For example, two register fields can use binary variables to indicate four different low power states (eg, different power modes indicated by each unique combination of variables 00, 01, 10, 11). could be.

FIG. 8C illustrates an example of a power mode bitmap 803 stored in the mode register corresponding to the low power modes and allocation of memory banks to DS levels illustrated in FIG. 8A. For example, the first register entry (eg, 0, 0, 0, 0, 0, 0, 0, 0) corresponds to the low power mode for the memory bank (BG0_B0 memory bank) with the first value (BG0_B0_0=0). ) and a second value (BG0_B0_1=0). Accordingly, a memory device may be configured to associate a sequence of mode register fields with one of a number of low power modes that may include different DS levels for memory banks operating in DS mode.

FIG. 9 illustrates an example command mode state diagram 900 that supports bank configurable power modes according to examples as disclosed herein. The mechanism of command mode state diagram 900 may be a memory device (eg, memory device 110, memory die 160, or memory die 200 described with reference to FIGS. 1-2) or a memory device described with reference to FIGS. It may be implemented by one or more components of a memory device such as controller 155, local memory controller 165, or local memory controller 265. Command mode state diagram 900 includes idle mode 905, which may be an example of idle mode 305 described with reference to FIG. 3, and low power modes 315, 320 (eg, PD mode or DS mode) described with reference to FIG. ) may be described as one or more commands 915, 920 used to switch the memory device to and from a low power mode 910, which may be an example.

In some cases, a memory device may be configured via a power down mode (PDM) command 915 that switches one or more banks, bank groups, bank ranges, etc. to one or more low power modes. In some examples, PDM command 915 may switch a memory bank to low power mode without accessing the PMD (eg, power mode bitmap) stored in the mode register. That is, the PDM command 915 may cause one or more memory banks to be switched to a low power mode (e.g., while other memory banks may remain in whatever mode they were operating when the PDM command was received). may include information identifying the In some examples, PDM command 915 may also indicate which low power mode (eg, PD mode, DS mode, or DS level) in which memory banks are switched.

In some examples, the PDM command 915 puts a single memory bank into low power mode by specifying a memory bank identifier (eg, memory bank address) and a low power mode (eg, PD mode or DS mode). can switch. A memory device receiving this command may be configured to identify the memory bank and low power mode indicated in the command and switch the memory bank to the specified low power mode.

In some examples, PDM command 915 may switch a group of memory banks to low power mode. PDM command 915 may include a memory bank group address associated with a group of memory banks and a low power mode in the memory device. The memory device may be configured to switch memory banks associated with the memory bank group address to a specified low power mode.

In another example, PDM command 915 may switch the range of memory banks to low power mode. PDM command 915 may include a first memory bank address that specifies the first memory bank in the range, a last memory bank address that specifies the last memory bank in the range, and a low power mode. The memory device may have a range of memory banks including the memory bank associated with the first address, the memory bank associated with the last address, and any memory bank having an address between the first and last addresses. can be identified. The memory device may switch the range of memory banks to a low power mode specified by PDM command 915 .

A memory device may be configured via a PDM exit command 920 that switches one or more portions of the memory device out of low power mode 910 . For example, PDM exit command 920 may be configured to identify a memory bank to be switched to idle mode 905 . Memory banks pointed to by PDM exit command 920 operating in one or more low power modes may switch to idle mode 905 within the exit time associated with their low power mode. In some cases, the PDM exit command 920 and PDM command 915 may include a PDM command 915 (to enter low power mode) or a PDM exit command 920 (to exit low power mode). It can be implemented as a single command containing variables whose values indicate what they contain.

In some examples, the PDM exit command 920 may switch a single memory bank out of low power mode by specifying a memory bank identifier (eg, memory bank address). A memory device receiving this command may be configured to identify a memory bank and switch it to idle mode 905 or some other mode.

In some examples, the PDM exit command 920 may include a memory bank group address associated with a group of memory banks in the memory device. A memory device may be configured to switch a memory bank associated with a memory bank group address from one or more low power modes.

In another example, the PDM end command 920 may include a first memory bank address designating the first memory bank in the range and a last memory bank address designating the last memory bank in the range. The memory device may have a range of memory banks including the memory bank associated with the first address, the memory bank associated with the last address, and any memory bank having an address between the first and last addresses. can be identified. The memory device may switch memory ranges out of one or more low power modes specified by the PDM exit command 920 . In some cases, the PDM exit command 920 may be configured with variables that switch all of the memory banks out of low power mode. For example, the PDM exit command 920 may include an "all" variable to indicate that each memory bank operating in low power mode is switched to a different mode (eg, idle mode). Accordingly, one or more parameters (eg, variables) included within a command may point to an action and address (of one or more memory banks) corresponding to the command.

FIG. 10 illustrates an example power level consumption profile 1000 that supports bank configurable power modes according to examples as disclosed herein. Power level consumption profile 1000 may provide a relative estimate of current usage in a memory device based on the number of banks in PD mode and the number of banks in DS mode. Power level consumption profile 1000 provides an example for a memory device with 32 banks, but this is provided for conceptual purposes and other amounts of memory banks are possible. Power level consumption profile 1000 may be implemented by memory device 110, memory die 160, or memory die 200 described with reference to FIGS. 1-2, or memory device controller 155, local memory controller 165 described with reference to FIGS. , or one or more components of a memory device, such as local memory controller 265, may describe the relative current usage for a memory device operating in one or more low power modes as described herein.

Power level consumption profile 1000 may relate relative levels of current consumption 1005 (y-axis) to the number of memory banks operating in PD mode 1010 (x-axis). If all of the memory banks (eg, 32 memory banks) are operating in PD mode, the relative current consumption 1005 in the memory device can be classified as 100% and any memory bank is operating in PD mode. If not (eg, all memory banks are in DS mode), the relative current consumption may be 40%. In some cases, for example, different ratios of memory banks operating in PD and DS modes may be desired to balance latency (time to exit from low power mode) and power consumption. Current consumption indicator 1015 may characterize the relationship between the proportion of banks in PD and DS modes and current consumption. For example, a first index point 1020 may relate to relative current consumption 1005 for a ratio including 9 memory banks operating in PD mode and 23 memory banks operating in DS mode. Therefore, if the memory device is operating 9 memory banks in PD mode and 23 banks in DS mode, the relative current consumption may be 60%.

A memory device may be configured with power level consumption profile 1000 to determine the number of memory banks operating in each of PD and DS modes. For example, if it is determined that the memory device operates at 60% relative current usage 1005, the memory device should operate 9 banks in PD mode and 23 banks in DS mode. could be determined.

FIG. 11 shows a block diagram 1100 of a memory device 1105 supporting bank configurable power modes according to examples as disclosed herein. Memory device 1105 may be an example of aspects of a memory device as described with reference to FIGS. 1-10. Memory device 1105 may include operational mode manager 1110 , command processing component 1115 , and power mode manager 1120 . Each of these modules may communicate with each other directly or indirectly (eg, via one or more buses).

Operational mode manager 1110 may cause a memory device to operate in a first mode, the memory device including a set of memory banks. In some examples, the operational mode manager 1110 places the first memory bank in a first low power mode and the second memory bank in a second low power mode based on receiving the command and information. can work with In some examples, operating mode manager 1110 may operate a set of memory banks in a separate first mode, where the set of memory banks are within the memory device. In some examples, operation mode manager 1110 may perform access operations on the first memory bank while the second memory bank is in the second low power mode. In some examples, operation mode manager 1110 may perform one or more access operations on the first subset of memory banks after switching the first subset of memory banks out of the first low power mode. .

The command processing component 1115 outputs commands for the memory device to transition to a second mode corresponding to less power consumption by the memory device than the first mode while operating the memory device in the first mode. can receive In some examples, command processing component 1115 may receive commands at a memory device to reduce the level of power consumption for the memory device. In some examples, the command processing component 1115 reduces the power consumption level for the first memory bank to a lower power consumption level than the respective first mode while operating the set of memory banks in the respective first mode. A Signaling may be received at the memory device indicating to operate the first memory bank of the set in a corresponding second mode. In some examples, command processing component 1115 may receive a command for the memory device to transition from the first power mode to the reduced power mode. In some examples, the command processing component 1115 causes the first memory bank to enter the first low power mode while the second memory bank is in the second low power mode and the first memory bank is in the first low power mode. may receive a termination command associated with the .

In some examples, the command processing component 1115 is configured to switch the first subset of memory banks from the first low power mode to the first mode while operating the memory device in the second mode. A second command may be received. In some examples, command processing component 1115 may receive a third command for the memory device to exit the second mode while operating the memory device in the second mode.

In some examples, command processing component 1115 may access one or more mode registers based on receiving a command for the memory device to transition to the second mode. In some examples, the command processing component 1115 receives a second signal at the memory device that indicates operating a third memory bank of the set of low power modes in a third mode included in the set of low power modes. obtain. In some examples, command processing component 1115 may receive a second command for the memory device to transition to the reduced power mode after switching the first memory bank out of the first low power mode. . In some examples, the command processing component 1115 causes the reduced power mode while the first memory bank is in the first low power mode and the second memory bank is in the second low power mode. A command may be received to terminate the memory device. In some examples, the command processing component 1115 selects the reduced power mode while the first memory bank is not in the first low power mode and the second memory bank is in the second low power mode. A command may be received to terminate the memory device.

In some cases, the signal includes an indication of a low power mode selected from a set of low power modes, the selected low power mode being the second mode. In some cases, the signal includes an identifier unique to the first memory bank. In some cases, the signal includes an identifier for the group of banks that includes the first memory bank. In some cases, the signal includes one or more identifiers corresponding to ranges of bank addresses, including bank addresses for the first memory bank.

Power mode manager 1120, based on receiving a command for the memory device to transition to the second mode, converts the first subset of memory banks of the set to a first power consumption level corresponding to a first power consumption level. switching the memory device to a low power mode and switching a second subset of memory banks of the set to a second low power mode corresponding to a second power consumption level lower than the first power consumption level; You can switch between 2 modes. In some examples, the power mode manager 1120 provides information assigning a first low power mode to a first memory bank of the memory device and a second low power mode to a second memory bank of the memory device; One or more mode registers of the memory device may be written. In some examples, power mode manager 1120 maintains a second memory bank of the set in a separate first mode for the second memory bank based on receiving the signal. , a first memory bank can be switched from a first mode to a second mode individually for the first memory bank.

In some examples, the power mode manager 1120 may switch a first memory bank of the memory device to a first low power mode based on receiving the command, the first low power mode associated with a power consumption level of 1. In some examples, power mode manager 1120 may switch a second memory bank of the memory device to a second low power mode based on receiving the command, wherein the second low power mode is Associated with a second power consumption level that is lower than the one power consumption level. In some examples, power mode manager 1120 may cause the first memory bank to exit the first memory bank while maintaining the second memory bank in the second low power mode based on receiving the exit command. low power mode. In some examples, power mode manager 1120 may switch the first subset of memory banks out of the first low power mode based on receiving the second command.

In some examples, the power mode manager 1120 maintains the second subset of memory banks in the second low power mode while switching the first subset of memory banks out of the first low power mode. obtain. In some examples, the power mode manager 1120 places the second subset of memory banks into a second low power mode while performing one or more access operations on the first subset of memory banks. can be maintained. In some examples, the power mode manager 1120 removes the first subset of memory banks from the first low power mode and removes the second subset of memory banks from the first low power mode based on receiving the second command. The memory device may be switched out of the second mode by switching out of two low power modes. In some examples, power mode manager 1120 may receive an indication of a second power consumption level, which is the power consumption supported by the memory device for the second low power mode. Corresponds to the power consumption level of the set of levels.

In some examples, power mode manager 1120 directs a first low power mode assignment to a first subset of memory banks and a second low power mode assignment to a second subset of memory banks. Information may be received. In some examples, power mode manager 1120 may write an indication of the allocation to one or more mode registers. In some examples, the power mode manager 1120 activates a first low power mode for the first subset of memory banks and a second low power mode for the second subset of memory banks based on the accessing. and switching the first subset of memory banks to the first low power mode and switching the second subset of memory banks to the second low power mode is based on said identifying.

In some examples, power mode manager 1120 may write an indication of the power consumption level associated with the second low power mode to one or more mode registers. In some examples, power mode manager 1120 may read one or more mode registers based on receiving the command. In some examples, power mode manager 1120 places the first memory bank in a first low power mode and the second memory bank in a second low power mode based on reading one or more mode registers. It may be determined to operate in power mode, and the operating is based on the determination. In some examples, power mode manager 1120 may write a first set of values and a second set of values, each of a set of memory banks included within the memory device from the first set of values. and a second value from the second set of values is associated with a corresponding low power mode.

In some examples, power mode manager 1120 may write an indication of the power consumption level associated with the second low power mode. In some examples, power mode manager 1120 may write a separate indication of the first low power mode or the second low power mode for each set of memory banks included within the memory device. In some examples, the power mode manager 1120 may write a separate indication of the low power mode of the set of low power modes for each set of memory banks included in the memory device, and The set includes a first low power mode, a second low power mode having a first power consumption level, and a second low power mode having a second power consumption level.

In some examples, power mode manager 1120 may switch the third memory bank to the second mode while maintaining the first memory bank in the second mode based on receiving the second signal. Individual first to third modes for the three memory banks can be switched. In some examples, power mode manager 1120 may switch the first memory bank to the first low power mode based on receiving the second command. In some examples, the power mode manager 1120 removes the first memory bank from the first low power mode and the second memory bank based on receiving a command for the memory device to exit the reduced power mode. 2 memory banks can be switched out of the second low power mode.

In some examples, the power mode manager 1120 determines that the first memory bank is accessible before the second memory bank is accessible based on the command for the memory device to exit the reduced power mode. make it possible. In some examples, power mode manager 1120 may switch the second memory bank out of the second low power mode based on receiving a command for the memory device to exit the reduced power mode.

In some cases, the first low power mode corresponds to a faster wakeup time than the second low power mode. In some cases, the allocation indication includes one or more bitmaps associating a first subset of memory banks with a first low power mode and a second subset of memory banks with a second low power mode. include. In some cases, the second mode is a low power mode of a set of low power modes supported by the memory device for a set of memory banks, each of the set of low power modes for a set of memory banks. , corresponds to a discrete power consumption level that is lower than the power consumption level corresponding to the idle mode supported by the memory device.

FIG. 12 presents a flowchart illustrating one or more methods 1200 of supporting bank configurable power modes in accordance with aspects of the present disclosure. The operations of method 1200 may be implemented by a memory device or components thereof, as described herein. For example, the operations of method 1200 may be performed by a memory device such as described with reference to FIG. In some examples, a memory device may execute sets of instructions to control functional elements of the memory device to perform the functions described. Additionally or alternatively, the memory device may use dedicated hardware to implement aspects of the described functionality.

At 1205, the memory device may operate in a first mode, the memory device including a set of memory banks. The operations of 1205 may be performed according to the methods described herein. In some examples, the operational aspects of 1205 may be implemented by an operational mode manager such as described with reference to FIG.

At 1210, the memory device, while operating the memory device in the first mode, allows the memory device to transition to a second mode corresponding to less power consumption by the memory device than the first mode. can receive commands. The operations of 1210 may be performed according to methods described herein. In some examples, the operational aspects of 1210 may be implemented by a command processing component such as described with reference to FIG.

At 1215, the memory device configures the first subset of memory banks of the set to a first power consumption level corresponding to a first power consumption level based on receiving a command for the memory device to transition to the second mode. and a second subset of memory banks of the set to a second low power mode corresponding to a second power consumption level lower than the first power consumption level. to the second mode. The operations of 1215 may be performed according to the methods described herein. In some examples, the operational aspects of 1215 may be implemented by a power mode manager such as described with reference to FIG.

In some examples, an apparatus as described herein may perform one or more methods, such as method 1200 . The apparatus operates a memory device in a first mode, the memory device including a set of memory banks; based on receiving a command for the memory device to transition to a second mode that corresponds to power consumption by the memory device that is less than and receiving a command for the memory device to transition to the second mode. a first subset of the set of memory banks into a first low power mode corresponding to a first power consumption level, and a second subset of the set of memory banks to a lower power consumption level than the first power consumption level. A mechanism, means or instructions (e.g., instructions executable by a processor (a non-transitory computer-readable medium for storing

Some examples of the method 1200 and apparatus described herein restore a first subset of memory banks from a first low power mode to a first power mode while operating the memory device in a second mode. Operations, mechanisms for receiving a second command to switch to a mode, and switching a first subset of memory banks from a first low power mode based on receiving the second command. , means, or instructions.

Some examples of the method 1200 and apparatus described herein switch a second subset of memory banks to a second low power mode while switching the first subset of memory banks from a first low power mode. It may further include acts, mechanisms, means, or instructions for maintaining in power mode.

Some examples of the method 1200 and apparatus described herein perform one or more accesses on the first subset of memory banks after switching the first subset of memory banks from the first low power mode. for performing operations and maintaining a second subset of memory banks in a second low power mode while performing one or more access operations on the first subset of memory banks; may further include the acts, mechanisms, means, or instructions of

Some examples of methods 1200 and apparatus described herein receive a third command for the memory device to exit the second mode while operating the memory device in the second mode. and switching a first subset of memory banks from a first low power mode and a second subset of memory banks from a second low power mode based on receiving a second command. may further include acts, mechanisms, means, or instructions for switching the memory device from the second mode.

In some examples of methods 1200 and apparatus described herein, the first low power mode corresponds to a faster wakeup time than the second low power mode.

Some examples of the methods 1200 and apparatus described herein are receiving an indication of a second power consumption level, the second power consumption level for a second low power mode: It may further include acts, mechanisms, means, or instructions for accommodating power consumption levels of a set of power consumption levels supported by the memory device.

Some examples of the method 1200 and apparatus described herein involve assigning a first low power mode to a first subset of memory banks and a second low power mode to a second subset of memory banks. It may further include acts, mechanisms, means, or instructions for receiving information indicative of mode assignments and writing an indication of the assignments to one or more mode registers.

Some examples of the method 1200 and apparatus described herein include accessing one or more mode registers based on receiving a command for the memory device to transition to the second mode; identifying a first low power mode for a first subset of memory banks and a second low power mode for a second subset of memory banks based on the accessing; an act, mechanism, means for switching a first subset to a first low power mode and a second subset of memory banks to a second low power mode may be based on said identifying; or may further include instructions.

In some examples of the methods 1200 and apparatus described herein, the indication of allocation is to place a first subset of memory banks in a first low power mode and place a second subset of memory banks in a second low power mode. contains one or more bitmaps associated with the low power modes of the .

Some example methods 1200 and apparatus described herein include acts, mechanisms, means for writing an indication of a power consumption level associated with the second low power mode to one or more mode registers. , or may further include instructions.

FIG. 13 presents a flowchart illustrating one or more methods 1300 of supporting bank configurable power modes in accordance with aspects of the present disclosure. The operations of method 1300 may be implemented by a memory device or components thereof, as described herein. For example, the operations of method 1300 may be performed by a memory device such as described with reference to FIG. In some examples, a memory device may execute sets of instructions to control functional elements of the memory device to perform the functions described. Additionally or alternatively, the memory device may use dedicated hardware to implement aspects of the described functionality.

At 1305, the memory device sends information to one or more of the memory devices assigning a first low power mode to a first memory bank of the memory device and a second low power mode to a second memory bank of the memory device. mode register. The operations of 1305 may be performed according to methods described herein. In some examples, aspects of the operation of 1305 may be implemented by a power mode manager such as described with reference to FIG.

At 1310, the memory device may receive a command at the memory device to reduce a level of power consumption for the memory device. The operations of 1310 may be performed according to methods described herein. In some examples, the operational aspects of 1310 may be implemented by a command processing component such as described with reference to FIG.

At 1315, the memory device may operate the first memory bank in a first low power mode and the second memory bank in a second low power mode based on receiving the command and information. The operations of 1315 may be performed according to the methods described herein. In some examples, the operational aspects of 1315 may be implemented by an operational mode manager such as described with reference to FIG.

In some examples, an apparatus as described herein may perform one or more methods, such as method 1300 . The apparatus stores information in one or more mode registers of the memory device that assigns a first low power mode to a first memory bank of the memory device and a second low power mode to a second memory bank of the memory device. writing, receiving a command at the memory device to reduce a level of power consumption for the memory device, and operating the first memory bank in a first low power mode based on receiving the command and the information. , and a mechanism, means, or instructions (eg, a non-transitory computer-readable medium storing instructions executable by the processor) for operating the second memory bank in the second low power mode.

Some examples of the methods 1300 and apparatus described herein read one or more mode registers based on receiving a command; determining to operate the first memory bank in a first low power mode and the second memory bank in a second low power mode, wherein the operating is based on the determining. may further include acts, mechanisms, means, or instructions for

In some examples of the methods 1300 and apparatus described herein, writing information to one or more mode registers is writing a first set of values and a second set of values, and Each set of memory banks included within the memory device corresponds based on a respective combination of a first value from the first set of values and a second value from the second set of values. It may include acts, mechanisms, means, or instructions for things that may be associated with a low power mode.

In some examples of the methods 1300 and apparatus described herein, writing information to one or more mode registers is to write an indication of the power consumption level associated with the second low power mode. may include the acts, mechanisms, means, or instructions of

In some examples of the methods 1300 and apparatus described herein, writing information to one or more mode registers is performed in a first low-level mode for each set of memory banks included within the memory device. It may include operations, mechanisms, means, or instructions for writing a separate indication of the power mode or the second low power mode.

In some examples of the methods 1300 and apparatus described herein, writing information to one or more mode registers causes each set of memory banks included in the memory device to enter a low power mode. writing a separate indication of a set of low power modes, the set of low power modes comprising: a first low power mode; a second low power mode having a first power consumption level; and a second low power mode having a power consumption level of .

FIG. 14 presents a flowchart illustrating one or more methods 1400 of supporting bank configurable power modes in accordance with aspects of the present disclosure. The operations of method 1400 may be implemented by a memory device or components thereof, as described herein. For example, the operations of method 1400 may be performed by a memory device such as described with reference to FIG. In some examples, a memory device may execute sets of instructions to control functional elements of the memory device to perform the functions described. Additionally or alternatively, the memory device may use dedicated hardware to implement aspects of the described functionality.

At 1405, the memory device may operate a set of memory banks in a separate first mode, the set of memory banks within the memory device. The operations of 1405 may be performed according to methods described herein. In some examples, the operational aspects of 1405 may be implemented by an operational mode manager such as described with reference to FIG.

At 1410, the memory device operates a first memory bank of the set rather than a respective first mode for the first memory bank while operating the set of memory banks in a respective first mode. A signal may be received at the memory device indicating to operate in a second mode corresponding to a lower power consumption level. The operations of 1410 may be performed according to methods described herein. In some examples, the operational aspects of 1410 may be implemented by a command processing component such as described with reference to FIG.

At 1415, the memory device, based on receiving a signal, stores the first memory bank while maintaining the second memory bank of the set in a separate first mode for the second memory bank. A bank may be switched from a first mode to a second mode individually for the first memory bank. The operations of 1415 may be performed according to the methods described herein. In some examples, aspects of the operation of 1415 may be implemented by a power mode manager such as described with reference to FIG.

In some examples, an apparatus as described herein may perform one or more methods, such as method 1400 . The apparatus comprises operating a set of memory banks in a respective first mode, the set of memory banks being within a memory device; and operating the set of memory banks in a respective first mode. a signal indicating that the first memory bank of the set is operated in a second mode corresponding to a lower power consumption level than the respective first mode for the first memory bank. and receiving a signal from a first memory bank while maintaining a second memory bank of the set in a separate first mode for the second memory bank. a mechanism, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for switching from a separate first mode to a second mode for the first memory bank can include

In some examples of the methods 1400 and apparatus described herein, the second mode may be a low power mode of a set of low power modes supported by the memory device for a set of memory banks, and low power Each set of modes corresponds to a separate power consumption level for the set of memory banks, which may be lower than the power consumption level corresponding to the idle mode supported by the memory device, the signal indicating a low power mode. An indication of a low power mode selected from the set, the selected low power mode being the second mode.

Some examples of the method 1400 and apparatus described herein provide a second signal indicating that the third memory bank of the set should operate in a third mode included within the set of low power modes. at the memory device and receiving a second signal, while maintaining the first memory bank in the second mode, switching the third memory bank to the third memory It may further include acts, mechanisms, means, or instructions for switching from the first mode to the third mode individually for the bank.

In some examples of the methods 1400 and apparatus described herein, the signal includes an identifier unique to the first memory bank.

In some examples of the methods 1400 and apparatus described herein, the signal includes an identifier of the group of banks that includes the first memory bank.

In some examples of the methods 1400 and apparatus described herein, the signal includes one or more identifiers corresponding to ranges of bank addresses, including bank addresses for the first memory bank.

FIG. 15 shows a flowchart illustrating one or more methods 1500 of supporting bank configurable power modes in accordance with aspects of the present disclosure. The operations of method 1500 may be implemented by a memory device or components thereof, as described herein. For example, the operations of method 1500 may be performed by a memory device such as described with reference to FIG. In some examples, a memory device may execute sets of instructions to control functional elements of the memory device to perform the functions described. Additionally or alternatively, the memory device may use dedicated hardware to implement aspects of the described functionality.

At 1505, the memory device may receive a command for the memory device to transition from the first power mode to the reduced power mode. The operations of 1505 may be performed according to the methods described herein. In some examples, aspects of the operations of 1505 may be implemented by a command processing component such as described with reference to FIG.

At 1510, the memory device may switch a first memory bank of the memory device to a first low power mode based on receiving the command, wherein the first low power mode is at a first power consumption level. associated with. The operations of 1510 may be performed according to methods described herein. In some examples, the operational aspects of 1510 may be implemented by a power mode manager such as described with reference to FIG.

At 1515, the memory device may switch a second memory bank of the memory device to a second low power mode based on receiving the command, the second low power mode being at the first power consumption level. is associated with a second power consumption level that is lower than The operations of 1515 may be performed according to the methods described herein. In some examples, aspects of the operation of 1515 may be implemented by a power mode manager such as described with reference to FIG.

At 1520, the memory device performs the exit associated with the first low power mode while the first memory bank is in the first low power mode and the second memory bank is in the second low power mode. can receive commands. The operations at 1520 may be performed according to methods described herein. In some examples, the operational aspects of 1520 may be implemented by a command processing component such as described with reference to FIG.

At 1525, the memory device causes the first memory bank to exit the first low power mode while maintaining the second memory bank in the second low power mode based on receiving the exit command. can switch. 1525 operations may be performed according to the methods described herein. In some examples, aspects of the operation of 1525 may be implemented by a power mode manager such as described with reference to FIG.

At 1530, the memory device may perform an access operation on the first memory bank while the second memory bank is in the second low power mode. The operations at 1530 may be performed according to methods described herein. In some examples, the operational aspects of 1530 may be implemented by an operational mode manager such as described with reference to FIG.

In some examples, an apparatus as described herein may perform one or more methods, such as method 1500 . The apparatus receives a command for the memory device to transition from the first power mode to the reduced power mode, and based on receiving the command, converts the first memory bank of the memory device to the first power mode. switching to a low power mode, the first low power mode being associated with a first power consumption level; wherein the second low power mode is associated with a second power consumption level lower than the first power consumption level; based on receiving an exit command associated with the first low power mode while in the low power mode and the second memory bank is in the second low power mode; , switching the first memory bank out of the first low power mode while maintaining the second memory bank in the second low power mode; and switching the second memory bank into the second low power mode. may include mechanisms, means, or instructions (eg, a non-transitory computer-readable medium storing instructions executable by a processor) for performing access operations on the first memory bank while in the memory bank.

Some examples of the method 1500 and apparatus described herein provide a second memory device for transitioning a memory device to a reduced power mode after switching a first memory bank from a first low power mode. An operation, mechanism, means, or instructions may further be included for switching the first memory bank to the first low power mode based on receiving the command and receiving the second command.

Some examples of the method 1500 and apparatus described herein can be performed while a first memory bank can be in a first low power mode and a second memory bank can be in a second low power mode. the first memory bank based on receiving a command for the memory device to exit the reduced power mode; and receiving a command for the memory device to exit the reduced power mode. It may further include an operation, mechanism, means or instructions for switching from one low power mode and a second memory bank from the second low power mode.

Some examples of the method 1500 and apparatus described herein provide a second memory bank before the second memory bank can become accessible based on a command for the memory device to exit the reduced power mode. It may further include an act, mechanism, means, or instruction for making a memory bank accessible.

Some examples of the method 1500 and apparatus described herein, the first memory bank may not be in the first low power mode and the second memory bank may be in the second low power mode. a second memory bank based on receiving a command for the memory device to exit the reduced power mode in between and receiving a command for the memory device to exit the reduced power mode; from the second low power mode.

It should be noted that the methods described above illustrate possible implementations, that the acts and steps may be rearranged or otherwise modified, and that other implementations are possible. Additionally, portions from two or more of the methods may be combined.

Describe the device. The apparatus is a set of memory banks in the memory device, each memory bank of the set having an access mode, a first low power mode corresponding to less power consumption than the access mode, and a first low power mode. a second low power mode corresponding to less power consumption than the mode; and a first low power mode coupled to the set of memory banks, other memory banks of the set being in access mode; at least one memory bank of the set in one of the access mode, the first low power mode, or the second low power mode, regardless of whether it is in one of the access mode, the first low power mode, or the second low power mode. and a controller configured to cause the device to operate in selected modes, including one.

Some examples of apparatus store a first low power mode assignment to a first subset of the set of memory banks and a second low power mode assignment to a second subset of the set of memory banks. It may include one or more mode registers configured to.

Some examples include accessing one or more mode registers based on the memory device receiving a command to reduce the amount of power consumption for the memory device; Based on that, it may further include operating a first subset of the set of memory banks in a first low power mode and a second subset of the set of memory banks in a second low power mode.

In some examples, the power consumption level for the second low power mode may be selectable from among a set of power consumption levels, and the one or more mode registers are set to the selected power consumption level for the second low power mode. It may be further configured to store an indication of power consumption level.

Some examples switch a first subset of a set of memory banks out of a first low power mode based at least in part on the memory device receiving an exit command for the first low power mode, and It may further include maintaining a second subset of the set of banks in a second low power mode.

In some examples, each of the set of memory banks is accessible with a first latency when switched from a first low power mode and a second latency when switched from a second low power mode. The access is enabled with a latency of 2, and the first latency can be configured to do something shorter than the second latency.

Some examples indicate one or more of a first low power mode for a first subset of the set of memory banks and a second low power mode for a second subset of the set of memory banks. operating a first subset of the set of memory banks in a first low power mode and a second subset of the set of memory banks in a second low power mode based on the memory device receiving the command of may further include causing

Aspects described herein with respect to mode registers or associated commands (e.g., MRW commands) also apply to other types of registers or any other type of storage and associated commands (e.g., such other types of registers or commands to read or write storage).

Information and signals described herein may be represented using any of a variety of different science and technology. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may refer to voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, light fields or particles, or any thereof. can be represented by a combination of Although some figures may describe the signal(s) as a single signal, it will be appreciated by those skilled in the art that a signal may represent a bus of signals where the bus may have varying bit widths. will be done.

The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” can refer to relationships between components that support the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact or connected or coupled) if there is some conductive path between them that can support the flow of signals between the components at any time. be At any given time, the conductive paths between components in electronic communication with each other (or in conductive contact or connected or coupled) are based on the operation of the device containing the connected components. It can be an open circuit or a closed circuit. Conductive paths between connected components may be direct conductive paths between components, or conductive paths between connected components may include intervening components such as switches, transistors, or other components. It can be a conductive path. In some cases, signal flow between connected components may be temporarily interrupted using one or more intervening components, such as switches or transistors.

The term "coupled" refers to the relationship between components in which signals can be communicated between components via conductive paths, from open circuit relationships between components where signals cannot currently be communicated between components via conductive paths. Refers to the state of transition to a closed circuit relationship. When a component, such as a controller, couples other components to each other, the component initiates changes that allow signals to flow between the other components via conductive paths that previously did not allow signals to flow. .

The term "isolated" refers to a relationship between components that does not currently allow signals to flow between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. If the controller isolates two components from each other, the controller affects changes that prevent signals from flowing between components using conductive paths that previously allowed signal flow.

As used herein, the term "layer" refers to a layer or sheet of geometric structure. Each layer can have three dimensions (eg, height, width, and depth) and can cover at least a portion of the surface. For example, a layer can be a three-dimensional structure, such as a thin film, in which two dimensions are greater than the third. Layers may include various elements, components, and/or materials. In some cases, a layer may contain more than one sublayer. In some of the accompanying figures, two dimensions of the three-dimensional layer are depicted for illustration purposes.

As used herein, the term "electrode" can refer to an electrical conductor, which in some cases can be used as an electrical contact to other components of a memory cell or memory array. Electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide conductive paths between elements or components of the memory array.

Devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled through doping with various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during initial formation or growth of the substrate by ion implantation or by any other doping means.

A switching component or transistor as discussed herein may represent a field effect transistor (FET) and may include a three terminal device including a source, drain and gate. The terminals can be connected to other electronic devices through conductive materials, such as metals. The source and drain may be conductive and may comprise heavily doped, eg, degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (ie, the predominant carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (ie, the predominant carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or p-type FET, respectively, can cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage equal to or greater than the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be "off" or "deactivated" when a voltage below the threshold voltage of the transistor is applied to the gate of the transistor.

The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or that fall within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration" rather than "preferred" or "preferred over other examples." The detailed description includes specific details to provide an understanding of the described technology. These techniques may, however, be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

Although the examples herein may in some cases be described with respect to one or more types of memory devices (eg, DRAM or FeRAM memory devices), the teachings herein apply to any type of memory device. It should be understood that

In the accompanying figures, similar components or features may have the same reference labels. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between similar components. Where only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label, regardless of the second reference label. .

The various illustrative blocks and modules described in connection with this disclosure may be general purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete devices designed to perform the functions described herein. It may be implemented or performed using gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (eg, a combination DSP and microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above may be implemented using software executed by a processor, hardware, firmware, wiring, or any combination thereof. The mechanisms implementing functions may also be physically located at various locations, including being distributed such that part(s) of the functions are implemented at different physical locations. Also, as used herein, including claims, in a list of items (e.g., a list of items preceded by a phrase such as "at least one" or "one or more of"). "or" includes, for example, a list of at least one of A, B, or C to mean A or B or C or AB or AC or BC or ABC (i.e., A and B and C) point to the target list. Also, as used herein, the phrase "based on" shall not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" will be interpreted in the same manner as the phrase "based at least in part."

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and without limitation, non-transitory computer readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage, magnetic disc storage or other A magnetic storage device or any other non-transitory accessible by a general purpose or special purpose computer or processor which may be used to carry or store desired program code means in the form of instructions or data structures. It can contain a medium. Also, any connection is properly termed a computer-readable medium. For example, using coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, the Software may be transmitted from a website, server, or other remote source; Where applicable, coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CDs, laser discs, optical discs, Digital Versatile Discs (DVDs), floppy discs, and Blu-ray discs, and discs are generally While data is reproduced magnetically, a disc optically reproduces data using a laser. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Accordingly, the disclosure is not limited to the examples and designs described herein, but is accorded the broadest scope consistent with the principles and novel mechanisms disclosed herein.

CROSS REFERENCE This patent application claims priority to International Application No. PCT/US2020/044736 by Mirichigni et al. No. 16/551,581 by Mirichigni et al., entitled "BANK CONFIGURABLE POWER MODES," filed Aug. 26 , 2019, each of which assigned to the assignee of the present application and is expressly incorporated herein by reference in its entirety.

FIG. 4A illustrates an example command mode state diagram 401 that supports bank configurable power modes according to examples as disclosed herein. The mechanism of command mode state diagram 401 may be a memory device (eg, memory device 110, memory die 160, or memory die 200 described with reference to FIGS. 1-2) or a memory device described with reference to FIGS. It may be implemented by one or more components of a memory device such as device controller 155, local memory controller 165, or local memory controller 265. Command mode state diagram 40 1 is an example of an idle mode 405, which may be an example of the idle mode 305 described with reference to FIG. 3, and an example of a low power mode 320 (eg, DS mode) described with reference to FIG. One or more commands 425, 426 used to switch the memory device between possible low power modes 415 may be described. In some cases, a mode register write (MRW) command 430 may be used to write data to one or more mode registers of the memory device.

FIG. 6C illustrates an example bitmap value 603 stored in the mode register according to the exemplary bitmap format 602 illustrated in FIG. 6B, which may point to the exemplary power mode assignment 601 illustrated in FIG. 6A. . For example, the first register entry 620 (1, 1, 1, 1, 0, 0, 0, 0) is the value of the exemplary bank mask variables 605 (B0=1, B1=1, B2=1, B3 =1, B4=0, B5=0, B6=0, B7=0), the second register entry 62 5 (1,0,1,1) corresponds to the values of the exemplary bank group mask 610 (BG0=1, BG1=0, BG2=1, BG3=1). Thus, the memory device accesses the mode register to identify the stored bitmap value and thereby determine which memory bank 615 (to which DS mode is assigned along with which DS level to use). ) to determine which low power mode to switch to.

In some cases, memory bank association 702 may include a fifth register entry 740 (PMD[4]) that may be used to store a value that indicates the DS level for memory banks assigned to DS mode. In some cases, a single DS level may be designated by a value stored in fourth register entry 735 , which may be an example of the DS level discussed in connection with FIG.

Claims (35)

operating a memory device in a first mode, the memory device including a plurality of memory banks;
while operating the memory device in the first mode, issuing a command for the memory device to transition to a second mode corresponding to less power consumption by the memory device than the first mode; to receive;
corresponding a first subset of memory banks of the plurality to a first power consumption level based at least in part on receiving the command for the memory device to transition to the second mode; switching a first low power mode and a second subset of memory banks of the plurality to a second low power mode corresponding to a second power consumption level lower than the first power consumption level; thereby switching the memory device to the second mode. receiving a second command to switch the first subset of memory banks from the first low power mode to the first mode while operating the memory device in the second mode; and
2. The method of claim 1, further comprising switching the first subset of memory banks out of the first low power mode based at least in part on receiving the second command. 3. Further comprising maintaining said second subset of memory banks in said second low power mode while switching said first subset of memory banks from said first low power mode. The method described in . performing one or more access operations on the first subset of memory banks after switching the first subset of memory banks from the first low power mode;
The claim further comprising maintaining said second subset of memory banks in said second low power mode while performing said one or more access operations on said first subset of memory banks. Item 2. The method according to item 2. receiving a third command for the memory device to exit the second mode while operating the memory device in the second mode;
switching the first subset of memory banks from the first low power mode and switching the second subset of memory banks to the second low power mode based at least in part on receiving the second command; 3. The method of claim 2, further comprising switching the memory device out of the second mode by switching out of power mode. 2. The method of claim 1, wherein the first low power mode corresponds to a faster wakeup time than the second low power mode. receiving an indication of the second power consumption level, the second power consumption level being among a plurality of power consumption levels supported by the memory device for the second low power mode; 2. The method of claim 1, further comprising corresponding to one. receiving information indicative of the first low power mode assignment to the first subset of memory banks and the second low power mode assignment to the second subset of memory banks;
2. The method of claim 1, further comprising writing the allocation index to one or more registers. accessing the one or more registers based at least in part on receiving the command for the memory device to transition to the second mode;
identifying the first low power mode for the first subset of memory banks and the second low power mode for the second subset of memory banks based at least in part on the accessing; wherein said switching said first subset of memory banks to said first low power mode and said second subset of memory banks to said second low power mode comprises said identifying 9. The method of claim 8, further comprising based at least in part on: The indication of the allocation is one or more bitmaps associating the first subset of memory banks with the first low power mode and the second subset of memory banks with the second low power mode. 9. The method of claim 8, comprising: the information further indicates a power consumption level associated with the second low power mode;
11. The method of claim 10, further comprising writing an indication of a power consumption level associated with said second low power mode to said one or more registers. Writing information to one or more registers of the memory device that assigns a first low power mode to a first memory bank of the memory device and a second low power mode to a second memory bank of the memory device. When,
receiving a command at the memory device to reduce a level of power consumption for the memory device;
operating the first memory bank in the first low power mode and the second memory bank in the second low power mode based at least in part on receiving the command and the information; a method comprising causing reading the one or more registers based at least in part on receiving the command;
operating the first memory bank in the first low power mode and operating the second memory bank in the second low power mode based at least in part on reading the one or more registers; 13. The method of claim 12, further comprising determining to cause, wherein said acting is based at least in part on said determining. Writing said information to said one or more registers comprises:
writing a first set of values and a second set of values, wherein each of a plurality of memory banks included within said memory device stores a first value and a value from said first set of values; 13. The method of claim 12, comprising associating with a corresponding low power mode based, at least in part, on the respective combination with a second value from the second set of . Writing said information to said one or more registers comprises:
13. The method of claim 12, comprising writing an indication of a power consumption level associated with the second low power mode. Writing said information to said one or more registers comprises:
13. The method of claim 12, comprising writing a separate indication of the first low power mode or the second low power mode for each of a plurality of memory banks included within the memory device. Writing said information to said one or more registers comprises:
writing a separate indication of one of a plurality of low power modes to each of a plurality of memory banks included within the memory device, wherein the plurality of low power modes are selected from the first low power mode; 13. The method of claim 12, comprising including a power mode, the second low power mode having a first power consumption level, and the second low power mode having a second power consumption level. . operating a plurality of memory banks in separate first modes, the plurality of memory banks being within a memory device;
while operating the plurality of memory banks in the respective first mode, operating the plurality of memory banks in a second mode corresponding to a lower power consumption level than the respective first mode for the first memory bank; receiving a signal at the memory device indicating to operate the first memory bank in
based at least in part on receiving said signal, while maintaining a second memory bank of said plurality in a separate first mode for said second memory bank; switching a memory bank from said separate first mode to said second mode for said first memory bank. The second mode is one of a plurality of low power modes supported by the memory device for the plurality of memory banks, each of the plurality of low power modes for the plurality of memory banks. , corresponding to a discrete power consumption level lower than the power consumption level corresponding to idle mode supported by said memory device;
said signal includes an indication of a low power mode selected from said plurality of low power modes, said selected low power mode being said second mode;
19. The method of claim 18. receiving a second signal at the memory device indicating to operate a third memory bank of the plurality in a third mode included within the plurality of low power modes;
switching the third memory bank to the third memory bank while maintaining the first memory bank in the second mode based at least in part on receiving the second signal; 20. The method of claim 19, further comprising switching from a respective first mode to the third mode for. 19. The method of claim 18, wherein said signal includes an identifier unique to said first memory bank. 19. The method of claim 18, wherein said signal includes an identifier of a group of banks containing said first memory bank. 19. The method of claim 18, wherein said signal includes one or more identifiers corresponding to a range of bank addresses including bank addresses for said first memory bank. receiving a command for the memory device to transition from the first power mode to a reduced power mode;
switching a first memory bank of the memory device to a first low power mode based at least in part on receiving the command, the first low power mode having a first power consumption; being associated with a level;
switching a second memory bank of the memory device to a second low power mode based at least in part on receiving the command, wherein the second low power mode is equivalent to the first being associated with a second power consumption level that is lower than the power consumption level;
issuing an exit command associated with the first low power mode while the first memory bank is in the first low power mode and the second memory bank is in the second low power mode; to receive;
switching the first memory bank to the first low power mode while maintaining the second memory bank in the second low power mode based at least in part on receiving the termination command; switching out of the mode; and
A method comprising performing an access operation on said first memory bank while said second memory bank is in said second low power mode. receiving a second command for the memory device to transition to the reduced power mode after switching the first memory bank from the first low power mode;
25. The method of claim 24, further comprising switching said first memory bank to said first low power mode based at least in part on receiving said second command. for the memory device to exit the reduced power mode while the first memory bank is in the first low power mode and the second memory bank is in the second low power mode; receiving a command for
at least partially based on receiving the command for the memory device to exit the reduced power mode, moving the first memory bank out of the first low power mode and into the second 26. The method of claim 25, further comprising switching memory banks out of the second low power mode. Based at least in part on the command for the memory device to exit the reduced power mode, the first memory bank becomes accessible before the second memory bank becomes accessible. 27. The method of claim 26. for the memory device to exit the reduced power mode while the first memory bank is not in the first low power mode and the second memory bank is in the second low power mode; receiving a command for
further comprising switching the second memory bank out of the second low power mode based at least in part on receiving the command for the memory device to exit the reduced power mode; 25. The method of claim 24. A plurality of memory banks in a memory device, each memory bank in the plurality having an access mode, a first low power mode corresponding to less power consumption than the access mode, and the first low power mode. a second low power mode corresponding to less power consumption than the power mode;
the plurality of memory banks coupled to the plurality of memory banks, regardless of whether other memory banks in the plurality are in the access mode, the first low power mode, or the second low power mode; in a selected mode comprising one of said access mode, said first low power mode, or said second low power mode. an apparatus comprising a configured controller; configured to store the first low power mode assignments to a first subset of the plurality of memory banks and the second low power mode assignments to a second subset of the plurality of memory banks; 30. The apparatus of claim 29, further comprising one or more registered registers. accessing the one or more registers based at least in part on the memory device receiving a command to reduce an amount of power consumption to the memory device;
operating the first subset of the plurality of memory banks in the first low power mode and the second subset of the plurality of memory banks based at least in part on accessing the one or more registers; 31. The device of claim 30, wherein the controller is further configured to cause the device to operate a subset in the second low power mode. a power consumption level for the second low power mode is selectable from among a plurality of power consumption levels;
the one or more registers further configured to store an indication of a selected power consumption level for the second low power mode;
31. Apparatus according to claim 30. switching a first subset of the plurality of memory banks out of the first low power mode based at least in part on the memory device receiving an exit command to the first low power mode; 30. The device of Claim 29, wherein the controller is further configured to cause the device to maintain a second subset of memory banks in the second low power mode. Each of the plurality of memory banks becomes accessible with a first latency when switched from the first low power mode, and has a second latency when switched from the second low power mode. 30. The apparatus of claim 29, wherein the first latency is shorter than the second latency. one or more commands to the memory device indicating the first low power mode for a first subset of the plurality of memory banks and the second low power mode for a second subset of the plurality of memory banks; the first subset of the plurality of memory banks in the first low power mode and the second subset of the plurality of memory banks in the second 30. The device of Claim 29, wherein the controller is further configured to cause the device to operate in a low power mode.

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