JP2009211550A - Nonvolatile memory control device, image processor equipped with the same, and nonvolatile memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To considerably shorten an evaluation time for a nonvolatile semiconductor memory such as a NAND flash memory. <P>SOLUTION: A logical block address: 7FF(H) is set to a register 403, and a maximum physical block address assignment command AA(H) is written in a "command" to rewrite data in the register 403 into 7FF(H). At this time, an address change control part 401 controls to apply 7FF(H) in the register 403 to the maximum value of a table NO. (the maximum table NO.), i.e., to change the maximum value of the table NO. to "OxO7ff" i.e., to set the maximum value of the table NO. to "OxO7ff" and to make an address change of only the table NO. below "OxO7ff" (the logical block address). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory control device that can reduce the time required for writing evaluation of a nonvolatile memory such as a NAND flash memory, an image processing device including the nonvolatile memory control device, and a nonvolatile memory control method.

  Conventionally, a NAND flash memory is known as a nonvolatile memory that can hold data even when power is not supplied. This NAND flash memory can electrically write and erase data, and the writing and erasing are performed by an FN (Fowler-Nordheim) tunnel phenomenon.

When data is written to the NAND flash memory, in order to generate this tunnel phenomenon, a high voltage of about 20 V is applied to the IC (Integrated Circuit) of the flash memory. ₂ : Silicon dioxide) deteriorates due to high voltage. Therefore, when data writing to a specific memory block is repeated a plurality of times, generally about 100,000 times, a so-called defective block is generated in which data cannot be recorded due to deterioration of the oxide film.

  In order to prevent data writing / erasing from being concentrated only on a specific memory block and the memory block becoming a defective block earlier than other memory blocks, the NAND flash memory includes a memory block for each memory block. A wear leveling method, which is a data writing method for averaging the number of data writes, is used.

As an example of this wear leveling method, a data writing method is known in which writing to a memory block that has been written a predetermined number of times or more is performed on an unused memory block.
That is, the upper limit of the virtually used address (logical address) is set smaller than the valid address (physical address) on the NAND flash memory, and a physical address that cannot be used is provided in advance. When writing to the NAND flash memory and a specific physical address with a large number of writes occurs, the logical address corresponding to this physical address is changed to correspond to an unused physical address, that is, an unused physical address Is used as an alternative area for a physical address with a large number of writes.

As another wear leveling method, for example, a writing method is known in which the number of times of writing to each memory block is counted and memory access control is performed so as to write to a block with a small number of counts.
That is, the number of times of writing data to each physical address is counted, and when writing data to a block corresponding to a certain physical address, if there is another physical address with a smaller number of writes compared to this physical address, The correspondence relationship between the logical address and the physical address is changed so that data is written to a block corresponding to another physical address.
As described above, conventionally, by performing memory access control so as to average the number of writes with respect to the physical address, the write is not concentrated on a specific physical address and the life of the NAND flash memory is extended. Yes.

  The number of times of writing until the memory block of the NAND flash memory becomes a defective block (number of times that data can be written) is data necessary for mounting the NAND flash memory on a product such as an image processing apparatus. Pre-evaluation is performed.

  However, the capacity of the NAND flash memory is 1 (GB (gigabytes)), the interface speed is (10 MB (megabytes) / second), wear leveling is ideally performed, and the capacity of the NAND flash memory x 100,000 writes Assuming that it can be performed, this evaluation time is (1000 (MB) × 10 (10,000 times)) / 10 (MB / second) = 10 million seconds = about 2777 hours = about 115 days, which requires a long time. There is. Further, when the number of evaluation samples is increased, a longer period is required.

In order to shorten the evaluation time, it is considered that shortening the data writing time is one of effective means.
For example, a nonvolatile semiconductor memory is known in which the number of verifications (reading) required after data writing is reduced to shorten the writing time (see Patent Document 1).
Further, when testing a plurality of nonvolatile semiconductor memories at the same time, an operation for verifying the result of the write operation is not required, the entire write time is shortened, and as a result, the test time is shortened, and the test method thereof Is also known (see Patent Document 2).

However, in the nonvolatile semiconductor memory and the like described in each of the above patent documents, although there is a possibility that the evaluation time is somewhat shortened, it is difficult to significantly reduce the evaluation time.
In order to shorten the evaluation time, it is possible to improve the writing method to the physical address, that is, the wear leveling method, but the wear leveling method is different for each company, and the contents are not disclosed to the user. Therefore, it is difficult for the user to control the address and shorten the evaluation time.
Japanese Patent Laid-Open No. 10-55691 JP 2007-250187 A

  The present invention has been made to solve the above-described conventional problems, and an object thereof is to greatly shorten the evaluation time of a nonvolatile semiconductor memory such as a NAND flash memory.

The present invention relates to a non-volatile memory control device including a read / write control unit that performs read / write processing of data to a predetermined physical block address of a non-volatile memory based on a logical block address from an external device, and the logical block address Storage means for storing correspondence information between the physical block address and the physical block address, address conversion means for converting a logical block address from an external device into a physical block address based on the correspondence information of the storage means, and input from the external device Storage means for storing the upper limit physical block address, and address conversion control means for controlling the address conversion means to perform address conversion with the upper limit physical block address stored in the storage means as an upper limit. It is characterized by.
The present invention also provides a nonvolatile memory control device including a read / write control unit that performs read / write processing of data to a predetermined physical block address of a nonvolatile memory based on a logical block address from an external device, Storage means for storing correspondence information between block addresses and physical block addresses; storage means for storing a plurality of physical block addresses in advance; and one of a plurality of physical block addresses stored in the storage means. A selection means for selecting; and an address translation control means for controlling the address translation means to perform address translation with the physical block address selected by the selection means as an upper limit.
The present invention also relates to a non-volatile memory control method for performing data read / write processing on a predetermined physical block address of a non-volatile memory based on a logical block address from an external device, and an upper limit physical input from the external device. A step of storing a block address; a step of receiving a logical block address corresponding to a physical block address for performing a read / write process from the external device; and the reception using the upper limit physical block address stored in the storage means as an upper limit. And a step of converting the logical block address into a physical block address.
The present invention also relates to a nonvolatile memory control method for performing read / write processing of data to a predetermined physical block address of a nonvolatile memory based on a logical block address from an external device, the physical block address performing the read / write processing Receiving a logical block address corresponding to the external device from the external device, a selection step of selecting one of a plurality of physical block addresses stored in advance in the storage means, and a physical block address stored in the storage means And a step of converting the received logical block address into a physical block address.

  According to the present invention, it is possible to greatly reduce the evaluation time of a nonvolatile semiconductor memory such as a NAND flash memory, and to reduce labor and power consumption for evaluation.

Hereinafter, an SSD (Solid State Disc) according to an embodiment of a nonvolatile memory control device of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram showing a configuration of a system including an SSD and a host device.

The host apparatus 101 and the SSD 100 are connected to each other by an ATA (AT Attachment) cable 110.
The SSD 100 includes an ATA slave interface unit 106 that connects the ATA cable 110, an ATA slave interface control unit 107 that controls the ATA slave interface unit 106 to transmit and receive data to and from the host device 101, and data received from the host device 101. NAND flash memory 109 which is a non-volatile memory for storing data, and a read / write control unit 108 which performs read / write control of the NAND flash memory 109.
The read / write control unit 108 performs a wear leveling process, which will be described later, in order to average the number of writes to each physical block address of the NAND flash memory 109.

The host apparatus 101 is an electronic apparatus such as an image forming apparatus or a personal computer that is an external apparatus of the SSD 100, and is a main control section 102 that controls the entire system, and a data that is a storage section that accumulates data transmitted to and received from the SSD 100. The storage unit 103, the ATA master interface unit 104 that connects the ATA cable 110, and the ATA master interface control unit 105 that controls the ATA master interface unit 104 and transmits / receives data to / from the SSD 100.
The main control unit 102 includes a microcomputer including a CPU (Central Processing Unit), a RAM (Random Access Memory), and a ROM (Read Only Memory), and requests for storing data (write commands) to the SSD 100 and the storage thereof. Data to be transmitted, a predetermined data read request (read command), and reception of data transmitted in response to the read request.

In this system, data transfer (writing) from the host device 101 to the SSD 100 is performed by the host device 101 writing an ATA command to an I / O register in the read / write control unit 108 of the SSD 100.
FIG. 2 is a diagram showing a list of I / O registers corresponding to the state of the signal lines of the ATA cable 110.
The I / O registers are classified into a command block register and a control block register as shown in the figure, and depending on the state of each signal line (CS0-, CS1-, DA2, DA1, DA0) of the ATA cable 110, Data is transferred when the host apparatus 101 writes an ATA command to either the command block register or the control block register.

  When writing the ATA command to the I / O register, necessary parameters are designated in the I / O register. That is, for example, when an ATA command (write command) is issued, a logical block address (LBA) to which data is written and an amount of data to be written are set (stored) in a register, and then the ATA command is written.

FIG. 3 is a diagram showing a list of registers (I / O registers) for setting parameters for the host device 101 to write data to the SSD 100.
Here, the logical block address set in the register is an address corresponding to the physical block address determined for each memory block of the NAND flash memory 109, and the host device 101 sets the logical block address and registers the ATA command. Thus, data is written to the memory block having the physical block address corresponding to the set logical block address.

The logical block address is 28-bit data, and one sector (512 bytes) on the NAND flash memory 109 corresponds to each address.
Figure 3 shows the logical block address values of 0 to 7 bits, 8 to 15 bits, 16 to 23 bits, and 24 to 27 bits, Sector Number (sector number register), Cylinder Low (cylinder low register), and Cylinder High. (Cylinder high register) and Device / Head (device / head register).
For example, when the logical block address: 7FF (H) is set in the register, “0xff” is set in the sector number register, “0x07” is set in the cylinder low register, “0x00” is set in the cylinder high register, and the device / head register is set. “0x0” is set.

  The amount of data that the host device 101 writes to the NAND flash memory 109 is set in the Sector Count (sector count register). That is, when storing the data amount of 1 to 255 sectors, the number of sectors is set in the sector count register, and when storing the data amount of 256 sectors, 0 is exceptionally set in the sector count register. .

As described above, in the SSD 100, when the logical block address for writing data and the amount of data to be written are set in the register and the ATA command is written in the register, the read / write control unit 108 shown in FIG. Data is written to 109.
At this time, the read / write control unit 108 writes data by a wear leveling method to be described later in order to average the number of times of writing to a specific physical block address.

FIG. 4 is a functional block diagram of a part of the read / write control unit 108 that performs this wear leveling process.
The functional block of the part performing the wear leveling processing in the read / write control unit 108 is stored in the conversion table 402 which is storage means for storing correspondence information between the logical block address and the physical block address, and stored in this conversion table 402. The address conversion control unit 401 converts a logical block address received from the host device 101 into a physical block address based on the correspondence information, and a register 403 which is a storage unit for various data.

FIG. 5 is a diagram showing data stored in the conversion table 402.
In the conversion table 402, table NO. And logical block addresses have a one-to-one correspondence. A physical block address and the number of times of writing with respect to the physical block address are recorded for each.
In addition, one table NO. Is set as an alternative physical block address table to be described later, and is used as an alternative area of a physical block address corresponding to a logical block address input from the host apparatus 101 when performing wear leveling to be described later (for example, (b Table No. “0x0f01”).

When the read / write control unit 108 writes to a predetermined physical block address, the write count corresponding to the physical block address in the table is incremented and stored.
Note that the address conversion control unit 401 reads data from the conversion table 402 and updates data.

FIG. 6 is a flowchart of wear leveling processing performed when the address translation control unit 401 writes data to the NAND flash memory 109.
First, the address conversion control unit 401 stores a table No. corresponding to the logical block address input from the host device 101. (“LB_N”), for example, refer to the table information “0x0000” shown in FIG. 5A (S101), and the table No. corresponding to the logical block address. Is read (S102).
Next, the read write count is compared with the minimum write count (MN_NUM) in the conversion table 402, and it is determined whether or not the difference is equal to or greater than a preset threshold value “0x7f” (S103).

When the difference is “0x7f” or more (S103, YES), the table No. corresponding to the logical block address is stored. The information stored in the table is temporarily stored in a buffer (BUF1) (not shown) provided in the register 403 (S104).
Subsequently, the alternative physical block address table NO. Referring to the table information of (SUB_N) (S105), the table NO. The physical block address in the table of the alternative physical block address NO. (S106), the table No. corresponding to the logical block address is changed. The number of rewrites of the physical block address in the table of the alternative physical block address NO. The value is changed to a value obtained by adding 1 to the number of writes in the table (S107).

Next, the address translation control unit 401 reads the alternative physical block address table NO. The table No. corresponding to the changed logical block address is stored in the physical block address in the table. The physical block address in the table is output (S108), and the alternative physical block address table NO. Table information corresponding to the logical block address in which the physical block address and the write count are stored in BUF1. The information is changed to the information in the table before the change of (LB_N) (S109).
After completing the above processing, the alternative physical block address table NO. Table No. storing the physical block address with the smallest number of writes. And the process ends (substitute physical block address update process) (S111).

  On the other hand, when the difference is less than “0x7f” (S103, NO), the table NO. The physical block address in the table is output as it is (S110), and the alternative physical block address table NO. Table No. storing the physical block address with the smallest number of writes. (S111).

FIG. 7 is a flowchart showing a subroutine of the alternative physical block address update process in step S111 shown in FIG.
First, a predetermined value “0xfffff” is set to the minimum number of times of writing (MN_NUM) in the conversion table 402, and the table NO. “TN” is set to “0x0000” (S201). Subsequently, the table NO. The value of the write count (R_NUM) stored in the table is read (S202). The number of writes stored in the table is compared with the minimum number of writes in the conversion table 402 (S203).
The minimum number of times of writing in the conversion table 402 is the table No. to be referenced. Is greater than the number of writes stored in the table (S203, YES), the alternative physical block address table NO. Table No. that refers to the value of (S204), the table No. to be referred to is changed. The write count value stored in the table is changed to the minimum write count value in the conversion table 402 (S205).
The table No. referred to by the minimum number of writes in the conversion table 402. Is smaller than the number of writes stored in the table (S203, NO), the alternative physical block address table NO. And the table No. to be referred to. The value of the number of times of writing stored in the table is not changed, and the process proceeds to the next step.

Next, the table NO. And the table No. stored in the conversion table 402. Is compared with the maximum value (MX_TBL_NUM) of the table No. (S206). Is the above table NO. Is smaller than the maximum value (S206, YES), the referenced table No. 1 is added to the value of (S207), and the process returns to step S202.
Reference table No. Is the above table NO. Is not smaller than the maximum value, that is, the table No. to be referred to is. And the above table NO. When the maximum value is the same value (S206, NO), the process is terminated.

  With the above processing, the alternative physical block address table NO. Table No. including the physical block address with the smallest number of writes in the conversion table 402. In the wear leveling process shown in FIG. 6, the write process can be performed to the physical block address with the smallest number of writes under a predetermined condition.

FIG. 8 is a diagram illustrating data stored in the conversion table 402 after the processing described with reference to FIGS. 6 and 7 is performed.
6 and FIG. 7, the table No. 1 shown in FIG. Table information in “0x0000” (physical block address and number of writes) ((a) in FIG. 5) is exchanged with table information in (0x0f02) ((b) in FIG. 5). Table NO. The number of writes in “0x0000” is incremented by 1 ((c) and (d) in the figure).

  As described above, in the SSD 100 including the read / write control unit 108, when the number of writes to a certain physical block address increases by a predetermined value or more compared to another physical block address, the physical block address that has increased the number of writes. Is changed so as to correspond to a physical block address with a small number of times of writing, thereby averaging the number of times of writing to a specific physical block address.

Next, the read / write control unit 108 will be described.
In the read / write control unit 108, when performing write evaluation to the NAND flash memory 109 of the SSD 100 while performing the wear leveling described above, the read / write control unit 108 determines whether data is to be written by an ATA command from the host device 101 to the SSD 100. Table NO. An upper limit of (logical block address) is set, and as a result, the physical block address corresponding to the logical block address is limited, and the write evaluation time is shortened.
That is, all the table Nos. Of the conversion table 402 shown in FIG. In the state where the number of times of writing is 0 and the logical block address matches the physical block address (hereinafter referred to as “initial state”), the upper limit physical block address is set in the register 403 shown in FIG. The command “AA (H)” that has not been written is written to “command” of the command block register shown in FIG. 2, so that the set upper limit physical block address becomes the upper limit of the physical block address to which data is to be written. In other words, in such an initial state, since the logical block address and the physical block address match, the wear leveling process is performed when the access is performed with the same value as the set upper limit physical address as the upper limit of the logical block address. However, the accessed physical address is in the range of 0 to the upper limit physical address.

For example, by setting the upper limit physical block address: 7FF (H) in the register 403 shown in FIG. 4 and writing the address upper limit setting command AA (H) to “command”, the data in the register 403 becomes 7FF (H ) Is rewritten (updated).
At this time, the address translation control unit 401 corresponding to the address translation control means of the present invention sets the table NO. Applied to the maximum value of the table NO. The maximum value of “0x07ff” is assumed, and the table NO. Control is performed so as to perform address conversion only on (logical block address). Therefore, writing is not performed to a physical block address corresponding to a logical block address larger than “0x07ff”.

When the maximum physical block address is 7FF (H), since one memory block is 512 bytes (bytes), the space (capacity) of the physical block address of the limited NAND flash memory is 7FF (H) × 512 = About 1MB.
Since the write evaluation time when the space of the physical block address is limited to 1 MB can be theoretically written by 1 MB × 100,000 times by the wear leveling process of the read / write control unit 401, the ATA master If the transfer rate between the interface control unit 105 and the ATA slave interface control unit 107 is 10 MB / second, (1 (MB) × 10 (10,000 times)) / 10 (MB / second) = 10,000 seconds = about 2.777. The time is shortened to 1/1000 of the evaluation time compared to the case of writing and evaluating the 1 GB physical block address space.

Thus, by setting the upper limit of the physical block address, the evaluation time can be shortened without changing the function of the read / write control unit 108 that performs processing such as wear leveling. As a result, the write evaluation It is possible to suppress power consumption necessary for the operation.
In addition, since the address conversion control unit 401 of the read / write control unit 108 automatically sets the upper limit of the physical block address, the evaluation time can be easily shortened simply by operating the host device 101 by the user.
Even if the upper limit is set for the physical block address as described above and only the physical block address within the range is evaluated, it is considered that the device characteristics do not substantially change depending on the address. The impact on

Next, another embodiment of the read / write control unit 108 will be described.
FIG. 9 is a functional block diagram of a part that performs wear leveling processing in the read / write control unit 108 according to another embodiment.
The functional block of the part that performs wear leveling processing in the read / write control unit 108 includes a conversion table 902 that stores data in which a logical block address and a physical block address are associated, and the conversion table 902. An address conversion control unit 901 that converts a logical block address received from the host apparatus 101 into a physical block address, and an actual table No. in the conversion table 902. The actual maximum value 904 that is the maximum value of the table No. or the table NO. And a selection unit 903 that selects the evaluation maximum value 905.
The actual maximum value 904 and the evaluation maximum value 905 are stored in a storage unit (not shown).

The selection unit 903 designates which of the actual maximum value 904 and the evaluation maximum value 905 is to be selected by a switch 906 that is an operation unit mounted on the SSD 100. That is, the switch 906 is in an off state (the state illustrated in FIG. ) Specifies that the actual maximum value 904 is selected, and in the ON state, the evaluation maximum value is selected.
Therefore, for example, when the evaluation maximum value 905 is set to 7 ff (H), when the selection unit 903 selects the evaluation maximum value 905, the address conversion control unit 901 stores the evaluation maximum value 905 in the table NO. As described above, the physical block address space can be set to about 1 MB for writing evaluation, and the evaluation time can be shortened.
Further, compared to the read / write control unit 108 according to the above embodiment, it is necessary to provide a switch mechanism outside, but no special software is required, and the upper limit of the physical block address can be set easily.

  If the switch 906 can be switched to a plurality of states, a physical block address corresponding to each state is stored in a storage unit (not shown), so that the switch 906 causes each selection unit 903 to store each physical block address. One of the block addresses can be selected, and the address conversion control unit 901 can control to perform address conversion with the physical block address as an upper limit.

Next, an image processing apparatus equipped with an SSD as the nonvolatile memory control apparatus will be described.
FIG. 10 is a schematic side view showing the configuration of a digital copying machine which is an embodiment of an image processing apparatus equipped with an SSD.
The digital copying machine 300 has a scanner unit 301 for reading an image of a document, a laser recording unit 302 that forms an image on a sheet based on the read image, and a sheet (output sheet) on which the image is formed. This includes a post-processing unit 303 that performs stapling and punching.

The scanner unit 301 includes a platen 304 made of a transparent glass body, a RADF (Reversing Auto Document Feeder) 305 for feeding a document on the platen 304, and a document on the platen 304. The scanner unit 306 reads the image of the sent document.
The RADF 305 reverses the one-sided document feed path from the document tray (not shown) to the paper discharge tray (not shown) through the document table 304 and the front and back surfaces of the document read by the scanner unit 306 on one side. A double-sided document feeding path for feeding again to the document table 304 is provided.
The scanner unit 306 irradiates the original fed from the RADF 305 with a semiconductor laser, and couples the reflected light of the original to the light receiving surface of the photoelectric conversion element with a lens, a mirror, or the like. The photoelectric conversion element converts the reflected light on the image surface of the document into an electrical signal.

The laser recording unit 302 includes a sheet conveying unit 307 that conveys a sheet, a laser writing unit 308 that forms an image of image data read by the scanner unit 306 on a photosensitive member, and an electrophotographic process unit (which forms an image on a sheet). An image forming unit) 309.
The paper transport unit 307 passes the paper that has passed through a fixing roller (not shown) in a main transport path for transporting paper from a paper feed tray (not shown) to the electrophotographic process unit 309 and a double-sided transfer mode in which images are formed on both sides of the paper. A double conveyance path for inverting the front and back surfaces and conveying the image to the electrophotographic process unit 309 again is provided.
The laser writing unit 308 includes a semiconductor laser that irradiates a laser beam based on the image data read by the scanner unit 306, and the photosensitive drum of the electrophotographic process unit 309 passes the light irradiated from the semiconductor laser through a mirror or a lens. The light distribution on the surface. As a result, an electrostatic latent image is formed on the surface of the photosensitive drum of the electrophotographic process unit 309, and toner is supplied from the developing device to form a toner image.
The toner image is transferred onto a sheet conveyed from the sheet conveying unit 307, and then heated and pressurized by a fixing roller, whereby the toner is melted and fixed on the surface of the sheet.

FIG. 11 is a block diagram of the control unit of the digital copying machine 300.
The control unit includes an image processing board 201 that performs various types of image processing on image data.
The image processing board 201 is a board arranged for each unit, that is, a CCD (Charge Coupled Device) board 210 on which photoelectric conversion elements are mounted together with peripheral components, and an LCD (Liquid Crystal) provided on the upper surface of the digital copying machine 300. Display) 223 and an operation panel board 228 for controlling an operation panel 225 provided with operation keys 224, a process unit 215, a reading scanner unit 216, and a machine control board 231 for controlling a duplex unit 217 are controlled.

  The image processing board 201 includes a CPU (Central Processing Unit) 202 that controls the boards 210, 228, and 231; a RAM (Random Access Memory) 203 that is a work area of the CPU 202; and a scanner unit 306 illustrated in FIG. An image processing unit 204 that processes the read image; a memory 206 that stores the image processed by the image processing unit; an image storage control unit 205 that stores the image in the memory 206 or reads the image from the memory 206; A laser control unit 207 that controls a laser writing unit 209 that writes an image processed by the unit 204 to the photosensitive member.

  The CCD board 212 includes a CCD 213 that reads an image of a document conveyed by the RADF 305, a CCD control unit 212 that controls the CCD 213, an analog circuit 214 that performs gain adjustment on an output signal of the read image data, and an analog signal that is converted into a digital signal. An A / D (analog / digital) converter 211 for converting the signal into a signal.

The operation panel board 228 includes a CPU 226 that transmits / receives control data to / from the CPU 202 of the image processing board 201 to control the operation panel 224, and a RAM 227 that is a work area.
The machine control board 231 includes a CPU 230 that drives and controls the machine of the digital copying machine 300, that is, the process unit 215, the reading scanner unit 216, the duplex unit 217, the post-processing unit 303, the RADF 305, and the paper transport unit 307. It has a certain RAM 229 and exchanges control data with the CPU 202 of the image processing board 201.

When copying in the digital copying machine 300, first, the CCD 213 sequentially reads the image of the document fed to the document table 304 shown in FIG. 10 by the RADF 305, and then the output signal of the read image data is an analog circuit. In 214, gain adjustment is performed, and the A / D converter 211 sends the image data to the image processing board 201 as 8-bit image data.
Subsequently, the image data is subjected to predetermined image processing in the image processing unit 204, and then stored in the memory 206 once by the image storage control unit 205, and then transferred (stored) to an SSD (Solid State Disc) 208. )
The above image data processing is performed for all the originals set in the RADF 305.

  When the image reading of the document is completed, the image accumulation control unit 205 repeatedly reads out the image data for a plurality of sheets stored in the SSD 208 in the order of pages, and the image processing unit 204 performs predetermined image processing. Thereafter, the output is supplied to the laser writing unit 209 via the laser control unit 207, and after the writing of the image on the paper is finished, a part of the output paper is aligned in the post-processing unit 303, and the stapling and punching processes are performed. The paper is discharged.

  In this digital copying machine 300, the SSD 208 is the nonvolatile memory control device SSD, and the maximum physical block address is set as described above, so that the state mounted in the digital copying machine 300, that is, close to the actual use conditions. Write evaluation can be performed in a state, and this evaluation time can be performed in a shorter time than in the past.

It is a block diagram which shows the structure of the system which consists of SSD and a host apparatus. It is a figure which shows the list of the I / O register corresponding to the state of the signal line | wire of an ATA cable. It is a figure which shows the list of the registers which set the parameter for a host apparatus to write data in SSD. It is a functional block diagram of the part which performs the wear leveling process in this read / write control part. It is a figure which shows the data stored in the conversion table. It is a flowchart of the wear leveling process performed when an address translation control part writes data in NAND flash memory. It is a flowchart which shows the subroutine of an alternative physical block address update process. It is a figure which shows the data stored in the conversion table. It is a functional block diagram of the part which performs the wear leveling process in the read / write control part which concerns on another embodiment. 1 is a schematic side view showing a configuration of a digital copying machine which is an embodiment of an image processing apparatus equipped with an SSD. 2 is a block diagram of a control unit of the digital copying machine. FIG.

Explanation of symbols

100, 208 ... SSD, 101 ... host device, 102 ... main control unit, 103 ... data storage unit, 104 ... ATA master interface unit, 105 ... ATA master interface control unit, 106: ATA slave interface unit, 107: ATA slave interface control unit, 108: Read / write control unit, 109: NAND flash memory, 110: ATA cable, 201: Image processing board 202, 221, 222, 226, 230 ... CPU, 203, 227, 229 ... RAM, 204 ... image processing unit, 205 ... image accumulation control unit, 206 ... memory, 207 ..Laser control unit, 209... Laser writing unit, 210... CCD board, 211. D conversion unit, 212 ... CCD control unit, 213 ... CCD, 214 ... analog circuit, 215 ... process unit, 216 ... reading scanner unit, 217 ... duplex unit, 223 ... LCD, 224 ... operation keys, 225 ... operation panel, 228 ... operation panel board, 231 ... machine control board, 301 ... scanner unit, 302 ... laser recording unit, 303 ... ..Post-processing section, 304... Document table, 305... RADF, 306... Scanner unit, 307... Paper transport section, 308 .. Laser writing unit, 309. .

Claims (7)

A non-volatile memory control device including a read / write control unit that performs read / write processing of data to a predetermined physical block address of a non-volatile memory based on a logical block address from an external device,
Storage means for storing correspondence information between logical block addresses and physical block addresses;
Address conversion means for converting a logical block address from an external device into a physical block address based on correspondence information of the storage means;
Storage means for storing an upper limit physical block address input from an external device;
A non-volatile memory control device comprising: address conversion control means for controlling the address conversion means to perform address conversion with the upper limit physical block address stored in the storage means as an upper limit. A non-volatile memory control device including a read / write control unit that performs read / write processing of data to a predetermined physical block address of a non-volatile memory based on a logical block address from an external device,
Storage means for storing correspondence information between logical block addresses and physical block addresses;
Storage means for storing a plurality of physical block addresses in advance;
Selection means for selecting one of a plurality of physical block addresses stored in the storage means;
A non-volatile memory control device comprising: address translation control means for controlling the address translation means to perform address translation with the physical block address selected by the selection means as an upper limit. The non-volatile memory control device according to claim 1 or 2,
The storage means stores data write count information to the physical block address,
The address translation control means includes
Means for acquiring from the storage means write count information of a physical block address corresponding to a logical block address received from an external device;
Means for comparing the write count information with the minimum write count information among the write count information of all physical block addresses stored in the storage means;
When the difference between the write count information and the minimum write count information is greater than or equal to a predetermined value, the physical block address corresponding to the logical block address is the physical block address with the minimum write count information. A non-volatile memory control device, wherein   An image processing apparatus comprising the non-volatile memory control device according to claim 1. A nonvolatile memory control method for performing data read / write processing on a predetermined physical block address of a nonvolatile memory based on a logical block address from an external device,
Storing an upper limit physical block address input from an external device;
Receiving a logical block address corresponding to a physical block address to be read / written from the external device;
And a step of converting the received logical block address into a physical block address with an upper limit physical block address stored in the storage means as an upper limit. A nonvolatile memory control method for performing data read / write processing on a predetermined physical block address of a nonvolatile memory based on a logical block address from an external device,
Receiving a logical block address corresponding to a physical block address to be read / written from the external device;
A selection step of selecting one of a plurality of physical block addresses stored in advance in the storage means;
And a step of converting the received logical block address into a physical block address with the physical block address stored in the storage means as an upper limit. The nonvolatile memory control method according to claim 5 or 6,
Obtaining the write count information of the physical block address corresponding to the logical block address received from the external device;
Comparing the write count information with the minimum write count information among the write count information of all physical block addresses;
When the difference between the write count information and the minimum write count information is greater than or equal to a predetermined value, the physical block address corresponding to the logical block address is the physical block address with the minimum write count information. And a non-volatile memory control method.

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