JP2022189868A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transistor structure that can make the threshold voltage of the electrical characteristics of a transistor using an oxide semiconductor as the channel forming region positive and realize a so-called normally-off switching element.

SOLUTION: An oxide semiconductor stack comprises at least of a first oxide semiconductor layer and a second oxide semiconductor layer having different energy gaps and a transistor is formed using the oxide semiconductor stack with a region that contains an excess of oxygen above the stoichiometric composition ratio.

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2023,JPO&INPIT

Description

One embodiment of the disclosed invention relates to a semiconductor device and a manufacturing method thereof.

In this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

In recent years, semiconductor devices have been developed and used as LSIs, CPUs, and memories. C.
A PU is an aggregate of semiconductor elements having semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and having electrodes as connection terminals formed thereon.

2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components of various electronic devices.

A technique for manufacturing a transistor or the like using an oxide semiconductor film for a channel formation region has also attracted attention. For example, a transistor using zinc oxide (ZnO) or a transistor using InGaO ₃ (ZnO) _m for the oxide semiconductor film can be given. Patent Document 1 and Patent Document 2 disclose a technique in which a transistor including such an oxide semiconductor film is formed over a light-transmitting substrate and used for a switching element of an image display device or the like.

Japanese Patent Application Laid-Open No. 2007-123861 JP 2007-96055 A

A transistor applied to a semiconductor device preferably has a channel formed with a positive threshold voltage (Vth) whose gate voltage is as close to 0V as possible. When the threshold voltage of the transistor is negative, current tends to flow between the source electrode layer and the drain electrode layer even when the gate voltage is 0 V, which is a so-called normally-on transistor.

Therefore, in one embodiment of the present invention, an n-channel transistor including an oxide semiconductor for a channel formation region has a positive threshold voltage and realizes a so-called normally-off switching element. One of the subjects is to provide a manufacturing method.

In addition, even if the manufactured transistor is not normally off depending on the material and manufacturing conditions, it is important to bring the characteristics close to normally off. Another object is to provide a structure in which the threshold voltage of a transistor can be close to zero even in a normally-on state and a manufacturing method thereof.

In addition, in order to realize a semiconductor device with higher performance, we will develop a structure and a manufacturing method for realizing high-speed response and high-speed driving of a semiconductor device by improving the on-characteristics (for example, on-current and field-effect mobility) of a transistor. One of the challenges is to provide

In addition, since the leakage current of the transistor also affects the power consumption of the semiconductor device, it is important to reduce the leakage current in order to realize a semiconductor device with low power consumption. Therefore, another object of one embodiment of the present invention is to provide a structure in which generation of leakage current (parasitic channel) in a source electrode layer and a drain electrode layer of a transistor is reduced.

Note that one embodiment of the present invention is to solve at least one of the above problems.

In one embodiment of the present invention, a transistor is formed using oxide semiconductor layers in which oxide semiconductors having different energy gaps and/or different electron affinities are stacked (hereinafter also referred to as oxide semiconductor stacks). In addition, the oxide semiconductor stack includes a region containing oxygen in excess of the stoichiometric composition ratio (hereinafter also referred to as an oxygen-excess region).

For example, a transistor using an oxide semiconductor stack including a first oxide semiconductor layer and a second oxide semiconductor layer having an energy gap different from that of the first oxide semiconductor layer and having an oxygen-excess region configure. Here, the first oxide semiconductor layer and the second oxide semiconductor layer may have energy gaps different from each other, and the stacking order of the layers does not matter. More specifically, one oxide semiconductor layer may have an energy gap of 3 eV or more and the other oxide semiconductor layer may have an energy gap of less than 3 eV.

Note that in this specification and the like, the term "energy gap" means "bandgap"
and "forbidden bandwidth".

Alternatively, the oxide semiconductor stack may include three or more oxide semiconductor layers. When the oxide semiconductor stack has three or more oxide semiconductor layers, all the oxide semiconductor layers may have energy gaps different from each other, or the oxide semiconductor layers may have the same energy gap. The layers may be used in multiple oxide semiconductor stacks.

For example, a first oxide semiconductor layer and, provided over the first oxide semiconductor layer, the electron affinity of the first oxide semiconductor layer is higher than that of the first oxide semiconductor layer, or the energy gap of the first oxide semiconductor layer is A second oxide semiconductor layer having an energy gap smaller than the layer's energy gap; and a third oxide semiconductor layer provided on the second oxide semiconductor layer so as to wrap side surfaces of the second oxide semiconductor layer. can be configured. Note that the electron affinity and energy gap of the third oxide semiconductor layer are preferably the same as those of the first oxide semiconductor layer. Here, the electron affinity represents the energy difference between the vacuum level and the conduction band of the oxide semiconductor. With a structure in which the second oxide semiconductor layer with a small energy gap is sandwiched between the first oxide semiconductor layer and the third oxide semiconductor layer with a large energy gap, the off-state current (leakage current) of the transistor can be further reduced. A reduction effect is obtained.

Specifically, the energy gap between the first oxide semiconductor layer and the third oxide semiconductor layer is
The energy gap of the second oxide semiconductor layer is set to be less than 3 eV. In a transistor including an oxide semiconductor layer, the energy gap of the oxide semiconductor layer affects electrical characteristics of the transistor. For example, in a transistor including an oxide semiconductor layer, when the energy gap of the oxide semiconductor layer is small, on-characteristics (for example, on-current and field-effect mobility) are improved, while the energy gap of the oxide semiconductor layer is increased. If it is large, the off current can be reduced.

In the case of a single-layer oxide semiconductor layer, the electrical characteristics of a transistor are almost determined by the size of the energy gap of the oxide semiconductor layer; therefore, it is difficult to provide the transistor with desired electrical characteristics. However, in the transistor according to one embodiment of the present invention, the use of an oxide semiconductor stack including a plurality of oxide semiconductor layers with different energy gaps makes it possible to control the electrical characteristics of the transistor with higher accuracy. It becomes possible to impart electrical characteristics to the transistor.

Therefore, it is possible to provide semiconductor devices that meet various purposes such as high functionality, high reliability, and low power consumption.

One embodiment of the structure of the invention disclosed in this specification is an oxide semiconductor including a first oxide semiconductor layer and a second oxide semiconductor layer having an energy gap different from that of the first oxide semiconductor layer. a source electrode layer or a drain electrode layer is formed over the oxide semiconductor stack; a gate insulating film is formed over the source electrode layer or the drain electrode layer; This is a method for manufacturing a semiconductor device in which oxygen is introduced into an oxide semiconductor stack in a self-aligned manner using a layer as a mask, and a gate electrode layer overlapping with the oxide semiconductor stack is formed with a gate insulating film interposed therebetween.

Another embodiment of the invention disclosed in this specification includes a first oxide semiconductor layer stacked in order and a second oxide semiconductor layer having an energy gap smaller than that of the first oxide semiconductor layer. and a third oxide semiconductor layer having an energy gap larger than that of the second oxide semiconductor layer, forming a source electrode layer or a drain electrode layer on the oxide semiconductor stack, A gate insulating film is formed over the source electrode layer or the drain electrode layer, oxygen is introduced into the oxide semiconductor stack from above the gate insulating film in a self-aligning manner using the source electrode layer or the drain electrode layer as a mask, and the gate insulating film is formed. This is a method for manufacturing a semiconductor device in which a gate electrode layer overlapping with an oxide semiconductor stack is formed through an oxide semiconductor stack.

In the above method for manufacturing a semiconductor device, a third oxide semiconductor layer is preferably stacked so as to cover side surfaces of the first oxide semiconductor layer and side surfaces of the second oxide semiconductor layer.

By forming the third oxide semiconductor layer so as to cover the side surfaces of the first oxide semiconductor layer and the side surfaces of the second oxide semiconductor layer, an increase in oxygen vacancies in the second oxide semiconductor layer is suppressed. , the threshold voltage of the transistor can be made close to zero. Furthermore, since the second oxide semiconductor layer serves as a buried channel, the channel formation region can be kept away from the interface of the insulating film, thereby reducing interface scattering of carriers and realizing high field-effect mobility. can.

In any of the above methods for manufacturing a semiconductor device, after forming the gate electrode layer, it is preferable to introduce a dopant into the oxide semiconductor stack in a self-aligning manner using the gate electrode layer as a mask.

In any one of the above methods for manufacturing a semiconductor device, an interlayer insulating film is formed over the gate electrode layer, a contact hole reaching the source electrode layer or the drain electrode layer is formed in the interlayer insulating film, and the interlayer insulating film is formed. A wiring layer connected to the source electrode layer or the drain electrode layer through the contact hole may be formed thereover.

Another embodiment of the present invention is an oxide semiconductor stack including a first oxide semiconductor layer and a second oxide semiconductor layer having an energy gap different from that of the first oxide semiconductor layer; A source electrode layer or a drain electrode layer provided over the oxide semiconductor stack, a gate insulating film provided over the source electrode layer or the drain electrode layer, and a gate overlapping the oxide semiconductor stack with the gate insulating film interposed therebetween. and an electrode layer, and in the oxide semiconductor stack, a region that does not overlap with the source electrode layer or the drain electrode layer has a higher oxygen concentration than a region that overlaps with the source electrode layer or the drain electrode layer.

In another embodiment of the present invention, a first oxide semiconductor layer is in contact with the first oxide semiconductor layer,
a second oxide semiconductor layer having an energy gap smaller than that of the first oxide semiconductor layer; and a third oxide semiconductor layer in contact with the second oxide semiconductor layer and having an energy gap larger than that of the second oxide semiconductor layer a source or drain electrode layer provided on the oxide semiconductor stack; a gate insulating film provided on the source or drain electrode layer; and a gate electrode layer overlapping with the oxide semiconductor stack with a film interposed therebetween, and a region of the oxide semiconductor stack that does not overlap with the source electrode layer or the drain electrode layer overlaps with the source electrode layer or the drain electrode layer. A semiconductor device having a higher oxygen concentration than a region.

In the semiconductor device having the above structure, the first oxide semiconductor layer and the second oxide semiconductor layer can be formed using the same mask, and the third oxide semiconductor layer is formed using the second oxide semiconductor layer. and the area thereof is larger than that of the second oxide semiconductor layer, so that the second oxide semiconductor layer can be surrounded. In the semiconductor device having such a configuration, the third oxide semiconductor layer is provided so as to contact and cover the side surface of the first oxide semiconductor layer and the side surface of the second oxide semiconductor layer. The source electrode layer or the drain electrode layer formed on the oxide semiconductor layer of the transistor is not in contact with the side surface of the second oxide semiconductor layer. This is preferable because the generation of current (parasitic channel) can be reduced.

Further, there is no particular limitation as long as the source electrode layer or the drain electrode layer does not contact the side surface of the second oxide semiconductor layer. A structure in which the third oxide semiconductor layer protrudes from the side surface of the semiconductor layer may be employed so that the third oxide semiconductor layer is in contact with part of the top surface of the first oxide semiconductor layer.

In any of the above semiconductor devices, a region of the oxide semiconductor stack that does not overlap with the gate electrode layer preferably contains a dopant. With such a structure, the oxide semiconductor stack includes a channel formation region overlapping with the gate electrode layer with the gate insulating film interposed therebetween, and a pair of low-resistance regions sandwiching the channel formation region in the channel length direction. have.

By forming oxide semiconductor layers including low-resistance regions with a channel formation region interposed in the channel length direction, the transistor has high on-state characteristics (for example, on-state current and field-effect mobility), high-speed operation, and high-speed response. It becomes possible. Moreover, since the low-resistance region is formed in a self-aligned manner and does not overlap with the gate electrode layer, parasitic capacitance can be reduced. Reducing the parasitic capacitance leads to reducing the power consumption of the entire semiconductor device.

The dopant concentration in the low resistance region is 5×10 ¹⁸ /cm ³ or more and 1×10 ²² /cm
It is preferably ³ or less.

Further, depending on the film thickness of the source electrode layer and the drain electrode layer and the conditions for introducing the dopant, these dopants may be added to the oxide semiconductor stack through the source electrode layer or the drain electrode layer. . Since it is important not to add a dopant to the channel formation region, the thickness of the source electrode layer and the drain electrode layer is set to be thinner than the thickness of the gate electrode layer.

In any of the above semiconductor devices, an interlayer insulating film provided over the gate electrode layer and having a contact hole reaching the source electrode layer or the drain electrode layer; It is preferable to further include a wiring layer connected to each of the source electrode layer and the drain electrode layer.

According to one embodiment of the present invention, on-characteristics (eg, on-current and field-effect mobility) of a transistor can be improved.

Further, according to one embodiment of the present invention, a normally-off transistor can be realized. Also, even if the transistor is normally on, the threshold value of the transistor can be made close to zero.

1A and 1B are a plan view, a cross-sectional view, and an energy band diagram illustrating a semiconductor device of one embodiment of the present invention; 4A and 4B illustrate a method for manufacturing a semiconductor device of one embodiment of the present invention; 1A and 1B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention; 1A and 1B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention; FIGS. 1A and 1B illustrate a semiconductor device of one embodiment of the present invention; FIGS. FIGS. 1A and 1B illustrate a semiconductor device of one embodiment of the present invention; FIGS. FIGS. 1A and 1B illustrate a semiconductor device of one embodiment of the present invention; FIGS. The figure which shows an electronic device. The figure which shows an ion potential. Energy band diagram. The TEM photograph figure of a sample, and its schematic diagram.

Embodiments of the present invention will be described in detail below with reference to the drawings. However, those skilled in the art will easily understand that the present invention is not limited to the following description, and that the forms and details thereof can be variously changed. Therefore, the present invention should not be construed as being limited to the descriptions of the embodiments shown below.

In the configuration of the present invention described below, the same reference numerals are used in common for the same parts or parts having similar functions in different drawings, and repeated description thereof will be omitted. also,
When referring to portions having similar functions, the same hatch pattern may be used and no particular reference numerals may be attached.

In each drawing described in this specification, the size of each configuration, the thickness of the film, or the region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

In this specification and the like, the ordinal numbers such as first and second are used for convenience and do not indicate the order of steps or the order of stacking. Moreover, in this specification and the like, specific names are not shown as matters for specifying the invention.

(Embodiment 1)
In this embodiment, one mode of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor including an oxide semiconductor stack is shown as an example of a semiconductor device.

A transistor 510 illustrated in FIGS. 1A, 1B, and 1C is an example of a top-gate transistor. FIG. 1A is a top view, the cross section cut along the chain line XY in FIG. 1A corresponds to FIG. 1B, and the cross section cut along the chain line VW in FIG. (C
). Note that in FIGS. 1B and 1C, interfaces between oxide semiconductor layers included in the oxide semiconductor stack 403 are schematically illustrated by dotted lines. Depending on the material and film formation conditions of the oxide semiconductor layers, the interface between the oxide semiconductor layers may not be clear. Further, when the interface is unclear, a portion which can be called a mixed region or a mixed layer of a plurality of different oxide semiconductor layers is formed in some cases.

As illustrated in FIG. 1B which is a cross-sectional view in the channel length direction, the transistor 510 includes a first oxide semiconductor layer and a second oxide semiconductor layer over a substrate 400 having an insulating surface provided with an oxide insulating film 436 . and a third oxide semiconductor layer, a source electrode layer 405 a, a drain electrode layer 405 b, a gate insulating film 402 , and a gate electrode layer 401 . In the transistor 510, the first oxide semiconductor layer is formed over and in contact with the oxide insulating film 436, and the second oxide semiconductor layer is formed over the first oxide semiconductor layer. In the transistor 510, the oxide semiconductor stack includes a third oxide semiconductor layer, and the third oxide semiconductor layer is the side surface of the first oxide semiconductor layer and the second oxide semiconductor layer. provided covering the sides. Note that the peripheral portion of the third oxide semiconductor layer is in contact with the oxide insulating film.

In the oxide semiconductor stack 403, a channel formation region overlapping with the gate electrode layer 401 with the gate insulating film 402 interposed therebetween includes three layers: a first channel formation region 121c, a second channel formation region 122c, and a second channel formation region 122c. 3 channel forming regions 123c are laminated.

In addition, the first low resistance region 12 is formed with the first channel forming region 121c interposed in the channel length direction.
1a, 121b. In addition, second low-resistance regions 122a and 122b are provided across the second channel formation region 122c in the channel length direction. In addition, third low-resistance regions 123a and 123b are provided with a third channel formation region 123c interposed therebetween in the channel length direction.

A first region 121d overlapping with the source electrode layer 405a or the drain electrode layer 405b is provided.
, 121e, second regions 122d, 122e, and third regions 123d, 123e.

In the transistor 510 illustrated in FIG. 1, the oxide semiconductor stack 403 includes first low-resistance regions 121a and 121b, a first channel formation region 121c, and first regions 121d and 121d.
a first oxide semiconductor layer including 1e, a second oxide semiconductor layer including second low-resistance regions 122a and 122b, a second channel formation region 122c, and second regions 122d and 122e; 3 low resistance regions 123a and 123b, a third channel formation region 123c, and a third
and a third oxide semiconductor layer including the regions 123d and 123e are stacked in this order.

Further, in the transistor 510, the second oxide semiconductor layer has an energy gap smaller than that of the first oxide semiconductor layer, and the energy of the third oxide semiconductor layer is larger than that of the second oxide semiconductor layer. have a gap. Further, the first oxide semiconductor layer and the third oxide semiconductor layer preferably have the same energy gap.

FIG. 1B is a cross-sectional view in the channel length direction, in which the end portions of the second oxide semiconductor layer, that is, the side surfaces of the second regions 122d and 122e are the end portions of the third oxide semiconductor layer; That is, the third area 1
A structure covered with 23d and 123e is preferable. With such a structure, generation of leakage current (parasitic channel) in the source electrode layer 405a and the drain electrode layer 405b of the transistor can be reduced.

FIG. 1C is a cross-sectional view in the channel width direction, and similarly to FIG. A structure covered with the end portion of the oxide semiconductor layer, that is, the third channel formation region 123c is preferable.

FIG. 1(D) is a diagram showing an energy band diagram in the film thickness direction (between DD') in FIG. 1(B). In this embodiment, materials for the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are selected so that the energy band diagram shown in FIG. . However, if a buried channel is formed in the conduction band, a sufficient effect can be obtained. It does not have to be limited. For example, the configuration may be such that an energy band diagram having a depression only in the conduction band can be obtained.

2A, 2B, 2C, and 2D illustrate an example of a method for manufacturing a transistor.

First, the oxide insulating film 436 and the first oxide semiconductor layer 10 are formed over the substrate 400 having an insulating surface.
1, a second oxide semiconductor layer 102 is formed.

There is no particular limitation on the substrate that can be used as the substrate 400 having an insulating surface, but it must have at least heat resistance to withstand heat treatment performed later. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates,
A quartz substrate, a sapphire substrate, or the like can be used. Further, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can also be applied. It may be used as the substrate 400 .

Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 400 . In order to manufacture a flexible semiconductor device, a transistor including an oxide semiconductor stack may be directly manufactured over a flexible substrate, or a transistor including an oxide semiconductor stack may be manufactured over another manufacturing substrate. ,
It may be peeled off and then transferred to a flexible substrate. Note that a separation layer is preferably provided between the formation substrate and the transistor including the oxide semiconductor stack in order to separate and transfer the transistor from the formation substrate to the flexible substrate.

As the oxide insulating film 436, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, silicon nitride oxide, aluminum nitride oxide, or a mixture thereof is formed by a plasma CVD method, a sputtering method, or the like. can be formed using The oxide insulating film 436 may have a single layer or a stacked layer. In this embodiment, a silicon oxide film formed by a sputtering method is used as the oxide insulating film 436 .

In the transistor 510, since the oxide insulating film 436 is in contact with the bottom layer and the top layer of the oxide semiconductor stack, oxygen in the film (in the bulk) preferably exceeds the stoichiometric composition ratio. . For example, in the case of using a silicon oxide film as the oxide insulating film 436, SiO _2+α (where α>0). By using such an oxide insulating film 436, oxygen can be supplied to the oxide semiconductor stack formed thereabove, and favorable characteristics can be obtained. By supplying oxygen to the oxide semiconductor stack, oxygen vacancies in the film can be filled.

In order to prevent hydrogen or water from being contained in the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 as much as possible in the step of forming the oxide semiconductor stack over the oxide insulating film 436 , the substrate provided with the oxide insulating film 436 is preheated in a preheating chamber of a sputtering apparatus as a pretreatment for the deposition of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 . Impurities such as hydrogen and moisture adsorbed to the oxide insulating film 436 are preferably desorbed and exhausted. A cryopump is preferably used as the evacuation means provided in the preheating chamber.

An oxide semiconductor used for the oxide semiconductor stack preferably contains at least indium (In) or zinc (Zn). In particular, it preferably contains In and Zn. In addition, gallium (Ga) is preferably included as a stabilizer for reducing variations in electrical characteristics of transistors using the oxide. It is also preferred to have tin (Sn) as a stabilizer. In addition, hafnium (Hf
). Moreover, it is preferable to have aluminum (Al) as a stabilizer.

In addition, as other stabilizers, lanthanoids such as lanthanum (La), cerium (
Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium ( Tm), ytterbium (Yb), and lutetium (Lu).

For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, In—Zn oxides that are binary metal oxides, Sn—Zn oxides, Al—Zn oxides, and Zn—Mg oxides. oxides, Sn--Mg-based oxides, In--Mg-based oxides, In--Ga-based oxides, In--Ga--Zn-based oxides (also referred to as IGZO) which are ternary metal oxides, In-- Al--Zn-based oxide, In--Sn--Zn-based oxide, Sn--Ga--Zn-based oxide, Al--Ga--Zn-based oxide, Sn--Al--Zn-based oxide, In--Hf--Zn-based oxide substance, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu -Zn-based oxide, In-Gd-Zn-based oxide,
In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, I
n—Er—Zn oxide, In—Tm—Zn oxide, In—Yb—Zn oxide, In
-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide which is a quaternary metal oxide, I
n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-
A Zn-based oxide, an In--Sn--Hf--Zn-based oxide, or an In--Hf--Al--Zn-based oxide can be used.

The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. In addition, it may be a structure including a portion having crystallinity in the amorphous, or may be non-amorphous. Even with the same material, the energy gap may be different between a single crystal and a non-single crystal, so it is important to appropriately select the crystal state. Materials for the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are selected so that the energy band diagram shown in FIG. 1D is obtained.

As the oxide semiconductor stack, an oxide semiconductor film containing crystals and having crystallinity (a crystalline oxide semiconductor film) can be used. The crystalline state of the crystalline oxide semiconductor film may be a state in which the directions of the crystal axes are disordered or a state in which the orientation is constant.

For example, as the crystalline oxide semiconductor film, an oxide semiconductor film containing crystals having a c-axis substantially perpendicular to the surface can be used.

An oxide semiconductor film containing crystals having a c-axis substantially perpendicular to the surface does not have a single-crystal structure.
CAAC-OS (C Axis Al
ignited Crystalline Oxide Semiconductor) film.

A CAAC-OS film is neither completely single-crystal nor completely amorphous. A CAAC-OS film is an oxide semiconductor film having a crystalline-amorphous mixed phase structure in which an amorphous phase has a crystalline part and an amorphous part. Note that the crystal part often has a size that fits within a cube having a side of less than 100 nm. In addition, a transmission electron microscope (TEM: Transmission Electron
(n Microscope), the boundary between the amorphous portion and the crystal portion included in the CAAC-OS film is not clear. Further, grain boundaries (also called grain boundaries) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

The crystal part included in the CAAC-OS film has a c-axis aligned in a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed or the normal vector of the surface, and has a triangular shape when viewed from a direction perpendicular to the ab plane. It has a shape or a hexagonal atomic arrangement, in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers when viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, when simply described as vertical, 8
The range of 5° or more and 95° or less is also included. Also, when simply describing parallel, -5
It is assumed that the range of 5° or less is also included.

Note that the distribution of crystal parts in the CAAC-OS film does not have to be uniform. For example, CAA
In the process of forming the C-OS film, in the case where crystals are grown from the surface side of the oxide semiconductor film, the proportion of crystal parts in the vicinity of the formation surface may be higher than in the vicinity of the formation surface. Also, CA
By adding an impurity to the AC-OS film, the crystal part may become amorphous in the impurity added region.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed or the normal vector to the surface of the CAAC-OS film, the shape of the CAAC-OS film (formation surface cross-sectional shape or surface cross-sectional shape) may face in different directions. The direction of the c-axis of the crystal part is parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS film is formed. The crystal part is formed by forming a film, or by performing a crystallization treatment such as heat treatment after forming a film.

A transistor using a CAAC-OS film can reduce variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

The thickness of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 is 5 nm or more.
nm or less (preferably 5 nm or more and 30 nm or less), sputtering, MBE (Mo
Lecular Beam Epitaxy) method, CVD method, pulse laser deposition method, AL
A D (Atomic Layer Deposition) method or the like can be used as appropriate. The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are formed using a sputtering apparatus in which film formation is performed with a plurality of substrate surfaces set substantially perpendicular to a sputtering target surface. It may be a film.

Note that the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are formed under conditions that contain a large amount of oxygen (for example, deposition is performed by a sputtering method in an atmosphere containing 100% oxygen). ) to form a film containing a large amount of oxygen (preferably, a film containing an excessive amount of oxygen with respect to the stoichiometric composition ratio in the crystal state of the oxide semiconductor). .

Note that in this embodiment, a target for manufacturing the first oxide semiconductor layer 101 by a sputtering method has a composition ratio of In ₂ O ₃ :Ga ₂ O ₃ :Zn, for example.
An In—Ga—Zn-based oxide film is formed using a metal oxide target with O=1:1:2 [molar ratio]. Also, the material and composition of this target are not limited, for example, In ₂ O ₃
A metal oxide target of :Ga ₂ O ₃ :ZnO=1:1:1 [molar ratio] may be used.

As a sputtering gas used for forming the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or a hydride have been removed can be used. preferable.

Further, the oxide insulating film 436 and the oxide semiconductor stack are preferably formed continuously without being exposed to the air. When the oxide insulating film 436 and the oxide semiconductor stack are formed continuously without being exposed to the air, adsorption of impurities such as hydrogen and moisture to the surface of the oxide insulating film 436 can be prevented.

The CAAC-OS film is formed, for example, by a sputtering method using a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, the crystal region included in the sputtering target is cleaved from the ab plane, and a
There are cases where the sputtered particles are exfoliated as plate-like or pellet-like sputtered particles having a plane parallel to the -b plane. In this case, the plate-like sputtered particles reach the substrate while maintaining their crystalline state, so that a CAAC-OS film can be formed.

Further, it is preferable to apply the following conditions for forming the CAAC-OS film.

By reducing the contamination of impurities during film formation, it is possible to suppress the deterioration of the crystal state due to the impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber may be reduced. Also, the impurity concentration in the deposition gas may be reduced. Specifically, a deposition gas having a dew point of −80° C. or lower, preferably −100° C. or lower is used.

In addition, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the film is formed at a substrate heating temperature of 100° C. or higher and 740° C. or lower, preferably 200° C. or higher and 500° C. or lower. By raising the substrate heating temperature during film formation, when flat plate-shaped sputtered particles reach the substrate, migration occurs on the substrate.
The flat sides of the sputtered particles adhere to the substrate.

Further, it is preferable to reduce plasma damage during film formation by increasing the proportion of oxygen in the film forming gas and optimizing the power. The oxygen ratio in the film-forming gas is 30% by volume or more, preferably 100% by volume.

As an example of the sputtering target, an In--Ga--Zn--O compound target is shown below.

InO 2 _X powder, GaO 2 _Y powder, and ZnO 2 _Z powder are mixed at a predetermined molar ratio, and after pressure treatment, heat treatment is performed at a temperature of 1000° C. or more and 1500° C. or less to obtain polycrystalline In-G.
An a-Zn-O compound target is used. Note that X, Y and Z are arbitrary positive numbers. Here, the predetermined molar ratio is such that, for example, InO _X powder, GaO _Y powder, and ZnO _Z powder are
2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 mo
l number ratio. The types of powders and the mixing ratio thereof may be appropriately changed depending on the sputtering target to be produced.

In this embodiment, as illustrated in FIG. 2A, the formed oxide semiconductor stack is formed into the island-shaped first oxide semiconductor layer 101 and the island-shaped second oxide semiconductor layer 101 through a first photolithography step. The oxide semiconductor layer 102 is processed. Alternatively, a resist mask for forming the island-shaped first oxide semiconductor layer 101 and the island-shaped second oxide semiconductor layer 102 may be formed by an inkjet method. Since a photomask is not used when the resist mask is formed by an inkjet method, the manufacturing cost can be reduced.

Note that the etching of the oxide semiconductor stack may be dry etching, wet etching, or both. For example, as an etchant used for wet etching of the oxide semiconductor film, a mixed solution of phosphoric acid, acetic acid, and nitric acid, or the like can be used. Also, I
TO07N (manufactured by Kanto Kagaku Co., Ltd.) may also be used.

Next, a third oxide semiconductor layer 103 is formed to cover the first island-shaped oxide semiconductor layer 101 and the second island-shaped oxide semiconductor layer 102 . Thus, an oxide semiconductor stack 403 is formed. The third oxide semiconductor layer 103 is formed using the same target as the first oxide semiconductor layer 101 . The deposition conditions for the third oxide semiconductor layer 103 are the same as those for the first oxide semiconductor layer 101; therefore, description thereof is omitted here. Note that a third oxide semiconductor layer 103 that overlaps with the second oxide semiconductor layer 102 and has a larger top surface area than the second oxide semiconductor layer 102 is formed by a second photolithography step. .

Next, the oxide semiconductor stack 403 may be subjected to heat treatment for removing excess hydrogen (including water and hydroxyl groups) (dehydration or dehydrogenation). The temperature of the heat treatment is 300°C or higher7
00° C. or less, or less than the strain point of the substrate. The heat treatment can be performed under reduced pressure, a nitrogen atmosphere, or the like. For example, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor stack 403 at 450° C. for 1 hour in a nitrogen atmosphere.

Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats an object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, GRTA (Gas R
apid Thermal Anneal) device, LRTA (Lamp Rapid T
RTA (rapid thermal anneal) such as a thermal anneal) device
al) the device can be used; An LRTA apparatus is an apparatus that heats an object by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas. For hot gases,
A rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be processed by heat treatment is used.

For example, as the heat treatment, GRTA may be performed in which the substrate is placed in an inert gas heated to a high temperature of 650° C. to 700° C., heated for several minutes, and then taken out of the inert gas.

Note that in the heat treatment, nitrogen or a rare gas such as helium, neon, or argon preferably does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen or rare gases such as helium, neon, argon, etc. introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably is 0.1
ppm or less).

In addition, after heating the oxide semiconductor stack 403 by heat treatment, high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry gas is added to the same furnace while maintaining the heating temperature or slowly cooling from the heating temperature. Air (air with a water content of 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less when measured using a CRDS (cavity ring-down laser spectroscopy) type dew point meter). may be introduced. Oxygen gas or nitrous oxide gas preferably does not contain water, hydrogen, or the like. Alternatively, the purity of the oxygen gas or dinitrogen monoxide gas introduced into the heat treatment apparatus is 6N or higher, preferably 7N or higher (that is, the impurity concentration in the oxygen gas or dinitrogen monoxide gas is 1 ppm or less, preferably 0.1 ppm or less. )
It is preferable to Oxidation is achieved by supplying oxygen, which is the main component material constituting the oxide semiconductor, which has been simultaneously reduced by the process of removing impurities by dehydration or dehydrogenation by the action of oxygen gas or dinitrogen monoxide gas. The semiconductor stack 403 can be highly purified and i-type (intrinsic).

Next, a conductive film to be a source electrode layer and a drain electrode layer (including wirings formed using the same layers) is formed over the oxide semiconductor stack 403 . A material that can withstand heat treatment later is used for the conductive film. As the conductive film used for the source electrode layer and the drain electrode layer, for example,
A metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above elements as components, or the like is used. can be used. In addition, a high-melting-point metal film such as Ti, Mo, W or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is provided on one or both of the lower side and the upper side of the metal film such as Al and Cu. may be laminated. Alternatively, the conductive film used for the source electrode layer and the drain electrode layer may be formed using a conductive metal oxide. Examples of conductive metal oxides include indium oxide (In ₂ O ₃ ), tin oxide (SnO
₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ ), indium zinc oxide (In ₂ O ₃ —ZnO), or these metal oxide materials containing silicon oxide can be used.

A resist mask is formed over the conductive film by a third photolithography step, and etching is selectively performed to form the source electrode layer 405a and the drain electrode layer 405b, and then the resist mask is removed. A cross section at this stage is shown in FIG. In this embodiment, a 10-nm-thick tungsten film is formed as the source electrode layer 405a and the drain electrode layer 405b. When the thickness of the source electrode layer 405a and the drain electrode layer 405b is small in this manner, the coverage with the gate insulating film 442 formed thereover is improved, and the light can pass through the source electrode layer 405a and the drain electrode layer 405b. A dopant can be introduced into the oxide semiconductor stack 403 below the source electrode layer 405a and the drain electrode layer 405b.

Next, the oxide semiconductor stack 403, the source electrode layer 405a, and the drain electrode layer 405b are formed.
A gate insulating film 402 is formed to cover the .

The film thickness of the gate insulating film 402 is set to 1 nm or more and 20 nm or less.
method, CVD method, pulse laser deposition method, ALD method, or the like can be used as appropriate. Alternatively, the gate insulating film 402 may be formed using a sputtering apparatus that performs film formation with a plurality of substrate surfaces set substantially perpendicular to the surface of the sputtering target.

As a material for the gate insulating film 402, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used.

Hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y x>0, y>0), hafnium silicate to which nitrogen is added (HfSiO _x N _y (x>0, y >0)), hafnium aluminate (HfAl _x O _y
(x>0, y>0)), and gate leakage current can be reduced by using a high-k material such as lanthanum oxide. Furthermore, the gate insulating film 402 may have a single-layer structure or a laminated structure.

Next, as shown in FIG. 2C, a source electrode layer 405a and a drain electrode layer 405b are formed.
is used as a mask, oxygen 431 is introduced into the oxide semiconductor stack 403 . Oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced to supply oxygen into at least the third oxide semiconductor layer. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

By introducing oxygen into the oxide semiconductor stack 403 , a region of the oxide semiconductor stack 403 that does not overlap with the source electrode layer 405 a or the drain electrode layer 405 b becomes the source electrode layer 4 .
05a or the region overlapping with the drain electrode layer 405b. It is preferable that oxygen content in a region which does not overlap with the source electrode layer 405a or the drain electrode layer 405b exceed the stoichiometric composition ratio by the oxygen introduction treatment. For example, the oxygen concentration peak of the oxide semiconductor stack 403 in the region into which oxygen is introduced by the oxygen introduction treatment is preferably 1×10 ¹⁸ /cm ³ or more and 5×10 ²¹ /cm ³ or less.

In this embodiment, by introducing oxygen 431, the first excess oxygen region 111, the second excess oxygen region 112, and A third oxygen-excess region 113 is formed in a self-aligned manner. However, the oxygen 431 may be contained at least at the interface between the third oxide semiconductor layer 103 and the gate insulating film 402 . Therefore, depending on the introduction depth of the oxygen 431, the oxygen concentrations in the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 differ from the region overlapping with the source electrode layer 405a or the drain electrode layer 405b and the other region. may be equivalent in The depth of introduction of oxygen into the oxide semiconductor stack 403 may be controlled by appropriately setting injection conditions such as acceleration voltage and dose amount, and the thickness of the gate insulating film 402 through which the oxygen is allowed to pass.

Note that the timing of introducing the oxygen 431 is not limited to after the formation of the gate insulating film 402 . However, when oxygen is introduced through a film stacked in the oxide semiconductor stack 403, the depth of oxygen introduction (introduction region) can be more easily controlled, so that oxygen can be efficiently injected into the oxide semiconductor stack 403. It has the advantage of being able to

Further, heat treatment may be performed after the treatment of introducing the oxygen 431 . As a heating condition, the temperature is 25
It is preferably carried out at 0° C. or higher and 700° C. or lower, preferably 300° C. or higher and 450° C. or lower in an oxygen atmosphere. Alternatively, the heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in the atmosphere (ultra-dry air).

In the case where at least one layer of the oxide semiconductor stack is a crystalline oxide semiconductor film, the introduction of oxygen 431 may make the layer amorphous. In this case, heat treatment is performed after the oxygen 431 is introduced, so that the crystallinity of the oxide semiconductor stack can be recovered.

Further, by forming the oxygen-excess region in the oxide semiconductor stack 403, oxygen vacancies can be immediately filled, so that the number of charge trapping centers in the oxide semiconductor stack 403 can be reduced. In the oxide semiconductor stack 403, oxygen vacancies are present in a portion where oxygen is released, and the oxygen vacancies generate a donor level that causes a change in electrical characteristics of the transistor. By introducing oxygen, oxygen vacancies in the film can be compensated for. Therefore, when such an oxide semiconductor stack is used for a transistor, variations in the threshold voltage Vth of the transistor due to oxygen vacancies are reduced. The threshold voltage shift ΔVth can be reduced. also,
It is also possible to shift the threshold voltage positively and turn the transistor normally off.

Next, a gate electrode layer 401 is formed over the gate insulating film 402 by plasma CVD, sputtering, or the like. The gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing these as main components. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used as the gate electrode layer 401 . The gate electrode layer 401 may have a single-layer structure or a stacked-layer structure.

Materials for the gate electrode layer 401 include indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium. Conductive materials such as zinc oxide, indium tin oxide with added silicon oxide can also be applied. Alternatively, a laminated structure of the conductive material and the metal material may be used.

Further, as one layer of the gate electrode layer 401 in contact with the gate insulating film 402, a metal oxide containing nitrogen, specifically, an In--Ga--Zn-based oxide film containing nitrogen or an In--Sn-based oxide film containing nitrogen. a film, an In—Ga-based oxide film containing nitrogen, an In—Zn-based oxide film containing nitrogen,
Sn-based oxide films containing nitrogen, In-based oxide films containing nitrogen, metal nitride films (InN, Sn
N, etc.) can be used. These films have a work function of 5 eV, preferably 5.5 eV or more, and when used as a gate electrode layer, can make the threshold voltage of electrical characteristics of a transistor positive, so-called normally-off switching. element can be realized.

Next, preferably, a process for selectively introducing a dopant 421 is performed. In this process, using the gate electrode layer 401 as a mask, the first low resistance region 12 is formed through the gate insulating film 402 .
1a, 121b, second low resistance regions 122a, 122b, third low resistance regions 123a, 1
23b. By this treatment, the first low-resistance regions 121a and 121b are formed in a self-aligned manner with the first channel forming region 121c sandwiched in the channel length direction. Further, second low-resistance regions 122a and 122b are formed in a self-aligned manner with a second channel forming region 122c interposed in the channel length direction. Further, third low-resistance regions 123a and 123b are formed in a self-aligned manner with a third channel forming region 123c interposed therebetween in the channel length direction.

In the transistor 510 of this embodiment, the first low-resistance regions 121a and 121b, the second low-resistance regions 122a and 122b, and the third low-resistance regions 123a and 123b are regions containing excess dopants and oxygen. becomes.

Further, in this treatment, the oxide semiconductor stack 403 (at least the third oxide semiconductor layer 103) passes through the gate insulating film 402, the source electrode layer 405a, and the drain electrode layer 405b.
to selectively introduce a dopant 421 into the first regions 121d, 121e, the second region 121
2d, 122e, and third regions 123d, 123e are formed (see FIG. 2D). By introducing the dopant 421 below the source electrode layer 405a and the drain electrode layer 405b, the resistance of the first regions 121d and 121e, the second regions 122d and 122e, and the third regions 123d and 123e is reduced. can be planned.

By introducing the dopant 421 and forming the oxide semiconductor stack 403 including low-resistance regions with the channel formation region interposed therebetween in the channel length direction, the on-state characteristics of the transistor 510 are improved, and the transistor can operate at high speed and respond quickly. can be Moreover, since the low-resistance region is formed in a self-aligned manner and does not overlap with the gate electrode layer, parasitic capacitance can be reduced. Reducing the parasitic capacitance leads to reducing the power consumption of the entire semiconductor device.

In addition, since the source electrode layer 405a and the drain electrode layer 405b are thin films in this embodiment, the oxide semiconductor stack 4 below the source electrode layer 405a and the drain electrode layer 405b is formed.
03 also introduces dopant 421 . Source electrode layer 405a and drain electrode layer 4
A structure in which the dopant 421 is not introduced into the oxide semiconductor stack under the source electrode layer 405a and the drain electrode layer 405b can be employed depending on the thickness of the layer 05b and conditions for introducing the dopant 421 .

The introduction process of the dopant 421 may be controlled by appropriately setting injection conditions such as acceleration voltage and dose amount, and the film thickness of the gate insulating film 402 through which the dopant 421 is allowed to pass. For example, when boron is used and boron ions are implanted by an ion implantation method, the dose may be 1×10 ¹³ ions/cm ² or more and 5×10 ¹⁶ ions/cm ² or less.

First low-resistance regions 121a and 121b, second low-resistance regions 122a and 122b, and third
The concentration of the dopant 421 in the low-resistance regions 123a and 123b of is 5×10 ¹⁸ /c
It is preferably m ³ or more and 1×10 ²² /cm ³ or less.

The dopant may be introduced while heating the substrate 400 .

Note that the treatment of introducing the dopant 421 into the first low-resistance regions 121a and 121b, the second low-resistance regions 122a and 122b, and the third low-resistance regions 123a and 123b may be performed multiple times. may also be used.

Further, heat treatment may be performed after the introduction treatment of the dopant 421 . As for the heating conditions, the temperature is preferably 300° C. or higher and 700° C. or lower, preferably 300° C. or higher and 450° C. or lower for 1 hour in an oxygen atmosphere. Alternatively, the heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in the atmosphere (ultra-dry air).

When at least one layer of the oxide semiconductor stack is a crystalline oxide semiconductor film, the dopant 42
Introduction of 1 may partially amorphize. In this case, heat treatment is performed after the dopant 421 is introduced, so that the crystallinity of the oxide semiconductor stack can be recovered.

In this embodiment mode, boron is used as a dopant. Therefore, the first low resistance region 121
a, 121b, second low resistance regions 122a, 122b, and third low resistance region 123a,
123b contains boron and excess oxygen.

Through the above steps, the transistor 510 of this embodiment is manufactured.

Note that an insulating film 407 may be formed so as to cover the transistor (FIGS. 1B and 1B).
(C)).

As the insulating film 407, an inorganic insulating film such as an aluminum oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film can be typically used instead of a silicon oxide film. For example, a stack of a silicon oxide film and an aluminum oxide film can be used as the insulating film 407 .

An aluminum oxide film that can be used as the insulating film 407 has a high shielding effect (blocking effect) that prevents both oxygen and impurities such as hydrogen and moisture from passing through the film.

Alternatively, a planarization insulating film may be used as the insulating film 407 . Organic materials such as polyimide resins, acrylic resins, and benzocyclobutene-based resins can be used as the planarization insulating film. In addition to the above organic materials, low dielectric constant materials (low-k materials) and the like can be used. Note that the planarizing insulating film may be formed by stacking a plurality of insulating films formed using these materials.

Next, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the insulating film 407, and wiring layers electrically connected to the source electrode layer 405a and the drain electrode layer 405b are formed in the openings. This wiring layer can be used to connect to other transistors to configure various circuits.

Note that the transistor described in this embodiment includes an oxide semiconductor layer in which oxide semiconductors having different energy gaps are stacked, and the oxide semiconductor stack contains oxygen in excess of the stoichiometric composition ratio. The technical essence is to have Therefore, the oxide semiconductor stack 4
It is not always necessary to introduce impurities into 03. For example, after forming the gate electrode layer 401 in the manufacturing process shown in FIGS. Transistor 520 may be formed.

The transistor 520 illustrated in FIG. 3 includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer over the substrate 400 having an insulating surface provided with the oxide insulating film 436 . a source electrode layer 405a; a drain electrode layer 405b; a gate insulating film 402; Configured.

In the transistor 520, the oxide semiconductor stack 403 includes the first oxygen-excess region 11 formed in a self-aligned manner using the source electrode layer 405a or the drain electrode layer 405b as a mask.
1, second oxygen-excess region 112 and third oxygen-excess region 113, and source electrode layer 405a
Alternatively, the first regions 131d and 131e and the second region 1 overlapping with the drain electrode layer 405b
32d, 132e and third regions 133d, 133e.

Regions (the first excess oxygen region 111, the second excess oxygen region 112, and the third excess oxygen region 113) that do not overlap with the source electrode layer 405a or the drain electrode layer 405b overlap with the source electrode layer 405a or the drain electrode layer 405b. Overlapping regions (first regions 131d, 131
e, the second regions 132d, 132e and the third regions 133d, 133e) have a higher oxygen concentration, but the constituent elements in both regions are the same.

Impurities such as hydrogen and water are sufficiently removed from the highly purified oxide semiconductor stack 403 in which oxygen vacancies are filled, which is used for the transistor 510 or the transistor 520.
The hydrogen concentration in the oxide semiconductor stack 403 is 5×10 ¹⁹ /cm ³ or less, preferably 5×10
¹⁸ /cm ³ or less. Note that the hydrogen concentration in the oxide semiconductor stack 403 can be measured by secondary ion mass spectrometry (SIMS).
y).

A transistor including the highly purified oxide semiconductor stack 403 containing excess oxygen for filling oxygen vacancies, which is manufactured according to this embodiment, has a current value in an off state (off current value) with a channel width of 1 μm. per 100 zA/μm at room temperature (1 zA (zeptoampere) is 1×
10 ⁻²¹ A) or less, preferably 10 zA/μm or less, more preferably 1 zA/μm or less, further preferably 100 yA/μm or less.

Further, in the transistors 510 and 520 described in this embodiment, a third oxide semiconductor layer is formed so as to cover side surfaces of the first oxide semiconductor layer and side surfaces of the second oxide semiconductor layer. there is With such a structure, an increase in oxygen vacancies in the second oxide semiconductor layer can be suppressed, and the threshold voltage of the transistor can be brought close to zero. Furthermore, since the second oxide semiconductor layer serves as a buried channel, carrier scattering is reduced, and high field-effect mobility can be achieved.

In addition, a structure in which the second oxide semiconductor layer with a small energy gap is sandwiched between the first oxide semiconductor layer and the third oxide semiconductor layer with a large energy gap,
An effect of reducing the off current (leakage current) of the transistor can be obtained.

A semiconductor device with high performance and high reliability can be provided by using a transistor with excellent electrical characteristics obtained in this manner.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment 2)
In this embodiment, an example of a transistor obtained by partially changing the steps of Embodiment 1 is shown in FIGS. Since it is only partially different from the first embodiment, the same reference numerals are used for the sake of simplification, and the detailed description of the same parts is omitted here.

In the transistor 530 illustrated in FIG. 4A, the same mask is used when the first oxide semiconductor layer and the second oxide semiconductor layer are processed into an island shape (or island shapes are formed by processing). In this structure, part of the oxide insulating film 436 is etched to be thin using the first oxide semiconductor layer and the second oxide semiconductor layer as masks. The oxide insulating film 43 in the transistor 530
6, a region overlapping with the island-shaped first oxide semiconductor layer and the second oxide semiconductor layer has a thicker film thickness than other regions (regions not overlapping with each other). When the first oxide semiconductor layer and the second oxide semiconductor layer are processed into an island shape, part of the oxide insulating film 436 is etched, so that residues of the first oxide semiconductor layer and the like are etched. The remainder can be removed to reduce leakage current generation.

In addition, the transistor 540 illustrated in FIG. 4B is manufactured by three photolithography steps.
It has a structure in which an oxide semiconductor stack 403 is formed. In the oxide semiconductor stack 403 included in the transistor 540, after a first oxide semiconductor layer is formed, an island-shaped first oxide semiconductor layer is formed using a first mask. After a second oxide semiconductor layer is formed over the oxide semiconductor layer, a second island-shaped oxide semiconductor layer is formed using a second mask, and the island-shaped first and second oxide semiconductor layers are formed. After forming a third oxide semiconductor layer over the semiconductor layer, the third oxide semiconductor layer is processed into an island shape using a third mask.

Note that the transistor 540 has a structure in which the side surface of the first oxide semiconductor layer protrudes from the side surface of the second oxide semiconductor layer, and the third oxide semiconductor layer is the top surface of the first oxide semiconductor layer. This is an example of a configuration in which it is in contact with a part of the A third region 12 corresponding to an end portion of the third oxide semiconductor layer
3d and 123e are first regions 121d and 121 corresponding to end portions of the first oxide semiconductor layer.
e, respectively contact and overlap.

In the transistor 550 illustrated in FIG. 4C, the source electrode layer has a stacked-layer structure of the source electrode layer 405c and the source electrode layer 405a, and the drain electrode layer has a stacked-layer structure of the drain electrode layer 405d and the drain electrode layer 405b. In this example, wiring layers 465a and 465b reaching the source electrode layer 405c and the drain electrode layer 405d are formed. Insulating film 407
In some cases, part of the source electrode layer 405a or the drain electrode layer 405b is removed by overetching in the etching step for forming the contact holes in the .
In the transistor 550, the source electrode layer 405a and the drain electrode layer 405b can have a stacked structure, and the underlying conductive layer can function as an etching stopper.

In the transistor 550 described in this embodiment, a tungsten film or a tantalum nitride film is used as the lower source electrode layer 405c and the drain electrode layer 405d, and a copper film is used as the upper source electrode layer 405a and the drain electrode layer 405b, which are thicker than the lower layers. Alternatively, an aluminum film is used. When the thickness of the source electrode layer 405a and the drain electrode layer 405b in FIG. 4C is set to 5 nm to 15 nm, good coverage with the gate insulating film 402 formed thereover can be obtained. . Note that in this embodiment, the wiring layer 465a and the wiring layer 4
65b can reduce the contact resistance by stacking a tantalum nitride film and a copper film or stacking a tantalum nitride film and a tungsten film.

4D, the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are formed by one photolithography process using the same mask. It has a structure in which an oxide semiconductor stack 403 is formed. In the oxide semiconductor stack 403 included in the transistor 560, the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are oxide semiconductor layers having the same shape and having aligned ends. Become. That is, in the oxide semiconductor stack 403, side surfaces (end portions) of the first oxide semiconductor layer and the second oxide semiconductor layer are exposed.

By forming the oxide semiconductor stack 403 through one photolithography process, the number of processes can be reduced, and the manufacturing cost of the semiconductor device can be reduced. Note that in the transistor 560, the source electrode layer 405a and the drain electrode layer 405b are formed over the third oxide semiconductor so as to be in contact with only the top surface of the third oxide semiconductor layer or only the top surface and side surfaces of the third oxide semiconductor stack. By being provided over the layer, a structure in which the source electrode layer 405a and the drain electrode layer 405b are not in contact with the side surface of the second oxide semiconductor layer can be obtained. Such a structure is preferable because generation of leakage current (parasitic channel) in the source electrode layer and the drain electrode layer of the transistor can be reduced.

The oxide semiconductor stack 403 does not necessarily have to have a three-layer structure. For example, a transistor 570 illustrated in FIG. 4E includes two semiconductor layers including a first oxide semiconductor layer and a second oxide semiconductor layer.
It includes an oxide semiconductor stack 403 having a layered structure. In the transistor 570, the second oxide semiconductor layer overlaps with the first oxide semiconductor layer and has an area larger than that of the first oxide semiconductor layer. It can be configured to wrap. Such a structure suppresses an increase in oxygen vacancies in the first oxide semiconductor layer,
A structure in which the threshold voltage of the transistor is close to zero can be employed. Note that it is preferable to include an aluminum oxide film as the oxide insulating film 436 in the transistor 570 because oxygen can be prevented from being released into the insulating film in contact with the first oxide semiconductor layer.

The transistor 570 illustrated in FIG. 4E has a structure in which the source electrode layer 405a or the drain electrode layer 405b formed over and in contact with the second oxide semiconductor layer does not contact the side surface of the first oxide semiconductor layer. Therefore, leakage current (parasitic channel) in the source electrode layer 405a and the drain electrode layer 405b can be reduced, which is preferable.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment 3)
Using the transistor described in Embodiment 1 or 2, a semiconductor device (also referred to as a display device) having a display function can be manufactured. Further, part or all of a driver circuit including a transistor can be formed over the same substrate as a pixel portion, so that a system-on-panel can be formed.

In FIG. 5A, a sealant 4005 is provided so as to surround a pixel portion 4002 provided over a first substrate 4001 and sealed with a second substrate 4006 . Figure 5 (
In A), in a region different from a region surrounded by the sealant 4005 over the first substrate 4001, a scanning line driver formed of a single crystal semiconductor film or a polycrystalline semiconductor film is formed over a separately prepared substrate. A circuit 4004 and a signal line driver circuit 4003 are mounted. Various signals and potentials applied to the signal line driver circuit 4003, the scanning line driver circuit 4004, or the pixel portion 4002, which are separately formed, are provided by an FPC (flexible printed circuit).
) 4018a, 4018b.

5B and 5C, the pixel portion 400 provided over the first substrate 4001
2 and the scanning line driver circuit 4004, a sealing material 4005 is provided. A second substrate 4006 is provided over the pixel portion 4002 and the scanning line driver circuit 4004 . Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are sealed together with the display element by the first substrate 4001 , the sealant 4005 and the second substrate 4006 . 5B and 5C, a single crystal semiconductor film or a polycrystalline semiconductor is formed over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001 . A signal line driver circuit 4003 formed of a film is mounted. 5(B) and (C)
, various signals and potentials are supplied from the FPC 4018 to the signal line driver circuit 4003 formed separately, the scanning line driver circuit 4004, or the pixel portion 4002 .

5B and 5C show an example in which the signal line driver circuit 4003 is separately formed and mounted over the first substrate 4001; however, the structure is not limited to this. The scanning line driver circuit may be separately formed and mounted, or only part of the signal line driver circuit or part of the scanning line driver circuit may be separately formed and mounted.

Note that the connection method of the separately formed drive circuit is not particularly limited, and COG (Ch
IP On Glass) method, wire bonding method, or TAB (Tape A
Automated Bonding) method or the like can be used. FIG. 5(A) shows C
This is an example of mounting the signal line driving circuit 4003 and the scanning line driving circuit 4004 by the OG method.
FIG. 5B shows an example of mounting the signal line driver circuit 4003 by the COG method, and FIG.
) is an example of mounting the signal line driver circuit 4003 by the TAB method.

Also, the display device includes a panel in which a display element is sealed, and a module in which an IC including a controller is mounted on the panel.

Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). In addition, an IC (integrated circuit) is directly mounted on a connector, for example, a module attached with FPC, TAB tape or TCP, a module with a printed wiring board provided at the tip of TAB tape or TCP, or a display element by the COG method. All modules are assumed to be included in the display device.

In addition, the pixel portion and the scan line driver circuit provided over the first substrate include a plurality of transistors, and any of the transistors described in Embodiments 1 and 2 can be used.

Liquid crystal elements (also called liquid crystal display elements), light emitting elements (
(also referred to as a light-emitting display element) can be used. Light-emitting elements include elements whose luminance is controlled by current or voltage.
Luminescence), organic EL, and the like. In addition, a display medium such as electronic ink whose contrast is changed by an electrical action can also be applied.

One mode of a semiconductor device is described with reference to FIGS. FIG. 6 shows M in FIG. 5(B).
-N corresponds to the cross-sectional view.

As shown in FIGS. 5 and 6, the semiconductor device has connection terminal electrodes 4015 and terminal electrodes 4016, and the connection terminal electrodes 4015 and terminal electrodes 4016 are connected to the terminals of the FPC 4018 via an anisotropic conductive film 4019. , are electrically connected.

The connection terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030, and the terminal electrode 4015
016 is formed using the same conductive film as the source electrode layers and drain electrode layers of the transistors 4040 , 4010 , and 4011 .

In addition, the pixel portion 4002 and the scanning line driver circuit 4004 provided over the first substrate 4001 are
A plurality of transistors are included, and FIG. 6A illustrates a transistor 4040 included in the pixel portion 4002 and a transistor 4011 included in the scan line driver circuit 4004 . In addition, FIG. 6B illustrates a transistor 4010 included in the pixel portion 4002 and a transistor 4011 included in the scan line driver circuit 4004 . In FIG. 6(A),
An insulating film 4020 is provided over the transistors 4040 and 4011, and insulating films 4020 and 4021 are provided over the transistors 4010 and 4011 in FIG. 6B. Note that the insulating film 4023 is an insulating film functioning as a base film.

As the transistor 4011 included in the scan line driver circuit 4004, the transistor having a buried channel described in Embodiment 1 or 2 can be used.
A transistor having a buried channel has high on-characteristics (eg, on-current and field-effect mobility) and enables high-speed operation and high-speed response of the scanning line driver circuit 4004 . In this embodiment, an example of applying a transistor having a structure similar to that of the transistor described in Embodiment 1 is described.

Transistors 4010 and 4040 provided in the pixel portion 4002 are electrically connected to a display element to form a display panel. The display element is not particularly limited as long as it can display, and various display elements can be used.

Further, since the transistor 4040 included in the pixel portion 4002 does not particularly require a buried channel, the transistor 40 having a single-layer oxide semiconductor layer as a channel formation region.
40 is provided. This transistor 4040 can be used as the transistor 4 without increasing the number of steps.
011 can be produced in the same process. The oxide semiconductor layer of the transistor 4040 can be formed in the same step as the third oxide semiconductor layer of the transistor 4011 . The transistor 4040 does not need to have particularly high on-state characteristics unless the display device is large. By using a single-layer oxide semiconductor layer, the transistor 4040 can have a lower off-state current value than the transistor 4011, so that a display device with low power consumption can be realized.

FIG. 6A shows an example of a liquid crystal display device using a liquid crystal element as a display element. In FIG. 6A, a liquid crystal element 4013 which is a display element includes a first electrode layer 4030 and a second electrode layer 403 .
1, and a liquid crystal layer 4008 . Insulating films 4032 and 4033 functioning as alignment films are provided so as to sandwich the liquid crystal layer 4008 . The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 are connected to the liquid crystal layer 400 .
8 are laminated.

4035 is a columnar spacer obtained by selectively etching the insulating film;
It is provided to control the film thickness (cell gap) of the liquid crystal layer 4008 . A spherical spacer may be used.

When a liquid crystal element is used as the display element, thermotropic liquid crystal, low-molecular-weight liquid crystal, polymer liquid crystal, polymer-dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials (liquid crystal compositions) exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc., depending on conditions.

Alternatively, the liquid crystal layer 4008 may be formed using a liquid crystal composition that exhibits a blue phase without using an alignment film. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the temperature of the cholesteric liquid crystal is increased. A blue phase can be developed using a liquid crystal composition in which a liquid crystal and a chiral agent are mixed. Further, in order to widen the temperature range in which the blue phase is exhibited, a polymerizable monomer, a polymerization initiator, and the like are added to the liquid crystal composition that exhibits the blue phase, and a polymer stabilization treatment is performed to form a liquid crystal layer. can also A liquid crystal composition exhibiting a blue phase has a short response speed, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependency. In addition, rubbing treatment is not required because an alignment film is not required, so that electrostatic damage caused by rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. . Therefore, it becomes possible to improve the productivity of the liquid crystal display device. In a transistor including an oxide semiconductor film, the electrical characteristics of the transistor might change significantly due to the influence of static electricity and deviate from the design range. Therefore, it is more effective to use a liquid crystal composition exhibiting a blue phase in a liquid crystal display device including a transistor including an oxide semiconductor film.

Further, the specific resistance of the liquid crystal material is 1×10 ⁹ Ω·cm or more, preferably 1×10 ¹¹ Ω·cm.
Ω·cm or more, more preferably 1×10 ¹² Ω·cm or more. It should be noted that the value of specific resistance in this specification is the value measured at 20°C.

The size of the storage capacitor provided in the liquid crystal display device is set in consideration of the leak current of the transistor arranged in the pixel portion and the like so that the charge can be held for a predetermined period. The size of the storage capacitor may be set in consideration of the off current of the transistor and the like. By using the transistor including the oxide semiconductor film disclosed in this specification, a storage capacitor having a capacitance that is ⅓ or less, preferably ⅕ or less of the liquid crystal capacitance of each pixel is provided. Enough.

The transistor 4040 including the oxide semiconductor film disclosed in this specification can control the current value in the off state (off-state current value) to be low. Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long in the power-on state. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

Further, since the transistor 4011 including the oxide semiconductor film disclosed in this specification can control high field-effect mobility, the scan line driver circuit 4004 can be driven at high speed. According to this embodiment mode, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed on the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced.

Further, in the pixel portion, a transistor including the same stack of oxide semiconductor layers as that of the transistor 4011 may be used. A display can also be provided.

TN (Twisted Nematic) mode, IPS (In-P
lane-switching) mode, FFS (Fringe Field Switch)
ching) mode, ASM (Axially Symmetrically aligned
Micro-cell) mode, OCB (Optical Compensated B)
irefringence) mode, FLC (Ferroelectric Liqui
d Crystal) mode, AFLC (AntiFerroelectric Liq
uid Crystal) mode or the like can be used.

Alternatively, a normally black liquid crystal display device, for example, a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. There are several vertical alignment modes,
For example, MVA (Multi-Domain Vertical Alignment)
mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, and the like can be used. It can also be applied to a VA type liquid crystal display device. What is a VA type liquid crystal display device?
This is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. The VA type liquid crystal display device is of a type in which the liquid crystal molecules are oriented perpendicularly to the panel surface when no voltage is applied. Also, a method called multi-domain formation or multi-domain design, in which a pixel is divided into several regions (sub-pixels) and molecules are tilted in different directions, can be used.

In the display device, optical members (optical substrates) such as a black matrix (light shielding layer), a polarizing member, a retardation member, and an antireflection member are provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Moreover, a backlight, a sidelight, or the like may be used as the light source.

Further, as a display method in the pixel portion, a progressive method, an interlaced method, or the like can be used. Further, the color elements controlled by the pixels for color display are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example RGBW (W stands for white)
, or RGB plus one or more colors such as yellow, cyan, and magenta. note that,
The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a color display device and can also be applied to a monochrome display device.

A light-emitting element utilizing electroluminescence can be used as a display element included in the display device. Light-emitting elements that utilize electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound.
The L element and the latter are called an inorganic EL element.

In the organic EL element, when a voltage is applied to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. Then, recombination of these carriers (electrons and holes) causes the light-emitting organic compound to form an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element. Note that an organic EL element is used as a light-emitting element in this description.

At least one of the pair of electrodes of the light-emitting element needs to be translucent in order to emit light. Then, a transistor and a light-emitting element are formed on a substrate, and top emission for extracting light from the surface opposite to the substrate, bottom emission for extracting light from the surface on the substrate side, and the surface on the side of the substrate and the surface opposite to the substrate. There is a light emitting element with a double emission structure in which light is emitted from a double-sided emission structure, and any light emitting element with an emission structure can be applied.

FIG. 6B shows an example of a light-emitting device using a light-emitting element as a display element. A light-emitting element 4513 which is a display element is electrically connected to the transistor 4010 provided in the pixel portion 4002 . Note that although the structure of the light-emitting element 4513 is a stacked structure of the first electrode layer 4030, the electroluminescent layer 4511, and the second electrode layer 4031, it is not limited to the structure shown. Light emitting element 4513
The structure of the light-emitting element 4513 can be changed as appropriate according to the direction of light extracted from the device.

The partition 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material, form an opening on the first electrode layer 4030, and form an inclined surface with a continuous curvature on the side wall of the opening.

The electroluminescent layer 4511 may be composed of a single layer or may be composed of a plurality of stacked layers.

A protective film may be formed over the second electrode layer 4031 and the partition 4510 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 4513 . As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

Further, a layer containing an organic compound covering the light-emitting element 4513 may be formed by an evaporation method so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 4513 .

A space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 is sealed with a filler 4514. FIG. It is preferable to package (enclose) with a protective film (laminated film, ultraviolet curable resin film, etc.) or a cover material that has high airtightness and little outgassing so as not to be exposed to the outside air.

As the filler 4514, in addition to an inert gas such as nitrogen or argon, ultraviolet curing resin or thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

In addition, if necessary, a polarizing plate or a circularly polarizing plate (including an elliptical polarizing plate) is provided on the exit surface of the light emitting element.
A retardation plate (λ/4 plate, λ/2 plate), an optical film such as a color filter may be provided as appropriate. Also, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be applied to diffuse reflected light by unevenness of the surface and reduce glare.

It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper, also known as an electrophoretic display (electrophoretic display), has the advantages of being as easy to read as paper, consuming less power than other display devices, and being able to be made thin and light. ing.

Various forms of electrophoretic display devices can be conceived, and a plurality of microcapsules containing positively charged first particles and negatively charged second particles are dispersed in a solvent or solute. By applying an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions to display only the color of the particles gathered on one side. The first particles or the second particles contain a dye and do not move in the absence of an electric field. Also, the color of the first particles and the color of the second particles are different (including colorless).

Thus, the electrophoretic display device is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surface of glass, plastic, cloth, paper, and the like. Color display is also possible by using a color filter or pigment-containing particles.

In addition, the first particles and the second particles in the microcapsules are a conductor material, an insulator material,
A material selected from a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof may be used.

A display device using a twist ball display method can also be used as the electronic paper. In the twist ball display method, white and black spherical particles are arranged between a first electrode layer and a second electrode layer, which are electrode layers used in a display element, and the first electrode layer and the second electrode layer are arranged. second
In this method, display is performed by controlling the orientation of spherical particles by generating a potential difference between the electrode layers.

Note that in FIGS. 5 and 6, as the first substrate 4001 and the second substrate 4006, a flexible substrate can be used in addition to a glass substrate. For example, a light-transmitting plastic substrate or the like can be used. can be used. As a plastic, FRP (Fiberglass
s-Reinforced Plastics) board, PVF (polyvinyl fluoride)
A film, polyester film or acrylic resin film can be used. Moreover, if translucency is not required, a metal substrate (metal film) made of aluminum, stainless steel, or the like may be used. For example, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

In this embodiment mode, an aluminum oxide film is used as the insulating film 4020 .

The aluminum oxide film provided as the insulating film 4020 over the oxide semiconductor film has a high shielding effect (blocking effect) of preventing penetration of both oxygen and impurities such as hydrogen and moisture.

Therefore, the aluminum oxide film contains hydrogen, which is a variable factor during and after the manufacturing process.
It functions as a protective film that prevents impurities such as moisture from entering the oxide semiconductor film and prevents oxygen, which is a main component of the oxide semiconductor, from being released from the oxide semiconductor film.

The insulating film 4021 functioning as a planarizing insulating film is made of acrylic resin, polyimide resin,
A heat-resistant organic material such as a benzocyclobutene-based resin, a polyamide resin, or an epoxy resin can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials),
A siloxane-based resin, PSG (phosphorus glass), BPSG (phosphor boron glass), or the like can be used. Note that the insulating film may be formed by stacking a plurality of insulating films formed using these materials.

In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) that apply a voltage to the display element, the direction of light to be extracted, the location where the electrode layer is provided, and Translucency and reflectivity may be selected according to the pattern structure of the electrode layer.

The first electrode layer 4030 and the second electrode layer 4031 are formed of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium oxide. A light-transmitting conductive material such as tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, or graphene can be used.

Further, the first electrode layer 4030 and the second electrode layer 4031 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N
b) metals such as tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag) ,
Alternatively, it can be formed using one or more of its alloys or metal nitrides thereof.

Further, since the transistor is easily destroyed by static electricity or the like, it is preferable to provide a protection circuit for protecting the driver circuit. The protection circuit is preferably configured using nonlinear elements.

By applying the transistor described in Embodiment 1 or 2 as described above,
A semiconductor device having various functions can be provided.

(Embodiment 4)
Using the transistor described in Embodiment 1 or 2, a semiconductor device having an image sensor function for reading information on an object can be manufactured.

FIG. 7A shows an example of a semiconductor device having an image sensor function. FIG. 7A is an equivalent circuit of a photosensor, and FIG. 7B is a cross-sectional view showing part of the photosensor.

The photodiode 602 has one electrode electrically connected to the photodiode reset signal line 658 and the other electrode electrically connected to the gate of the transistor 640 . transistor 640
, one of its source and drain is electrically connected to the photosensor reference signal line 672 and the other of the source and drain is electrically connected to one of the source and drain of the transistor 656 . The transistor 656 has its gate electrically connected to the gate signal line 659 and the other of its source and drain electrically connected to the photosensor output signal line 671 .

Note that in circuit diagrams in this specification, the symbol of a transistor including an oxide semiconductor film is “OS” so that the transistor including an oxide semiconductor film can be clearly identified. In FIG. 7A, the transistor described in Embodiment 1 or 2 can be applied to a transistor 640 and a transistor 656, and an oxide semiconductor stack is used. In this embodiment, an example of applying a transistor having a structure similar to that of the transistor described in Embodiment 1 is described.

FIG. 7B is a cross-sectional view showing a photodiode 602 and a transistor 640 in a photosensor, in which the photodiode 602 and the transistor 640 functioning as a sensor are provided over a substrate 601 (TFT substrate) having an insulating surface. there is A substrate 613 is provided over the photodiode 602 and the transistor 640 using an adhesive layer 608 .

An insulating film 631 , an insulating film 632 , an interlayer insulating film 633 , and an interlayer insulating film 634 are provided over the transistor 640 . The photodiode 602 is provided on the interlayer insulating film 633,
Between the electrode layer 641 formed on the interlayer insulating film 633 and the electrode layer 642 provided on the interlayer insulating film 634, a first semiconductor film 606a and a second semiconductor film 60 are provided in this order from the interlayer insulating film 633 side.
6b and a third semiconductor film 606c.

The electrode layer 641 is electrically connected to the conductive layer 643 formed over the interlayer insulating film 634 , and the electrode layer 642 is electrically connected to the conductive layer 645 through the electrode layer 641 . The conductive layer 645 is
It is electrically connected to the gate electrode layer of the transistor 640 and the photodiode 602 is electrically connected to the transistor 640 .

Here, a semiconductor film having p-type conductivity as the first semiconductor film 606a, a high-resistance semiconductor film (I-type semiconductor film) as the second semiconductor film 606b, and an n-type conductivity as the third semiconductor film 606c. 1 illustrates a pin-type photodiode in which semiconductor films having a structure are stacked.

The first semiconductor film 606a is a p-type semiconductor film and can be formed of an amorphous silicon film containing an impurity element imparting p-type conductivity. The first semiconductor film 606a is formed by plasma CVD using a semiconductor material gas containing a Group 13 impurity element (eg, boron (B)). Silane (SiH ₄ ) may be used as the semiconductor material gas. or S
i ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF ₄ and the like may also be used. Alternatively, after forming an amorphous silicon film containing no impurity element, the impurity element may be introduced into the amorphous silicon film by using a diffusion method or an ion implantation method. The impurity element is preferably diffused by heating or the like after introducing the impurity element by an ion implantation method or the like. Methods for forming an amorphous silicon film in this case include LPCVD, vapor deposition,
Alternatively, a sputtering method or the like may be used. The film thickness of the first semiconductor film 606a is 10 nm or more.
It is preferable to form the film so as to have a thickness of 0 nm or less.

The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film) and is formed of an amorphous silicon film. In forming the second semiconductor film 606b, an amorphous silicon film is formed by a plasma CVD method using a semiconductor material gas. Silane (SiH ₄ ) may be used as the semiconductor material gas. _{Or Si2H6} , _SiH2Cl2 , _{SiHCl3 ,} S
iCl ₄ , SiF ₄ or the like may also be used. The second semiconductor film 606b is formed by the LPCVD method,
A vapor deposition method, a sputtering method, or the like may be used. The film thickness of the second semiconductor film 606b is 2
It is preferable to form the film so as to have a thickness of 00 nm or more and 1000 nm or less.

The third semiconductor film 606c is an n-type semiconductor film and is formed of an amorphous silicon film containing an impurity element imparting n-type conductivity. The third semiconductor film 606c is formed by plasma CVD using a semiconductor material gas containing a Group 15 impurity element (for example, phosphorus (P)). Silane (SiH ₄ ) may be used as the semiconductor material gas. or _{Si2H6 ,}
SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF ₄ and the like may also be used. Alternatively, after forming an amorphous silicon film containing no impurity element, the impurity element may be introduced into the amorphous silicon film by using a diffusion method or an ion implantation method. The impurity element is preferably diffused by heating or the like after introducing the impurity element by an ion implantation method or the like. In this case, an LPCVD method, a vapor deposition method, a sputtering method, or the like may be used as a method for forming an amorphous silicon film. It is preferable to form the third semiconductor film 606c to have a film thickness of 20 nm or more and 200 nm or less.

Further, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c may be formed using a polycrystalline semiconductor instead of an amorphous semiconductor, or may be formed using a microcrystalline (Semi-Amorphous Semiconductor: It may be formed using a SAS)) semiconductor.

Further, since the mobility of holes generated by the photoelectric effect is smaller than the mobility of electrons, the pin-type photodiode exhibits better characteristics when the p-type semiconductor film side is used as the light-receiving surface. Here, p
The photodiode 602 is viewed from the substrate 601 on which the in-type photodiode is formed.
shows an example of converting the light received by the into an electrical signal. In addition, since the light from the semiconductor film side having the conductivity type opposite to that of the semiconductor film side serving as the light-receiving surface becomes ambient light, it is preferable to use a conductive film having a light shielding property for the electrode layer. Also, the n-type semiconductor film side can be used as a light receiving surface.

As the insulating film 632, the interlayer insulating film 633, and the interlayer insulating film 634, an insulating material is used, and depending on the material, a sputtering method, a plasma CVD method, an SOG method, spin coating, dipping, spray coating, or droplet discharge is used. method (inkjet method, etc.), printing method (screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, and the like.

In this embodiment mode, an aluminum oxide film is used as the insulating film 631 . The insulating film 631 can be formed by a sputtering method or a plasma CVD method.

The aluminum oxide film provided as the insulating film 631 over the oxide semiconductor film has a high shielding effect (blocking effect) of preventing penetration of both oxygen and impurities such as hydrogen and moisture.

Therefore, the aluminum oxide film contains hydrogen, which is a variable factor during and after the manufacturing process.
It functions as a protective film that prevents impurities such as moisture from entering the oxide semiconductor film and prevents oxygen, which is a main component of the oxide semiconductor, from being released from the oxide semiconductor film.

As the insulating film 632, inorganic insulating materials such as a silicon oxide layer, a silicon oxynitride layer,
A single layer or a stack of an oxide insulating film such as an aluminum oxide layer or an aluminum oxynitride layer, or a nitride insulating film such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer can be used. can.

As the interlayer insulating films 633 and 634, an insulating film that functions as a planarizing insulating film is preferable in order to reduce surface unevenness. As the interlayer insulating films 633 and 634, heat-resistant organic insulating materials such as polyimide resin, acrylic resin, benzocyclobutene resin, polyamide resin, and epoxy resin can be used. In addition to the above organic insulating materials, low dielectric constant materials (
low-k material), siloxane-based resin, PSG (phosphorus glass), BPSG (phosphor boron glass), etc., may be used as a single layer or a laminate.

By detecting light incident on the photodiode 602, information on the object can be read. A light source such as a backlight can be used when reading information on an object to be detected.

As described above, by using an oxide semiconductor stack having a buried channel, the electrical characteristics of a transistor can be controlled with higher accuracy, and desired electrical characteristics can be imparted to the transistor. Therefore, by using the transistor, a semiconductor device that meets various purposes such as high functionality, high reliability, and low power consumption can be provided.

This embodiment can be implemented in appropriate combination with any structure described in any of the other embodiments.

(Embodiment 5)
The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). Electronic devices include televisions (also called televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, sound Playback devices, gaming machines (pachinko machines, slot machines, etc.), and game cabinets are included. Specific examples of these electronic devices are shown in FIG.

FIG. 8A shows a table 9000 having a display portion. A table 9000 has a display unit 9003 incorporated in a housing 9001 . A semiconductor device manufactured using one embodiment of the present invention can be used for the display portion 9003 and can display images on the display portion 9003 . Note that a configuration in which the housing 9001 is supported by four legs 9002 is shown. Further, the housing 9001 has a power cord 9005 for power supply.

The display portion 9003 has a touch input function, and by touching a display button 9004 displayed on the display portion 9003 of the table 9000 with a finger or the like, it is possible to operate the screen or input information. By enabling communication or control with home appliances, the control device may be configured to control other home appliances through screen operations. For example, with the use of the semiconductor device having an image sensor function described in Embodiment 3, the display portion 9003 can have a touch input function.

In addition, the screen of the display portion 9003 can be set vertically with respect to the floor by a hinge provided in the housing 9001, so that the display portion 9003 can also be used as a television set. In a small room, if a large-screen television is installed, the free space becomes narrow.

FIG. 8B shows a television device 9100. FIG. The television device 9100 is
A display portion 9103 is incorporated in a housing 9101 . A semiconductor device manufactured using one embodiment of the present invention can be used for the display portion 9103 and can display images on the display portion 9103 . Note that a configuration in which the housing 9101 is supported by a stand 9105 is shown here.

The television set 9100 can be operated using operation switches provided in the housing 9101 or a separate remote controller 9110 . Channels and volume can be operated with operation keys 9109 included in the remote controller 9110, and images displayed on the display portion 9103 can be operated. Further, the remote controller 9110 may be provided with a display portion 9107 for displaying information output from the remote controller 9110 .

A television device 9100 shown in FIG. 8B includes a receiver, a modem, and the like. The television apparatus 9100 can receive general television broadcasts by means of a receiver, and can be connected to a wired or wireless communication network via a modem to enable one-way (from the sender to the receiver) or two-way It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

By using the semiconductor device having the embedded channel described in the above embodiment, the semiconductor device can be used for the display portion 9103 of the television device, whereby the television device can have higher display quality than conventional television devices. can.

FIG. 8C shows a computer including a main body 9201, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like.
The computer is manufactured using the semiconductor device manufactured using one embodiment of the present invention for the display portion 9203 .

Further, by using the semiconductor device described in any of the above embodiments for the display portion 9203 of the computer, the display portion can have higher display quality than the conventional display portion.

FIG. 8D shows an example of a mobile phone. A mobile phone 9500 includes a display portion 9502 incorporated in a housing 9501, operation buttons 9503, an external connection port 9504, a speaker 9505, a microphone 9506, and the like. The mobile phone 9500 is manufactured using a semiconductor device manufactured using one embodiment of the present invention for the display portion 9502 .

By touching the display portion 9502 of the mobile phone 9500 shown in FIG. 8D with a finger or the like, operations such as inputting information, making a call, and composing mail can be performed.

The screen of the display unit 9502 mainly has three modes. The first is a display mode mainly for displaying images, and the second is an input mode mainly for inputting information such as characters. The third is a mixture of two modes, a display mode and an input mode.

For example, in the case of making a call or composing an email, the display portion 9502 is set to an input mode mainly for inputting characters, and characters displayed on the screen can be input. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display portion 9502 .

Further, by providing a detection device having a sensor such as a gyro or an acceleration sensor for detecting inclination inside the mobile phone 9500, the orientation of the mobile phone 9500 (vertical or horizontal) can be determined, and the screen of the display unit 9502 can be detected. You can set the display to switch automatically.

Switching of the screen mode is performed by touching the display portion 9502 or operating the operation button 9503 of the housing 9501 . Further, switching can be performed according to the type of image displayed on the display portion 9502 . For example, if the image signal to be displayed on the display unit is moving image data, the mode is switched to the display mode, and if the image signal is text data, the mode is switched to the input mode.

In the input mode, a signal detected by the optical sensor of the display portion 9502 is detected, and if there is no input by a touch operation on the display portion 9502 for a certain period of time, the screen mode is switched from the input mode to the display mode. may be controlled.

The display portion 9502 can also function as an image sensor. For example, personal authentication can be performed by touching the display portion 9502 with a palm or a finger and taking an image of a palm print, a fingerprint, or the like. Further, by using a backlight that emits near-infrared light or a sensing light source that emits near-infrared light for the display portion, an image of a finger vein, a palm vein, or the like can be captured.

When the semiconductor device described in any of the above embodiments is used, color bleeding, color shift, and the like are less likely to occur in a display. It is possible to make a mobile phone with a high In addition, since the pair of substrates are held by the light-shielding spacers, the device is extremely resistant to external forces such as impact and distortion, and can be suitably used as the mobile phone shown in FIG. 8D.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

In this example, a second oxide semiconductor layer having an energy gap smaller than that of the first oxide semiconductor layer is formed over the first oxide semiconductor layer, and a second oxide semiconductor layer is formed over the second oxide semiconductor layer. A sample in which the oxide semiconductor layer of No. 3 was formed was manufactured, the ionization potential of the sample was measured, and an energy band diagram was calculated based on the result. In this specification, the value of ionization potential is the value obtained by adding the bandgap and electron affinity, and the value of bandgap is the value obtained by measuring a single film of material with ellipsometer.

The sample was an IGZO film with a thickness of 5 nm and an In—Sn film with a thickness of 5 nm over a single crystal silicon substrate.
- A Zn-based oxide film and a 5 nm-thickness IGZO film were laminated. Each film was formed under conditions of a substrate temperature of 300° C. and an oxygen atmosphere (oxygen 100%) using a sputtering method. An IGZO film was formed using an oxide target of In:Ga:Zn=1:1:1 [atomic ratio] as a target. Further, the In—Sn—Zn-based oxide film has In:Sn:Zn=
An oxide target of 2:1:3 [atomic ratio] is used.

Further, using a quartz substrate as a substrate, a first IGZO film 1001 with a thickness of 5 nm, an In--Sn--Zn-based oxide film 1002 with a thickness of 5 nm, and a second IGZO film 1002 with a thickness of 5 nm were formed over the quartz substrate 1000 under the same film formation conditions. FIG. 11A is a TEM photograph of a cross section of Sample 2 obtained by laminating the IGZO film 1003 of . Note that a schematic diagram is shown in FIG. In FIG. 11(B),
Although the interface of the oxide semiconductor layer is illustrated with a dotted line, it is schematically illustrated. The interface with each oxide semiconductor layer may be unclear depending on the material, deposition conditions, and heat treatment. Figure 1
In Sample 2 of 1A, an interface between the In--Sn--Zn-based oxide film and the IGZO film can be confirmed. In addition, in FIG. 11A, the second IGZO film 1003 and the In--Sn--Zn-based oxide film 1002 contain crystals and are crystalline oxide semiconductor films having c-axis orientation (CAAC- O.
S film). Further, in FIG. 11A, the first IGZO film 1001
is an amorphous structure. Note that in FIG. 11A, two of the three layers are oxide semiconductor films having a crystalline structure; however, there is no particular limitation, and only the second IGZO film 1003 has a crystalline structure. Alternatively, all three layers may have a crystalline structure, or all three layers may have an amorphous structure.

While sputtering from the surface of sample 1, ultraviolet photoelectron spectroscopy (UPS: Ultra
FIG. 9 shows the result of measuring the ionization potential by aviolet Photoelectron Spectroscopy).

In FIG. 9, the horizontal axis represents the sputtering time from the sample surface, and the vertical axis represents the ionization potential. Note that the sample boundaries are shown on the assumption that the IGZO film and the In—Sn—Zn-based oxide film have the same sputtering rate. From FIG. 9, it can be seen that the ionization potential is lowered in the In--Sn--Zn-based oxide film sandwiched between the IGZO films. note that,
The ionization potential represents the energy difference from the vacuum level to the valence band.

The energy of the conduction band was calculated by subtracting the bandgap measured by ellipsometry from the value of the ionization potential, and the band structure of this laminated film was created. However, the IGZO film and the In-
The bandgaps of the Sn--Zn oxide films were set to 3.2 eV and 2.8 eV, respectively. The result is shown in FIG. It can be seen from FIG. 10 that a buried channel is formed as shown in the energy band diagram of FIG. 1(D).

In this example, IGZO films were used as the first oxide semiconductor layer and the third oxide semiconductor layer, and had a higher ionization potential than the first oxide semiconductor layer and the third oxide semiconductor layer. In addition, In—Sn as the second oxide semiconductor layer having a small energy gap
It was confirmed that the stack using the -Zn-based oxide film can be represented by the energy band diagram shown in FIG. 10 or FIG. There is no particular limitation on the combination of materials for the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer.
In order to obtain the energy band diagram shown in , a material may be selected and combined as appropriate in consideration of the energy gap of the materials used by the practitioner.
An IGZO film is used as the oxide semiconductor layer of the second oxide semiconductor layer, and an In—Sn—Z film is used as the second oxide semiconductor layer.
A lamination using an n-type oxide film may be used.

101 oxide semiconductor layer 102 oxide semiconductor layer 103 oxide semiconductor layer 111 excess oxygen region 112 excess oxygen region 113 excess oxygen region 121a first low-resistance region 121b first low-resistance region 121c channel formation region 121d first region 121e First region 122a Second low resistance region 122b Second low resistance region 122c Channel formation region 122d Second region 122e Second region 123a Third low resistance region 123b Third low resistance region 123c Channel formation Region 123d Third region 123e Third region 131d First region 131e First region 132d Second region 132e Second region 133d Third region 400 Substrate 401 Gate electrode layer 402 Gate insulating film 403 Oxide semiconductor Stack 405a Source electrode layer 405b Drain electrode layer 405c Source electrode layer 405d Drain electrode layer 407 Insulating film 421 Dopant 431 Oxygen 436 Oxide insulating film 442 Gate insulating film 465a Wiring layer 465b Wiring layer 510 Transistor 520 Transistor 530 Transistor 540 Transistor 550 Transistor 560 Transistor 570 Transistor 601 Substrate 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c Semiconductor film 608 Adhesive layer 613 Substrate 631 Insulating film 632 Insulating film 633 Interlayer insulating film 634 Interlayer insulating film 640 Transistor 641 Electrode layer 642 Electrode layer 643 Conductive layer 645 Conductive layer 656 transistor 658 photodiode reset signal line 659 gate signal line 671 photosensor output signal line 672 photosensor reference signal line 1000 quartz substrate 1001 first IGZO film 1002 In—Sn—Zn oxide film 1003 second IGZO film 4001 Substrate 4002 Pixel portion 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealant 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC
4019 Anisotropic conductive film 4020 Insulating film 4021 Insulating film 4023 Insulating film 4030 Electrode layer 4031 Electrode layer 4032 Insulating film 4040 Transistor 4510 Partition 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filler 9000 Table 9001 Housing 9002 Leg 9003 Display 9004 Display button 9005 Power cord 9100 Television device 9101 Housing 9103 Display unit 9105 Stand 9107 Display unit 9109 Operation keys 9110 Remote controller 9201 Main unit 9202 Housing 9203 Display unit 9204 Keyboard 9205 External connection port 9206 Pointing device 9500 Mobile phone 9501 Housing 9502 Display unit 9503 Operation button 9504 External connection port 9505 Speaker 9506 Microphone

Claims (1)

an oxide semiconductor layer;
a gate electrode layer overlapping with the oxide semiconductor layer via a gate insulating film;
a source electrode layer electrically connected to the oxide semiconductor layer;
a drain electrode layer electrically connected to the oxide semiconductor layer;
The oxide semiconductor layer has a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer,
the first oxide semiconductor layer contains In, Sn, and Zn;
the second oxide semiconductor layer contains In, Ga, and Zn;
an energy gap of the first oxide semiconductor layer is smaller than an energy gap of the second oxide semiconductor layer;
The semiconductor device, wherein the second oxide semiconductor layer has a crystal structure.

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