JP2022188699A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

To provide a semiconductor device which improves adhesion to a mounting object when mounted on the mounting object.SOLUTION: A semiconductor device A1 includes: a first semiconductor chip 31; a metal substrate 10 having the first semiconductor chip 31 mounted on one side in a thickness direction z; and a resin member 70 formed on the side where the first semiconductor chip 31 is mounted of the metal substrate 10 in the thickness direction z. The resin ember 70 has: a first resin layer 71 formed on the metal substrate 10 and covering the first semiconductor chip 31; and a second resin layer 72 formed on the first resin layer 71. A different between a coefficient of thermal expansion of the first resin layer 71 and a coefficient of thermal expansion of the first semiconductor chip 31 is smaller than a difference between the coefficient of thermal expansion of the first resin layer 71 and a coefficient of thermal expansion of the metal substrate 10, and a coefficient of thermal expansion of the second resin layer 72 is higher than the coefficient of thermal expansion of the first resin layer 71.SELECTED DRAWING: Figure 12

Description

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device.

2. Description of the Related Art Conventionally, semiconductor devices equipped with power semiconductor elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are widely known. Such a semiconductor device constitutes a part of a power converter such as an inverter, for example. Patent Literature 1 discloses an example of a semiconductor device equipped with a power semiconductor element. When the semiconductor device is used, heat is generated from the power semiconductor element. For example, the semiconductor device described in Patent Literature 1 is configured to be attachable with radiation fins as a cooler in order to radiate heat generated by the power semiconductor element.

JP 2020-92223 A

When a cooler is attached to a semiconductor device, heat may not be properly transferred from the semiconductor device to the cooler if the cooler and the semiconductor device are not tightly adhered to each other. If the heat is not properly transferred, the heat from the power semiconductor element stays in the semiconductor device, causing deterioration in the performance of the power semiconductor element and destruction of the element. In particular, as the output power of semiconductor devices increases, the amount of heat generated by power semiconductor elements tends to increase. Therefore, it is required to improve the adhesion between the semiconductor device and the cooler. Moreover, unlike the configuration of Patent Document 1, even in the configuration in which the semiconductor device is attached to the circuit board instead of the cooler and the heat is transferred to the circuit board, the semiconductor device and the circuit board are required to have good adhesion. In other words, it is required to improve the adhesion between the semiconductor device and the mounting object.

The present disclosure has been conceived in view of the above circumstances, and an object of the present disclosure is to provide a semiconductor device capable of improving adhesion to an attachment target when attached to the attachment target. be. Another object of the present invention is to provide a method of manufacturing a semiconductor device that provides good adhesion to an object to be attached.

A semiconductor device provided by a first aspect of the present disclosure includes: a first semiconductor chip; a metal substrate on which the first semiconductor chip is mounted on one side in a thickness direction; a resin member formed on the side on which the first semiconductor chip of is mounted, the resin member being a first resin layer formed on the metal substrate and covering the first semiconductor chip; and a second resin layer formed on the first resin layer, wherein the coefficient of thermal expansion of the first resin layer is different from the coefficient of thermal expansion of the first semiconductor chip by the coefficient of thermal expansion of the metal substrate. The coefficient of thermal expansion of the second resin layer is higher than the coefficient of thermal expansion of the first resin layer.

A method of manufacturing a semiconductor device provided by a second aspect of the present disclosure includes steps of preparing a metal substrate, and mounting a first semiconductor chip on one side of the metal substrate in a thickness direction of the metal substrate. and a resin member forming step of forming a resin member on the side of the metal substrate on which the first semiconductor chip is mounted in the thickness direction, wherein the resin member forming step comprises: A first resin layer is arranged to cover the first semiconductor chip, and a second resin layer is arranged on the first resin layer, and the coefficient of thermal expansion of the first resin layer is equal to the first resin layer. The difference from the thermal expansion coefficient of the semiconductor chip is smaller than the difference from the thermal expansion coefficient of the metal substrate, and the thermal expansion coefficient of the second resin layer is higher than the thermal expansion coefficient of the first resin layer.

According to the semiconductor device of the present disclosure, it is possible to improve adhesion to an attachment target such as a cooler. Further, according to the method of manufacturing a semiconductor device of the present disclosure, it is possible to manufacture a semiconductor device having good adhesion to an attachment object such as a cooler.

1 is a perspective view showing a semiconductor device according to a first embodiment; FIG. FIG. 2 is a plan view of the semiconductor device according to the first embodiment; FIG. FIG. 3 is a perspective view of FIG. 1 with resin members and wires omitted. FIG. 4 is a diagram showing the resin member in imaginary lines in the plan view of FIG. FIG. 5 is a front view of the semiconductor device according to the first embodiment; FIG. 6 is a right side view of the semiconductor device according to the first embodiment; 7 is a left side view of the semiconductor device according to the first embodiment; FIG. 8 is a bottom view of the semiconductor device according to the first embodiment; FIG. 9 is a right side enlarged view of the plan view shown in FIG. 4. FIG. 10 is an enlarged left side view of the plan view shown in FIG. 4. FIG. 11 is a cross-sectional view along line XI-XI in FIG. 4. FIG. FIG. 12 is a cross-sectional view along line XII-XII in FIG. FIG. 13 is a cross-sectional view along line XIII-XIII in FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 4. FIG. FIG. 15 is a partially enlarged view of FIG. 9 (around the first semiconductor chip). 16 is a cross-sectional view taken along line XVI--XVI of FIG. 15. FIG. FIG. 17 is a partially enlarged view (periphery of the second semiconductor chip) of FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 17. FIG. 19 is a cross-sectional view showing a state in which the semiconductor device in which the resin member is composed only of the first resin layer is attached to the cooler, and is a cross-sectional view corresponding to FIG. 12. FIG. 20 is a cross-sectional view showing a state in which the semiconductor device according to the first embodiment is attached to the cooler, and is a cross-section corresponding to FIG. 12. FIG. 21 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment, the cross-section corresponding to FIG. 12. FIG. 22 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment, the cross-section corresponding to FIG. 12. FIG. 23 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment, the cross-section corresponding to FIG. 12. FIG. FIG. 24 is a perspective view showing a semiconductor device according to a second embodiment; 25 is a perspective view of FIG. 24 with the resin member omitted. FIG. 26 is a plan view of the semiconductor device according to the second embodiment, showing the resin member with imaginary lines. 27 is a partially enlarged view of FIG. 26. FIG. FIG. 28 is a bottom view of the semiconductor device according to the second embodiment; 29 is a cross-sectional view along line XXIX-XXIX in FIG. 26. FIG. 30 is a cross-sectional view taken along line XXX-XXX in FIG. 26. FIG.

Preferred embodiments of the present disclosure will be described with reference to the drawings. Below, the same or similar components are denoted by the same reference numerals, and overlapping descriptions are omitted.

The terms "first", "second", "third", etc. in this disclosure are used merely as labels and are not necessarily intended to impose a permutation of the objects.

In the present disclosure, "a certain entity A is formed on a certain entity B" and "a certain entity A is formed on (of) an entity B" mean "a certain entity A is directly formed in a certain thing B", and "a certain thing A is formed in a certain thing B while another thing is interposed between a certain thing A and a certain thing B" including. Similarly, ``an entity A is arranged on an entity B'' and ``an entity A is arranged on (of) an entity B'' mean ``an entity A being placed directly on a certain thing B", and "a thing A being placed on a certain thing B with another thing interposed between something A and something B" include. Similarly, unless otherwise specified, ``an object A is located on (of) an object B'' means ``a certain object A is in contact with an object B, and an object A is located on an object B. Being located on (of)" and "something A is located on (something) B while another thing is interposed between something A and something B including "things". In addition, unless otherwise specified, ``an object A overlaps an object B when viewed in a certain direction'' means ``an object A overlaps all of an object B'' and ``an object A overlaps an object B.'' It includes "overlapping a part of a certain thing B".

<First embodiment>
1 to 18 show a semiconductor device A1 according to the first embodiment. As shown in FIGS. 1 to 18, a semiconductor device A1 includes a metal substrate 10, a plurality of terminals, a plurality of first semiconductor chips 31, a plurality of second semiconductor chips 32, a plurality of conductive members 40, a plurality of wires, a second It has a first layer 51 , a second layer 52 , a third layer 53 , a case 60 and a resin member 70 . In this embodiment, the plurality of terminals includes a first power terminal 23A, a second power terminal 23B, an output terminal 24, a first gate terminal 25A, a second gate terminal 25B, a first detection terminal 26A, a second detection terminal 26B, It has a power supply current detection terminal 27 and a thermistor terminal 28 . The plurality of wires includes a plurality of first gate wires 431, a plurality of second gate wires 432, a third gate wire 433, a fourth gate wire 434, a plurality of first detection wires 441, and a plurality of second detection wires 442. , a third sensing wire 443 , a fourth sensing wire 444 , a supply current sensing wire 45 and a pair of thermistor wires 46 . For convenience of understanding, FIG. 3 omits the resin member 70 and the plurality of wires. Moreover, FIG. 4 omits the resin member 70 .

A semiconductor device A1 shown in FIG. 1 is a power module. The semiconductor device A1 is used in inverters for various electric appliances and hybrid vehicles. As shown in FIGS. 1 and 2, the semiconductor device A1 has a substantially rectangular shape when viewed in the thickness direction z of the metal substrate 10 (hereinafter abbreviated as "thickness direction z"). Here, for convenience of explanation, the direction orthogonal to the thickness direction z is called the first direction x. A direction orthogonal to both the thickness direction z and the first direction x is called a second direction y. The first direction x is the longitudinal direction of the semiconductor device A1.

The metal substrate 10 supports a plurality of first semiconductor chips 31, a plurality of second semiconductor chips 32, and the like. The metal substrate 10 has a conductor layer 11, a metal base 12 and an insulating layer 13, as shown in FIG.

The metal base 12 is located on the side opposite to the conductor layer 11 (the other side in the thickness direction z) with respect to the insulating layer 13 , and the insulating layer 13 is laminated on the metal base 12 . The metal base 12 is made of a conductive metal material, such as a metal plate made of aluminum or an aluminum alloy. The metal base 12 may be copper or a copper alloy instead of aluminum or an aluminum alloy.

The metal base 12 has a main surface 12a and a back surface 12b. The main surface 12a and the back surface 12b are spaced apart in the thickness direction z. An insulating layer 13 is formed on the main surface 12a. The back surface 12b faces the opposite side of the principal surface 12a in the thickness direction z and is exposed from the case 60 . In the example shown in FIG. 12, the back surface 12b is convex, for example. That is, the back surface 12b is curved and convex downward in the thickness direction z. In this example, part of the back surface 12b bulges below the case 60 . The back surface 12b may be a substantially flat surface orthogonal to the thickness direction z. However, the back surface 12b does not curve concavely in the thickness direction z due to the configuration described in detail later.

The insulating layer 13 is interposed between the conductor layer 11 and the metal base 12 in the thickness direction z. The insulating layer 13 has electrical insulation. The constituent material of the insulating layer 13 is, for example, an epoxy resin, but may be a prepreg.

As an example of the thicknesses of the conductor layer 11, the metal base 12 and the insulating layer 13, the thickness of the conductor layer 11 is 0.1 mm or more and 2.0 mm or less, and the thickness of the metal base 12 is 0.3 mm. The thickness of the insulating layer 13 is 0.12 mm or more and 0.18 mm or less.

The conductor layer 11 is laminated on the insulating layer 13 . The conductor layer 11 includes a mounting surface 11a. The mounting surface 11a faces one side in the thickness direction z (the upper side in FIG. 11). The conductor layer 11 is made of a conductive metal material, such as a metal foil made of copper (Cu) or a copper alloy.

In this embodiment, the conductor layer 11 includes a first wiring portion 111, a second wiring portion 112, a third wiring portion 113, a first gate portion 114, a first detection portion 115, a pair of thermistor mounting portions 116, a second A gate portion 117 and a second detection portion 118 are included. Each part constituting the conductor layer 11 is formed, for example, by partially removing the copper foil laminated on the insulating layer 13 by wet etching. The surface of each portion of the conductor layer 11 may be plated with silver (Ag).

As shown in FIGS. 4 and 9 to 12, a plurality of first semiconductor chips 31 are mounted on the first wiring portion 111. As shown in FIG. As shown in FIG. 4 and the like, the first wiring portion 111 is positioned on one end side (upper side in FIG. 4) of the metal substrate 10 in the second direction y. The first wiring portion 111 has a strip shape extending in the first direction x. In the semiconductor device A1, ten first semiconductor chips 31 are mounted on the first wiring portion 111, but the number of the first semiconductor chips 31 is not limited to this. A strip-shaped pad 111a extending in the second direction y is formed at one end (right side in FIG. 4) of the first wiring portion 111 in the first direction x.

As shown in FIGS. 4 , 9 , 10 and 12 , a plurality of second semiconductor chips 32 are mounted on the second wiring section 112 . As shown in FIG. 4 and the like, the second wiring portion 112 is positioned between the first wiring portion 111 and the third wiring portion 113 in the second direction y. The second wiring portion 112 has a strip shape extending in the first direction x. In the semiconductor device A1, ten second semiconductor chips 32 are mounted on the second wiring portion 112, but the number of the second semiconductor chips 32 is not limited to this. A strip-shaped pad 112a extending in the second direction y is formed at one end (left side in FIG. 4) of the second wiring portion 112 in the first direction x. A portion of the pad 112a located on one side (upper side in FIG. 4) of the second wiring portion 112 in the second direction y is located next to the first wiring portion 111 in the first direction x. A portion of the pad 112a positioned on the other side (lower side in FIG. 4) of the second wiring portion 112 in the second direction y is positioned next to the third wiring portion 113 in the first direction x.

As shown in FIGS. 4, 9 and 10, the third wiring section 113 is electrically connected to the multiple first semiconductor chips 31 and the multiple second semiconductor chips 32 . The third wiring portion 113 is located on the side opposite to the first wiring portion 111 with respect to the second wiring portion 112 in the second direction y. The third wiring portion 113 has a strip shape extending in the first direction x. A strip-shaped pad 113a extending in the second direction y is formed at one end (right side in FIG. 4) of the third wiring portion 113 in the first direction x. As shown in FIG. 4, the third wiring portion 113 is formed with a notch 113b extending in the first direction x. The notch 113b is positioned in the center of the third wiring portion 113 in the second direction y and extends from one end (the right end in FIG. 4) in the first direction x to the center in the first direction x.

The first gate section 114 is electrically connected to the plurality of first semiconductor chips 31 as shown in FIGS. 4, 9 and 10 . The first gate portion 114 has a strip shape extending in the first direction x. The first gate portion 114 is positioned between the first wiring portion 111 and the case 60 in the second direction y. In the semiconductor device A1, the first gate portions 114 are folded at one end portion (the right end portion in FIG. 4) in the first direction x, and are formed in two rows in the second direction y. The width (dimension in the second direction y) of the first gate portion 114 is smaller than the widths of the first wiring portion 111, the second wiring portion 112, and the third wiring portion 113, respectively.

The first detector 115 is electrically connected to the plurality of first semiconductor chips 31 as shown in FIGS. 4, 9 and 10 . The first detection unit 115 has a strip shape extending in the first direction x. The first detector 115 is located between the first wiring part 111 and the case 60 in the second direction y. In the semiconductor device A1, the first detectors 115 are folded at one end (the left end in FIG. 4) in the first direction x, and formed in two rows in the second direction y. The width of the first detection section 115 (dimension in the second direction y) is the same as the width of the first gate section 114 .

As shown in FIGS. 4 and 9, the pair of thermistor mounting portions 116 are spaced apart from each other in the second direction y and mount the thermistor 33 thereon. A pair of thermistor mounting portions 116 are positioned near the corners of the metal substrate 10 . The first wiring portion 111 , the first gate portion 114 and the first detection portion 115 are positioned around the pair of thermistor mounting portions 116 .

The second gate portion 117 is electrically connected to the plurality of second semiconductor chips 32, as shown in FIGS. The second gate portion 117 has a strip shape extending in the first direction x. The second gate portion 117 is positioned between the third wiring portion 113 and the case 60 in the second direction y. In the semiconductor device A1, the second gate portions 117 are folded back at one end portion (the left end portion in FIG. 4) in the first direction x, and are formed in two rows in the second direction y. The width (dimension in the second direction y) of the second gate portion 117 is smaller than the widths of the first wiring portion 111, the second wiring portion 112, and the third wiring portion 113, respectively.

The second detector 118 is electrically connected to the plurality of second semiconductor chips 32, as shown in FIGS. The second detector 118 has a strip shape extending in the first direction x. The second detection section 118 is positioned between the third wiring section 113 and the case 60 in the second direction y. In the semiconductor device A1, the second detectors 118 are folded at one end (the right end in FIG. 4) in the first direction x, and formed in two rows in the second direction y. The width of the second detection section 118 (dimension in the second direction y) is the same as the width of the second gate section 117 .

The first power terminal 23A and the second power terminal 23B are part of the external connection terminals provided on the semiconductor device A1, as shown in FIGS. 2 to 4 and the like. The first power terminal 23A and the second power terminal 23B are connected to a DC power supply arranged outside the semiconductor device A1. The first power terminal 23A and the second power terminal 23B are supported by the case 60 . The first power terminal 23A and the second power terminal 23B are made of metal plates. A constituent material of the metal plate is, for example, copper. The thickness of first power terminal 23A and second power terminal 23B is, for example, about 1.0 mm.

The first power terminal 23A is a positive electrode (P terminal). The first power terminal 23A is connected to the pad 111a of the first wiring portion 111. As shown in FIG. The second power terminal 23B is a negative electrode (N terminal). The second power terminal 23B is connected to the pad 113a of the third wiring portion 113. As shown in FIG. The first power terminal 23A and the second power terminal 23B are separated from each other in the second direction y.

As shown in FIGS. 9 and 13, each of the first power terminal 23A and the second power terminal 23B has an external connection portion 231, an internal connection portion 232 and an intermediate portion 233. As shown in FIGS.

The external connection portion 231 is exposed in the semiconductor device A1 and has a flat plate shape orthogonal to the thickness direction z. A DC power cable or the like is connected to the external connection portion 231 . The external connection portion 231 is supported by the case 60 . The external connection portion 231 is provided with a connection hole 231a penetrating in the thickness direction z. A fastening member such as a bolt is inserted into the connection hole 231a. Note that the surface of the external connection portion 231 may be plated with nickel (Ni).

The internal connection portion 232 is connected to the pad 111a of the first wiring portion 111 at the first power terminal 23A, and is connected to the pad 113a of the third wiring portion 113 at the second power terminal 23B. The internal connection portion 232 has a comb shape. In the semiconductor device A1, the internal connection portion 232 has three teeth, and these multiple teeth are arranged along the second direction y. A plurality of teeth are bent in the thickness direction z. Therefore, the plurality of teeth are hook-shaped when viewed in the second direction y. All of the teeth are connected to pad 111a or pad 113a by ultrasonic bonding.

The intermediate portion 233 connects the external connection portion 231 and the internal connection portion 232 to each other. The intermediate portion 233 has an L-shaped cross section with respect to the first direction x. The intermediate portion 233 has a base portion 233a and an upright portion 233b. The base 233a extends along the first direction x and the second direction y. One end of the base portion 233 a in the first direction x is connected to the internal connection portion 232 . The standing portion 233b stands up in the thickness direction z from the base portion 233a. One end of the standing portion 233 b in the thickness direction z is connected to the external connection portion 231 .

The output terminals 24 are part of the external connection terminals provided on the semiconductor device A1, as shown in FIGS. 2 to 4 and the like. The output terminal 24 is connected to a power supply object (such as a motor) arranged outside the semiconductor device A1. The output terminal 24 is supported by the case 60 and located on the side opposite to the first power terminal 23A and the second power terminal 23B with respect to the metal substrate 10 in the first direction x. The output terminal 24 is made of a metal plate. A constituent material of the metal plate is, for example, copper. The thickness of output terminal 24 is, for example, 1.0 mm.

In the semiconductor device A1, the output terminal 24 is separated into two, a first terminal portion 24A and a second terminal portion 24B. Note that the output terminal 24 may be a single member that is not separated, unlike this configuration. The first terminal portion 24A and the second terminal portion 24B are conductively joined to the second wiring portion 112 . The first terminal portion 24A and the second terminal portion 24B are separated from each other in the second direction y.

As shown in FIGS. 10 and 14, each of the first terminal portion 24A and the second terminal portion 24B has an external connection portion 241, an internal connection portion 242 and an intermediate portion 243. As shown in FIGS.

The external connection portion 241 is exposed in the semiconductor device A1 and has a flat plate shape orthogonal to the thickness direction z. A cable or the like that conducts to a power supply target is connected to the external connection portion 241 . The external connection portion 241 is supported by the case 60 . The external connection portion 241 is provided with a connection hole 241a penetrating in the thickness direction z. A fastening member such as a bolt is inserted into the connection hole 241a. Note that the surface of the external connection portion 241 may be plated with nickel.

The internal connection portion 242 is connected to the pad 112 a of the second wiring portion 112 . The internal connection portion 242 has a comb shape. In the semiconductor device A1, the internal connection portion 242 has three teeth, and these multiple teeth are arranged along the second direction y. A plurality of teeth are bent in the thickness direction z. Therefore, the plurality of teeth are hook-shaped when viewed in the second direction y. All of the teeth are connected to the pad 112a by ultrasonic bonding.

The intermediate portion 243 connects the external connection portion 241 and the internal connection portion 242 to each other. The intermediate portion 243 has an L-shaped cross section with respect to the first direction x. The intermediate portion 243 has a base portion 243a and an upright portion 243b. The base 243a extends along the first direction x and the second direction y. One end of the base portion 243 a in the first direction x is connected to the internal connection portion 242 . The standing portion 243b stands up in the thickness direction z from the base portion 243a. One end of the standing portion 243 b in the thickness direction z is connected to the external connection portion 241 .

The first gate terminal 25A and the second gate terminal 25B are external connection terminals provided in the semiconductor device A1, as shown in FIGS. 2 to 5 and the like. The first gate terminal 25A and the second gate terminal 25B are each connected to a driving circuit (eg, gate driver) of the semiconductor device A1 arranged outside. The first gate terminal 25A and the second gate terminal 25B are supported by the case 60 respectively. Each of the first gate terminal 25A and the second gate terminal 25B is composed of a metal rod. A constituent material of the metal bar is, for example, copper or a copper alloy. The surfaces of the first gate terminal 25A and the second gate terminal 25B may be plated with tin (Sn) or nickel and tin. As shown in FIG. 12, each of the first gate terminal 25A and the second gate terminal 25B has an L-shaped cross section with respect to the first direction x. A part of each of the first gate terminal 25A and the second gate terminal 25B protrudes from the case 60 toward the mounting surface 11a of the conductor layer 11 (metal substrate 10) in the thickness direction z.

The first gate terminal 25A is electrically connected to the first gate section 114 . The first gate terminal 25A is close to the first gate section 114 in the second direction y, as shown in FIG. The second gate terminal 25B conducts to the second gate section 117 . As shown in FIG. 9, the second gate terminal 25B is located on the side opposite to the first gate terminal 25A with respect to the conductor layer 11 (metal substrate 10) in the second direction y. The second gate terminal 25B is close to the second gate section 117 .

The first detection terminal 26A and the second detection terminal 26B are part of the external connection terminals provided on the semiconductor device A1, as shown in FIGS. 2 to 5 and the like. The first detection terminal 26A and the second detection terminal 26B are each connected to a control circuit of the semiconductor device A1 arranged outside. The first detection terminal 26A and the second detection terminal 26B are supported by the case 60 respectively. 26 A of 1st detection terminals and the 2nd detection terminal 26B are each comprised from a metal rod. A constituent material of the metal bar is, for example, copper or a copper alloy. The surfaces of the first detection terminal 26A and the second detection terminal 26B may be tin-plated, or nickel-plated and tin-plated. As shown in FIG. 12, each of the first detection terminal 26A and the second detection terminal 26B has an L-shaped cross section with respect to the first direction x. A part of each of the first detection terminal 26A and the second detection terminal 26B protrudes from the case 60 toward the mounting surface 11a of the conductor layer 11 (metal substrate 10) in the thickness direction z.

The first detection terminal 26A is electrically connected to the first detection section 115 . The first detection terminal 26A is located next to the first gate terminal 25A in the first direction x, as shown in FIG. The second detection terminal 26B is electrically connected to the second detection section 118 . The second detection terminal 26B is located next to the second gate terminal 25B in the first direction x, as shown in FIG.

As shown in FIGS. 2 to 5 and 10, the semiconductor device A1 has a power supply current detection terminal 27. FIG. The power supply current detection terminal 27 is part of the external connection terminals provided on the semiconductor device A1. The power supply current detection terminal 27 is connected to the control circuit of the semiconductor device A1 arranged outside. The power supply current detection terminal 27 is supported by the case 60 . The power supply current detection terminal 27 is composed of a metal rod. A constituent material of the metal bar is, for example, copper or a copper alloy. The surface of the power supply current detection terminal 27 may be tin-plated, or nickel-plated and tin-plated. The shape of the power supply current detection terminal 27 is the same as each of the first gate terminal 25A and the second gate terminal 25B shown in FIG. A part of the power supply current detection terminal 27 is the mounting surface of the conductor layer 11 (metal substrate 10) in the thickness direction z from the case 60, like each of the first gate terminal 25A and the second gate terminal 25B shown in FIG. It protrudes to the side to which 11a faces. In the second direction y, the position of the power supply current detection terminal 27 is the same as the position of the first gate terminal 25A. The power supply current detection terminal 27 is separated from the first gate terminal 25A toward the first terminal portion 24A in the first direction x.

As shown in FIGS. 2 to 5 and 9, the semiconductor device A1 has a pair of thermistor terminals 28. As shown in FIG. The pair of thermistor terminals 28 are part of the external connection terminals provided on the semiconductor device A1. A pair of thermistor terminals 28 are connected to a control circuit of the semiconductor device A1 arranged outside. A pair of thermistor terminals 28 are supported by a case 60 . A pair of thermistor terminals 28 are composed of metal rods. A constituent material of the metal bar is, for example, copper or a copper alloy. Each surface of the pair of thermistor terminals 28 may be tin-plated, or nickel-plated and tin-plated. The shape of the pair of thermistor terminals 28 is the same as each of the first gate terminal 25A and the second gate terminal 25B shown in FIG. A part of the pair of thermistor terminals 28, like the first gate terminal 25A and the second gate terminal 25B shown in FIG. It protrudes to the side to which 11a faces. In the second direction y, the position of the pair of thermistor terminals 28 is the same as the position of the first gate terminal 25A. The pair of thermistor terminals 28 are separated from the first gate terminal 25A toward the first power supply terminal 23A in the first direction x. The pair of thermistor terminals 28 are separated from each other in the first direction x.

Each of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 has a semiconductor layer containing silicon carbide (SiC), for example, and has a switching function. Each of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 is a MOSFET configured using a semiconductor material mainly composed of silicon carbide. Each semiconductor layer of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 may contain silicon (Si) instead of SiC. Moreover, the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 are not limited to MOSFETs, and may be IGBTs. In the semiconductor device A1, the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 are each a MOSFET. As shown in FIGS. 15 and 17, each of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 has a rectangular shape (square shape in the semiconductor device A1) when viewed in the thickness direction z. In the semiconductor device A1, each thickness of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 is, for example, 400 μm or less, more preferably 150 μm or less.

Each of the plurality of first semiconductor chips 31 is mounted on the first wiring portion 111 . The plurality of first semiconductor chips 31 are arranged at predetermined intervals along the first direction x.

Each of the plurality of second semiconductor chips 32 is mounted on the second wiring portion 112 . The plurality of second semiconductor chips 32 are arranged at predetermined intervals along the first direction x. In the semiconductor device A1, each second semiconductor chip 32 overlaps each first semiconductor chip 31 when viewed in the second direction y, but unlike this configuration, they do not have to overlap.

As shown in FIGS. 15 to 18, the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 each have a source electrode 301, a drain electrode 302 and a gate electrode 303. FIG.

The source electrode 301 is provided on the upper end of each first semiconductor chip 31 and each second semiconductor chip 32 . The upper end is the end surface on the side facing the mounting surface 11a in the thickness direction z. A source current flows from inside each of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 to the source electrode 301 .

A drain electrode 302 is provided at the lower end of each first semiconductor chip 31 and each second semiconductor chip 32 . The lower end is the end face on the side opposite to the side facing the mounting surface 11a in the thickness direction z. A drain current flows through the drain electrode 302 toward the interior of each of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 .

The gate electrode 303 is provided on the upper end of each first semiconductor chip 31 and each second semiconductor chip 32 . A gate voltage for driving each of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 is applied to the gate electrode 303 . The area of the gate electrode 303 is smaller than the area of the source electrode 301 when viewed in the thickness direction z.

Each of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 performs switching operation according to the gate voltage applied to each gate electrode 303 . The switching operation is an operation of switching between a state in which current flows between each drain electrode 302 and each source electrode 301 (conducting state) and a state in which current does not flow (interrupting state).

As shown in FIGS. 11, 12, and 15 to 18, the first layer 51 has a mounting surface 11a and a mounting surface 11a of the conductor layer 11 (the first wiring portion 111 and the second wiring portion 112) in the thickness direction z. , and each of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 . The first layer 51 is made of a conductive metal material. The first layer 51 is made of a material having the same thermal conductivity as the metal base 12 or a material having a higher thermal conductivity than the metal base 12 . First layer 51 is made of, for example, copper or a copper alloy. When the constituent material of the first layer 51 is copper, the thermal conductivity of the first layer 51 is 398 W/mk. Examples of the constituent material of the first layer 51 include aluminum, iron, carbon, etc., in addition to copper and copper alloys.

In the semiconductor device A1, the first layer 51 includes a plurality of individual portions 511 separated from each other. In the semiconductor device A1, the plurality of individual portions 511 are arranged individually corresponding to the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32, respectively. The plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 are each supported by one of the plurality of individual portions 511 . In the semiconductor device A1, the plurality of individual portions 511 corresponding to the plurality of first semiconductor chips 31 are supported by the first wiring portion 111 and arranged at intervals in the first direction x. The plurality of individual portions 511 corresponding to the plurality of second semiconductor chips 32 are supported by the second wiring portion 112 and arranged at intervals in the first direction x. Each individual portion 511 has a rectangular shape (square shape in the semiconductor device A1) when viewed in the thickness direction z. The configuration of the individual portions 511 is not limited to that described above. may be configured to support the first semiconductor chip 31 (or the plurality of second semiconductor chips 32). For example, one individual portion 511 may support two first semiconductor chips 31 (or second semiconductor chips 32) adjacent in the first direction x, or one individual portion 511 may support three The above first semiconductor chip 31 (or second semiconductor chip 32) may be supported.

The second layer 52 is positioned between the conductor layer 11 (the first wiring portion 111 and the second wiring portion 112) and the first layer 51 (the plurality of individual portions 511) in the thickness direction z. The second layer 52 has conductivity, and conductively joins the respective mounting surfaces 11 a of the first wiring portion 111 and the second wiring portion 112 and the plurality of individual portions 511 . The constituent material of the second layer 52 is, for example, lead-free solder whose main component is tin. The thickness of the second layer 52 is, for example, 0.02 mm or more and 0.20 mm or less.

In the semiconductor device A1, the second layer 52 has multiple regions separated from each other. The plurality of regions of the second layer 52 individually correspond to the plurality of individual portions 511, respectively. Note that the second layer 52 may be configured to have a region common to some of the plurality of individual portions 511 . For example, the second layer 52 has a region common to the plurality of individual portions 511 supported by the first wiring portion 111 and a region common to the plurality of individual portions 511 supported by the second wiring portion 112. It may be a configuration.

The third layer 53 is positioned between the first layer 51 (the plurality of individual portions 511) and each of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 in the thickness direction z. The third layer 53 has electrical conductivity and electrically connects the plurality of individual portions 511 to each of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 . More specifically, each drain electrode 302 of the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 and the first layer 51 (individual portion 511) are conductively joined by the third layer 53. . The third layer 53 is made of a bonding material containing a metal material. In the semiconductor device A1, the constituent material of the third layer 53 contains silver. In the semiconductor device A1, the third layer 53 is sintered silver. The third layer 53 may be made of a sintered metal containing a metal other than silver (for example, sintered copper), solid-phase diffusion-bonded aluminum, solder, or a metal paste material. The thickness of the third layer 53 is, for example, 0.02 mm or more and 0.20 mm or less.

In the semiconductor device A1, the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 are formed by the first layer 51, the second layer 52 and the third layer 53, respectively. It is mounted on one of the second wiring portions 112 . Unlike this configuration, the first layer 51, the second layer 52, and the third layer 53 are not provided, and each of the plurality of first semiconductor chips 31 is bonded to the first wiring portion 111 with a conductive bonding material. Alternatively, each of the plurality of second semiconductor chips 32 may be bonded to the second wiring portion 112 with a conductive bonding material.

The plurality of conducting members 40 are made of metal plates. The metal in question is copper or a copper alloy. The plurality of conduction members 40 are metal plate members that are bent. The plurality of conducting members 40 includes a plurality of first conducting members 41 and a plurality of second conducting members 42 .

Each of the plurality of first conductive members 41 is joined to one of the source electrodes 301 of the plurality of first semiconductor chips 31 and the second wiring portion 112 . Each first conduction member 41 and the second wiring portion 112 are joined via a conduction member joining layer 48 . Each first conductive member 41 and the source electrode 301 of each first semiconductor chip 31 are bonded via a conductive member bonding layer 49 . Conductive member bonding layer 48 and conductive member bonding layer 49 that bond first conductive member 41 are conductive bonding materials such as solder, metal paste, or sintered metal.

Each of the plurality of second conductive members 42 is joined to the source electrode 301 of one of the plurality of second semiconductor chips 32 and the third wiring portion 113 . Each second conducting member 42 and the third wiring portion 113 are joined via a conducting member joining layer 48 . Each second conductive member 42 and the source electrode 301 of each second semiconductor chip 32 are bonded via a conductive member bonding layer 49 . Conductive member bonding layer 48 and conductive member bonding layer 49 that bond second conductive member 42 are, for example, solder, metal paste material, or sintered metal.

The semiconductor device A1 includes a thermistor 33 as shown in FIGS. The thermistor 33 is electrically connected to the pair of thermistor mounting portions 116 . In the semiconductor device A1, the thermistor 33 is an NTC (Negative Temperature Coefficient) thermistor. An NTC thermistor has a characteristic that its resistance gradually decreases with temperature rise. The thermistor 33 is used as a temperature detection sensor for the semiconductor device A1. The thermistor 33 is electrically connected to the pair of thermistor terminals 28 via the pair of thermistor mounting portions 116 and the pair of thermistor wires 46 .

The plurality of first gate wires 431, the plurality of second gate wires 432, the third gate wires 433 and the fourth gate wires 434 are respectively bonding wires. Each of these constituent materials may be, for example, aluminum, gold, or copper.

4, 9, 10 and 17, each of the plurality of first gate wires 431 has one end joined to the gate electrode 303 of each first semiconductor chip 31 and the other end connected to the first gate. It is joined to the portion 114 . The third gate wire 433 has one end joined to the first gate portion 114 and the other end joined to the first gate terminal 25A. Thereby, the first gate terminal 25</b>A is electrically connected to each gate electrode 303 of the plurality of first semiconductor chips 31 .

4, 9, 10 and 17, each of the plurality of second gate wires 432 has one end joined to the gate electrode 303 of each second semiconductor chip 32 and the other end connected to the second gate. It is joined to the portion 117 . The fourth gate wire 434 has one end joined to the second gate portion 117 and the other end joined to the second gate terminal 25B. Thereby, the second gate terminal 25B is electrically connected to each gate electrode 303 of the plurality of second semiconductor chips 32 .

The plurality of first detection wires 441, the plurality of second detection wires 442, the third detection wires 443 and the fourth detection wires 444 are respectively bonding wires. Each of these constituent materials may be, for example, aluminum, gold, or copper.

As shown in FIGS. 4, 9, 10 and 15, the plurality of first detection wires 441 has one end joined to the source electrode 301 of each first semiconductor chip 31 and the other end connected to the first detection section 115. are spliced. The third detection wire 443 has one end joined to the first detection section 115 and the other end joined to the first detection terminal 26A. As a result, the first detection terminals 26A are electrically connected to the respective source electrodes 301 of the plurality of first semiconductor chips 31 .

As can be understood from FIGS. 4, 9, 10 and 17, the plurality of second detection wires 442 has one end joined to the source electrode 301 of each second semiconductor chip 32 and the other end connected to the second detection section. 118. The fourth detection wire 444 has one end joined to the second detection section 118 and the other end joined to the second detection terminal 26B. Thereby, the second detection terminal 26B is electrically connected to each source electrode 301 of the plurality of second semiconductor chips 32 .

The power supply current detection wire 45 and the pair of thermistor wires 46 are bonding wires, respectively. Each of these constituent materials may be, for example, aluminum, gold, or copper. The power current detection wire 45 is joined to the power current detection terminal 27 and the first wiring portion 111, as shown in FIG. The power current detection wire 45 electrically connects the power current detection terminal 27 to the first wiring portion 111 . A pair of thermistor wires 46 are individually joined to a pair of thermistor terminals 28 and a pair of thermistor mounting portions 116, respectively. Each thermistor wire 46 conducts each thermistor terminal 28 to each thermistor mounting portion 116 .

As shown in FIGS. 3 to 7, the case 60 is an electrically insulating member surrounding the conductor layer 11 (metal substrate 10) when viewed in the thickness direction z. A constituent material of the case 60 is a synthetic resin having excellent heat resistance, such as PPS (polyphenylene sulfide). The case 60 includes a pair of first side walls 611 , a pair of second side walls 612 , multiple mounting portions 62 , a power terminal block 63 and an output terminal block 64 . Moreover, the case 60 includes the metal substrate 10 as a bottom plate.

As shown in FIGS. 2 and 4, the pair of first sidewalls 611 are spaced apart from each other in the first direction x. A pair of first side walls 611 are arranged along both the second direction y and the thickness direction z.

As shown in FIGS. 2 and 4, the pair of second sidewalls 612 are spaced apart from each other in the second direction y. A pair of second side walls 612 are arranged along both the first direction x and the thickness direction z. Both ends of the pair of second side walls 612 in the first direction x are connected to the pair of first side walls 611 . A first gate terminal 25A, a first detection terminal 26A, a power supply current detection terminal 27 and a pair of thermistor terminals 28 are arranged inside one of the second side walls 612 . A second gate terminal 25B and a second detection terminal 26B are arranged inside the other second side wall 612 . As shown in FIGS. 9, 10, and 12, the ends of these terminals that are close to the conductor layer 11 (metal substrate 10) in the thickness direction z are supported by a pair of second sidewalls 612. As shown in FIGS.

As shown in FIGS. 2, 9 and 10, the plurality of mounting portions 62 are portions provided at the four corners of the case 60 when viewed in the thickness direction z. Each of the plurality of mounting portions 62 is formed with a through-hole penetrating in the thickness direction z, and a mounting member 621 is fitted in each of the through-holes. Each mounting member 621 is provided with a mounting hole 621a penetrating in the thickness direction z. In the semiconductor device A1, for example, by fitting a fastening member (not shown) into the mounting hole 621a, a heat dissipating member (for example, a heat sink) (not shown) can be attached.

As shown in FIGS. 2, 6 and 9, the power terminal block 63 protrudes outward in the first direction x from one first side wall 611 . The power terminal block 63 supports the first power terminal 23A and the second power terminal 23B. The power terminal block 63 has a first terminal block 631 and a second terminal block 632 . The first terminal block 631 and the second terminal block 632 are separated from each other in the second direction y. The first terminal block 631 supports the first power terminal 23A. The external connection portion 231 of the first power terminal 23A is exposed from the first terminal block 631 . The second terminal block 632 supports the second power terminal 23B. The external connection portion 231 of the second power terminal 23B is exposed from the second terminal block 632 . A plurality of grooves 633 extending in the first direction x are formed between the first terminal block 631 and the second terminal block 632 . As shown in FIGS. 9 and 13 , a pair of nuts 634 and a pair of intermediate members 635 are arranged inside the first terminal block 631 and the second terminal block 632 . The intermediate member 635 is located on the other side of the nut 634 in the thickness direction z (lower side in FIG. 13) and is in contact with the nut 634 . One nut 634 and intermediate member 635 are engaged with the external connection portion 231 and the intermediate portion 233 of the first power terminal 23A. The other nut 634 and intermediate member 635 are engaged with the external connection portion 231 and intermediate portion 233 of the second power terminal 23B. A part of each of the pair of intermediate members 635 is exposed from the power terminal block 63 . A pair of nuts 634 correspond to a pair of connection holes 231a provided in the first power terminal 23A and the second power terminal 23B. Fastening members such as bolts inserted into the pair of connection holes 231 a are fitted to the pair of nuts 634 .

As shown in FIGS. 2, 7 and 10, the output terminal block 64 protrudes outward in the first direction x from the other first side wall 611 . The output terminal block 64 supports the output terminals 24 . The output terminal block 64 has a first terminal block 641 and a second terminal block 642 . The first terminal block 641 and the second terminal block 642 are separated from each other in the second direction y. The first terminal block 641 supports the first terminal portion 24A of the output terminal 24 . The external connection portion 241 of the first terminal portion 24A is exposed from the first terminal block 641 . The second terminal block 642 supports the second terminal portion 24B of the output terminal 24 . The external connection portion 241 of the second terminal portion 24B is exposed from the second terminal block 642 . A plurality of grooves 643 extending in the first direction x are formed between the first terminal block 641 and the second terminal block 642 . As shown in FIGS. 10 and 14 , a pair of nuts 644 and a pair of intermediate members 645 are arranged inside the first terminal block 641 and the second terminal block 642 . The intermediate member 645 is located on the other side of the nut 644 in the thickness direction z (lower side in FIG. 14) and is in contact with the nut 644 . One nut 644 and intermediate member 645 are engaged with the external connection portion 241 and intermediate portion 243 of the first terminal portion 24A. The other nut 644 and intermediate member 645 are engaged with the external connection portion 241 and intermediate portion 243 of the second terminal portion 24B. A part of each of the pair of intermediate members 645 is exposed from the output terminal block 64 . A pair of nuts 644 correspond to a pair of connection holes 241a provided in the first terminal portion 24A and the second terminal portion 24B. Fastening members such as bolts inserted into the pair of connection holes 241 a are fitted to the pair of nuts 644 .

Resin member 70 is accommodated in a region surrounded by case 60 and metal substrate 10, as shown in FIGS. The resin member 70 includes a first resin layer 71 and a second resin layer 72 laminated in the thickness direction z. First resin layer 71 and second resin layer 72 are housed in regions surrounded by case 60 and metal substrate 10, respectively.

The first resin layer 71 is formed on the metal substrate 10 . The first resin layer 71 covers the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 respectively. The thickness of the first resin layer 71 (the distance along the thickness direction z from the top surface of the insulating layer 13 to the top surface of the first resin layer 71) is the top surface of the first semiconductor chip 31 or the second semiconductor chip 32. above and below the top surface of the second side wall 612 . That is, the first resin layer 71 is formed so as to have a height equal to or higher than the height covering the first semiconductor chip 31 and the second semiconductor chip 32 and a height not overflowing the case 60 .

The second resin layer 72 is formed on the first resin layer 71 . The upper surface of the second resin layer 72 (the surface facing upward in the thickness direction z) is exposed to the outside of the semiconductor device A1, and the lower surface of the second resin layer 72 (the surface facing downward in the thickness direction z) is 1 contacts the upper surface of the resin layer 71 (the surface facing downward in the thickness direction z). The thickness of the second resin layer 72 (the distance from the lower surface of the second resin layer 72 to the upper surface of the second resin layer 72 along the thickness direction z) is the distance from the uppermost surface of the second side wall 612 to the first semiconductor chip 31 or It is equal to or less than the distance to the top surface of the second semiconductor chip 32 . For example, the thickness of the second resin layer 72 is 20% or more and 80% or less of the thickness of the first resin layer 71 .

The first resin layer 71 and the second resin layer 72 are made of a material containing epoxy resin or silicone gel as a main agent. For example, this main agent contains a filler such as silica or BN (boron nitride). The first resin layer 71 and the second resin layer 72 have different coefficients of thermal expansion due to differences in the composition of the main agent and the amount and type of filler contained in the main agent. The coefficient of thermal expansion of the second resin layer 72 is higher than the coefficient of thermal expansion of the first resin layer 71 . For example, the amount of filler changes the coefficient of thermal expansion, eg, increasing the amount of filler tends to decrease the coefficient of thermal expansion. The difference between the thermal expansion coefficient of the first resin layer 71 and the thermal expansion coefficients of the first semiconductor chips 31 and the second semiconductor chips 32 is smaller than that of the metal substrate 10 . Therefore, the thermal expansion coefficient of the first resin layer 71 is closer to the thermal expansion coefficients of the first semiconductor chips 31 and the second semiconductor chips 32 than the thermal expansion coefficient of the metal substrate 10 . Also, the thermal expansion coefficient of the second resin layer 72 is, for example, 50% or more and 150% or less with respect to the thermal expansion coefficient of the metal substrate 10 . For example, in the semiconductor device A1, the thermal expansion coefficient of the metal substrate 10 is about 16 [10 ^-6 /K], and the thermal expansion coefficient of each first semiconductor chip 31 and each second semiconductor chip 32 is about 4 [10 ^-6 /K]. /K], the coefficient of thermal expansion of the first resin layer 71 is about 9 [10 ^-6 /K], and the coefficient of thermal expansion of the second resin layer 72 is about 16 [10 ^-6 /K]. However, these coefficients of thermal expansion are not limited to the above numerical examples. In the present disclosure, the thermal expansion coefficient of the metal substrate 10 is the thermal expansion coefficient of the metal substrate 10 , and is determined by the thermal expansion coefficients of the conductor layer 11 , metal base 12 and insulating layer 13 . In this embodiment, of the metal substrate 10, the metal base 12 has a relatively larger volume than the conductor layer 11 and the insulating layer 13, and the thermal expansion coefficient of the metal substrate 10 is equal to the thermal expansion coefficient of the metal base 12 alone. close values.

In the semiconductor device A1, due to the difference in coefficient of thermal expansion between the first resin layer 71 and the second resin layer 72, the thickness of the first resin layer 71, the thickness of the second resin layer 72, etc., as described above, The degree of curvature of the back surface 12b of the metal base 12 changes to be convex or flat.

Semiconductor device A1 includes two switching circuits, an upper arm circuit and a lower arm circuit. The upper arm circuit is composed of a first wiring portion 111 and a plurality of first semiconductor chips 31 mounted on the first wiring portion 111 . A plurality of first semiconductor chips 31 are connected in parallel between the first power terminal 23A and the output terminal 24 . The gate electrodes 303 of the plurality of first semiconductor chips 31 in the upper arm circuit are each connected in parallel to the first gate terminal 25A. A driving circuit such as a gate driver arranged outside the semiconductor device A1 applies a gate voltage to the first gate terminal 25A, thereby simultaneously driving the plurality of first semiconductor chips 31 in the upper arm circuit. The source electrodes 301 of the plurality of first semiconductor chips 31 in the upper arm circuit are each connected in parallel to the first gate terminal 25A. Source currents flowing through the plurality of first semiconductor chips 31 in the upper arm circuit are input to the control circuit of the semiconductor device A1 arranged outside the semiconductor device A1 via the first detection terminals 26A.

The lower arm circuit is composed of a second wiring portion 112 and a plurality of second semiconductor chips 32 mounted on the second wiring portion 112 . A plurality of second semiconductor chips 32 are connected in parallel between the output terminal 24 and the second power terminal 23B. The gate electrodes 303 of the plurality of second semiconductor chips 32 in the lower arm circuit are each connected in parallel to the second gate terminal 25B. A driving circuit such as a gate driver arranged outside the semiconductor device A1 applies a gate voltage to the second gate terminal 25B, thereby simultaneously driving the plurality of second semiconductor chips 32 in the lower arm circuit. The source electrodes 301 of the plurality of second semiconductor chips 32 in the lower arm circuit are each connected in parallel to the second detection terminal 26B. Source currents flowing through the plurality of second semiconductor chips 32 in the lower arm circuit are input to the control circuit of the semiconductor device A1 arranged outside the semiconductor device A1 via the second detection terminals 26B.

A DC power supply is connected to the first power supply terminal 23A and the second power supply terminal 23B, and by driving the plurality of first semiconductor chips 31 in the upper arm circuit and the plurality of second semiconductor chips 32 in the lower arm circuit, the output terminal 24 (first terminal portion 24A and second terminal portion 24B) output AC voltages of various frequencies. The AC voltage output from the output terminal 24 is supplied to a power supply target such as a motor.

Next, a method for manufacturing the semiconductor device A1 will be described.

First, a metal substrate 10 is prepared. The metal substrate 10 to be prepared has a structure in which the conductor layer 11, the metal base 12 and the insulating layer 13 are laminated as described above.

Next, the plurality of first semiconductor chips 31 and the plurality of second semiconductor chips 32 are mounted on one side of the metal substrate 10 in the thickness direction z (mounting step). Specifically, a plurality of first semiconductor chips 31 are mounted on the first wiring portion 111 on the upper side of the metal substrate 10 (the side on which the conductor layer 11 is formed with respect to the insulating layer 13), A plurality of second semiconductor chips 32 are mounted on the second wiring portion 112 . At this time, the plurality of first semiconductor chips 31 are bonded to the first wiring portion 111 via the first layer 51 (the plurality of individual portions 511), the second layer 52, and the third layer 53, and the plurality of second semiconductor chips A chip 32 is bonded to the second wiring portion 112 .

Next, the first power terminal 23A, the second power terminal 23B and the output terminal 24 are joined to the conductor layer 11, respectively. The first power supply terminal 23A, the second power supply terminal 23B and the output terminal 24 are joined by, for example, ultrasonic joining, but other joining methods such as laser joining or joining via a conductive joining material may be used instead of ultrasonic joining. may At this time, other terminals (the first gate terminal 25A, the second gate terminal 25B, the first detection terminal 26A, the second detection terminal 26B, etc.) are also arranged at the positions described above.

Next, the plurality of conducting members 40 (the plurality of first conducting members 41 and the plurality of second conducting members 42) and the plurality of wires (the gate wires 431 to 434, the detection wires 441 to 444, etc.) are joined. Do each.

Next, the case 60 is arranged on the metal substrate 10 so as to surround the first semiconductor chip 31 and the second semiconductor chip 32 (case arrangement step). In the case placement step, the case 60 is placed on the metal substrate 10 by forming the case 60 by molding, for example. The case 60 may be formed directly on the metal substrate 10, or may be placed on the metal substrate 10 after forming the case 60 alone. When forming the case 60 alone, each terminal (first power terminal 23A, second power terminal 23B, output terminal 24, first gate terminal 25A, second gate terminal 25B, 1st detection terminal 26A, 2nd detection terminal 26B, etc.) may be attached. The case arranging step may be performed before joining the plurality of conducting members 40 and the plurality of wires.

Next, the resin member 70 is formed in the housing space of the case 60 on the metal substrate 10 (resin member forming step). In the resin member forming step, first, the first resin layer 71 is formed by potting. Specifically, a first resin material, which is the material of the first resin layer 71, is poured into the case 60 and cured. Thereby, the first resin layer 71 is formed. Next, the second resin material, which is the material of the second resin layer 72, is poured onto the first resin layer 71 inside the case 60 by potting, and the second resin material is cured. Thereby, the second resin layer 72 is formed.

Through the steps described above, the semiconductor device A1 is manufactured. The manufacturing method of the semiconductor device A1 described above is an example, and is not limited to this.

The actions and effects of the semiconductor device A1 are as follows.

A semiconductor device A1 includes a resin member 70 having a first resin layer 71 and a second resin layer 72 . The first resin layer 71 is formed on the metal substrate 10 and covers the first semiconductor chip 31 (and the second semiconductor chip 32). The second resin layer 72 is formed on the first resin layer 71 . The thermal expansion coefficient of the first resin layer 71 is smaller than the thermal expansion coefficient of the first semiconductor chip 31 (and the second semiconductor chip 32). The coefficient of thermal expansion of the resin layer 72 is higher than the coefficient of thermal expansion of the first resin layer 71 . In the semiconductor device A1, for example, the coefficient of thermal expansion of the first semiconductor chip 31 (and the second semiconductor chip 32) is approximately 4 [10 ^-6 /K], and the coefficient of thermal expansion of the metal substrate 10 is approximately 16 [10 ^-6 /K]. K], the coefficient of thermal expansion of the first resin layer 71 is about 9 [10 ^-6 /K], and the coefficient of thermal expansion of the second resin layer 72 is about 16 [10 ^-6 /K ] satisfies the relationship of the coefficient of thermal expansion.

In a semiconductor device A1′ (see FIG. 19), which has a configuration different from that of the semiconductor device A1, and in which the resin member 70 does not have the second resin layer 72 and is composed only of the first resin layer 71, the first semiconductor chip 31 and the In order to suppress peeling from the first resin layer 71, the difference between the coefficient of thermal expansion of the first resin layer 71 and the coefficient of thermal expansion of the first semiconductor chip 31 may be reduced. In this case, the difference in the coefficient of thermal expansion between the first resin layer 71 and the metal substrate 10 increases, and this difference in coefficient of thermal expansion causes the metal substrate 10 to warp and the back surface 12b of the metal base 12 to become concave. Sometimes. Although FIG. 19 shows an example in which only the back surface 12b is curved upward in the thickness direction z due to warpage of the metal substrate 10, the entire metal substrate 10 may be curved upward in the thickness direction z. In this case, as shown in FIG. 19, if the cooler 91 is attached via the heat-resistant grease 92, there is a risk that a gap 93 will be formed between the cooler 91 (including the heat-resistant grease 92) and the semiconductor device A1'. Therefore, in such a semiconductor device A1', when attaching the cooler 91, the adhesion with the cooler was not good.

On the other hand, in the semiconductor device A1, since the resin member 70 has the second resin layer 72 having a higher thermal expansion coefficient than the first resin layer 71, the warping of the metal substrate 10 is suppressed, and the back surface 12b of the metal base 12 is A concave surface can be suppressed. Therefore, in the semiconductor device A1, formation of the gap 93 is suppressed. That is, when the semiconductor device A1 is attached to an attachment target such as a cooler, it is possible to improve the adhesion to the attachment target.

The semiconductor device A1 includes a case 60 that accommodates a resin member 70. As shown in FIG. In this configuration, the thermal expansion of the resin member 70 is restricted by the case 60 when the first semiconductor chips 31 and the second semiconductor chips 32 generate heat, so the thermal stress applied to the metal substrate 10 increases. As a result, as in the semiconductor device A1' (see FIG. 19), when the resin member 70 is composed only of the first resin layer 71, the upward warp of the metal substrate 10 increases, and the metal base 12 The degree of concave surface of the back surface 12b of is increased. As the warpage of the metal substrate 10 increases, the adhesion between the semiconductor device A1 and the cooler decreases. This configuration is more effective in improving the adhesion between the semiconductor device A1 and the mounting object.

In the semiconductor device A1, the back surface 12b of the metal base 12 is curved and protrudes downward in the thickness direction z. FIG. 20 shows a state in which a cooler 91 is attached to the semiconductor device A1 via heat-resistant grease 92. FIG. Although FIG. 20 shows an example in which only the back surface 12b is curved downward in the thickness direction z due to warping of the metal substrate 10, the entire metal substrate 10 may be curved downward in the thickness direction z. As shown in FIG. 20, when the back surface 12b is convex, the heat-resistant grease 92 is pressed against and expelled around the semiconductor device A1. Therefore, the gap 93 is not formed between the semiconductor device A1 and the cooler 91 (including the heat resistant grease 92). Therefore, when the semiconductor device A1 is attached to an attachment target such as a cooler, the semiconductor device A1 has good adhesion to the attachment target.

In the semiconductor device A<b>1 , the thermal expansion coefficient of the second resin layer 72 is 50% or more and 150% or less with respect to the thermal expansion coefficient of the metal substrate 10 . According to this configuration, the back surface 12b of the metal base 12 is not concave, but can be convex or a plane orthogonal to the thickness direction z.

The semiconductor device A1 includes a first semiconductor chip 31 and a second semiconductor chip 32, and the first semiconductor chip 31 and the second semiconductor chip 32 are electrically connected in series. The switching operation of the first semiconductor chip 31 and the second semiconductor chip 32 is performed with the first semiconductor chip 31 serving as an upper arm circuit and the second semiconductor chip 32 serving as a lower arm circuit. Therefore, since the semiconductor device A1 can effectively dissipate heat generated by the switching operations of the first semiconductor chip 31 and the second semiconductor chip 32, the switching performance of the first semiconductor chip 31 and the second semiconductor chip 32 is lowered. is suppressed.

<Modified Example of First Embodiment>
21 to 23 respectively show semiconductor devices A2 to A4 according to modifications of the first embodiment.

In semiconductor device A2 shown in FIG. 21, resin member 70 has third resin layer 73 in addition to first resin layer 71 and second resin layer 72, as compared with semiconductor device A1. The third resin layer 73 is interposed between the first resin layer 71 and the second resin layer 72 in the thickness direction z. The material of the third resin layer 73 includes the material of the first resin layer 71 and the material of the second resin layer 72 . The third resin layer 73 shown in FIG. 21 extends along a plane perpendicular to the thickness direction z. The dimension along the thickness direction z of the third resin layer 73 may be non-uniform as shown in FIG. 21, or may be uniform unlike the example shown in FIG. The third resin layer 73 may cover the entire upper surface of the first resin layer 71, or the first resin layer 71 may cover the first resin layer 71 so that there is an interface between the first resin layer 71 and the second resin layer 72. You may expose a part of upper surface of. The third resin layer 73 may be formed in one region as shown in FIG. 21, or may be divided into a plurality of regions.

The semiconductor device A2 shown in FIG. 21 is formed, for example, as follows. That is, in the resin member forming step of the manufacturing method of the semiconductor device A1, after pouring the first resin material into the case 60 and before curing the first resin material, the first resin material inside the case 60 Pour the second resin material into. At this time, a layer in which the first resin material and the second resin material are mixed is formed between the first resin material and the second resin material. Then, the first resin material and the second resin material are collectively cured. At this time, the layer in which the first resin material and the second resin material are mixed is also cured to form the third resin layer 73 . Therefore, as described above, the third resin layer 73 includes the material of the first resin layer 71 and the material of the second resin layer 72 .

Since the resin member 70 has the first resin layer 71 and the second resin layer 72, the semiconductor device A2 can achieve the same effect as the semiconductor device A1. In the semiconductor device A2, the third resin layer 73 functions as an adhesive layer between the first resin layer 71 and the second resin layer 72, and the first resin layer 71 and the second resin layer 72 are separated. can be suppressed.

In the semiconductor device A3 shown in FIG. 22, the upper surface of the first resin layer 71 is rough compared to the semiconductor device A1. For example, the top surface of the first resin layer 71 is rougher than the top surface of the second resin layer 72 .

The semiconductor device A3 shown in FIG. 22 is formed, for example, as follows. In the resin member forming step of the method of manufacturing the semiconductor device A1, after the first resin layer 71 is formed and before the second resin layer 72 is formed, the upper surface of the first resin layer 71 is sandblasted, for example. The upper surface of the first resin layer 71 is roughened by performing treatment, laser irradiation, sanding treatment, or the like.

Since the resin member 70 has the first resin layer 71 and the second resin layer 72, the semiconductor device A3 can achieve the same effect as the semiconductor device A1. In the semiconductor device A3, since the upper surface of the first resin layer 71 is a rough surface, the adhesion between the first resin layer 71 and the second resin layer 72 is improved due to the anchor effect. can be suppressed from peeling off from the first resin layer 71 .

A semiconductor device A4 shown in FIG. 23 has a plurality of dimples 711 formed on the upper surface of the first resin layer 71, unlike the semiconductor device A1. Each of the plurality of dimples 711 is a depression downward in the thickness direction z. Each of the plurality of dimples 711 has, for example, a substantially circular shape when viewed in the thickness direction z, but the shape when viewed in the thickness direction z is not limited to a circular shape. The plurality of dimples 711 may be arranged regularly when viewed in the thickness direction z (for example, lattice arrangement or matrix arrangement), or may be formed irregularly.

The semiconductor device A4 shown in FIG. 23 is formed, for example, as follows. That is, in the resin member forming step of the method of manufacturing the semiconductor device A1, after the first resin layer 71 is formed and before the second resin layer 72 is formed, the upper surface of the first resin layer 71 is irradiated with, for example, a laser. , a plurality of dimples 711 are formed.

Since the resin member 70 has the first resin layer 71 and the second resin layer 72, the semiconductor device A4 can achieve the same effect as the semiconductor device A1. Further, since the plurality of dimples 711 are formed on the upper surface of the first resin layer 71 in the semiconductor device A4, the first resin layer 71 and the second resin layer 71 and the second resin layer 71 and the second resin layer 71 are separated from each other by the anchor effect as in the case of the rough surface. Since the adhesion with the layer 72 is improved, it is possible to prevent the second resin layer 72 from peeling off from the first resin layer 71 .

<Second embodiment>
24 to 30 show the semiconductor device B1 according to the second embodiment. The semiconductor device B1 differs from the semiconductor device A1 mainly in that the case 60 is not provided. Other differences in configuration between the semiconductor device B1 and the semiconductor device A1 will be described below.

In the semiconductor device B1, the metal substrate 10 differs from the semiconductor device A1 in the structure of the conductor layer 11. FIG. The conductor layer 11 of the semiconductor device B1 includes, as shown in FIG. It includes a portion 118 and two insulating portions 119 .

As shown in FIGS. 29 and 30, in the semiconductor device B1, the first wiring portion 111 and the second wiring portion 112 are formed on the insulating layer 13, similarly to the semiconductor device A1. On the other hand, unlike the semiconductor device A1, the first gate portion 114 and the first detection portion 115 are arranged on the first wiring portion 111 with one of the two insulating portions 119 interposed therebetween. Therefore, one of the two insulating portions 119 is formed on the first wiring portion 111 , and the first gate portion 114 and the first detecting portion 115 are arranged on the insulating portion 119 . Further, unlike the semiconductor device A1, the second gate portion 117 and the second detection portion 118 are arranged on the second wiring portion 112 with the other of the two insulating portions 119 interposed therebetween. Therefore, the other of the two insulating portions 119 is formed on the second wiring portion 112 , and the second gate portion 117 and the second detecting portion 118 are arranged on the insulating portion 119 .

As shown in FIGS. 28 to 30, in semiconductor device B1, rear surface 12b of metal base 12 is exposed from the lower surface of resin member . As shown in FIG. 28, the lower surface of the resin member 70 has a frame shape surrounding the back surface 12b.

As shown in FIG. 29, in the semiconductor device B1, the first power terminal 23A is joined to the first wiring portion 111, and the output terminal 24 is joined to the second wiring portion 112, similarly to the semiconductor device A1. . On the other hand, unlike the semiconductor device A1, the second power supply terminal 23B is not joined to the conductor layer 11. As shown in FIG. However, the second power supply terminal 23B is electrically connected to the source electrode 301 of each second semiconductor chip 32, as in the semiconductor device A1, due to the configuration described in detail later.

In the semiconductor device B1, the first power terminal 23A and the second power terminal 23B are arranged substantially parallel to the thickness direction z with the insulating member 239 interposed therebetween. As can be seen from FIG. 26, the first power terminal 23A and the second power terminal 23B partially overlap when viewed in the thickness direction z.

The insulating member 239 has electrical insulation, and is made of insulating paper, for example. A portion of the insulating member 239 is interposed between the first power terminal 23A and the second power terminal 23B in the thickness direction z, as shown in FIG. At least a portion of each of the first power terminal 23A and the second power terminal 23B overlaps the insulating member 239 when viewed in the thickness direction z. The insulating member 239 insulates the first power terminal 23A and the second power terminal 23B from each other. The insulating member 239 has a portion covered with the resin member 70 (first resin layer 71 ) and a portion exposed from the resin member 70 .

As shown in FIGS. 26 and 29, the first power terminal 23A includes an external connection portion 231 and an internal connection portion 232. As shown in FIGS. In the first power terminal 23A, the external connection portion 231 and the internal connection portion 232 are connected to each other. The external connection portion 231 is exposed from the resin member 70, and the internal connection portion 232 is covered with the resin member 70 (first resin layer 71). In the first power supply terminal 23A, as shown in FIG. 26, the internal connection portion 232 has a comb-shaped end portion opposite to the side connected to the external connection portion 231 in the first direction x. All of the teeth are joined to the first wiring portion 111 by ultrasonic joining.

As shown in FIGS. 26 and 29, the second power terminal 23B includes an external connection portion 231 and an internal connection portion 232. As shown in FIGS. In the second power terminal 23B, the external connection portion 231 and the internal connection portion 232 are connected to each other. The external connection portion 231 is exposed from the resin member 70, and the internal connection portion 232 is covered with the resin member 70 (for example, the first resin layer 71). The external connection portion 231 of the first power terminal 23A and the external connection portion 231 of the second power terminal 23B overlap each other when viewed in the thickness direction z. In the second power supply terminal 23B, the internal connection portion 232 is formed in a comb shape and includes a connecting portion 232a and a plurality of extension portions 232b as shown in FIG.

As shown in FIG. 26, the connecting portion 232a has a strip shape extending in the y direction. The connection portion 232 a is connected to the external connection portion 231 . Each of the plurality of extending portions 232b extends from the connecting portion 232a in one direction in the first direction x and has a strip shape when viewed in the thickness direction z. The plurality of extending portions 232b are arranged in the y direction when viewed in the thickness direction z and are spaced apart from each other. Each extending portion 232 b has a lower surface (a surface facing downward in the thickness direction z) in contact with the base portion 59 , and is supported by the first wiring portion 111 via the base portion 59 . Each of the base portions 59 is an electrically insulating (for example, ceramic) block.

As shown in FIGS. 26 and 29, output terminal 24 includes an external connection portion 241 and an internal connection portion 242 . The external connection portion 241 and the internal connection portion 242 are connected to each other. The external connection portion 241 is exposed from the resin member 70, and the internal connection portion 242 is covered with the resin member 70 (first resin layer 71). As shown in FIG. 26, the internal connection part 242 has a comb-like end on the side opposite to the side connected to 241 in the first direction x. All of the teeth are joined to the second wiring portion 112 by ultrasonic joining.

As shown in FIGS. 24 to 28, the semiconductor device B1 has a plurality of non-connect terminals 29. FIG. The plurality of non-connect terminals 29 are located on the opposite side of the first detection terminal 26A with respect to the first gate terminal 25A in the first direction x, and on the second side with respect to the second gate terminal 25B in the first direction x. There is one located on the opposite side of the detection terminal 26B. The number of non-connect terminals 29 is not limited to the illustrated example, and the semiconductor device B<b>1 may be configured without a plurality of non-connect terminals 29 . The plurality of non-connect terminals 29 have the same shape as each of the first gate terminal 25A, the second gate terminal 25B, the first detection terminal 26A and the second detection terminal 26B.

In the semiconductor device B1, as shown in FIGS. 26, 27 and 30, each first conduction member 41 is joined to the source electrode 301 and the second wiring portion 112 of each first semiconductor chip 31. FIG. Therefore, the second wiring portions 112 are electrically connected to the source electrodes 301 of the first semiconductor chips 31 by the first conductive members 41 . Since the second wiring portion 112 is connected to the second semiconductor chips 32 and electrically connected to the drain electrodes 302 of the second semiconductor chips 32, the output terminals 24 connected to the second wiring portion 112 are connected to the respective first semiconductor chips 32. The source electrode 301 of the semiconductor chip 31 and the drain electrode 302 of each second semiconductor chip 32 are electrically connected.

In the semiconductor device B1, as shown in FIGS. 26, 27 and 29, each second conduction member 42 extends between the source electrode 301 of each second semiconductor chip 32 and the internal connection portion 232 of the second power supply terminal 23B. are joined to the protruding portion 232b. As a result, the second power terminal 23B is electrically connected to the source electrode 301 of each second semiconductor chip 32 .

As shown in FIGS. 24 and 26 to 30, since the semiconductor device B1 does not have a case 60, the side surfaces of the resin member 70 (surfaces other than the upper and lower surfaces) are exposed to the outside of the semiconductor device B1. there is

In semiconductor device B1 as well, resin member 70 has first resin layer 71 and second resin layer 72 as in semiconductor device A1. Therefore, like the semiconductor device A1, the semiconductor device B1 can have good adhesion to an attachment target such as a cooler. In addition, the semiconductor device B1 can achieve the same effects as the semiconductor device A1 due to the configuration common to the semiconductor device A1.

A configuration similar to that of the modified example of the first embodiment may be applied to the semiconductor device B1 according to the second embodiment. That is, in the semiconductor device B1, the resin member 70 may have the third resin layer 73, like the semiconductor device A2 (see FIG. 21). Further, as in the semiconductor device A3 (see FIG. 22), the upper surface of the first resin layer 71 may be roughened. A plurality of dimples 711 may be formed on the upper surface.

In each of the semiconductor devices A1 and B1 according to the first embodiment and the second embodiment, the resin member 70 may be composed only of the second resin layer 72 . Even with such a configuration, it is possible to prevent the back surface 12b of the metal base 12 from becoming a concave surface. However, in order to prevent the back surface 12b from becoming concave while suppressing separation between the first semiconductor chip 31 and the second semiconductor chip 32 and the resin member 70 (the second resin layer 72), the resin member 70 is It is preferable to have the first resin layer 71 and the second resin layer 72 .

The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device of the present disclosure and the specific processing of each step of the manufacturing method of the semiconductor device of the present disclosure can be changed in design in various ways. For example, a semiconductor device and a method for manufacturing a semiconductor device of the present disclosure include embodiments related to the following notes.
[Appendix 1]
a first semiconductor chip;
a metal substrate on which the first semiconductor chip is mounted on one side in the thickness direction;
a resin member formed on a side of the metal substrate on which the first semiconductor chip is mounted in the thickness direction;
and
The resin member has a first resin layer formed on the metal substrate and covering the first semiconductor chip, and a second resin layer formed on the first resin layer,
a difference between a coefficient of thermal expansion of the first resin layer and a coefficient of thermal expansion of the first semiconductor chip is smaller than a difference between a coefficient of thermal expansion of the metal substrate;
The semiconductor device, wherein the coefficient of thermal expansion of the second resin layer is higher than the coefficient of thermal expansion of the first resin layer.
[Appendix 2]
1. The semiconductor device according to appendix 1, further comprising a case including the metal substrate as a bottom plate and housing the first semiconductor chip, the first resin layer and the second resin layer.
[Appendix 3]
further comprising a third resin layer interposed between the first resin layer and the second resin layer,
The semiconductor device according to appendix 2, wherein the third resin layer includes a material of the first resin layer and a material of the second resin layer.
[Appendix 4]
The semiconductor device according to appendix 1, wherein a surface of the first resin layer facing one of the thickness directions is rougher than a surface of the second resin layer facing one of the thickness directions.
[Appendix 5]
The semiconductor device according to appendix 1, wherein a plurality of dimples are formed on a surface of the first resin layer facing one of the thickness directions.
[Appendix 6]
6. The semiconductor device according to any one of appendices 1 to 5, wherein the thermal expansion coefficient of the second resin layer is 50% or more and 150% or less with respect to the thermal expansion coefficient of the metal substrate.
[Appendix 7]
The metal substrate has a metal base, an insulating layer and a conductor layer,
The metal base has a main surface and a back surface spaced apart in the thickness direction,
The insulating layer is interposed between the main surface of the metal base and the conductor layer,
7. The semiconductor device according to any one of appendices 1 to 6, wherein the first semiconductor chip is bonded to the conductor layer.
[Appendix 8]
8. The semiconductor device according to appendix 7, wherein the insulating layer is made of epoxy resin.
[Appendix 9]
8. The semiconductor device according to any one of appendices 7 and 8, wherein the metal base has a curved back surface and a protrusion in the other thickness direction.
[Appendix 10]
The semiconductor device according to any one of appendices 7 to 9, wherein the first semiconductor chip performs a switching operation.
[Appendix 11]
further comprising a second semiconductor chip that performs a switching operation;
11. The semiconductor device according to appendix 10, wherein the first semiconductor chip and the second semiconductor chip are electrically connected in series.
[Appendix 12]
a first power supply terminal electrically connected to the first semiconductor chip;
a second power supply terminal electrically connected to the second semiconductor chip;
an output terminal conducting to an electrical connection point between the first semiconductor chip and the second semiconductor chip;
12. The semiconductor device according to Appendix 11, further comprising:
[Appendix 13]
the conductor layer includes a first wiring portion, a second wiring portion, and a third wiring portion spaced apart from each other;
the first wiring portion is connected to the first semiconductor chip and the first power supply terminal;
the second wiring portion is connected to the second semiconductor chip and the output terminal;
13. The semiconductor device according to appendix 12, wherein the third wiring portion is joined to the second power supply terminal.
[Appendix 14]
a first conduction member that electrically connects the first semiconductor chip and the second wiring portion;
a second conduction member that electrically connects the second semiconductor chip and the third wiring portion;
14. The semiconductor device according to Appendix 13, further comprising:
[Appendix 15]
preparing a metal substrate;
a mounting step of mounting a first semiconductor chip on one side of the metal substrate in the thickness direction of the metal substrate;
a resin member forming step of forming a resin member on a side of the metal substrate on which the first semiconductor chip is mounted in the thickness direction;
has
In the resin member forming step, a first resin layer disposed on the metal substrate and covering the first semiconductor chip, and a second resin layer disposed on the first resin layer are formed,
a difference between a coefficient of thermal expansion of the first resin layer and a coefficient of thermal expansion of the first semiconductor chip is smaller than a difference between a coefficient of thermal expansion of the metal substrate;
The method of manufacturing a semiconductor device, wherein the coefficient of thermal expansion of the second resin layer is higher than the coefficient of thermal expansion of the first resin layer.
[Appendix 16]
16. The semiconductor device according to appendix 15, further comprising, after the mounting step and before the resin member forming step, a case placement step of placing a case surrounding the first semiconductor chip on the metal substrate. manufacturing method.
[Appendix 17]
The resin member forming step includes:
a first step of pouring a first resin material to be the first resin layer into the case;
a second step of pouring a second resin material to be the second resin layer into the interior of the case after the first step;
a third step of collectively curing the first resin material and the second resin material;
17. The method of manufacturing a semiconductor device according to appendix 16, comprising:
[Appendix 18]
The resin member forming step includes:
a first step of pouring a first resin material into the case and curing the first resin material to form the first resin layer;
After the first step, a second step of roughening the surface of the first resin layer facing the one in the thickness direction;
a third step of, after the second step, pouring a second resin material onto the first resin layer inside the case and curing the second resin material to form the second resin layer;
17. The method of manufacturing a semiconductor device according to appendix 16, comprising:
[Appendix 19]
The resin member forming step includes:
a first step of pouring a first resin material into the case and curing the first resin material to form the first resin layer;
a second step of forming a plurality of dimples on the surface of the first resin layer facing the one thickness direction after the first step;
a third step of, after the second step, pouring a second resin material onto the first resin layer inside the case and curing the second resin material to form the second resin layer;
17. The method of manufacturing a semiconductor device according to appendix 16, comprising:

A1 to A4, B1: semiconductor device 10: metal substrate 11: conductor layer 11a: mounting surface 111: first wiring portion 111a: pad 112: second wiring portion 112a: pad 113: third wiring portion 113a: pad 113b: Notch 114 : First gate portion 115 : First detection portion 116 : Thermistor mounting portion 117 : Second gate portion 118 : Second detection portion 119 : Insulation portion 12 : Metal base 12a : Main surface 12b : Back surface 13 : Insulation layer 23A: first power terminal 23B: second power terminal 231: external connection portion 231a: connection hole 232: internal connection portion 232a: connecting portion 232b: extension portion 233: intermediate portion 233a: base portion 233b: standing portion 239: insulating member 24: output terminal 24A: first terminal portion 24B: second terminal portion 241: external connection portion 241a: connection hole 242: internal connection portion 243: intermediate portion 243a: base portion 243b: standing portion 25A: first gate terminal 25B: second terminal portion 2 gate terminal 26A: first detection terminal 26B: second detection terminal 27: power supply current detection terminal 28: thermistor terminal 29: non-connect terminal 31: first semiconductor chip 32: second semiconductor chip 301: source electrode 302: drain electrode 303: gate electrode 33: thermistor 40: conductive member 41: first conductive member 42: second conductive member 431: first gate wire 432: second gate wire 433: third gate wire 434: fourth gate wire 441: third 1 detection wire 442 : second detection wire 443 : third detection wire 444 : fourth detection wire 45 : power supply current detection wire 46 : thermistor wire 48 : conductive member bonding layer 49 : conductive member bonding layer 51 : first layer 511 : Individual part 52 : Second layer 53 : Third layer 59 : Base part 60 : Case 611 : First side wall 612 : Second side wall 62 : Mounting part 621 : Mounting member 621a : Mounting hole 63 : Power supply terminal block 631 : First Terminal block 632 : Second terminal block 633 : Groove 634 : Nut 635 : Intermediate member 64 : Output terminal block 641 : First terminal block 642 : Second terminal block 643 : Groove 644 : Nut 645 : Intermediate member 70 : Resin member 71 : First resin layer 711 : Dimple 72 : Second resin layer 73 : Third resin layer 91 : Cooler 92 : Heat resistant grease 93 : Gap

Claims (19)

a first semiconductor chip;
a metal substrate on which the first semiconductor chip is mounted on one side in the thickness direction;
a resin member formed on a side of the metal substrate on which the first semiconductor chip is mounted in the thickness direction;
and
The resin member has a first resin layer formed on the metal substrate and covering the first semiconductor chip, and a second resin layer formed on the first resin layer,
a difference between a coefficient of thermal expansion of the first resin layer and a coefficient of thermal expansion of the first semiconductor chip is smaller than a difference between a coefficient of thermal expansion of the metal substrate;
The coefficient of thermal expansion of the second resin layer is higher than the coefficient of thermal expansion of the first resin layer.
semiconductor device. A case that includes the metal substrate as a bottom plate and houses the first semiconductor chip, the first resin layer, and the second resin layer,
A semiconductor device according to claim 1 . further comprising a third resin layer interposed between the first resin layer and the second resin layer,
The third resin layer contains the material of the first resin layer and the material of the second resin layer,
3. The semiconductor device according to claim 2. The surface of the first resin layer facing one of the thickness directions is rougher than the surface of the second resin layer facing one of the thickness directions.
A semiconductor device according to claim 1 . A plurality of dimples are formed on the surface of the first resin layer facing one of the thickness directions,
A semiconductor device according to claim 1 . The thermal expansion coefficient of the second resin layer is 50% or more and 150% or less with respect to the thermal expansion coefficient of the metal substrate.
6. The semiconductor device according to claim 1. The metal substrate has a metal base, an insulating layer and a conductor layer,
The metal base has a main surface and a back surface spaced apart in the thickness direction,
The insulating layer is interposed between the main surface of the metal base and the conductor layer,
The first semiconductor chip is bonded to the conductor layer,
7. The semiconductor device according to claim 1. The insulating layer is made of epoxy resin,
8. The semiconductor device according to claim 7. The metal base has a curved back surface and is convex in the other thickness direction.
9. The semiconductor device according to claim 7 or 8. the first semiconductor chip performs a switching operation;
10. The semiconductor device according to claim 7. further comprising a second semiconductor chip that performs a switching operation;
The first semiconductor chip and the second semiconductor chip are electrically connected in series,
11. The semiconductor device according to claim 10. a first power supply terminal electrically connected to the first semiconductor chip;
a second power supply terminal electrically connected to the second semiconductor chip;
an output terminal conducting to an electrical connection point between the first semiconductor chip and the second semiconductor chip;
further comprising
12. The semiconductor device according to claim 11. the conductor layer includes a first wiring portion, a second wiring portion, and a third wiring portion spaced apart from each other;
the first wiring portion is connected to the first semiconductor chip and the first power supply terminal;
the second wiring portion is connected to the second semiconductor chip and the output terminal;
The third wiring portion is joined to the second power terminal,
13. The semiconductor device according to claim 12. a first conduction member that electrically connects the first semiconductor chip and the second wiring portion;
a second conduction member that electrically connects the second semiconductor chip and the third wiring portion;
further comprising
14. The semiconductor device according to claim 13. preparing a metal substrate;
a mounting step of mounting a first semiconductor chip on one side of the metal substrate in the thickness direction of the metal substrate;
a resin member forming step of forming a resin member on a side of the metal substrate on which the first semiconductor chip is mounted in the thickness direction;
has
In the resin member forming step, a first resin layer disposed on the metal substrate and covering the first semiconductor chip, and a second resin layer disposed on the first resin layer are formed,
a difference between a coefficient of thermal expansion of the first resin layer and a coefficient of thermal expansion of the first semiconductor chip is smaller than a difference between a coefficient of thermal expansion of the metal substrate;
The coefficient of thermal expansion of the second resin layer is higher than the coefficient of thermal expansion of the first resin layer.
A method of manufacturing a semiconductor device. After the mounting step and before the resin member forming step, the method further includes a case placement step of placing a case surrounding the first semiconductor chip on the metal substrate.
16. The method of manufacturing a semiconductor device according to claim 15. The resin member forming step includes:
a first step of pouring a first resin material to be the first resin layer into the case;
a second step of pouring a second resin material to be the second resin layer into the interior of the case after the first step;
a third step of collectively curing the first resin material and the second resin material;
having
17. The method of manufacturing a semiconductor device according to claim 16. The resin member forming step includes:
a first step of pouring a first resin material into the case and curing the first resin material to form the first resin layer;
After the first step, a second step of roughening the surface of the first resin layer facing the one in the thickness direction;
a third step of, after the second step, pouring a second resin material onto the first resin layer inside the case and curing the second resin material to form the second resin layer;
having
17. The method of manufacturing a semiconductor device according to claim 16. The resin member forming step includes:
a first step of pouring a first resin material into the case and curing the first resin material to form the first resin layer;
a second step of forming a plurality of dimples on the surface of the first resin layer facing the one thickness direction after the first step;
a third step of, after the second step, pouring a second resin material onto the first resin layer inside the case and curing the second resin material to form the second resin layer;
having
17. The method of manufacturing a semiconductor device according to claim 16.

Images