JP2022188629A - electronic circuit - Google Patents

Abstract

To reduce the area of a PLL circuit while preventing both thermal noise from the PLL circuit and fixed jitter in a reference clock component.SOLUTION: An electronic circuit has: a variable delay unit that generates a standard clock and a variable clock based on a reference clock; a phase comparator that generates a first UP signal, a second UP signal, and a DOWN signal based on the reference clock, the variable clock, and a frequency dividing clock; an integration path that outputs an integrated current based on the first UP signal and the DOWN signal; a proportional path that outputs a proportional current based on the second UP signal and the DOWN signal; an oscillator that outputs an output signal in a frequency according to a control current that is the sum of the proportional current and the integrated current; and a frequency divider that divides the frequency of the output signal to output the frequency dividing clock.SELECTED DRAWING: Figure 1

Description

The present invention relates to an electronic circuit that generates an output clock based on a reference clock.

Patent Document 1 describes a phase-locked loop (PLL) circuit that has a proportional path including a charge pump circuit and an integration path including a charge pump circuit, and is capable of independently setting the integral gain and the proportional gain. there is

JP 2013-126146 A

However, in the PLL circuit described in Patent Document 1, if the integral gain and the proportional gain are set so as to satisfy the stability of the PLL circuit, the integral path charge pump circuit and the proportional path charge pump circuit have different sizes. . As a result, the PLL circuit described in Patent Document 1 has a problem that different skews occur in the integration path and the proportional path. Furthermore, due to this skew, the current charge timing of the proportional path is shifted relative to the current charge timing of the integration path, so that the fixed jitter of the reference clock component increases in the PLL circuit described in Patent Document 1. There are also challenges.

On the other hand, in the lag-lead loop filter circuit included in the PLL circuit, the resistance that determines the proportional gain generates thermal noise. had to pay to Here, in order to maintain the stability of the PLL circuit, it is required to set the cutoff frequency of the loop filter circuit to a desired value. However, since it is necessary to increase the capacitance by the amount corresponding to the decrease in the resistance value, there is a problem that the circuit area increases. Thus, the PLL circuit also has the problem that it is difficult to achieve both suppression of thermal noise and reduction in area.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the area of a PLL circuit while suppressing the thermal noise of the PLL circuit and the fixed jitter of the reference clock component.

An electronic circuit according to the present invention includes: a variable delay device that generates a reference clock and a variable clock based on a reference clock; an integration path that outputs an integrated current based on the first UP signal and the DOWN signal; and a proportional current based on the second UP signal and the DOWN signal. a proportional path for outputting; a current controlled oscillator for outputting an output signal having a frequency corresponding to a control current that is the sum of the proportional current and the integral current; and dividing the output signal to output the frequency-divided clock. and a frequency divider.

According to the present invention, it is possible to reduce the area of the PLL circuit while suppressing the thermal noise of the PLL circuit and the fixed jitter of the reference clock component.

1 is a block diagram for explaining the configuration of a PLL circuit 100, which is an electronic circuit according to Embodiment 1; FIG. 3 is a block diagram for explaining the configuration of variable delay device 101. FIG. 3 is a block diagram for explaining the configuration of a phase comparator 102; FIG. 4 is a flowchart for explaining control processing performed by a control unit 110; FIG. 4 is a diagram showing timing charts of a plurality of clock signals; 4 is a timing chart of input signals and output signals of a first charge pump circuit 111 and a second charge pump circuit 114; FIG.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments.

[Embodiment 1]
FIG. 1 is a block diagram for explaining the configuration of a phase-locked loop (PLL) circuit 100, which is an electronic circuit according to the first embodiment.

As shown in FIG. 1, the PLL circuit 100 includes a variable delay device 101, a phase comparator 102, an integrating path 103, a proportional path 104, an adding section 105, a current controlled oscillator 106, a frequency divider 107, a detecting section 108, an ADC 109, It has a control unit 110 .

The PLL circuit 100 receives the reference clock N001 and outputs an output clock N013 having a frequency obtained by multiplying the frequency of the reference clock N001. Furthermore, the PLL circuit 100 can set the frequency division ratio of the frequency divider 107 by inputting frequency division ratio setting information. The frequency of the output clock N013 is determined according to the division ratio setting information.

The variable delay device 101 generates and outputs a reference clock N002 and a variable clock N003 based on the input reference clock N001. Details will be described later.

The phase comparator 102 generates and outputs a first UP signal N004, a second UP signal N005 and a DOWN signal N006 based on the input reference clock N002, variable clock N003 and frequency-divided clock N014. Details will be described later.

Integration path 103 has first charge pump circuit 111 , integration section 112 , and voltage-current conversion section 113 . Further, integration path 103 generates and outputs integration current N010 based on input first UP signal N004 and DOWN signal N006.

The first charge pump circuit 111 outputs a first pulse current N007 based on the input first UP signal N004 and DOWN signal N006. The first charge pump circuit 111 outputs the first pulse current N007 as a positive pulse current while the first UP signal N004 is being input. Further, the first charge pump circuit 111 outputs the first pulse current N007 as a negative pulse current while the DOWN signal N006 is being input. The magnitude of the first pulse current N007 output by the first charge pump circuit 111 is determined based on the integral gain setting information.

The integrating section 112 is a capacitive circuit. An integrated voltage N008 is generated by integrating the input first pulse current N007.

The voltage-current converter 113 is a conversion circuit that converts the input integrated voltage N008 into an integrated current N010 and outputs the integrated current N010. For example, it is a source follower circuit.

Proportional path 104 has a second charge pump circuit 114 and a filter circuit 115 . Further, proportional path 104 generates and outputs second pulse current N009 based on second UP signal N005 and DOWN signal N006 that are input.

The second charge pump circuit 114 outputs a second pulse current N009 based on the input second UP signal N005 and DOWN signal N006. The second charge pump circuit 114 outputs the second pulse current N009 as a positive pulse current while the second UP signal N005 is being input. Further, the second charge pump circuit 114 outputs the second pulse current N009 as a negative pulse current while the DOWN signal N006 is being input. The magnitude of the second pulse current N009 output by the second charge pump circuit 114 is determined based on the proportional gain setting information.

Filter circuit 115 outputs proportional current N011, which is a current obtained by passing only a predetermined frequency band from second pulse current N009.

Adder 105 is a connection node for adding integral current N010 and proportional current N011. The current after the addition is set as control current N012.

The current controlled oscillator 106 is an oscillator that generates a clock with a frequency corresponding to the control current N012 and outputs it as an output clock N013. The current controlled oscillator 106 has, for example, a ring oscillator, an LC oscillator, or the like.

The frequency divider 107 divides the frequency of the output clock N013 according to the frequency division ratio determined according to the frequency division ratio setting information, and outputs the frequency-divided clock N014.

Detector 108 selects and detects either the offset amount or the pulse amount of second pulse current N009 based on mode change signal N018 transmitted from controller 110, thereby generating detection voltage N015.

The ADC 109 converts the detected voltage N015 from an analog amount to a digital amount and outputs it as detection information N016.

Control unit 110 outputs control signal N017 determined based on detection information N016. Processing for determining the control signal N017 will be described later.

Next, the configuration of variable delay device 101 will be described with reference to FIG.

Variable delay device 101 has five buffers 116-a to 116-e, five capacitors 117-a to 117-e, and three switches 118-a to 118-c.

Buffer 116-a amplifies reference clock N001 and sends the output to buffers 116-b and 116-d.

Buffer 116-b amplifies the output of buffer 116-a. A capacitor 117-a is connected to the output of the buffer 116-b to reduce the slew rate of the output of the buffer 116-b. The size of capacity 117-a is four times that of capacity 117-e.

Buffer 116-c amplifies the output of buffer 116-b and outputs reference clock N002. Let the delay time of the reference clock N002 with respect to the reference clock N001 in this case be the first time.

Buffer 116-d amplifies the output of buffer 116-a. Capacitors 117-b to 117-e are connected to the output of the buffer 116-d to reduce the slew rate of the output of the buffer 116-d. The size of capacity 117-b is four times that of capacity 117-e. The size of capacity 117-c is twice that of capacity 117-e. The size of capacitor 117-d is the same as that of capacitor 117-e.

Switches 118-a, 118-b and 118-c connected to capacitors 117-b, 117-c and 117-d are opened and closed by control signal N017.

Buffer 116-e amplifies the output of buffer 116-d and outputs variable clock N003. Let the delay time of the variable clock N003 with respect to the reference clock N001 in this case be the second time.

With this configuration, the variable delay device 101 can generate the reference clock N002 by delaying the reference clock N001 by the first time. Furthermore, the variable delay device 101 determines a second time by increasing or decreasing the amount of time based on the control signal N017 with the first time as a reference, and delays the reference clock N001 by the second time to obtain a variable clock. N003 can be generated.

Next, the configuration of phase comparator 102 will be described with reference to FIG.

The phase comparator 102 has a buffer 116-f, a NAND circuit 119, three flip-flops 120-a to 120-c, and a high level output circuit 121.

The flip-flop 120-a outputs the first UP signal N004 as a high level voltage in response to the transition of the reference clock N002 in the rising direction.

The flip-flop 120-b outputs the second UP signal N005 as a high level voltage in response to the transition of the variable clock N003 in the rising direction.

The flip-flop 120-c outputs the DOWN signal N006 as a high level voltage in response to the transition of the divided clock N014 in the rising direction.

The NAND circuit 119 outputs a low level voltage when all of the first UP signal N004, the second UP signal N005, and the DOWN signal N006 are output as high level voltages.

Buffer 116-f amplifies the output of NAND circuit 119 and outputs it.

The flip-flops 120-a to 120-c convert the first UP signal N004, the second UP signal N005, and the DOWN signal N006 to low level voltages when the output of the buffer 116-f becomes a low level voltage. Output.

The high level output circuit 121 outputs a fixed high level voltage.

With this configuration, the phase comparator 102 can output the first UP signal N004 in response to the transition of the reference clock N002 with a predetermined polarity. The phase comparator 102 can output the second UP signal N005 in response to the transition of the variable clock N003 with a predetermined polarity. The phase comparator 102 can also output the DOWN signal N006 in response to the transition of the divided clock N014 with a predetermined polarity. Further, the phase comparator 102 outputs the first UP signal N004, the second UP signal N005 and the DOWN signal when all of the first UP signal N004, second UP signal N005 and DOWN signal N006 are output. The output of N006 can also be stopped.

Next, control processing performed by the control unit 110 will be described with reference to the flowchart of FIG. The control processing illustrated in FIG. 4 is performed by a computer in control unit 110 executing a program stored in memory.

In step S1, the control unit 110 changes the mode change signal N018 so as to detect the offset amount of the second pulse current N009. By the process of step S1, control unit 110 changes the state of detection unit 108 so that detection unit 108 detects the offset amount of second pulse current N009 at timing T3 shown in FIG. After that, the controller 110 proceeds from step S1 to step S2.

In step S2, control unit 110 acquires detection information N016. After that, the controller 110 proceeds from step S2 to step S3.

In step S3, control unit 110 stores detection information N016 acquired in step S2 as offset amount information. After that, the controller 110 proceeds from step S3 to step S4.

In step S4, control unit 110 changes mode change signal N018 to detect the pulse amount of second pulse current N009. By the processing of step S4, control unit 110 changes the state of detection unit 108 so that detection unit 108 detects the pulse amount of second pulse current N009 at timing T4 shown in FIG. After that, the controller 110 proceeds from step S4 to step S5.

In step S5, the control unit 110 repeats processing. The control unit 110 adds 1 to the integer i (initial value is 0) for each iteration. When i is less than 8, repeat processing is performed, and when i is 8 or more, the repeat processing is exited. After that, the controller 110 proceeds from step S5 to step S6.

In step S6, control unit 110 sets control signal N017 to the value of i. By the process of step S6, the switch 118 in the variable delay device 101 is opened and closed, the corresponding capacitor 117 is enabled, and the second time is changed. Thereafter, the controller 110 proceeds from step S6 to step S7.

In step S7, control unit 110 acquires detection information N016. Thereafter, the controller 110 proceeds from step S7 to step S8.

In step S8, the control unit 110 stores the detection information N016 acquired in step S7 as the i-th pulse amount information. After that, the controller 110 proceeds from step S8 to step S9.

In step S9, the control unit 110 stores the difference between the offset amount information and the i-th pulse amount information as the i-th difference information. Thereafter, the controller 110 proceeds from step S9 to step S10.

In step S10, control unit 110 determines whether the value of i is greater than zero. When the control unit 110 determines that the value of i is greater than 0, the control unit 110 proceeds from step S10 to step S11. When the control unit 110 determines that the value of i is not greater than 0, the control unit 110 proceeds from step S10 to step S14.

In step S11, the control unit 110 determines whether the value indicated by the i-th difference information is greater than the value indicated by the i-1-th difference information. When the control unit 110 determines that the value indicated by the i-th difference information is larger than the value indicated by the (i−1)-th difference information, the control unit 110 proceeds from step S11 to step S12. When the control unit 110 determines that the value indicated by the i-th difference information is not larger than the value indicated by the (i-1)-th difference information, the control unit 110 proceeds from step S11 to step S13.

In step S12, control unit 110 sets the value of j to i. Thereafter, the controller 110 proceeds from step S12 to step S15.

In step S13, control unit 110 sets the value of j to i−1. Thereafter, the controller 110 proceeds from step S13 to step S15.

In step S14, control unit 110 sets the value of j to zero. Thereafter, the controller 110 proceeds from step S14 to step S15.

In step S15, control unit 110 terminates the repetition process started in step S5. After that, the controller 110 proceeds from step S15 to step S16.

In step S16, control unit 110 sets the value of control signal N017 to j. After that, the control unit 110 terminates the control process.

The above-described control processing performed by the control unit 110 is performed at least once when the PLL circuit 100 is activated. Further, even if the characteristics of the PLL circuit 100 change due to a change in temperature or the like, it is performed again at an arbitrary timing as necessary.

By controlling in this manner, the control unit 110 controls the detection unit 108 to detect the offset amount by changing the mode change signal N018, and saves the detection information N016 indicating the offset amount as the offset amount information. be able to. The control unit 110 can also control the detection unit 108 to detect the pulse amount by changing the mode change signal N018, and store the detection information N016 indicating the pulse amount as the pulse amount information. Further, the control section 110 can compare the offset amount information and the pulse amount information and determine the control signal N017 so that the difference between the offset amount information and the pulse amount information becomes small.

Next, a timing chart of a plurality of clock signals will be described with reference to FIG.

W001 shown in FIG. 5 is a timing chart of the reference clock N001. W002 shown in FIG. 5 is a timing chart of the reference clock N002. W002 is delayed from W001 by a first time T1.

W003-0 shown in FIG. 5 is a timing chart of the variable clock N003 when the control signal N017 is "0". W003-0 is delayed from W001 by the second time T2(0) when the value of the control signal N017 is 0.

W003-1 to W003-7 shown in FIG. 5 are timing charts of the variable clock N003 when the control signal N017 changes from 1 to 7. FIG. W003-1 to W003-7 are delayed from W001 by a second time T2(i) when the value of the control signal N017 is i.

W014 shown in FIG. 5 is a timing chart of the frequency-divided clock N014.

Next, a timing chart of input signals and output signals of the first charge pump circuit 111 and the second charge pump circuit 114 will be described with reference to FIG.

W004-(a), W005-(a), W006-(a), W007-(a) and W009-(a) shown in FIG. 6 are waveforms before fixed jitter reduction. W004-(b), W005-(b), W006-(b), W007-(b) and W009-(b) shown in FIG. 6 are waveforms after fixed jitter is reduced.

W004-(a) and W004-(b) shown in FIG. 6 are waveforms of the first UP signal N004. W005-(a) and W005-(b) shown in FIG. 6 are waveforms of the second UP signal N005. W006-(a) and W006-(b) shown in FIG. 6 are waveforms of the DOWN signal N006.

W007-(a) and W007-(b) shown in FIG. 6 are waveforms of the first pulse current N007. W009-(a) and W009-(b) shown in FIG. 6 are waveforms of the second pulse current N009.

A period T3 shown in FIG. 6 is a period during which the detection unit 108 detects the offset amount of the second pulse current N009. A period T4 shown in FIG. 6 is a period during which the detection unit 108 detects the pulse amount of the second pulse current N009.

P1 shown in FIG. 6 is the second pulse current N009 during the period of T3 before fixed jitter reduction. Since the second pulse current N009 is a stable offset current, the detection unit 108 can detect the offset amount of the second pulse current N009 during the period of T3.

P2 shown in FIG. 6 is the second pulse current N009 during the period of T4 before fixed jitter reduction. Due to the skew between the integral path 103 and the proportional path 104, the current charge timing of the proportional path 104 shifts relative to the current charge timing of the integral path 103. Therefore, during the period T4, the second pulse current N009 has a pulse-like current. A current is generated. Therefore, the detection unit 108 can detect the pulse amount of the second pulse current N009.

P3 shown in FIG. 6 is the second pulse current N009 during the period of T4 after fixed jitter reduction.

The skew between the integral path 103 and the proportional path 104 can be canceled by the controller 110 performing the above-described control processing to control the phase of the variable clock N003. Here, P3, which is the pulse amount of the second pulse current N009 during the period T4, becomes smaller than P2, making it possible to reduce fixed jitter.

Note that the configuration of the PLL circuit 100 is not limited to the configuration described in the first embodiment. For example, the components included in PLL circuit 100 may be replaced with one or more components having similar functions.

[Embodiment 2]
At least one of the various functions, processes and methods described in Embodiment 1 can be implemented using a program. Hereinafter, in the second embodiment, a program for realizing at least one of the various functions, processes and methods described in the first embodiment will be referred to as "program X". Furthermore, in the second embodiment, a computer for executing program X is called "computer Y". Examples of the computer Y are a personal computer, a microcomputer, a CPU (Central Processing Unit), and the like.

At least one of the various functions, processes and methods described in Embodiment 1 can be implemented by computer Y executing program X. In this case, program X is supplied to computer Y via a computer-readable storage medium. A computer-readable storage medium in the second embodiment includes at least one of a hard disk device, a magnetic storage device, an optical storage device, a magneto-optical storage device, a memory card, a ROM, and a RAM. Furthermore, the computer-readable storage medium in Embodiment 2 is a non-transitory storage medium.

100 PLL circuit (electronic circuit)
101 variable delay device 102 phase comparator 103 integration path 104 proportional path 105 adder 106 current controlled oscillator 107 frequency divider 108 detector 109 ADC
110 control unit 111 first charge pump circuit 112 integration unit 113 voltage-current conversion unit 114 second charge pump circuit 115 filter circuit

Claims (7)

a variable delay that generates a reference clock and a variable clock based on a reference clock;
a phase comparator that generates a first UP signal, a second UP signal and a DOWN signal based on the reference clock, the variable clock and the divided clock;
an integration path that outputs an integration current based on the first UP signal and the DOWN signal;
a proportional path that outputs a proportional current based on the second UP signal and the DOWN signal;
an oscillator that outputs an output signal having a frequency corresponding to a control current that is the sum of the proportional current and the integral current;
and a frequency divider that outputs the frequency-divided clock by frequency-dividing the output signal. The integral path is
a first charge pump circuit that outputs a first pulse current based on the first UP signal and the DOWN signal;
an integration unit that generates an integration voltage by inputting the first pulse current to a capacitor;
2. The electronic circuit according to claim 1, further comprising: a converter that outputs the integrated current based on the integrated voltage. The proportional path is
a second charge pump circuit that outputs a second pulse current based on the second UP signal and the DOWN signal;
3. The electronic circuit according to claim 1, further comprising a filter circuit for outputting the proportional current, which is a current obtained by passing only a predetermined frequency band from the second pulse current. a detection unit that selects and detects either the offset amount or the pulse amount of the second pulse current based on a mode change signal transmitted from the control unit to generate a detection voltage;
an ADC that converts the detected voltage from an analog amount to a digital amount and outputs it as detection information;
4. The electronic circuit according to claim 3, further comprising the control section that outputs a control signal determined based on the detection information. The control unit
controlling the detection unit to detect the offset amount by changing the mode change signal;
storing the detection information indicating the offset amount as offset amount information;
controlling the detection unit to detect the pulse amount by changing the mode change signal;
storing the detection information indicating the pulse amount as pulse amount information;
comparing the offset amount information and the pulse amount information;
5. The electronic circuit according to claim 4, wherein the control signal is determined so that a difference between the offset amount information and the pulse amount information is small. The variable delay device
generating the reference clock by delaying the reference clock by a first time;
generating the variable clock by delaying the reference clock by a second time;
6. The electronic circuit according to claim 4, wherein the second time is determined by increasing or decreasing the amount of time based on the control signal with respect to the first time. The phase comparator is
outputting the first UP signal in response to the transition of the reference clock with a predetermined polarity;
outputting the second UP signal in response to the transition with the predetermined polarity of the variable clock;
outputting the DOWN signal in response to the transition with the predetermined polarity of the frequency-divided clock;
stopping the output of the first UP signal, the second UP signal and the DOWN signal when all of the first UP signal, the second UP signal and the DOWN signal are output; 7. An electronic circuit as claimed in any one of claims 1 to 6.

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