JP2006025131A - Pll circuit and dll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit and a DLL circuit that shorten a time up to locking, vary an initial control voltage according to use of a circuit, and prevent the time up to locking from varying with manufacturing conditions etc., and also to provide a DLL circuit capable of speedily reducing jitters. <P>SOLUTION: The PLL circuit includes: a phase comparator 3; a charge pump 4; a loop filter 5; a voltage-controlled oscillator 6; a voltage setting circuit 10 which selects a level of a control voltage according to a select signal; and a set value decision circuit 9 which outputs at least one of a plurality of select signals, detects a multiple of an input clock for an output clock increased or decreased in frequency by the voltage-controlled oscillator 6, and specifies and outputs an optimum select signal among the plurality of select signals to the voltage setting circuit 10. The respective circuits start and stop processes according to a standby signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PLL circuit and a DLL circuit, and more particularly to a PLL circuit and a DLL circuit that shorten the time until locking. The present invention also relates to a DLL circuit, and more particularly to a DLL circuit that suppresses fluctuations in an output clock.

  A PLL (phase locked loop) circuit and a DLL (delay locked loop) circuit are widely used in ICs (integrated circuits) such as communication LSIs, microcomputers, and DSPs (Digital Signal Processors).

  In the conventional PLL circuit, the switching transistor is turned on and off so that the power supply can be intermittently performed as needed, and at a certain time immediately after the switching transistor is turned on and the power supply is started, A capacitor is rapidly charged by a rapid charging circuit so that the rise of the control voltage of the voltage controlled oscillator is made steep, and the disadvantage associated with intermittent power supply is overcome (see, for example, Patent Document 1).

  By using such a PLL circuit for a mobile phone, in order to reduce power consumption in the standby mode, the power supply to the PLL circuit is stopped, and when the standby mode is canceled and the power supply is started, the PLL circuit is immediately started. Is locked, and the operation of the PLL circuit can be stabilized.

  Further, in the conventional PLL circuit, the control voltage of the voltage controlled oscillator corresponding to the frequency to be used is stored in advance, and the digital value of the stored control voltage corresponding to the set frequency at the end of the frequency setting. Is converted to an analog voltage and applied to a voltage controlled oscillator (see, for example, Patent Document 2).

  In the conventional DLL circuit, the variable delay circuit delays the reference clock signal to generate the control clock signal. The dummy circuit delays the control clock signal to generate a delayed clock signal. The phase comparison circuit compares the phases of the delayed clock signal and the reference clock signal. The delay control circuit sequentially receives a plurality of phase comparison results by the phase comparison circuit, adjusts the delay time of the variable delay circuit based on the plurality of phase comparison results, the delay clock signal and the reference clock signal Match the phase with. Since the delay control circuit and the variable delay circuit are prevented from operating excessively, the amount of advance or delay of the phase of the control clock signal in one phase adjustment is the smallest unit that can be adjusted by the variable delay circuit. As a result, the control clock signal jitter, that is, phase noise is reduced (see, for example, Patent Document 3).

Here, “lock” means that the phases of two clocks subject to phase comparison, that is, the phases of the input clock and the output clock of the PLL circuit and the DLL circuit match, or either one or both of the input clock and the output clock. This means that the phases of the clocks obtained by dividing the frequency are matched.
JP-A-5-129945 JP-A-6-61852 JP 2001-290555 A

  However, in the PLL circuit described in Patent Document 1, the capacitor is charged after the power supply is started, and the rise of the control voltage of the voltage controlled oscillator is made steep so that the capacitor is charged to a desired control voltage. Since the PLL circuit does not lock until it reaches, there is a drawback that the time until the PLL circuit is locked cannot be shortened sufficiently.

  Further, in the PLL circuit described in Patent Document 2, the control voltage of the voltage controlled oscillator corresponding to the desired frequency is fixedly stored, and this control voltage is applied to the voltage controlled oscillator. The control voltage for accelerating the lock immediately after release (hereinafter referred to as the initial control voltage) cannot be changed according to the application of the IC in which the PLL circuit is used, and due to the influence of manufacturing conditions and the surrounding environment, There was a drawback that it was not possible to prevent the time until locking from fluctuating.

  This is because, for example, the microcomputer can change the setting of the operating frequency, that is, the setting change of the frequency of the output clock of the voltage controlled oscillator in the PLL circuit, but the initial control voltage can be changed as in the PLL circuit described in Patent Document 2. This is because the initial control voltage cannot be changed in accordance with the setting change of the operating frequency of the microcomputer in the configuration in which the fixed storage is performed. In addition, since the control voltage that is actually locked by the PLL circuit varies depending on the manufacturing conditions and the surrounding environment such as temperature, a configuration in which the initial control voltage is fixedly stored as in the PLL circuit described in Patent Document 2. The reason for this is that the time until locking varies depending on these factors.

  Further, the DLL circuit described in Patent Document 3 has a configuration in which the delay adjustment is performed using the result of a plurality of phase comparisons in the phase comparison circuit, so that the jitter generated in the clock cannot be quickly reduced. there were.

  Therefore, the present invention can sufficiently shorten the time until the PLL circuit and the DLL circuit are locked, and the initial control voltage is changed according to the application of the IC in which the PLL circuit and the DLL circuit are used. It is another object of the present invention to provide a PLL circuit and a DLL circuit that can prevent fluctuations in the time until locking due to the influence of manufacturing conditions and the surrounding environment.

  It is another object of the present invention to provide a DLL circuit that can quickly reduce jitter generated in a clock.

  In order to solve the above problems, a PLL circuit according to an aspect of the present invention detects a phase difference between an input clock and an output clock, and performs a phase comparison process for outputting a phase difference signal corresponding to the phase difference. And a charge pump that performs phase difference current conversion processing to increase / decrease the control current according to the phase difference signal, and to smooth the output control current and convert the smoothed control current to the first control voltage An output loop filter, a voltage controlled oscillator that performs voltage frequency conversion processing to increase and decrease the frequency of the output clock according to the first control voltage or the second control voltage, and an input selection signal A voltage setting circuit for performing a control voltage output process for selecting and outputting a level of the second control voltage, and a plurality of levels for setting the level of the second control voltage output by the voltage setting circuit. A first multiplication number of the output clock output from the voltage controlled oscillator according to the second control voltage output from the voltage setting circuit according to the selection signal by outputting at least one of the selection signals to the voltage setting circuit. Is detected, the optimum selection signal is identified from among the plurality of selection signals based on the first multiplication number, and a set value determination process is performed to fix the identified selection signal as a selection signal to be output to the voltage setting circuit. A charge pump, a voltage-controlled oscillator, a voltage setting circuit, and a setting value determination circuit including a phase difference current conversion process, a voltage frequency conversion process, a control voltage output process, and a setting value determination process. Start and stop.

  In order to solve the above problems, a DLL circuit according to an aspect of the present invention detects a phase difference between an input clock and an output clock, and performs a phase comparison process for outputting a phase difference signal corresponding to the phase difference. And a charge pump that performs phase difference current conversion processing to increase / decrease the control current according to the phase difference signal, and to smooth the output control current and convert the smoothed control current to the first control voltage Then, a loop clock to be output, and a delay clock and an output clock in which the delay amount given to the input clock is increased or decreased according to the first control voltage or the second control voltage are generated and output voltage delay amount conversion processing is performed. A voltage-controlled delay circuit, a multiplexer that generates and multiplies the input clock from the delay clock and the output clock, and outputs a multiplexer. In order to set the level of the second control voltage output from the voltage setting circuit for performing the control voltage output process for selecting and outputting the control voltage level, and at least one of the plurality of selection signals Is output to the voltage setting circuit, the first multiplication number of the multiplication clock with respect to the input clock is detected, and the optimum selection signal is identified from the plurality of selection signals based on the first multiplication number and specified. A set value determination circuit for performing a set value determination process for fixing the selected signal as a selection signal to be output to the voltage setting circuit. The charge pump, the voltage control delay circuit, the voltage setting circuit, and the set value determination circuit are used as standby signals. Accordingly, phase difference current conversion processing, voltage delay amount conversion processing, control voltage output processing, and set value determination processing are started and stopped.

  According to still another aspect of the present invention, a DLL circuit detects a phase difference between an input clock and an output clock and outputs a phase difference signal according to the phase difference, and a control current according to the phase difference signal. A charge pump that performs phase difference current conversion processing that outputs and outputs, a loop filter that smoothes the output control current, converts the smoothed control current into a control voltage, and outputs it according to the control voltage Generates a delay clock and output clock with the amount of delay applied to the input clock increased or decreased, detects the phase difference between the voltage control delay circuit that performs voltage delay amount conversion processing and the input clock and output clock, and responds to the phase difference A phase difference determination circuit that generates and outputs a selection signal, and a correction delay clock that increases or decreases the amount of delay applied to the delay clock and output clock according to the selection signal. And a jitter correction circuit for outputting corrected output clock, and generates a multiplied clock of the input clock from the corrected delayed clock and the correction output clock, and an output multiplexer.

  In the PLL circuit and the DLL circuit, it is possible to shorten the time until locking, and the initial control voltage can be changed according to the application of the IC in which the PLL circuit and the DLL circuit are used. It is possible to prevent the time until locking from fluctuating due to the influence of the conditions and the surrounding environment, and it is possible to quickly reduce jitter generated in the clock in the DLL circuit.

<First Embodiment>
[PLL circuit assumed to be used conventionally]
First, for comparison with the PLL circuit according to the present embodiment, a PLL circuit assumed to be conventionally used will be described with reference to the drawings.

[Constitution]
FIG. 1 shows the configuration of a PLL circuit that is assumed to be used conventionally. Referring to FIG. 1, this PLL circuit includes a frequency divider 1, a frequency divider 2, a phase comparator 3, a charge pump 4, a loop filter 5, a voltage controlled oscillator 6, and a voltage setting circuit 7. And timer 8.

[Operation]
First, the operation of the PLL circuit in the normal state will be described.

  The frequency divider 1 receives the reference clock CR and outputs a frequency-divided clock CRM obtained by dividing the reference clock 1 / M. The frequency divider 2 receives the output clock CO from the voltage controlled oscillator 6 and outputs a frequency-divided clock CON obtained by dividing the output clock CO by 1 / N.

  Here, the frequency divider 1 and the frequency divider 2 are provided because a microcomputer or the like normally generates an operation clock, that is, an output clock CO by multiplying the reference clock CR, and an output clock of the voltage controlled oscillator 6. This is because the frequency of the CO and the reference clock CR is different, and therefore it is necessary to perform phase comparison after matching the frequencies of the two. Further, the design is facilitated by reducing the operating frequencies of the phase comparator 3, the charge pump 4, and the loop filter 5.

  Therefore, the multiplication number of the output clock CO with respect to the reference clock CR set in the PLL circuit is N / M.

  The phase comparator 3 detects the phase difference between the frequency-divided clock CRM sent from the frequency divider 1 and the frequency-divided clock CON sent from the frequency divider 2, and the phase of the frequency-divided clock CON to match the phases. When it is necessary to advance, the up signal SU is output, and when it is necessary to delay the phase, the down signal SD is output.

  The charge pump 4 increases or decreases the output current IC in accordance with the up signal SU or the down signal SD sent from the phase comparator 3 and outputs it.

  The loop filter 5 smoothes the output current IC sent from the charge pump 4 and outputs a control voltage VC corresponding to the output current IC.

  The voltage controlled oscillator 6 changes the frequency of the output clock CO according to the control voltage VC sent from the loop filter 5.

  Therefore, in this PLL circuit, the phase of the divided clock CON is changed by changing the frequency of the output clock CO that is the basis of the divided clock CON in accordance with the phase difference between the divided clock CRM and the divided clock CON. The phase of the divided clock CON and the divided clock CRM are matched, that is, controlled to be locked.

  Here, “lock” means that the phases of two clocks to be phase-matched coincide as described above. However, the fact that the phases coincide with each other in every clock cycle means that the frequencies of both clocks are equal. Means you are doing it. Therefore, the lock of the PLL circuit means that the frequencies of the two clocks that are the objects of the phase comparison match and the phases match.

  Next, the operation when the PLL circuit transitions from the reset state to the normal state will be described.

  When the reset signal RST sent from the outside changes from the reset state to the logic level indicating the normal state, the timer 8 generates and outputs a reset pulse RSTP having a width corresponding to several cycles of the reference clock CR.

  When the reset pulse RSTP is sent from the timer 8, the charge pump 4 stops the increase / decrease of the output current IC according to the up signal SU or the down signal SD and the output of the output current IC during the period of receiving the reset pulse RSTP, The voltage setting circuit 7 outputs a constant voltage as the control voltage VC while receiving the reset pulse RSTP. That is, this constant voltage is such a voltage that the voltage controlled oscillator 6 outputs the output clock CO having a desired frequency.

  When the reset pulse RSTP is not sent, the charge pump 4 starts increasing / decreasing the output current IC and outputting the output current IC according to the up signal SU or the down signal SD, and the voltage setting circuit 7 controls the control voltage VC. Stop the output of.

  Next, the voltage setting circuit 7 in the PLL circuit will be described with reference to the drawings.

[Constitution]
FIG. 2 shows the configuration of the voltage setting circuit 7 in this PLL circuit. Referring to FIG. 3, voltage setting circuit 7 includes a load 17, an analog buffer 13, a switch 14, and a switch 15.

[Operation]
When the reset pulse RSTP is received from the timer 8, the switch 14 and the switch 15 are turned on, and the voltage divided by the load 17 is applied to the analog buffer 13 and output as the control voltage VC.

  When the reset pulse RSTP is not sent from the timer 8, the switch 14 and the switch 15 are turned off, and the output of the control voltage VC is stopped.

  As described above, when the PLL circuit transitions from the reset state to the normal state, the PLL circuit immediately applies the control voltage VC corresponding to a desired frequency to the voltage controlled oscillator 6 so that the PLL circuit immediately after transition from the reset state to the normal state. The frequency of the output clock CO is significantly different from the desired frequency, and it can be prevented that it takes a long time for the PLL circuit to lock, and the time to lock can be shortened.

  However, in the PLL circuit assumed to be conventionally used as shown in FIG. 1, since the control voltage VC applied by the voltage setting circuit 7 is fixed, the initial control voltage of the voltage controlled oscillator 6 is set as the PLL circuit. There is a drawback that it cannot be changed according to the application of the IC used, and that it cannot be prevented that the time until locking is fluctuated due to the influence of manufacturing conditions and the surrounding environment.

  Next, embodiments of the present invention will be described with reference to the drawings.

[PLL circuit of the present invention]
[Constitution]
FIG. 3 shows the configuration of the PLL circuit according to the first embodiment. Referring to the figure, this PLL circuit further includes a set value determination circuit 9, a power supply control circuit 12, a voltage, in addition to the PLL circuit assumed to be conventionally used as shown in FIG. A voltage setting circuit 10 is included instead of the setting circuit 7, and a timer 11 is included instead of the timer 8.

  The standby signal STY sent from the outside is sent to the timer 11, the frequency divider 1, the frequency divider 2, the phase comparator 3, the charge pump 4, and the voltage controlled oscillator 6.

  The timer 11 generates a standby signal STYP1 (first control signal) and a standby signal STYP2 (second control signal) in response to a standby signal STY sent from the outside, and sets the standby signal STYP1 to the voltage-controlled oscillator 6. Output to value determination circuit 9 and voltage setting circuit 10, and output standby signal STYP 2 to charge pump 4 and voltage setting circuit 10.

  The power supply control circuit 12 is connected to the frequency divider 1, the frequency divider 2, the phase comparator 3, the charge pump 4, the voltage control oscillator 6, the set value determination circuit 9, and the voltage setting circuit 10, and sends control signals to each circuit. By outputting, power supply to each circuit is stopped.

  Hereinafter, the start and stop of the operation of each circuit according to the logic levels of the standby signal STY, standby signal STYP1, and standby signal STYP2 received by each circuit will be briefly described. Details of the operation will be described later.

  The charge pump 4 starts operation when the standby signal STY is at a logic high level (hereinafter referred to as H level) and the standby signal STYP2 is at a logic low level (hereinafter referred to as L level). The charge pump 4 stops operating when the standby signal STY is at a logic low level or when the standby signal STYP2 is at a logic high level.

  Here, “stopping the operation” means fixing the input signal at the H level or the L level in the circuit. As a result, the dynamic power consumption accompanying the switching operation of the transistor is reduced, and the output signal of the circuit is fixed by fixing the output signal of the circuit to the H level or the L level by fixing the logic level. This is performed for the purpose of reducing the dynamic power consumption of the subsequent circuit that receives the signal.

  The frequency divider 1, the frequency divider 2, and the phase comparator 3 start operating when the standby signal STY becomes H level and stop operating when the standby signal STY becomes L level.

  The voltage controlled oscillator 6 starts operation when at least one of the standby signal STY and the standby signal STYP1 becomes H level, and stops operation when both of them become L level.

  The set value determination circuit 9 starts its operation when the standby signal STYP1 becomes H level and stops its operation when it becomes L level.

  The voltage setting circuit 10 starts the operation when at least one of the standby signal STYP1 and the standby signal STYP2 becomes the H level, and stops the operation when both become the L level.

  Other configurations are the same as those of the PLL circuit assumed to be conventionally used shown in FIG.

[Operation]
Next, the operation of the PLL circuit according to the present embodiment will be described with reference to the time chart shown in FIG.

  This PLL circuit is in a normal state before (a) in FIG. 4 and after (d) in FIG. 4, and operates in the same manner as in the normal state of the PLL circuit assumed to be conventionally used shown in FIG. To do.

  When the standby signal STY changes from the H level to the L level, the PLL circuit shifts to the standby mode ((a) in FIG. 4).

  First, when the standby signal STY changes from the H level to the L level, the timer 11 changes the standby signal STYP1 from the L level to the H level.

  When the standby signal STY becomes L level, the frequency divider 1 stops outputting the frequency-divided clock CRM.

  When the standby signal STY becomes L level, the frequency divider 2 stops outputting the frequency-divided clock CON.

  When the standby signal STY becomes L level, the phase comparator 3 stops outputting the up signal SU or the down signal SD.

  When the standby signal STY becomes L level, the charge pump 4 stops increasing / decreasing the output current IC according to the up signal SU or the down signal SD and stops outputting the output current IC.

  Thus, the phase difference between the divided clock CRM and the divided clock CON is not reflected in the control voltage VC, that is, the frequency of the output clock CO of the voltage controlled oscillator 6.

  Therefore, when the operation of the charge pump 4 is stopped, the operations of the frequency divider 1, the frequency divider 2, and the phase comparator 3 do not affect the frequency of the output clock CO. Therefore, in this case, the frequency divider 1, the frequency divider 2, and the phase comparator 3 do not necessarily have to stop operating.

  When the standby signal STYP1 becomes H level, the voltage setting circuit 10 outputs a voltage corresponding to the selection signal SV sent from the set value determination circuit 9 to the voltage controlled oscillator 6 as the control voltage VC. That is, the frequency of the output clock CO is determined not by the control voltage VC output from the charge pump 4 but by the control voltage VC output from the voltage setting circuit 10.

  When the standby signal STYP1 becomes H level, the set value determining circuit 9 changes the control voltage VC output from the voltage setting circuit 10 by changing the selection signal SV, and changes the frequency of the output clock CO. Then, the multiplication number of the output clock CO with respect to the reference clock CR is detected from the output clock CO and the reference clock CR, and compared with a desired multiplication number set in the PLL circuit. The selection signal SV is selected and held. At this time, the held selection signal SV is output to the voltage setting circuit 10.

  Next, the timer 11 changes the standby signal STYP1 from the H level to the L level when a sufficient period of time has elapsed for the set value determination circuit 9 to select and hold the selection signal SV (FIG. 4B). ).

  The set value determination circuit 9 stops its operation when the standby signal STYP1 becomes L level, but the selection signal SV remains held and is output to the voltage setting circuit 10.

  The voltage setting circuit 10 stops the output of the control voltage VC when the standby signal STYP1 becomes L level.

  The voltage controlled oscillator 6 stops the output of the output clock CO when the standby signal STYP1 becomes L level.

  Next, when the standby signal STY changes from the L level to the H level, the standby mode is canceled ((c) in FIG. 4).

  When the standby signal STY changes from the L level to the H level, the timer 11 changes the standby signal STYP2 from the L level to the H level.

  When the standby signal STY becomes H level, the frequency divider 1 starts outputting the frequency-divided clock CRM.

  When the standby signal STY becomes H level, the frequency divider 2 starts outputting the frequency-divided clock CON.

  When the standby signal STY becomes H level, the phase comparator 3 starts outputting the up signal SU or the down signal SD.

  Since the standby signal STYP2 is at the H level, the charge pump 4 continues to stop the increase / decrease of the output current IC and the output of the output current IC according to the up signal SU or the down signal SD.

  For the reasons described above, the frequency divider 1, the frequency divider 2, and the phase comparator 3 do not necessarily need to start operation.

  The voltage setting circuit 10 starts outputting the control voltage VC when the standby signal STYP2 becomes H level. At this time, the control voltage VC is a voltage corresponding to the selection signal SV selected and held by the set value determination circuit 9 in the standby mode.

  When the standby signal STY becomes H level, the voltage controlled oscillator 6 starts outputting the output clock CO. Here, since the charge pump 4 stops outputting the control voltage VC, the frequency of the output clock CO is determined by the control voltage VC output from the voltage setting circuit 10.

  Next, the timer 11 stabilizes the frequency of the output clock CO to a frequency corresponding to the control voltage VC output from the voltage setting circuit 10, and stabilizes the up signal SU and the down signal SD of the phase comparator 3. When a sufficient period of time elapses, the standby signal STYP2 is changed from the H level to the L level ((d) in FIG. 4).

  The voltage setting circuit 10 stops the output of the control voltage VC when the standby signal STYP2 becomes L level.

  When the standby signal STYP2 becomes L level, the charge pump 4 starts to increase / decrease the output current IC according to the up signal SU or the down signal SD and output the output current IC.

  Thereafter, the PLL circuit is in a normal state.

  Next, the voltage setting circuit 7 in the PLL circuit according to the present embodiment will be described with reference to the drawings.

[Constitution]
FIG. 5 shows the configuration of the voltage setting circuit 10 in this PLL circuit. Referring to FIG. 2, voltage setting circuit 10 includes a load 27, a selector 22, an analog buffer 23, a switch 24, a switch 25, and an OR gate 26.

  A first fixed voltage Vdd and a load 27 are connected to the switch 24.

  A second fixed voltage (ground voltage) is connected to the load 27, and VH level, VM level, and VL level are output to the selector 22 from three voltage dividing points.

[Operation]
When at least one of the standby signal STYP1 and the standby signal STYP2 becomes the H level, the output of the OR gate 26 becomes the H level, the switch 24 and the switch 25 are turned on, and the voltage divided by the load 27 is the selector 22 To the analog buffer 23 and output as a control voltage VC.

  Here, the voltage of VH level, VM level and VL level divided by the load 27 is sent to the selector 22, and the selector 22 in the PLL circuit according to the first embodiment shown in FIG. In response to the selection signal SV sent from the set value determination circuit 9, one of these voltages is selected and output.

  When both standby signal STYP1 and standby signal STYP2 become L level, the output of OR gate 26 becomes L level, switch 24 and switch 25 are turned off, and output of control voltage VC is stopped.

  Next, the set value determination circuit 9 in the PLL circuit according to the present embodiment shown in FIG. 3 will be described with reference to the drawings.

[Constitution]
FIG. 6 shows a configuration of the set value determination circuit 9 in the PLL circuit according to the present embodiment shown in FIG. Referring to the figure, this set value determination circuit 9 includes a counter 31, an FF (also referred to as a flip-flop) 32, a control circuit 33, an FF 34, a pulse generation circuit 35, an AND gate 36, and an AND gate. 37 and a power supply control circuit 38.

  The FF 32 holds the count result sent from the counter 31 for each cycle of the reference clock CR and outputs it to the control circuit 33.

  The FF 34 holds the selection signal SV sent from the control circuit 33 for each cycle of the reference clock CR, and outputs it to the voltage setting circuit 10 in the PLL circuit according to the present embodiment shown in FIG.

  When the pulse generation circuit 35 receives the reference clock CR from the AND gate 37, the pulse generation circuit 35 periodically generates a one-cycle width pulse of the reference clock CR and outputs it to the counter 31.

  The counter 31 receives the output clock CO from the AND gate 36, counts the number of clocks of the output clock CO during the period of receiving the pulse from the pulse generation circuit 35, and outputs the count result to the FF 32. Further, when the counter 31 stops receiving the pulse from the pulse generation circuit 35, the counter 31 initializes the count result to zero.

  Here, since the count result is the number of clocks of the output clock CO in one cycle of the reference clock CR, it is a multiplication number of the output clock CO with respect to the reference clock CR.

  The power supply control circuit 38 is connected to the counter 31, the FF 32, the control circuit 33, the FF 34, the pulse generation circuit 35, the AND gate 36, and the AND gate 37, and outputs a control signal to each circuit. The power supply to each circuit is stopped.

[Operation]
When the PLL circuit according to the present embodiment shown in FIG. 3 shifts to the standby mode, that is, when the standby signal STYP1 becomes the H level ((a) of FIG. 4), the control circuit 33 starts with the voltage shown in FIG. The setting circuit 10 outputs a selection signal SV that outputs the control voltage VC at the VH level, and also outputs a control signal to the pulse generation circuit 35.

  When the control circuit 33 outputs the control signal, the pulse generation circuit 35 periodically generates a one-cycle width pulse of the reference clock CR and outputs it to the counter 31 when receiving the reference clock CR from the AND gate 37. To do.

  The counter 31 counts the number of clocks of the output clock CO sent from the AND gate 36 during a period of receiving a pulse from the pulse generation circuit 35, that is, for one cycle of the reference clock CR, and outputs the count result to the FF 32. .

  When receiving the count result held by the FF 32, the control circuit 33 holds the count result.

  Next, the control circuit 33 outputs a selection signal SV such that the voltage setting circuit 10 shown in FIG. 5 outputs the control voltage VC at the VM level.

  The counter 31 counts the number of clocks of the output clock CO sent from the AND gate 36 during a period of receiving a pulse from the pulse generation circuit 35, that is, for one cycle of the reference clock CR, and outputs the count result to the FF 32. .

  When receiving the count result held by the FF 32, the control circuit 33 holds the count result.

  Next, the control circuit 33 outputs a selection signal SV such that the voltage setting circuit 10 shown in FIG. 5 outputs the control voltage VC at the VL level.

  The counter 31 counts the number of clocks of the output clock CO sent from the AND gate 36 during a period of receiving a pulse from the pulse generation circuit 35, that is, for one cycle of the reference clock CR, and outputs the count result to the FF 32. .

  Upon receiving the count result held by the FF 32, the control circuit 33, the count result corresponding to the VL level, the count result corresponding to the held VH level, and the count corresponding to the held VM level. Among the results, the one closest to the multiplication number set in the PLL circuit is selected, and the selection signal SV corresponding to this is output to the FF 34. Note that when the frequency dividing ratios of the frequency divider 1 and the frequency divider 2 in the PLL circuit according to the present embodiment shown in FIG. 3 are set, the control circuit 33 sets the frequency dividing ratio, that is, the PLL. It is assumed that the multiplication number set in the circuit is held.

  The control circuit 33 stops outputting the control signal to the pulse generation circuit 35. As a result, the pulse generation circuit 35 stops outputting pulses to the counter 31.

  When the FF 34 receives the selection signal SV from the control circuit 33, it holds it. At this time, the held selection signal SV is output to the voltage setting circuit 10 shown in FIG.

  Therefore, the PLL circuit described in Patent Document 1 has a disadvantage that the time until the PLL circuit is locked cannot be sufficiently shortened. In addition, the PLL circuit described in Patent Document 2 has an initial application to the voltage controlled oscillator. The disadvantage that the control voltage cannot be changed according to the application of the IC in which the PLL circuit is used, and that the time until the lock cannot be changed due to the influence of the manufacturing conditions and the surrounding environment cannot be prevented. However, in the PLL circuit according to the present embodiment, after transitioning to the standby mode, the control voltage VC of the VH level, the VM level, and the VL level is output, and the reference clock CR of the output clock CO is output for each level. Is detected, the selection signal SV closest to the desired multiplication number is selected in advance, and held in the FF 34 After the standby mode is canceled, the control voltage VC corresponding to the selection signal SV held in the FF 34 is output to the voltage controlled oscillator 6 for a certain period of time, so that the reference clock of the output clock CO is released after the standby mode is canceled. The multiplication number for the CR is greatly different from the desired multiplication number, and it is possible to prevent a long time until the PLL circuit is locked, and to sufficiently shorten the time until the PLL circuit is locked.

  Further, in the PLL circuit according to the present embodiment, the selection signal SV corresponding to the desired multiplication number is not stored in a fixed manner, but the selection signal SV is selected every time the standby mode is entered. The initial control voltage applied to the can be changed according to the application of the IC in which the PLL circuit is used, and it is possible to prevent the time until the lock from fluctuating due to the influence of the manufacturing conditions and the surrounding environment. it can.

  In the PLL circuit according to the present embodiment, as described above, the frequency divider 1 and the frequency divider 2 from the time point (a) in FIG. 4 or the time point (b) in FIG. By stopping the operations of the phase comparator 3, the charge pump 4, the voltage control oscillator 6, the set value determination circuit 9, and the voltage setting circuit 10, dynamic power consumption can be reduced.

  If the selection signal SV is held in the set value determination circuit 9, the initial control voltage corresponding to the desired multiplication number is applied to the voltage controlled oscillator 6 in the PLL circuit according to the present embodiment after the standby mode is released. Can be applied.

  That is, the frequency divider 1, the frequency divider 2, the phase comparator 3, and the charge pump are circuits that stop the operation from the time point of FIG. 4A or the time point of FIG. 4B after the standby mode transition. 4. Of the voltage control oscillator 6, the set value determination circuit 9 and the voltage setting circuit 10, the operation other than the set value determination circuit 9 not only stops the operation but also cancels the standby mode when the power supply is stopped. Therefore, the time until the PLL circuit is locked is not affected. Therefore, by stopping the power supply of the circuits other than the set value determination circuit 9 among these circuits, not only the dynamic power consumption but also the static power consumption due to the leakage current of the transistor and the like is reduced. be able to.

  In this case, when the standby signal STY changes from the H level to the L level ((a) in FIG. 4), the power supply control circuit 12 supplies the frequency divider 1, the frequency divider 2, the phase comparator 3 and the charge pump 4. By outputting the control signal, the power supply to each circuit is stopped. Then, when a sufficient period of time has passed for the set value determination circuit 9 to select and hold the selection signal SV and the timer 11 changes the standby signal STYP1 from the H level to the L level ((b) of FIG. 4). ), The power supply control circuit 12 outputs a control signal to the voltage controlled oscillator 6 and the voltage setting circuit 10, whereby the power supply to each circuit is stopped. When the standby signal STY changes from the L level to the H level ((c) in FIG. 4), the power supply control circuit 12 causes the frequency divider 1, the frequency divider 2, the phase comparator 3, the voltage controlled oscillator 6 and the voltage setting. By stopping the output of the control signal to the circuit 10, the power supply to these circuits is resumed. When the timer 11 changes the standby signal STYP2 from the H level to the L level ((d) in FIG. 4), the power supply control circuit 12 stops the output of the control signal to the charge pump 4, thereby charging The power supply to the pump 4 is resumed, and the power supply control circuit 12 outputs control signals to the set value determination circuit 9 and the voltage setting circuit 10, whereby the power supply to these circuits is stopped.

  Further, in the set value determination circuit 9, the circuits other than the FF 34 not only stop the operation, but even if the power supply is stopped, the time until the PLL circuit is locked after the standby mode is released is affected. Not give. Therefore, static power consumption can be further reduced by stopping the power supply of the circuits other than the FF 34 in the set value determination circuit 9.

  In this case, when a sufficient period of time has elapsed for the set value determination circuit 9 to select and hold the selection signal SV and the timer 11 changes the standby signal STYP1 from the H level to the L level ((( b)) The power supply control circuit 38 outputs control signals to the counter 31, the FF 32, the control circuit 33, the pulse generation circuit 35, the AND gate 36, and the AND gate 37, thereby supplying power to each circuit. Supply is stopped. Even when the standby signal STY changes from the L level to the H level ((c) of FIG. 4), the power supply control circuit 38 maintains this state. When the timer 11 changes the standby signal STYP2 from the H level to the L level ((d) in FIG. 4), the power supply control circuit 38 outputs a control signal to the FF 34, thereby supplying power to the FF 34. Is stopped.

<Second Embodiment>
[DLL circuit assumed to be used conventionally]
Next, an embodiment of the present invention for a DLL circuit will be described with reference to the drawings.

  First, for comparison with the DLL circuit according to the present embodiment, a DLL circuit assumed to be conventionally used will be described with reference to the drawings.

[Constitution]
FIG. 7 shows a configuration of a DLL circuit assumed to be conventionally used. Referring to FIG. 3, the DLL circuit includes a phase comparator 21, a charge pump 22, a loop filter 23, a voltage control delay circuit 24, and a multiplexer 25.

[Operation]
The phase comparator 21 detects the phase difference between the reference clock CR and the output clock CO and delays the phase of the output clock CO in order to match the phases, that is, when the delay amount of the reference clock CR needs to be increased. Outputs the up signal SU and outputs the down signal SD when it is necessary to advance the phase, that is, to reduce the delay amount of the reference clock CR.

  The charge pump 22 increases or decreases the output current IC in response to the up signal SU or the down signal SD sent from the phase comparator 21 and outputs it.

  The loop filter 23 smoothes the output current IC sent from the charge pump 22 and outputs a control voltage VC corresponding to the output current IC.

  The voltage control delay circuit 24 changes the delay amount of the output clock CO, that is, the delay amount given to the reference clock CR, according to the control voltage VC sent from the loop filter 23.

  Therefore, in this DLL circuit, by changing the delay amount of the output clock CO in accordance with the phase difference between the reference clock CR and the output clock CO delayed from the reference clock CR, the output clock CO is changed to one cycle of the reference clock CR ( In the following control, the phase is matched with the reference clock CR, that is, the DLL circuit is locked.

  Since the output clock CO is a delayed version of the reference clock CR, the reference clock CR and the output clock CO, which are the objects of phase comparison, have the same frequency. Therefore, in order to lock the DLL circuit, an output is required. It is only necessary to change the delay amount of the clock CO so that the phases of both clocks coincide.

  Therefore, in the PLL circuit, even if an initial control voltage is applied so that the frequency of the output clock CO of the voltage controlled oscillator 6 matches the desired frequency, the two clocks that are subject to phase comparison in the phase comparator 21. If the phases do not match, it is necessary to change the control voltage VC to match the phases. Further, in the PLL circuit, when the control voltage VC is changed, the frequency of the output clock CO of the voltage controlled oscillator 6 is changed, so that a certain time is required until locking. However, in the DLL circuit, the output clock CO is locked immediately by applying to the voltage control delay circuit 24 an initial control voltage that delays the reference clock CR by one cycle of the reference clock CR. Can do.

  Next, the voltage control delay circuit 24 in the DLL circuit assumed to be conventionally used shown in FIG. 7 will be described with reference to the drawings.

[Constitution]
FIG. 8 shows a configuration of the voltage control delay circuit 24 and the multiplexer 25 in the DLL circuit assumed to be conventionally used shown in FIG. Referring to FIG. 4, voltage control delay circuit 24 includes delay elements 41 to 48, buffers 51 to 58, and bias generation circuit 49.

  Each buffer is arranged in order to improve the current drive capability of the output to the multiplexer 25, and description will be made assuming that the delay amount of the output signal with respect to the input signal of these buffers is zero. .

[Operation]
The bias generation circuit 49 generates a bias voltage VB according to the control voltage VC sent from the loop filter 23 in the DLL circuit assumed to be used conventionally shown in FIG. Output to 48.

  The delay element 41 changes the delay amount according to the control voltage VB. As a result, the delay clock C1 obtained by delaying the reference clock CR sent from the outside by a delay amount corresponding to the control voltage VB is output to the delay element 42 and the buffer 51.

  The delay element 42 changes the delay amount according to the control voltage VB. Thus, the delay clock C2 obtained by delaying the delay clock C1 by the delay amount corresponding to the control voltage VB is output to the delay element 43 and the buffer 52.

  The delay element 43 changes the delay amount according to the control voltage VB. As a result, the delay clock C3 obtained by delaying the delay clock C2 by the delay amount corresponding to the control voltage VB is output to the delay element 44 and the buffer 53.

  The delay element 44 changes the delay amount according to the control voltage VB. As a result, the delay clock C4 obtained by delaying the delay clock C3 by the delay amount corresponding to the control voltage VB is output to the delay element 45 and the buffer 54.

  The delay element 45 changes the delay amount according to the control voltage VB. As a result, the delay clock C5 obtained by delaying the delay clock C4 by the delay amount corresponding to the control voltage VB is output to the delay element 46 and the buffer 55.

  The delay element 46 changes the delay amount according to the control voltage VB. As a result, the delay clock C6 obtained by delaying the delay clock C5 by the delay amount corresponding to the control voltage VB is output to the delay element 47 and the buffer 56.

  The delay element 47 changes the delay amount according to the control voltage VB. As a result, the delay clock C7 obtained by delaying the delay clock C6 by the delay amount corresponding to the control voltage VB is output to the delay element 48 and the buffer 57.

  The delay element 48 changes the delay amount according to the control voltage VB. As a result, the output clock CO obtained by delaying the delay clock C7 by the delay amount corresponding to the control voltage VB is output to the external circuit and the buffer 58.

  Each delay element has the same characteristics. Further, since the control voltage VB is common to each delay element, each delay element gives the same delay amount to the input signal and outputs it.

  Therefore, when the DLL circuit according to the present embodiment shown in FIG. 7 is locked, that is, when the output clock CO is delayed by Ts with respect to the reference clock CR, the delay amount in each delay element. Is a delay amount obtained by dividing Ts into eight equal parts.

  That is, when the DLL circuit according to the present embodiment shown in FIG. 7 is locked, the delay clock C1 is delayed by Ts / 8 phase with respect to the reference clock CR, and the delay clock C2 is Ts with respect to the reference clock CR. / 4 phase is delayed, delay clock C3 is delayed by (3 × Ts) / 8 phase with respect to reference clock CR, delay clock C4 is delayed by Ts / 2 phase with respect to reference clock CR, and delay clock C5 is reference clock. The delay clock C6 is delayed by (3 × Ts) / 4 phase with respect to the reference clock CR, and the delayed clock C7 is delayed by (7 × Ts) with respect to the reference clock CR. ) / 8 phase is delayed.

  Next, operations of the voltage control delay circuit 24 and the multiplexer 25 when the DLL circuit assumed to be conventionally used shown in FIG. 7 is locked will be described with reference to a time chart shown in FIG. .

  Referring to the figure, voltage control delay circuit 24 changes the amount of delay applied to reference clock CR in accordance with control voltage VC sent from loop filter 23, and as described above, one cycle of reference clock CR. A delay clock C1, a delay clock C2, a delay clock C3, a delay clock C4, a delay clock C5, a delay clock C7, and an output lock CO, each having a phase obtained by dividing Ts into eight equal parts, are generated and output.

  Referring to the figure, multiplexer 25 receives delay clock C1 to delay clock C7 and output clock CO from voltage control circuit 24, and from these eight phase clocks, a reference is made as follows. A multiplied clock CX multiplied by 1 of the clock CR, a multiplied clock CX2 multiplied by 1, and a multiplied clock CX4 multiplied by 4 are generated and output.

  Here, assuming that the pulses of these multiplied clocks within one cycle of the reference clock CR are pulse # 0, pulse # 1, pulse # 2 and pulse # 3 in order from the rising edge of the reference clock CR, the multiplexer 25 The rising edge of the pulse # 0 of the multiplied clock CX1 is generated from the rising edge of the output clock CO, and the falling edge of the pulse # 0 of the multiplied clock CX1 is generated from the rising edge of the delay clock C4.

  Further, the multiplexer 25 generates the rising edges of the pulse # 0 and the pulse # 1 of the multiplied clock CX2 from the rising edges of the output clock CO and the delay clock C4, respectively, and multiplies them from the rising edges of the delay clock C2 and the delay clock C6. The falling edges of pulse # 0 and pulse # 1 of clock CX2 are generated.

  The multiplexer 25 sequentially outputs the rising edges of the output clock CO, the delay clock C2, the delay clock C4, and the delay clock C6 to the rising edge of the pulse # 0, pulse # 1, pulse # 2, and pulse # 3 of the multiplied clock CX4. And the falling edges of the pulse # 0, pulse # 1, pulse # 2, and pulse # 3 of the multiplied clock CX4 are generated from the rising edges of the delay clock C1, the delay clock C3, the delay clock C5, and the delay clock C7.

  Here, the pulse width of the multiplied clock CX1 is Ts / 2, the pulse width of the multiplied clock CX2 is Ts / 4, and the pulse width of the multiplied clock CX4 is Ts / 8.

  Next, referring to the time chart shown in FIG. 10, in this DLL circuit, when a jitter whose phase advances occurs in the reference clock CR, that is, normally, it should appear every period of the reference clock CR. The relationship between the reference clock CR and the multiplied clock CX4 when the first clock appears earlier than one cycle will be described.

  Referring to the figure, jitter occurs in the second clock with respect to the first clock of the reference clock CR.

  A pulse corresponding to the first clock of the reference clock CR among the pulses # 0, # 1, # 2, and # 3 of the multiplied clock CX4 generated by the voltage control delay circuit 24 shown in FIG. # 0a, pulse # 1a, pulse # 2a, and pulse # 3a, and those corresponding to the second clock of the reference clock CR are pulse # 0b, pulse # 1b, pulse # 2b, and pulse # 3b.

  The arrows indicated by C1a to C7a and COa indicate the rising edges of the delay clock C1 to the delay clock C7 and the output clock CO that are generated using the first clock of the reference clock CR in the voltage controlled delay circuit 24 shown in FIG. It is.

  Arrows indicated by C1b to C7b and COb indicate rising edges of the delay clock C1 to the delay clock C7 and the output clock CO generated by using the second clock of the reference clock CR in the voltage control delay circuit 24 shown in FIG. It is.

  The arrows indicated by C1b ′ to C7b ′ use the second clock of the reference clock CR in the voltage control delay circuit 24 shown in FIG. 8 when it is assumed that no jitter has occurred in the second clock of the reference clock CR. This is the rising edge of the generated delay clock C1 to delay clock C7 and output clock CO.

  Further, in the multiplied clock CX4, the solid line is the position of the multiplied clock CX4 due to the occurrence of jitter at the second clock of the reference clock CR, and the alternate long and short dash line is that no jitter has occurred at the second clock of the reference clock CR. This is the position of the multiplied clock CX4 when assumed.

  When jitter occurs in the second clock of the reference clock CR and the second clock of the reference clock CR appears earlier by Tj than the cycle of the reference clock CR, the falling edge of the pulse # 0b of the multiplied clock CX4 is determined. C1b is C1b 'Appears earlier by Tj, and COa which determines the rising edge of the pulse # 0b of the multiplied clock CX4 is not affected by the jitter generated at the second clock of the reference clock CR, so the pulse # 0b of the multiplied clock CX4 Is shorter by Tj than the original pulse width Ts / 8.

  The same applies to the pulse # 0 of the multiplied clock CX2 and the pulse # 0 of the multiplied clock CX1.

  The rising edge of the pulse # 1b of the multiplied clock CX4 is determined. C2b appears earlier by Tj than C2b ′, and the falling edge of the pulse # 1b of the multiplied clock CX4 is determined. C3b is determined by Tj from C3b ′. Since it appears earlier, the pulse # 1b of the multiplied clock CX4 has a pulse start position that is advanced by Tj, but the pulse width does not change and becomes Ts / 8.

  The same applies to the pulse # 1 of the multiplied clock CX2.

  As for the pulse # 2b and the pulse # 3b of the multiplied clock CX4, the pulse start position is advanced by Tj as in the case of the pulse # 1b, but the pulse width does not change and becomes Ts / 8.

  On the other hand, in this DLL circuit, when a jitter whose phase is delayed occurs in the reference clock CR, that is, when a clock that should normally appear in every cycle of the reference clock CR appears later than one cycle. As follows (not shown).

  When jitter occurs in the second clock of the reference clock CR and the second clock of the reference clock CR appears later by Tj than the period of the reference clock CR, the falling edge of the pulse # 0b of the multiplied clock CX4 is determined. C1b is C1b 'Appears later by Tj, and COa, which determines the rising edge of the pulse # 0b of the multiplied clock CX4, is not affected by the jitter generated at the second clock of the reference clock CR, so the pulse # 0b of the multiplied clock CX4 The pulse width is longer by Tj than the original pulse width Ts / 8.

  The same applies to the pulse # 0 of the multiplied clock CX2 and the pulse # 0 of the multiplied clock CX1.

  The rising edge of the pulse # 1b of the multiplied clock CX4 is determined. C2b appears later by Tj than C2b ′, and the falling edge of the pulse # 1b of the multiplied clock CX4 is determined. C3b is determined by Tj from C3b ′. Since it appears late, the pulse # 1b of the multiplied clock CX4 is delayed by the pulse start position by Tj, but the pulse width does not change and becomes Ts / 8.

  The same applies to the pulse # 1 of the multiplied clock CX2.

  As for the pulse # 2b and the pulse # 3b of the multiplied clock CX4, the pulse start position is delayed by Tj as in the case of the pulse # 1b, but the pulse width does not change and becomes Ts / 8.

  Therefore, in the DLL circuit assumed to be used conventionally shown in FIG. 7, when jitter occurs in the reference clock CR, the pulse width of the pulse # 0 of the multiplied clock generated in the multiplexer 25 is the reference due to the jitter. There has been a drawback that it fluctuates by the variation of the clock CR.

  Next, embodiments of the present invention will be described with reference to the drawings.

Embodiment of the present invention
[Constitution]
FIG. 11 shows a configuration of a DLL circuit according to the second embodiment. Referring to FIG. 7, this DLL circuit further includes a set value determination circuit 26, a voltage setting circuit 27, a timer 28, and a DLL circuit that is assumed to be conventionally used as shown in FIG. And a power supply control circuit 29.

  The standby signal STY sent from the outside is sent to the timer 28, the phase comparator 21, the charge pump 22, and the voltage control delay circuit 24.

  The timer 28 generates a standby signal STYP1 and a standby signal STYP2 in response to a standby signal STY sent from the outside, and outputs the standby signal STYP1 to the voltage control delay circuit 24, the set value determination circuit 26, and the voltage setting circuit 27. The standby signal STYP2 is output to the charge pump 22 and the voltage setting circuit 27.

  The set value determination circuit 26 receives the reference clock CR and the multiplied clock CX4 generated by the multiplexer 25.

  The power supply control circuit 29 is connected to the phase comparator 21, the charge pump 22, the voltage control delay circuit 24, the set value determination circuit 26 and the voltage setting circuit 27, and outputs a control signal to each circuit. Stop the power supply.

  Hereinafter, the start and stop of the operation of each circuit according to the logic levels of the standby signal STY, standby signal STYP1, and standby signal STYP2 received by each circuit will be briefly described. Details of the operation will be described later.

  The phase comparator 21 starts its operation when the standby signal STY becomes H level and stops its operation when it becomes L level.

  The charge pump 22 starts operation when the standby signal STY is at a logic high level and the standby signal STYP2 is at a logic low level. The charge pump 22 stops operating when the standby signal STY is at a logic low level or the standby signal STYP2 is at a logic high level.

  The voltage control delay circuit 24 starts the operation when at least one of the standby signal STY and the standby signal STYP1 becomes the H level, and stops the operation when both of them become the L level.

  The set value determination circuit 26 starts operation when the standby signal STYP1 becomes H level, and stops operation when it becomes L level.

  The voltage setting circuit 27 starts operation when at least one of the standby signal STYP1 and the standby signal STYP2 becomes H level, and stops operation when both of them become L level.

  Other configurations are the same as those of the DLL circuit assumed to be conventionally used shown in FIG.

[Operation]
Next, the operation of the DLL circuit according to the second embodiment will be described with reference to the time chart shown in FIG.

  This DLL circuit is in a normal state before (a) in FIG. 12 and after (d) in FIG. 12, and operates in the same manner as the normal state of the DLL circuit assumed to be conventionally used shown in FIG. To do.

  When the standby signal STY changes from the H level to the L level, the DLL circuit shifts to the standby mode ((a) in FIG. 12).

  First, when the standby signal STY changes from the H level to the L level, the timer 28 changes the standby signal STYP1 from the L level to the H level.

  When the standby signal STY becomes L level, the phase comparator 21 stops outputting the up signal SU or the down signal SD.

  When the standby signal STY becomes L level, the charge pump 22 stops the increase / decrease of the output current IC and the output of the output current IC according to the up signal SU or the down signal SD.

  As described above, the phase difference between the reference clock CR and the output clock CO is not reflected in the control voltage VC, that is, the delay amount of the output clock CO in the voltage control delay circuit 24.

  For this reason, when the charge pump 22 is not operating, the operation of the phase comparator 21 does not affect the delay amount of the output clock CO. Therefore, in this case, the phase comparator 22 does not necessarily stop operating.

  When the standby signal STYP1 becomes H level, the voltage setting circuit 27 outputs a voltage corresponding to the selection signal SV sent from the set value determination circuit 26 to the voltage control delay circuit 24 as the control voltage VC. That is, the delay amount of the output clock CO is determined not by the control voltage VC output from the charge pump 22 but by the control voltage VC output from the voltage setting circuit 27.

  When the standby signal STYP1 becomes H level, the set value determination circuit 26 changes the control voltage VC output from the voltage setting circuit 27 by the selection signal SV and changes the delay amount of the output clock CO. Then, the multiplication number of the multiplication clock CX4 with respect to the reference clock CR is detected, compared with the multiplication number of the multiplication clock CX4, and the selection signal SV that is closest to each other is selected and held. At this time, the held selection signal SV is output to the voltage setting circuit 27.

  Next, the timer 28 changes the standby signal STYP1 from the H level to the L level when a sufficient period of time has elapsed for the set value determination circuit 9 to select and hold the selection signal SV (FIG. 12B). ).

  The set value determination circuit 9 stops the operation when the standby signal STYP1 becomes L level, but the selection signal SV is held and is output to the voltage setting circuit 27.

  The voltage setting circuit 27 stops outputting the control voltage VC when the standby signal STYP1 becomes L level.

  The voltage control delay circuit 24 stops the output of each clock when the standby signal STYP1 becomes L level.

  Next, when the standby signal STY changes from L level to H level, the standby mode is canceled ((c) in FIG. 12).

  When the standby signal STY changes from L level to H level, the timer 28 changes the standby signal STYP2 from L level to H level.

  The voltage setting circuit 27 starts outputting the control voltage VC when the standby signal STYP2 becomes H level. At this time, the control voltage VC is a voltage corresponding to the selection signal SV selected and held by the set value determination circuit 9 in the standby mode.

  The voltage control delay circuit 24 starts outputting each clock when the standby signal STY becomes H level. Here, since the charge pump 22 stops outputting the control voltage VC, the delay amount of the output clock CO is determined by the control voltage VC output from the voltage setting circuit 27.

  When the standby signal STY becomes H level, the phase comparator 21 starts outputting the up signal SU or the down signal SD.

  Since the standby signal STYP2 is at the H level, the charge pump 22 continues to stop the increase / decrease of the output current IC and the output of the output current IC according to the up signal SU or the down signal SD.

  For the reasons described above, the phase comparator 21 does not necessarily need to start operating.

  Next, the timer 28 stabilizes the phase of the output clock CO to a phase corresponding to the control voltage VC output from the voltage setting circuit 27, and stabilizes the up signal SU and the down signal SD of the phase comparator 21. When a sufficient period of time elapses, the standby signal STYP2 is changed from the H level to the L level ((d) in FIG. 12).

  The voltage setting circuit 27 stops outputting the control voltage VC when the standby signal STYP2 becomes L level.

  When the standby signal STYP2 becomes L level, the charge pump 22 starts to increase / decrease the output current IC and output the output current IC according to the up signal SU or the down signal SD.

  Thereafter, the DLL circuit is in a normal state.

  Other configurations and operations of the voltage setting circuit 27 according to the present embodiment are the same as those of the voltage setting circuit 10 in the PLL circuit according to the first embodiment.

  Next, the set value determination circuit 26 in the DLL circuit according to the second embodiment shown in FIG. 11 will be described with reference to the drawings.

[Constitution]
FIG. 13 shows the configuration of the set value determination circuit 26 in the DLL circuit according to the second embodiment shown in FIG. Referring to the figure, this set value determination circuit 26 includes a counter 71, an FF 72, a control circuit 73, an FF 74, a pulse generation circuit 75, an AND gate 76, an AND gate 77, and a power supply control circuit 78. Including.

  Other than the AND gate 76 receiving the multiplied clock CX4 and the counter 71 counting the number of clocks of the multiplied clock CX4, the other configuration of the set value determination circuit 26 according to the present embodiment is the same as that of the first embodiment. This is the same as the set value determination circuit 9 in the PLL circuit.

[Operation]
The operation when the DLL circuit according to the second embodiment shown in FIG. 11 shifts to the standby mode, that is, when the standby signal STYP1 becomes the H level ((a) of FIG. 12) will be described. Since this operation is substantially the same as that of the set value determination circuit 9 in the PLL circuit according to the first embodiment, only the difference in operation will be described below.

  For the VH level and the VM level of the control voltage VC output from the voltage setting circuit 27, the counter 71 is sent from the AND gate 76 during a period of receiving a pulse from the pulse generation circuit 75, that is, for one cycle of the reference clock CR. The number of clocks of the multiplied clock CX4 is counted, and two count results corresponding to the VH level and the VM level are sequentially output to the FF 72.

  When receiving two count results corresponding to the VH level and the VM level held by the FF 72, the control circuit 73 holds this.

  Next, the control circuit 73 outputs a selection signal SV such that the voltage setting circuit 27 outputs the control voltage VC at the VL level.

  The counter 71 counts the number of multiplied clocks CX4 sent from the AND gate 76 during a period of receiving a pulse from the pulse generation circuit 75, that is, for one cycle of the reference clock CR, and outputs the count result to the FF 72. .

  When the control circuit 73 receives the count result held by the FF 72, the count result corresponding to the VL level, the count result corresponding to the held VH level, and the count corresponding to the held VM level. Among the results, the one closest to the multiplication number of the multiplication clock CX4 is selected, and the selection signal SV corresponding to this is output to the FF 74. It is assumed that the control circuit 73 holds the multiplication number of the multiplication clock CX4 sent to the set value determination circuit 26 in advance.

  Further, the control circuit 73 stops outputting the control signal to the pulse generation circuit 75. As a result, the pulse generation circuit 75 stops outputting pulses to the counter 71.

  When the FF 74 receives the selection signal SV from the control circuit 73, it holds it. At this time, the held selection signal SV is output to the voltage setting circuit 27.

  Here, when the DLL circuit is not locked, the delay of the output clock CO with respect to the reference clock CR does not become Ts, and the delay amount of each delay element in the voltage control delay circuit 24 does not become Ts / 8. Since the interval between the edges of each delay clock that determines the pulse of the multiplied clock does not become Ts / 8, the multiplied clock generated by the multiplexer 25 varies from the desired multiplied number with respect to the reference clock CR.

  Therefore, selecting the level of the control voltage VC that is closest to the multiplication number of the multiplied clock CX4 means that the control voltage VC is selected such that the delay of the output clock CO with respect to the reference clock CR is closest to Ts. .

  Therefore, the PLL circuit described in Patent Document 1 has a drawback that the time until the PLL circuit is locked cannot be sufficiently shortened. However, the DLL circuit according to the present embodiment is also the first embodiment. As in the PLL circuit according to FIG. 2, after transitioning to the standby mode, the selection signal SV whose multiplication number with respect to the reference clock CR of the multiplication clock CX4 is closest to the desired multiplication number is selected and held in advance, and the standby mode Is released, the control voltage VC corresponding to the selection signal SV is output to the voltage control delay circuit 24 for a certain period, so that after the standby mode is released, the multiplication number of the multiplication clock CX4 with respect to the reference clock CR becomes the desired multiplication. Unlike the number, the DLL circuit is prevented from taking a long time to lock, and the time to lock is sufficient. It is possible to shrinkage.

  Further, in the DLL circuit according to the present embodiment, as in the PLL circuit according to the first embodiment, from the time point of FIG. 12 (a) or the time point of FIG. 12 (b) after the standby mode transition, By stopping the operations of the phase comparator 21, the charge pump 22, the voltage control delay circuit 24, the set value determination circuit 26, and the voltage setting circuit 27, dynamic power consumption can be reduced.

  If the selection signal SV is held in the set value determination circuit 27, the initial control corresponding to the desired delay amount is made to the voltage control delay circuit 24 in the DLL circuit according to the present embodiment after the standby mode is released. A voltage can be applied.

  That is, the phase comparator 21, the charge pump 22, the voltage control delay circuit 24, the set value, which are circuits that stop the operation from the time point of FIG. 12A or the time point of FIG. 12B after the standby mode transition. Of the determination circuit 26 and the voltage setting circuit 27, operations other than the set value determination circuit 26 are not only stopped, but even when the power supply is stopped, the standby mode is canceled and the DLL circuit is locked. Does not affect the time. Therefore, by stopping the power supply to the circuits other than the set value determination circuit 26 among these circuits, not only dynamic power consumption but also static power consumption due to a leakage current of a transistor or the like is reduced. be able to.

  In this case, when the standby signal STY changes from the H level to the L level ((a) in FIG. 12), the power supply control circuit 29 outputs a control signal to the phase comparator 21 and the charge pump 22, whereby each circuit. The power supply to is stopped. Then, when a sufficient period of time has elapsed for the set value determination circuit 26 to select and hold the selection signal SV and the timer 28 changes the standby signal STYP1 from the H level to the L level ((b) of FIG. 12). ), The power supply control circuit 29 outputs a control signal to the voltage control delay circuit 24 and the voltage setting circuit 27, whereby the power supply to each circuit is stopped. When the standby signal STY changes from L level to H level ((c) in FIG. 12), the power supply control circuit 29 outputs control signals to the phase comparator 21, voltage control delay circuit 24, and voltage setting circuit 27. By stopping, power supply to these circuits is resumed. When the timer 28 changes the standby signal STYP2 from the H level to the L level ((d) in FIG. 12), the power supply control circuit 29 stops the output of the control signal to the charge pump 22, thereby charging The power supply to the pump 22 is resumed, and the power supply control circuit 29 outputs control signals to the set value determination circuit 26 and the voltage setting circuit 27, whereby the power supply to these circuits is stopped.

  Further, in the set value determination circuit 26, the circuits other than the FF 74 not only stop the operation, but even if the power supply is stopped, the time until the DLL circuit is locked after the standby mode is released is affected. Not give. Therefore, static power consumption can be further reduced by stopping the power supply of the circuits other than the FF 74 in the set value determination circuit 26.

  In this case, when a sufficient period of time has elapsed for the set value determination circuit 26 to select and hold the selection signal SV, and the timer 28 changes the standby signal STYP1 from the H level to the L level ((( b)) The power supply control circuit 78 outputs control signals to the counter 71, the FF 72, the control circuit 73, the pulse generation circuit 75, the AND gate 76, and the AND gate 77, thereby supplying power to each circuit. Supply is stopped. Even when the standby signal STY changes from the L level to the H level ((c) in FIG. 12), the power supply control circuit 78 maintains this state. When the timer 28 changes the standby signal STYP2 from the H level to the L level ((d) in FIG. 12), the power supply control circuit 78 outputs a control signal to the FF 74, thereby supplying power to the FF 74. Is stopped.

  Next, another embodiment of the present invention will be described with reference to the drawings.

<Third Embodiment>
[Constitution]
FIG. 14 shows a configuration of a DLL circuit according to the third embodiment. Referring to FIG. 7, this DLL circuit further includes a jitter correction circuit 29 and a phase difference determination circuit 30 in addition to the DLL circuit assumed to be conventionally used as shown in FIG.

[Operation]
The phase difference determination circuit 30 receives the reference clock CR from the outside and the output clock CO from the voltage control delay circuit 24, detects the phase difference between the two clocks due to jitter generated in the reference clock CR, and responds to this phase difference. The selection signal SP is output to the jitter correction circuit 29.

  The jitter correction circuit 29 changes the delay amounts of the delay clocks C1 to C7 and the output clock CO sent from the voltage control delay circuit 24 in accordance with the selection signal SP sent from the phase difference determination circuit 30, respectively. This prevents fluctuation of the multiplied clock generated by the multiplexer 25 due to jitter generated in the reference clock CR.

  Other configurations and operations are the same as those of the DLL circuit assumed to be conventionally used shown in FIG.

  Next, the configuration and operation of the jitter correction circuit 29 in the DLL circuit according to the present embodiment will be described with reference to the drawings.

[Constitution]
FIG. 15 shows the configuration of the jitter correction circuit 29 in the DLL circuit according to the third embodiment shown in FIG. Referring to FIG. 6, this jitter correction circuit 29 includes selectors 61-68.

  The delay line D10 is a path for directly outputting the delay clock C1 to the selector 61. The delay line D11 includes one delay element having a fixed delay amount Td, and delays the delay clock C1 by Td. The delay line D12 includes two delay elements having a fixed delay amount Td, and is a path for delaying the delay clock C1 by 2 × Td and outputting it to the selector 61. The delay line D13 includes three delay elements having a fixed delay amount Td, and is a path for delaying the delay clock C1 by 3 × Td and outputting it to the selector 61. The delay line D14 is a fixed line A path for delaying the delay clock C1 by 4 × Td and outputting it to the selector 61, including four delay elements having the delay amount Td The delay line D15 includes five delay elements having a fixed delay amount Td, and is a path for delaying the delay clock C1 by 5 × Td and outputting it to the selector 61. The delay line D12 has a fixed delay amount Dd. This is a path for including six delay elements having the delay amount Td and delaying the delay clock C1 by 6 × Td and outputting it to the selector 61.

  Similarly to the above, the delay line D20 is a path for directly outputting the delay clock C2 to the selector 62, the delay line D21 delays the delay clock C2 by Td, and the delay line D22 is The delay clock C2 is delayed by 2 × Td, the delay line D23 delays the delay clock C2 by 3 × Td, and the delay line D24 delays the delay clock C2 by 4 × Td. The delay line D25 is a path for delaying the delay clock C2 by 5 × Td, and the delay line D26 is a path for delaying the delay clock C2 by 6 × Td and outputting it to the selector 62, respectively. .

  The delay line D31 delays the delay clock C3 by Td, the delay line D32 delays the delay clock C3 by 2 × Td, and the delay line D33 delays the delay clock C3 by 3 × Td. The delay line D34 delays the delay clock C3 by 4 × Td, and the delay line D35 delays the delay clock C3 by 5 × Td and outputs them to the selector 63, respectively. It is.

  The delay line D41 delays the delay clock C4 by Td, the delay line D42 delays the delay clock C4 by 2 × Td, and the delay line D43 delays the delay clock C4 by 3 × Td. The delay line D44 delays the delay clock C4 by 4 × Td, and the delay line D45 delays the delay clock C4 by 5 × Td and outputs them to the selector 64, respectively. It is.

  The delay line D52 delays the delay clock C5 by 2 × Td, the delay line D43 delays the delay clock C5 by 3 × Td, and the delay line D44 delays the delay clock C5 by 4 × This is a path for delaying by Td and outputting to each selector 65.

  The delay line D62 delays the delay clock C6 by 2 × Td, the delay line D63 delays the delay clock C6 by 3 × Td, and the delay line D64 delays the delay clock C6 by 4 ×. This is a path for delaying by Td and outputting to the selector 66 respectively.

  The delay line D73 is a path for delaying the delay clock C7 by 3 × Td and outputting it to the selector 67.

  The delay line D83 is a path for delaying the delay clock CO by 3 × Td and outputting it to the selector 68.

  Each selector is connected to at least one delay line.

[Operation]
The selector 61 changes the delay line to be selected according to the selection signal SP, and outputs the delay clock C1D obtained by delaying the delay clock C1 to the multiplexer 25.

  Similarly to the above, the selector 62 delays the delay clock C2 and outputs the delay clock C2D to the multiplexer 25, and the selector 63 outputs the delay clock C3D that delays the delay clock C3 to the multiplexer 25. The selector 64 delays the delay clock C4 and outputs the delay clock C4D to the multiplexer 25. The selector 65 delays the delay clock C5 and outputs the delay clock C5D to the multiplexer 25. The selector 66 outputs the delayed clock C6D obtained by delaying the delayed clock C6 to the multiplexer 25.

  Since the selector 67 is connected only to the delay line D73, the selector 67 is always selected and outputs the delayed clock C7D, which is the delayed clock C7 delayed, to the multiplexer 25.

  Further, since only the delay line D83 is connected, the selector 68 always selects this and outputs the delayed clock COD obtained by delaying the delayed clock CO to the multiplexer 25.

  Next, the configuration and operation of the phase difference determination circuit 30 in the DLL circuit according to the present embodiment will be described with reference to the drawings.

[Constitution]
FIG. 16 shows the configuration of the phase difference determination circuit 30 in the DLL circuit according to the third embodiment shown in FIG. Referring to the figure, phase difference determination circuit 30 includes delay elements 81 to 86, FF 71 to FF 76, and phase difference determination control circuit 77.

  The delay elements 81 to 86 delay the output signal by Td with respect to the input signal.

  The delay element 81 receives the reference clock CR and outputs a delay clock CR1 delayed by Td with respect to the reference clock CR to the delay element 82 and the FF 71.

  The delay element 82 receives the delay clock CR1 and outputs a delay clock CR2 delayed by Td with respect to the delay clock CR1 to the delay element 83 and the FF 72.

  The delay element 83 receives the delay clock CR2, and outputs the delay clock CR3 delayed by Td with respect to the delay clock CR2 to the FF 73.

  The delay element 84 receives the output clock CO and outputs a delay clock CO1 delayed by Td with respect to the output clock CO to the delay element 85 and the FF 74.

  The delay element 85 receives the delay clock CO1 and outputs the delay clock CO2 delayed by Td with respect to the delay clock CO1 to the delay element 86 and the FF75.

  The delay element 86 receives the delay clock CO2, and outputs the delay clock CO3 delayed by Td with respect to the delay clock CO2 to the FF76.

  The FF 71 holds the output clock CO in synchronization with the rising edge of the delay clock CR1, and outputs the sampling signal SU1.

  The FF 72 holds the output clock CO in synchronization with the rising edge of the delay clock CR2, and outputs the sampling signal SU2.

  The FF 73 holds the output clock CO in synchronization with the rising edge of the delay clock CR3, and outputs the sampling signal SU3.

  The FF 74 holds the reference clock CR in synchronization with the rising edge of the delay clock CO1, and outputs the sampling signal SD1.

  The FF 75 holds the reference clock CR in synchronization with the rising edge of the delay clock CO2, and outputs the sampling signal SD2.

  The FF 76 holds the reference clock CR in synchronization with the rising edge of the delay clock CO3, and outputs the sampling signal SD3.

  The phase difference determination control circuit 77 generates a selection signal SP from the sampling signal SD1, the sampling signal SD2, the sampling signal SD3, the sampling signal SU1, the sampling signal SU2, and the sampling signal SU3, and corrects jitter in the DLL circuit according to the present embodiment. Output to circuit 29.

[Operation]
Next, the operation of the phase difference determination circuit 30 will be described with reference to the time chart shown in FIG.

  The arrows CR1, CR2, and CR3 indicate the rising edges of the delay clock CR1, the delay clock CR2, and the delay clock CR3, respectively.

  The rising edge of the delay clock CR1 appears with a delay of Td with respect to the rising edge of the reference clock CR, and the rising edge of the delay clock CR2 appears with a delay of Td with respect to the rising edge of the delay clock CR1. The rising edge of the delay clock CR3 appears with a delay of Td from the rising edge.

  The arrows CO1, CO2 and CO3 indicate the rising edges of the delay clock CO1, the delay clock CO2 and the delay clock CO3, respectively.

  The rising edge of the delay clock CO1 appears with a delay of Td with respect to the rising edge of the output clock CO, and the rising edge of the delay clock CO2 appears with a delay of Td with respect to the rising edge of the delay clock CO1. The rising edge of the delay clock CO3 appears with a delay of Td with respect to the rising edge.

  As shown in (a) of FIG. 17, a jitter whose phase advances occurs in the reference clock CR, the reference clock CR appears earlier than the output clock CO by Tj, and 2 × Td ≦ Tj <3 × Td. explain.

  At the timing of the rising edge of the delay clock CR1 that appears late by Td from the rising edge of the reference clock CR, the output clock CO is at the L level, so the sampling signal SU1 output from the FF 71 is at the L level.

  At the timing of the rising edge of the delay clock CR2 that appears later by 2 × Td from the rising edge of the reference clock CR, the output clock CO is at the L level, so the sampling signal SU2 output from the FF 72 is at the L level.

  At the timing of the rising edge of the delay clock CR3 that appears 3 × Td later than the rising edge of the reference clock CR, the output clock CO is at the H level, so the sampling signal SU3 output from the FF 73 is at the H level.

  At the timing of the rising edge of the delay clock CO1 that appears later by Td from the rising edge of the output clock CO, the reference clock CR is at the H level, so the sampling signal SD1 output from the FF 74 is at the H level.

  At the timing of the rising edge of the delayed clock CO1, which appears later by 2 × Td from the rising edge of the output clock CO, the reference clock CR is at the H level, so the sampling signal SD2 output from the FF 75 is at the H level.

  At the timing of the rising edge of the delay clock CO1 that appears later by 3 × Td from the rising edge of the output clock CO, the reference clock CR is at the H level, so the sampling signal SD3 output from the FF 76 is at the H level.

  Since the sampling signal SU1 and the sampling signal SU2 are at the L level and the sampling signal SU3, the sampling signal SD1, the sampling signal SD2, and the sampling signal SD3 are at the H level, the phase difference determination control circuit 77 has the phase of the reference clock CR. It is determined that the forward jitter occurs and the reference clock CR appears 2 × Td or more earlier than the output clock CO and less than 3 × Td.

  Then, the phase difference determination control circuit 77 causes the jitter correction circuit 29 shown in FIG. 15 to select the delay line D15 so that the delay clock C1 is delayed by 5 × Td, and the delay clock C2 is 5 ×. The delay line D25 is selected so as to be delayed by Td, the delay line D34 is selected so that the delay clock C3 is delayed by 4 × Td, and the delay clock C4 is delayed by 4 × Td. The delay line D44 is selected, the delay line D53 is selected so that the delay clock C5 is delayed by 3 × Td, and the delay line D63 is selected so that the delay clock C6 is delayed by 3 × Td. The delay line D73 is selected so that the delay clock C7 is delayed by 3 × Td, and the delay clock As click C8 is delayed by 3 × Td, it generates a selection signal SP to select a delay line D83, and outputs.

  In the same manner as described above, when the reference clock CR has jitter whose phase advances, the reference clock CR appears earlier than the output clock CO by Tj, and 3 × Td ≦ Tj, the sampling signal SU1 and the sampling signal SU2 And the sampling signal SU3 becomes L level, and the sampling signal SD1, sampling signal SD2, and sampling signal SD3 become H level.

  In this case, the phase difference determination control circuit 77 causes the jitter correction circuit 29 shown in FIG. 15 to select the delay line D16 so that the delay clock C1 is delayed by 6 × Td, and the delay clock C2 is 6 The delay line D26 is selected so as to be delayed by × Td, the delay line D35 is selected so that the delay clock C3 is delayed by 5 × Td, and the delay clock C4 is delayed by 5 × Td. The delay line D64 is selected, the delay line D54 is selected so that the delay clock C5 is delayed by 4 × Td, and the delay line D64 is set so that the delay clock C6 is delayed by 4 × Td. The delay line D73 is selected so that the delay clock C7 is delayed by 3 × Td, and the delay clock C7 is selected. Tsu so click C8 is delayed by 3 × Td, it generates a selection signal SP to select a delay line D83, and outputs.

  In the same manner as described above, when the reference clock CR has jitter whose phase is advanced, the reference clock CR appears earlier than the output clock CO by Tj, and Td ≦ Tj <2 × Td, the sampling signal SU1 is L The sampling signal SU2, the sampling signal SU3, the sampling signal SD1, the sampling signal SD2, and the sampling signal SD3 become H level.

  In this case, the phase difference determination control circuit 77 causes the jitter correction circuit 29 shown in FIG. 15 to select the delay line D14 so that the delay clock C1 is delayed by 4 × Td, and the delay clock C2 is 4 The delay line D24 is selected so as to be delayed by × Td, the delay line D33 is selected so that the delay clock C3 is delayed by 3 × Td, and the delay clock C4 is delayed by 3 × Td. The delay line D43 is selected, the delay line D53 is selected so that the delay clock C5 is delayed by 3 × Td, and the delay line D63 is set so that the delay clock C6 is delayed by 3 × Td. The delay line D73 is selected so that the delay clock C7 is delayed by 3 × Td, and the delay clock C7 is selected. Tsu so click C8 is delayed by 3 × Td, it generates a selection signal SP to select a delay line D83, and outputs.

  As shown in FIG. 17C, a case where a jitter whose phase is delayed occurs in the reference clock CR, is delayed by Tj from the output clock CO, the reference clock CR appears, and Td ≦ Tj <2 × Td will be described. .

  At the timing of the rising edge of the delay clock CR1, which appears later by Td from the rising edge of the reference clock CR, the output clock CO is at the H level, so the sampling signal SU1 output from the FF 71 is at the H level.

  At the timing of the rising edge of the delay clock CR2, which appears later by 2 × Td from the rising edge of the reference clock CR, the output clock CO is at the H level, so the sampling signal SU2 output from the FF 72 is at the H level.

  At the timing of the rising edge of the delay clock CR3 that appears 3 × Td later than the rising edge of the reference clock CR, the output clock CO is at the H level, so the sampling signal SU3 output from the FF 73 is at the H level.

  At the timing of the rising edge of the delay clock CO1 that appears later by Td from the rising edge of the output clock CO, the reference clock CR is at the L level, so the sampling signal SD1 output from the FF 74 is at the L level.

  At the timing of the rising edge of the delayed clock CO1, which appears later by 2 × Td from the rising edge of the output clock CO, the reference clock CR is at the H level, so the sampling signal SD2 output from the FF 75 is at the H level.

  At the timing of the rising edge of the delay clock CO1 that appears later by 3 × Td from the rising edge of the output clock CO, the reference clock CR is at the H level, so the sampling signal SD3 output from the FF 76 is at the H level.

  Since the sampling signal SU1, the sampling signal SU2, and the sampling signal SU3 are at the H level, the sampling signal SD1 is at the L level, and the sampling signal SD2 and the sampling signal SD3 are at the H level, the phase difference determination control circuit 77 Jitter with a phase delay is generated in the clock CR, and it is determined that the reference clock CR appears after the output clock CO by Td or more and less than 2 × Td.

  Then, the phase difference determination control circuit 77 causes the jitter correction circuit 29 shown in FIG. 15 to select the delay line D14 so that the delay clock C1 is delayed by 2 × Td, and the delay clock C2 is 2 ×. The delay line D24 is selected so as to be delayed by Td, the delay line D33 is selected so that the delay clock C3 is delayed by 3 × Td, and the delay clock C4 is delayed by 3 × Td. The delay line D43 is selected, the delay line D53 is selected so that the delay clock C5 is delayed by 3 × Td, and the delay line D63 is selected so that the delay clock C6 is delayed by 3 × Td. The delay line D73 is selected so that the delay clock C7 is delayed by 3 × Td, and the delay clock As click C8 is delayed by 3 × Td, it generates a selection signal SP to select a delay line D83, and outputs.

  In the same manner as described above, when the reference clock CR has a phase delay jitter, is delayed by Tj from the output clock CO, the reference clock CR appears, and 3 × Td ≦ Tj, the sampling signal SU1 and the sampling signal SU2 The sampling signal SU3 becomes H level, and the sampling signal SD1, sampling signal SD2, and sampling signal SD3 become L level.

  In this case, the phase difference determination control circuit 77 causes the jitter correction circuit 29 shown in FIG. 15 to select the delay line D10 so that the delay clock C1 is not delayed, and so that the delay clock C2 is not delayed. The delay line D20 is selected, the delay line D31 is selected so that the delay clock C3 is delayed by Td, and the delay line D41 is selected so that the delay clock C4 is delayed by Td. The delay line D52 is selected so that the clock C5 is delayed by 2 × Td, the delay line D62 is selected so that the delay clock C6 is delayed by 2 × Td, and the delay clock C7 is 3 × Td. Delay line D73 is selected so that the delay is delayed by 3 × Td. As to, it generates a selection signal SP as to select a delay line D83, and outputs.

  In the same manner as described above, when the reference clock CR has a phase-lag jitter, is delayed by Tj from the output clock CO, appears as the reference clock CR, and 2 × Td ≦ Tj <3 × Td, the sampling signal SU1 The sampling signal SU2 and the sampling signal SU3 become H level, the sampling signal SD1 and the sampling signal SD2 become L level, and the sampling signal SD3 becomes H level.

  In this case, the phase difference determination control circuit 77 causes the jitter correction circuit 29 shown in FIG. 15 to select the delay line D11 so that the delay clock C1 is delayed by Td, and the delay clock C2 is delayed by Td. The delay line D21 is selected, the delay line D32 is selected so that the delay clock C3 is delayed by 2 × Td, and the delay line is selected so that the delay clock C4 is delayed by 2 × Td. D42 is selected, the delay line D53 is selected so that the delay clock C5 is delayed by 3 × Td, and the delay line D63 is selected so that the delay clock C6 is delayed by 3 × Td, and The delay line D73 is selected so that the delay clock C7 is delayed by 3 × Td, and the delay clock C A selection signal SP for selecting the delay line D83 is generated and output so that 8 is delayed by 3 × Td.

  As shown in FIG. 17B, a case will be described in which a jitter whose phase advances occurs in the reference clock CR, the reference clock CR appears earlier than the output clock CO by Tj, and 0 ≦ Tj <Td.

  The phase difference determination control circuit 77 generates the sampling signal SU1, if the reference clock CR appears and the reference clock CR appears earlier by Tj than the output clock CO, and 0 ≦ Tj <Td. Since the signal SU2, the sampling signal SU3, the sampling signal SD1, the sampling signal SD2, and the sampling signal SD3 are at the H level, it is determined that the phases of the reference clock CR and the output clock CO match.

  Then, the phase difference determination control circuit 77 causes the jitter correction circuit 29 shown in FIG. 15 to select the delay line D13 so that the delay clock C1 is delayed by 3 × Td, and the delay clock C2 is 3 ×. The delay line D23 is selected so as to be delayed by Td, the delay line D33 is selected so that the delay clock C3 is delayed by 3 × Td, and the delay clock C4 is delayed by 3 × Td. The delay line D43 is selected, the delay line D53 is selected so that the delay clock C5 is delayed by 3 × Td, and the delay line D63 is selected so that the delay clock C6 is delayed by 3 × Td. The delay line D73 is selected so that the delay clock C7 is delayed by 3 × Td, and the delay clock As click C8 is delayed by 3 × Td, it generates a selection signal SP to select a delay line D83, and outputs.

  In addition, the phase difference determination control circuit 77 causes jitter whose phase is delayed in the reference clock CR, is delayed by Tj from the output clock CO, the reference clock CR appears, and 0 ≦ Tj <Td, and the reference clock CR When no jitter occurs and the phases of the reference clock CR and the output clock CO match, the sampling signal SU1, the sampling signal SU2, the sampling signal SU3, the sampling signal SD1, the sampling signal SD2, and the sampling signal SD3 are at the H level. Therefore, it is determined that the phases of the reference clock CR and the output clock CO are the same, and the same operation as described above is performed.

  Operations other than the jitter correction circuit 29 and the phase difference determination circuit 30 are the same as those of the DLL circuit assumed to be conventionally used as shown in FIG.

  Next, referring to the time chart shown in FIG. 18, in the DLL circuit according to the present embodiment, when a jitter whose phase advances occurs in the reference clock CR, that is, originally, 1 of the reference clock CR. The operation of the jitter correction circuit 29 and the relationship between the reference clock CR and the multiplied clock CX4 when the clock that should appear every period appears by Tj earlier than one period and 3 × Td ≦ Tj will be described.

  Also, only the reference numerals different from those in the time chart shown in FIG. 10 will be described.

  Since jitter does not occur in the reference clock CR at the first clock of the reference clock CR, the jitter correction circuit 29 uses the selection signal SP sent from the phase difference determination circuit 30 to output the delay clock C1 to the delay clock C7 and the output. The clock CO is delayed by 3 × Td and output to the multiplexer 25.

  The arrows indicated by C1Da to C7Da and CODa indicate the rising edges of the clocks after the delay 3Cd as described above is given to the delay clocks C1 to C7 and the output clock CO in the jitter correction circuit 29. It is.

  The arrows indicated by C1Db ′ to C7Db ′ indicate that jitter does not occur in the second clock of the reference clock CR, and the delay clock C1 to the delay clock C7 and the output clock CO are delayed by 3 × Td in the jitter correction circuit 29. Is the rising edge of each delay clock. The alternate long and short dash line in the multiplied clock CX4 is the position of the multiplied clock CX4 in this case.

  First, in spite of the occurrence of jitter whose phase advances at the second clock of the reference clock CR, as in the first clock of the reference clock CR, the jitter correction circuit 29 performs the delay clock C1 to the delay clock C7 and the output clock CO. A case where it is assumed that is delayed by 3 × Td will be described.

  In this case, the rising edges of the delay clocks C1 to C7 corresponding to the second clock of the reference clock CR are defined as C1Dbj to C7Dbj. In this case, the multiplied clock CX4 is set as the multiplied clock CX4j. Also, the pulse corresponding to the second clock of the reference clock CR of the multiplied clock CX4j is set to pulse # 0bj, pulse # 1bj, pulse # 2bj, and pulse # 3bj in order from the rising edge of the reference clock CR.

  Then, C1Dbj to C7Dbj appear at positions earlier by Tj than C1Db 'to C7Db', respectively. Further, CODa that determines the rising edge of the pulse # 0bj of the multiplied clock CX4j is not affected by the jitter generated at the second clock of the reference clock CR. Therefore, the pulse width of the pulse # 0bj of the multiplied clock CX4j is shorter by Tj than the pulse # 0b of the multiplied clock CX4 when it is assumed that no jitter has occurred, which is represented by a one-dot chain line.

  However, in practice, in the DLL circuit according to the present embodiment, the phase difference determination circuit 30 generates the selection signal SP corresponding to this jitter as described below, and the delay clock C1 to the delay clock C7 and the output clock are generated. By adjusting the amount of delay applied to the CO, fluctuations in the pulse width of the pulse # 0b of the multiplied clock CX4 can be reduced.

  That is, in the second clock of the reference clock CR, a jitter whose phase advances in the reference clock CR occurs, the reference clock CR appears earlier by Tj than the output clock CO, and 3 × Td ≦ Tj. Based on the selection signal SP sent from the phase difference determination circuit 30, the circuit 29 sets the delay clock C1 to 6 × Td, the delay clock C2 to 6 × Td, the delay clock C3 to 5 × Td, the delay clock C4 to 5 × Td, Delayed clock C5 is delayed by 4 × Td, delayed clock C6 is delayed by 4 × Td, delayed clock C7 is delayed by 3 × Td, and output clock CO is delayed by 3 × Td and output to multiplexer 25.

  Here, arrows indicated by C1Db to C7Db and CODb are rising edges of the respective clocks after the delays C1 to C7 and the output clock CO are delayed as described above in the jitter correction circuit 29. is there. Further, the solid line in the multiplied clock CX4 is the position of the multiplied clock CX4 in this case.

  Due to the operation of the jitter correction circuit 29 as described above, the delay clock C1 has a 3 × Td delay of 6 × Td given when no jitter occurs, so the falling edge of the pulse # 0b of the multiplied clock CX4 C1Db appears earlier than C1Db ′ by Tj−3 × Td. Further, CODa, which determines the rising edge of the pulse # 0b of the multiplied clock CX4, is not affected by the jitter generated at the second clock of the reference clock CR, and is therefore at the same position as when no jitter occurs. Therefore, the decrease width of the pulse # 0b of the multiplied clock CX4 is Tj−3 × Td.

  The delay clock C2 has a 3 × Td delay of 6 × Td given when no jitter occurs. Therefore, the rising edge of the pulse # 1b of the multiplied clock CX4 is determined. C2Db is Tj− from C2Db ′. Appears earlier by 3 × Td. The delay clock C3 has a 3 × Td delay of 5 × Td given when jitter does not occur. Therefore, the falling edge of the pulse # 1b of the multiplied clock CX4 is determined. C3Db is Tj from C3Db ′. Appears as early as −2 × Td. Accordingly, the decrease width of the pulse # 1b of the multiplied clock CX4 is Td.

  The delay clock C4 has a 3 × Td delay of 5 × Td given when jitter does not occur. Therefore, the rising edge of the pulse # 2b of the multiplied clock CX4 is determined. C4Db is more than Tj− from C4Db ′. Appears as early as 2 × Td. The delay clock C5 has a 3 × Td delay of 4 × Td given when no jitter occurs, so the falling edge of the pulse # 2b of the multiplied clock CX4 is determined. C5Db is Tj from C5Db ′. Appears earlier by -Td. Therefore, the decrease width of the pulse # 2b of the multiplied clock CX4 is Td.

  Further, the delay clock C6 has a 3 × Td delay of 4 × Td given when no jitter occurs, so that the rising edge of the pulse # 3b of the multiplied clock CX4 is determined. C6Db is Tj− from C6Db ′. Appears earlier by Td. Since the delay clock C7 is delayed by 3 × Td as in the case where no jitter occurs, C7Db that determines the falling edge of the pulse # 3b of the multiplied clock CX4 appears earlier by Tj than C7Db ′. Accordingly, the decrease width of the pulse # 3b of the multiplied clock CX4 is Td.

  By the operation as described above, the decrease in the pulse width of the multiplied clock CX4 in the pulse # 0b caused by the jitter generated in the reference clock CR can be distributed to other pulses. That is, the pulse # 0b of the multiplied clock CX4 is shortened by Tj−3 × Td, the pulse # 1b is shortened by Td, the pulse # 2b is shortened by Td, and the pulse # 3b is shortened by Td.

  Similarly for the multiplied clock CX2, C2Db, which determines the falling edge of the pulse # 0b of the multiplied clock CX2, appears earlier than C2Db ′ by Tj−3 × Td. Further, CODa, which determines the rising edge of the pulse # 0b of the multiplied clock CX2, is not affected by the jitter generated at the second clock of the reference clock CR, and is therefore at the same position as when no jitter occurs. Accordingly, the decrease width of the pulse # 0b of the multiplied clock CX2 is Tj−3 × Td.

  C4Db, which determines the rising edge of the pulse # 1b of the multiplied clock CX2, appears earlier by Tj−2 × Td than C4Db ′. Further, C6Db, which determines the falling edge of the pulse # 1b of the multiplied clock CX2, appears earlier than C6Db 'by Tj-Td. Therefore, the decrease width of the pulse # 1b of the multiplied clock CX2 is Td.

  By the operation as described above, the reduction in the pulse width of the pulse # 0b of the multiplied clock CX2 due to the jitter generated in the reference clock CR can be distributed to other pulses. That is, the pulse # 0b of the multiplied clock CX2 is shortened by Tj−3 × Td, and the pulse # 1b is shortened by Td.

  Similarly, for the multiplied clock CX1, C4Db, which determines the falling edge of the pulse # 0b of the multiplied clock CX1, appears Tj−2 × Td earlier than C4Db ′. Further, CODA, which determines the rising edge of the pulse # 0b of the multiplied clock CX1, is not affected by the jitter generated at the second clock of the reference clock CR, and is therefore at the same position as when no jitter occurs. Therefore, the decrease width of the pulse # 0b of the multiplied clock CX1 is Tj−2 × Td.

  By the operation as described above, it is possible to suppress the decrease in the pulse width in the pulse # 0b of the multiplied clock CX1 due to the jitter generated in the reference clock CR from Tj to Tj−2 × Td.

  Next, referring to the time chart shown in FIG. 19, in the DLL circuit according to the present embodiment, when a jitter whose phase is delayed occurs in the reference clock CR, that is, originally, 1 of the reference clock CR. The operation of the jitter correction circuit 29 and the relationship between the reference clock CR and the multiplied clock CX4 when the clock that should appear in each period appears by Tj later than one period and 3 × Td ≦ Tj will be described.

  First, in spite of the occurrence of a jitter whose phase is delayed at the second clock of the reference clock CR, the jitter correction circuit 29 performs the delay clock C1 to the delay clock C7 and the output clock CO in the same manner as the first clock of the reference clock CR. However, the case where it is assumed that the jitter correction circuit 29 is delayed by 3 × Td will be described.

  C1Dbj to C7Dbj appear at positions later by Tj than C1Db 'to C7Db', respectively. Further, CODa that determines the rising edge of the pulse # 0bj of the multiplied clock CX4j is not affected by the jitter generated at the second clock of the reference clock CR. Accordingly, the pulse width of the pulse # 0bj of the multiplied clock CX4j is longer by Tj than the pulse # 0b of the multiplied clock CX4 when it is assumed that no jitter has occurred, which is represented by a one-dot chain line.

  The description of the other symbols is the same as that of the time chart shown in FIG.

  However, in practice, in the DLL circuit according to the present embodiment, the phase difference determination circuit 30 generates the selection signal SP corresponding to this jitter as described below, and the delay clock C1 to the delay clock C7 and the output clock are generated. By adjusting the amount of delay applied to the CO, fluctuations in the pulse width of the pulse # 0b of the multiplied clock CX4 can be reduced.

  That is, in the second clock of the reference clock CR, a jitter whose phase is delayed occurs in the reference clock CR, is delayed by Tj from the output clock CO, the reference clock CR appears, and 3 × Td ≦ Tj. The circuit 29 does not delay the delay clock C1, delay the delay clock C2, and delay the clock C3 as Td, delay clock C4 as Td, and delay clock according to the selection signal SP sent from the phase difference determination circuit 30. Delay C5 by 2 × Td, delay clock C6 by 2 × Td, delay clock C7 by 3 × Td, and output clock CO by 3 × Td, and output to multiplexer 25.

  By the operation of the jitter correction circuit 29 as described above, the delay clock C1 determines the falling edge of the pulse # 0b of the multiplied clock CX4 because the delay of 3 × Td given when no jitter occurs is 0. , C1Db appears later than C1Db ′ by Tj−3 × Td. Further, CODa, which determines the rising edge of the pulse # 0b of the multiplied clock CX4, is not affected by the jitter generated at the second clock of the reference clock CR, and is therefore at the same position as when no jitter occurs. Therefore, the increase width of the pulse # 0b of the multiplied clock CX4 is Tj−3 × Td.

  Further, the delay clock C2 has a delay of 3 × Td given when no jitter occurs, and therefore the rising edge of the pulse # 1b of the multiplied clock CX4 is determined. C2Db is Tj−3 × from C2Db ′. Appears later by Td. Further, the delay clock C3 has a delay of 3 × Td given when no jitter occurs, so that the delay of the pulse # 1b of the multiplied clock CX4 is determined as Td. C3Db is determined by Tj−2 from C3Db ′. Appears slower by Td. Therefore, the increase width of the pulse # 1b of the multiplied clock CX4 is Td.

  The delay clock C4 has a delay of 3 × Td given when jitter does not occur, so that the rising edge of the pulse # 2b of the multiplied clock CX4 is determined. C4Db is Tj−2 × Appears later by Td. The delay clock C5 has a 3 × Td delay of 2 × Td given when jitter does not occur. Therefore, the falling edge of the pulse # 2b of the multiplied clock CX4 is determined. Appears slower by -Td. Therefore, the increase width of the pulse # 2b of the multiplied clock CX4 is Td.

  The delay clock C6 has a 3 × Td delay of 2 × Td given when no jitter occurs. Therefore, the rising edge of the pulse # 3b of the multiplied clock CX4 is determined. C6Db is Tj− from C6Db ′. Appears later by Td. Since the delay clock C7 is given a delay of 3 × Td as in the case where no jitter occurs, C7Db, which determines the falling edge of the pulse # 3b of the multiplied clock CX4, appears later by Tj than C7Db ′. Therefore, the increase width of the pulse # 3b of the multiplied clock CX4 is Td.

  By the operation as described above, the increase in the pulse width in the pulse # 0b of the multiplied clock CX4 caused by the jitter generated in the reference clock CR can be distributed to other pulses. That is, the pulse # 0b of the multiplied clock CX4 becomes longer by Tj−3 × Td, the pulse # 1b becomes longer by Td, the pulse # 2b becomes longer by Td, and the pulse # 3b becomes longer by Td.

  Similarly, for the multiplied clock CX2, C2Db, which determines the falling edge of the pulse # 0b of the multiplied clock CX2, appears later than C2Db ′ by Tj−3 × Td. Further, CODa, which determines the rising edge of the pulse # 0b of the multiplied clock CX2, is not affected by the jitter generated at the second clock of the reference clock CR, and is therefore at the same position as when no jitter occurs. Therefore, the increase width of the pulse # 0b of the multiplied clock CX2 is Tj−3 × Td.

  C4Db, which determines the rise of the pulse # 1b of the multiplied clock CX2, appears later by Tj−2 × Td than C4Db ′. Further, C6Db, which determines the falling edge of the pulse # 1b of the multiplied clock CX2, appears later than C6Db 'by Tj-Td. Therefore, the increase width of the pulse # 1b of the multiplied clock CX2 is Td.

  By the operation as described above, the increase in the pulse width in the pulse # 0b of the multiplied clock CX2 caused by the jitter generated in the reference clock CR can be distributed to other pulses. That is, the pulse # 0b of the multiplied clock CX2 becomes longer by Tj−3 × Td, and the pulse # 1b becomes longer by Td.

  Similarly, for the multiplied clock CX1, C4Db, which determines the falling edge of the pulse # 0b of the multiplied clock CX1, appears later by Tj−2 × Td than C4Db ′. Further, CODA, which determines the rising edge of the pulse # 0b of the multiplied clock CX1, is not affected by the jitter generated at the second clock of the reference clock CR, and is therefore at the same position as when no jitter occurs. Therefore, the increase width of the pulse # 0b of the multiplied clock CX1 is Tj−2 × Td.

  By the operation as described above, an increase in the pulse width in the pulse # 0b of the multiplied clock CX1 due to the jitter generated in the reference clock CR can be suppressed from Tj to Tj−2 × Td.

  Therefore, the DLL circuit described in Patent Document 3 has a drawback that jitter generated in the clock cannot be quickly reduced. However, in the DLL circuit according to the present embodiment, when jitter occurs in the reference clock CR. The jitter is immediately detected by the phase difference determination circuit 30 and the selection signal SP is output to the jitter correction circuit 29, whereby the delay amount given to the delay clock C1 to the delay clock C7 and the output clock CO is adjusted in the jitter correction circuit 29. Thus, it is possible to quickly reduce the influence of jitter, that is, fluctuation of the pulse width in the pulse # 0 of the multiplied clock.

  Further, in the DLL circuit assumed to be conventionally used as shown in FIG. 7, when jitter occurs in the reference clock CR, the pulse width of the pulse # 0 of the multiplied clock generated in the multiplexer 25 depends on the jitter. Although the DLL circuit according to the present embodiment has a drawback that the reference clock CR fluctuates, the jitter correction circuit 29 adjusts the delay amount given to the delay clock C1 to the delay clock C7 and the output clock CO. Thus, fluctuations in the pulse width of the pulse # 0 of the multiplied clock can be reduced.

[Modification]
The present invention is not limited to the above embodiment, and includes, for example, the following modifications.

[Modification 1]
The jitter correction circuit 29 in the DLL circuit according to the third embodiment of the present invention is configured as shown in FIG. 15, but is not limited thereto.

  FIG. 20 shows the configuration of a jitter correction circuit in which the configuration of the delay element is changed for the jitter correction circuit 29 in the DLL circuit according to the third embodiment. Referring to FIG. 15, in this jitter correction circuit 29, delay elements are arranged in parallel for each delay amount given to delay clock C1 to delay clock C7 and output clock CO, as in jitter correction circuit 29 shown in FIG. Instead, delay elements are arranged in series, and the output of each delay element is connected to the selector. Here, the number of delay elements included in each delay line is the same as that of the jitter correction circuit 29 shown in FIG.

  Therefore, the jitter correction circuit 29 according to the present embodiment can reduce the number of buffers compared to the jitter correction circuit 29 shown in FIG.

[Modification 2]
In the PLL circuit according to the first embodiment of the present invention, the voltage setting circuit 10 is configured to output three types of control voltages of the VH level, the VM level, and the VL level, but the present invention is not limited to this. It may be one that can select various types of voltage levels according to the application of the IC in which the PLL circuit is used. With such a configuration, a more accurate initial control voltage can be applied to the voltage controlled oscillator 6 and the time until the PLL circuit is locked can be sufficiently shortened. The same applies to the DLL circuit according to the second embodiment of the present invention.

[Modification 3]
In the control circuit 33 in the set value determination circuit 9 of the PLL circuit according to the first embodiment of the present invention, when the PLL circuit transitions to the standby mode, the voltage setting circuit 10 in the order of VH level, VM level, and VL level. Outputs the selection signal SV so as to output the control voltage VC, counts the number of clocks of the output clock CO for one cycle of the reference clock CR, and among these count results, the multiplication number set in the PLL circuit However, the present invention is not limited to this.

  When the PLL circuit transitions to the standby mode, the voltage setting circuit 10 outputs the selection signal SV so as to output the control voltage VC at the VM level, counts the number of clocks of the output clock CO for one cycle of the reference clock CR, If the count result is within a certain range with respect to the multiplication number set in the PLL circuit, the VM level is selected. If the count result is larger than the certain range, a VL level having a lower voltage may be selected. If the count result is smaller than the certain range, a VH level having a higher voltage may be selected. With such a configuration, an optimal initial control voltage can be selected with a smaller number of trials, and the stop of each circuit or the stop of power supply in the PLL circuit can be accelerated. The control circuit 73 in the set value determination circuit 26 of the DLL circuit according to the second embodiment of the present invention is the same as described above.

[Modification 4]
In the PLL circuit according to the first embodiment of the present invention, the set value determination circuit 9 is configured to select and hold the optimum selection signal SV. However, the present invention is not limited to this. It is only necessary that the voltage setting circuit 10 can receive the selection signal SV even when the setting value determination circuit 9 stops operation by the setting value determination circuit 9 selecting and fixing the optimum selection signal SV. . The setting value determination circuit 26 in the DLL circuit according to the second embodiment of the present invention is the same as described above.

[Modification 5]
In the PLL circuit according to the first embodiment of the present invention, the FF 34 is arranged at the output of the set value determination circuit 9, but the present invention is not limited to this. It is only necessary that the FF 34 can receive the selection signal SV output from the setting value determination circuit 9, hold the selection signal SV, and send the selection signal SV to the voltage setting circuit 10. That is, the FF 34 may be included in the voltage setting circuit 10 or may be configured between the output of the set value determination circuit 9 and the input of the voltage setting circuit 10.

  In such a case, the power supply control circuit 12 can send a control signal to the FF 34 to stop the power supply to the FF 34.

  Moreover, although FF34 is a flip-flop, it is not limited to this. Other storage elements that can write, hold, and read the selection signal SV can be used. The same applies to the FF 74 in the DLL circuit according to the second embodiment of the present invention.

[Modification 6]
In the DLL circuit according to the third embodiment of the present invention, the voltage control delay circuit 24 is configured to generate and output a clock obtained by dividing one period of the reference clock CR into eight, but the present invention is not limited to this. It is not a thing. A clock may be generated by equally dividing one cycle of the reference clock CR by 2 × m (m is a natural number of 1 or more). With this configuration, the multiplexer 25 can generate a clock that is m times the reference clock CR.

[Modification 7]
The jitter correction circuit 29 in the DLL circuit according to the third embodiment of the present invention is not limited to the configuration shown in FIG.

  The jitter correction circuit 29 receives the output clock CO and (k-1) delay clocks (k is a natural number of 2 or more). The jitter correction circuit 29 includes j selectors (j is a natural number satisfying 1 ≦ j ≦ k). Hereinafter, the description of “delayed clock” without reference numerals includes the output clock CO.

  Each selector receives separate delay clocks via three or more delay lines. Note that the number of delay lines connected to each selector may not be the same.

  At least one of the three or more delay lines connected to each selector is a delay line having a common delay amount among the selectors. This common delay amount is a delay amount given to each delay clock when no jitter occurs in the reference clock CR (hereinafter referred to as a steady delay amount).

  In addition, in order to cope with jitter that advances in phase and jitter that delays in phase, each selector is connected to a delay line having a delay amount larger than the steady delay amount and a delay line having a delay amount smaller than the steady delay amount. Is done.

  Also, a delay clock connected to only one delay line need not be connected to the selector. The delay amount of this delay line is a steady delay amount.

  Here, in order to prevent fluctuation of the pulse # 0 of the multiplied clock, the delay clock C1 is connected to the selector via three or more delay lines, so that the delay amount to be given to the delay clock C1 can be selected by the selector. It is necessary to make such a configuration.

  In order to disperse the fluctuation of the pulse # 0 after the pulse # 1, the selector can select the delay amount to be given to the delay clock starting from the delay clock C2 and continuing to the delay clock C3, the delay clock C4,. It is necessary to make such a configuration. .. Are connected to the selector in the range corresponding to pulse # 1, pulse # 2,... To which the fluctuation of pulse # 0 is to be dispersed. These delay clocks may be connected to one delay line having a steady delay amount.

  Next, the operation of the jitter correction circuit 29 will be described.

  The selector that receives the delayed clock C1 is the first selector, the selector that receives the delayed clock C2 is the second selector, and the selector that receives the delayed clock Cj is the jth selector.

  First, when no jitter occurs in the reference clock CR, each selector selects a delay line with a steady delay amount.

  Next, when the jitter whose phase advances occurs, the first selector selects a delay line having a delay amount larger than the steady delay amount, and the second to jth selectors have a delay amount equal to or greater than the steady delay amount. Select the delay line. In order to control to suppress the influence of jitter, as shown in FIG. 18, the delay amount of the delay line selected by each selector is set to delay clock C1, delay clock C2,... Delay clock C7, output clock CO. It is desirable to decrease monotonically in this order. That is, among the delay amounts of the delay line selected by each selector, the delay amount given to the delay clock C1 is the maximum delay amount, and the delay amount given to the output clock CO is the minimum delay amount.

  Here, monotonically decreasing means that the function f (x) satisfies f (a) ≧ f (b) for any a and b satisfying A <a <b <B, and f (A)> A relationship that satisfies f (B) is assumed. That is, there may be a section in which f (x) is constant within a range from A to B.

  In the third embodiment of the present invention, x is the number of delay elements through which the reference clock CR passes in the voltage control delay circuit 24. The delay clock C1 is obtained by passing one delay element for the reference clock CR. Accordingly, the delay clock C1 corresponds to x = 1, and the number of delay elements through which the reference clock CR passes is the smallest in each delay clock in the case of the delay clock C1, and therefore A = 1. . The output clock CO is obtained by passing eight delay elements with respect to the reference clock CR. Therefore, the output clock CO corresponds to x = 8, and the number of delay elements through which the reference clock CR passes is the largest in each delay clock in the case of the output clock CO, so B = 8. . F (x) is the delay amount of the delay line selected by each selector.

  For example, in the time chart shown in FIG. 18, f (1) = 6 × Td, f (2) = 6 × Td, f (3) = 5 × Td, f (4) = 5 × Td, f (5) = 4 * Td, f (6) = 4 * Td, f (7) = 3 * Td, f (8) = 3 * Td.

  Next, when a jitter whose phase is delayed occurs, the first selector selects a delay line having a delay amount smaller than the steady delay amount, and the second to jth selectors have a delay amount equal to or less than the steady delay amount. Select the delay line. In order to perform control to suppress the influence of jitter, as shown in FIG. 19, the delay amount of the delay line selected by each selector is set to delay clock C1, delay clock C2,... Delay clock C7, output clock CO. It is desirable to increase monotonically in this order. That is, among the delay amounts of the delay line selected by each selector, the delay amount given to the delay clock C1 is the minimum delay amount, and the delay amount given to the output clock CO is the maximum delay amount.

  Here, monotonically increasing means that the function f (x) satisfies f (a) ≦ f (b) for any a and b satisfying A <a <b <B, and f (A) < A relationship that satisfies f (B) is assumed.

  Then, the phase difference determination control circuit 77 in the phase difference determination circuit 30 of the DLL circuit according to the third embodiment of the present invention causes the jitter correction circuit 29 to select the delay line as described above. By generating the SP, fluctuations in the pulse width of the multiplied clock can be reduced.

  In the present embodiment, the case where k = 8, j = 6, and the steady delay amount is 3 × Td has been described. In FIG. 15, eight selectors are arranged. However, the selector 67 and the selector 68 connected to one delay line need not be arranged, so j = 6.

[Modification 8]
In the DLL circuit according to the third embodiment of the present invention, the phase difference determination circuit 30 uses (3 × Td) the reference clock CR and the output clock CO by using three buffers and flip-flops, respectively. Although the following phase difference can be detected, the present invention is not limited to this. Assuming that the maximum multiplication number of the multiplication clock generated by the multiplexer is n (n is a natural number of 2 or more), as described above, phase correction is performed on a clock obtained by dividing one cycle of the reference clock CR into (2 × n). Therefore, by using (2 × n−2) buffers and flip-flops, a phase difference of ((n−1) × Td) or less can be detected.

  In the present embodiment, the case where n = 4 has been described.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows the structure of the PLL circuit assumed to be used conventionally. It is a figure which shows the structure of the voltage setting circuit 7 in the PLL circuit shown in FIG. It is a figure which shows the structure of the PLL circuit concerning 1st Embodiment. It is a time chart which shows operation | movement of the PLL circuit concerning 1st Embodiment. It is a figure which shows the structure of the voltage setting circuit 10 in the PLL circuit concerning 1st Embodiment. It is a figure which shows the structure of the setting value determination circuit 9 in the PLL circuit concerning 1st Embodiment. It is a figure which shows the structure of the DLL circuit assumed to be used conventionally. FIG. 8 is a diagram showing a configuration of a voltage control delay circuit 24 and a multiplexer 25 in the DLL circuit shown in FIG. 7. 9 is a time chart illustrating operations of the voltage control delay circuit 24 and the multiplexer 25 illustrated in FIG. 8. 8 is a time chart showing the operation of the DLL circuit shown in FIG. It is a figure which shows the structure of the DLL circuit concerning 2nd Embodiment. It is a time chart which shows the operation | movement of the DLL circuit concerning 2nd Embodiment. It is a figure which shows the structure of the setting value determination circuit 26 in the DLL circuit concerning 2nd Embodiment. It is a figure which shows the structure of the DLL circuit concerning 3rd Embodiment. It is a figure which shows the structure of the jitter correction circuit 29 in the DLL circuit concerning 3rd Embodiment. It is a figure which shows the structure of the phase difference determination circuit 30 in the DLL circuit concerning 3rd Embodiment. 17 is a time chart illustrating an operation of the phase difference determination circuit 30 illustrated in FIG. 16. 16 is a time chart showing the operation of the jitter correction circuit 29 shown in FIG. 16 is a time chart showing the operation of the jitter correction circuit 29 shown in FIG. FIG. 16 is a diagram showing another configuration of the jitter correction circuit 29 shown in FIG. 15.

Explanation of symbols

  1, 2 frequency divider, 3, 21 phase comparator, 4, 22 charge pump, 5, 23 loop filter, 6 voltage controlled oscillator, 7, 10, 27 voltage setting circuit, 8, 11, 28 timer, 17, 27 Load, 13 Analog buffer, 14, 15 switch, 9, 26 Set value judgment circuit, 12, 26, 29, 38, 78 Power supply control circuit, 22, 61, 62, 63, 64, 65, 66, 67, 68 Selector , 23 Analog buffer, 24, 25 switch, 26 OR gate, 31, 71 counter, 32, 34, 71, 72, 73, 74, 75, 76 FF, 33, 73 control circuit, 35, 75 pulse generation circuit, 36 , 37, 76, 77 AND gate, 24 voltage control delay circuit, 25 multiplexer, 41, 42, 43, 44, 45, 46, 47, 48 81, 82, 83, 84, 85, 86 Delay element 51, 52, 53, 54, 55, 56, 57, 58 Buffer, 49 Bias generation circuit, 29 Jitter correction circuit, 30 Phase difference determination circuit, 77th place Phase difference determination control circuit.

Claims (17)

A phase comparator that detects a phase difference between an input clock and an output clock and performs a phase comparison process that outputs a phase difference signal according to the phase difference;
A charge pump for performing phase difference current conversion processing to increase and decrease the control current according to the phase difference signal and output;
A loop filter that smoothes the output control current, converts the smoothed control current into a first control voltage, and outputs the first control voltage;
A voltage controlled oscillator that performs voltage frequency conversion processing to increase and decrease the frequency of the output clock according to the first control voltage or the second control voltage,
A voltage setting circuit for performing control voltage output processing for selecting and outputting the level of the second control voltage in accordance with an input selection signal;
In order to set the level of the second control voltage output from the voltage setting circuit, at least one of a plurality of selection signals is output to the voltage setting circuit, and the voltage setting circuit outputs the selection signal according to the selection signal. Detecting a first multiplication number of the output clock output from the voltage controlled oscillator according to the second control voltage with respect to the input clock, and selecting the plurality of selection signals based on the first multiplication number. A set value determination circuit that performs a set value determination process that specifies an optimum selection signal from among the above, and fixes the specified selection signal as a selection signal to be output to the voltage setting circuit,
The charge pump, the voltage controlled oscillator, the voltage setting circuit, and the set value determination circuit are configured to perform the phase difference current conversion process, the voltage frequency conversion process, the control voltage output process, and the set value determination process according to a standby signal. PLL circuit for starting and stopping. A timer for receiving the standby signal and generating a first control signal and a second control signal;
A storage element that holds the selection signal;
The voltage setting circuit acquires the selection signal from the storage element,
The charge pump performs the phase difference current conversion process when the standby signal is at a first logic level and the second control signal is at a second logic level, and the standby signal is at a second logic level or Stopping the phase difference current conversion process when the second control signal is at a first logic level;
The voltage-controlled oscillator performs the voltage frequency conversion processing when the standby signal is at a first logic level or the first control signal is at a first logic level, and the standby signal and the first control signal Stops the voltage frequency conversion process when is at the second logic level;
The voltage setting circuit performs the control voltage output processing when the first control signal is at a first logic level or the second control signal is at a first logic level, and the first control signal and Stopping the control voltage output process when the second control signal is at a second logic level;
The set value determination circuit performs the set value determination process when the first control signal reaches a first logic level, and stops the set value determination process when the first control signal reaches a second logic level. The PLL circuit according to claim 1. The first period is a period from when the standby signal changes from the first logic level to the second logic level until a period sufficient for the set value determination circuit to fix the specified selection signal elapses. Period,
The second period, which is the period following the first period, is a period until the standby signal changes from the second logic level to the first logic level,
A third period, which is a period subsequent to the second period, is a period until a period sufficient for the output clock whose frequency has been increased or decreased to be stabilized corresponding to the fixed selection signal elapses.
The fourth period, which is the period following the third period, is a period until the standby signal changes from the first logic level to the second logic level,
The timer sets the first control signal to a first logic level during the first period, and sets the second control signal to a second logic level, and the first control signal during the second period. The control signal and the second control signal are set to a second logic level, the first control signal is set to a second logic level in the third period, and the second control signal is set to a first logic level. 3. The PLL circuit according to claim 2, wherein the first control signal and the second control signal are set to a second logic level during the fourth period.   When the standby signal, the first control signal, and the second control signal are at a second logic level, power is supplied to the storage element, and the phase comparator, the charge pump, The PLL circuit according to claim 2, further comprising: a power supply control circuit that stops power supply of at least one of the voltage controlled oscillator, the voltage setting circuit, and the set value determination circuit. The set value determination circuit includes:
A pulse generation circuit for periodically generating and outputting a pulse of one cycle width of the input clock;
A counter that counts the number of clocks of the output clock during the period of receiving the pulse and outputs the first multiplication number;
A first flip-flop that holds and outputs the first multiplication number for each period of an input clock;
In order to set the level of the second control voltage output from the voltage setting circuit, a plurality of selection signals are sequentially output to the voltage setting circuit, and a plurality of first signals corresponding to the plurality of selection signals are output. A control circuit that specifies the selection signal corresponding to the first multiplication number closest to the second multiplication number among the multiplication numbers of the first and second, and fixes the specified selection signal as a selection signal to be output to the voltage setting circuit The PLL circuit according to claim 1, comprising: The set value determination circuit includes:
A pulse generation circuit for periodically generating and outputting a pulse of one cycle width of the input clock;
A counter that counts the number of clocks of the output clock during the period of receiving the pulse and outputs the first multiplication number;
A first flip-flop that holds and outputs the first multiplication number for each period of an input clock;
The voltage setting circuit outputs the selection signal that causes the first level to be selected as the second control voltage, and the first multiplication number output from the first flip-flop corresponding to the first level is: If the second multiplication number is within a predetermined range, the selection signal for selecting the first level is fixed as a selection signal to be output to the voltage setting circuit, and the first multiplication number is the predetermined number. The selection signal for causing the voltage setting circuit to set a second level as the second control voltage is fixed as a selection signal to be output to the voltage setting circuit, and the first multiplication number is A control circuit that fixes the selection signal that causes the voltage setting circuit to select a third level as the second control voltage as a selection signal that is output to the voltage setting circuit if smaller than the predetermined range; PLL circuit free claim 1. The voltage setting circuit includes:
A first switch having one end connected to a first fixed voltage and switching between an on state and an off state in response to the standby signal;
One end is connected to the other end of the first switch, the other end is connected to a second fixed voltage, and the first to n-th (n is the range of the first fixed voltage to the second fixed voltage). A load that supplies a voltage of 2 or more natural numbers),
A selector that selects one of the first to nth voltages in response to the selection signal;
An analog buffer that has an input terminal connected to the selector and outputs the second control voltage;
The PLL circuit according to claim 1, further comprising: a second switch having one end connected to an output end of the analog buffer and switching between an on state and an off state in accordance with the standby signal. A phase comparator that detects a phase difference between an input clock and an output clock and performs a phase comparison process that outputs a phase difference signal according to the phase difference;
A charge pump for performing phase difference current conversion processing to increase and decrease the control current according to the phase difference signal and output;
A loop filter that smoothes the output control current, converts the smoothed control current into a first control voltage, and outputs the first control voltage;
A voltage control delay circuit for generating a delay clock in which a delay amount applied to the input clock is increased or decreased according to the first control voltage or the second control voltage and a voltage delay amount conversion process for generating and outputting the output clock; ,
A multiplexer that generates and outputs a multiplied clock of the input clock from the delayed clock and the output clock; and
A voltage setting circuit for performing control voltage output processing for selecting and outputting the level of the second control voltage in accordance with an input selection signal;
In order to set the level of the second control voltage output from the voltage setting circuit, at least one of a plurality of selection signals is output to the voltage setting circuit, and the multiplied clock has a second frequency with respect to the input clock. As a selection signal for detecting a multiplication number of 1, specifying an optimum selection signal from the plurality of selection signals based on the first multiplication number, and outputting the specified selection signal to the voltage setting circuit A set value determination circuit for performing a fixed set value determination process,
The charge pump, the voltage control delay circuit, the voltage setting circuit, and the set value determination circuit are configured to perform the phase difference current conversion process, the voltage delay amount conversion process, the control voltage output process, and the set value according to a standby signal A DLL circuit for starting and stopping determination processing. A timer for receiving the standby signal and generating a first control signal and a second control signal;
A storage element that holds the selection signal;
The voltage setting circuit acquires the selection signal from the storage element,
The charge pump performs the phase difference current conversion process when the standby signal is at a first logic level and the second control signal is at a second logic level, and the standby signal is at a second logic level or Stopping the phase difference current conversion process when the second control signal is at a first logic level;
The voltage control delay circuit performs the voltage delay amount conversion processing when the standby signal is at the first logic level or the first control signal is at the first logic level, and the standby signal and the first Stopping the voltage delay amount conversion process when the control signal is at the second logic level;
The voltage setting circuit performs the control voltage output processing when the first control signal is at a first logic level or the second control signal is at a first logic level, and the first control signal and Stopping the control voltage output process when the second control signal is at a second logic level;
The set value determination circuit performs the set value determination process when the first control signal reaches a first logic level, and stops the set value determination process when the first control signal reaches a second logic level. The DLL circuit according to claim 8. The first period is a period from when the standby signal changes from the first logic level to the second logic level until a period sufficient for the set value determination circuit to fix the specified selection signal elapses. Period,
The second period, which is the period following the first period, is a period until the standby signal changes from the second logic level to the first logic level,
The third period, which is the period following the second period, is a period until a period sufficient for the output clock whose delay amount has been increased or decreased to be stabilized corresponding to the fixed selection signal elapses.
The fourth period, which is the period following the third period, is a period until the standby signal changes from the first logic level to the second logic level,
The timer sets the first control signal to a first logic level during the first period, and sets the second control signal to a second logic level, and the first control signal during the second period. The control signal and the second control signal are set to a second logic level, the first control signal is set to a second logic level in the third period, and the second control signal is set to a first logic level. 10. The DLL circuit according to claim 9, wherein the first control signal and the second control signal are set to a second logic level in the fourth period.   When the standby signal, the first control signal, and the second control signal are at a second logic level, power is supplied to the storage element, and the phase comparator, the charge pump, The DLL circuit according to claim 9, further comprising a power control circuit that stops power supply of at least one of the voltage control delay circuit, the voltage setting circuit, and the set value determination circuit. The set value determination circuit includes:
A pulse generation circuit for periodically generating and outputting a pulse of one cycle width of the input clock;
A counter that counts the number of clocks of the multiplied clock during the period of receiving the pulse, and outputs the first multiplied number;
A first flip-flop that holds and outputs the first multiplication number for each period of an input clock;
In order to set the level of the second control voltage output from the voltage setting circuit, a plurality of selection signals are sequentially output to the voltage setting circuit, and a plurality of first signals corresponding to the plurality of selection signals are output. A control circuit that specifies the selection signal corresponding to the first multiplication number closest to the second multiplication number among the multiplication numbers of the first and second, and fixes the specified selection signal as a selection signal to be output to the voltage setting circuit The DLL circuit according to claim 8, comprising: The set value determination circuit includes:
A pulse generation circuit for periodically generating and outputting a pulse of one cycle width of the input clock;
During the period of receiving the pulse, a counter that counts the number of clocks of the multiplied clock and outputs a count result;
A first flip-flop that holds and outputs the count result for each period of the input clock;
The voltage setting circuit outputs the selection signal that causes the first level to be selected as the second control voltage, and the first multiplication number output from the first flip-flop corresponding to the first level is: If the second multiplication number is within a predetermined range, the selection signal for setting the first level is fixed as a selection signal to be output to the voltage setting circuit, and the first multiplication number is the predetermined number. The selection signal for causing the voltage setting circuit to select the second level as the second control voltage is fixed as a selection signal to be output to the voltage setting circuit, and the first multiplication number is A control circuit that fixes the selection signal that causes the voltage setting circuit to select a third level as the second control voltage as a selection signal that is output to the voltage setting circuit if smaller than the predetermined range; DLL circuit no claim 8. The voltage setting circuit includes:
A first switch having one end connected to a first fixed voltage and switching between an on state and an off state in response to the standby signal;
One end is connected to the other end of the first switch, the other end is connected to a second fixed voltage, and the first to n-th (n is the range of the first fixed voltage to the second fixed voltage). A load that supplies a voltage of 2 or more natural numbers),
A selector that selects one of the first to nth voltages in response to the selection signal;
An analog buffer that has an input terminal connected to the selector and outputs the second control voltage;
The DLL circuit according to claim 8, further comprising: a second switch having one end connected to the output end of the analog buffer and switching between an on state and an off state in accordance with the standby signal. A phase comparator that detects a phase difference between an input clock and an output clock and outputs a phase difference signal corresponding to the phase difference;
A charge pump for performing phase difference current conversion processing to increase and decrease the control current according to the phase difference signal and output;
A loop filter that smoothes the output control current, converts the smoothed control current into a control voltage, and outputs the control voltage;
A voltage controlled delay circuit for generating a delay clock that increases or decreases a delay amount applied to the input clock according to the control voltage and a voltage delay amount conversion process for generating and outputting the output clock;
A phase difference determination circuit that detects a phase difference between the input clock and the output clock, generates a selection signal corresponding to the phase difference, and outputs the selection signal;
A jitter correction circuit that outputs a corrected delay clock and a corrected output clock in which a delay amount applied to the delay clock and the output clock is increased or decreased according to the selection signal;
A DLL circuit including a multiplexer that generates and outputs a multiplied clock of the input clock from the corrected delay clock and the corrected output clock. The phase difference determination circuit includes a first delay element to a (2 × n−2) delay element (n is a natural number of 2 or more), a first flip-flop to a (2 × n−2) flip-flop. Including
The input clock is connected to an input of the first delay element;
The output of the first delay element is connected to the clock terminal of the first flip-flop, the output clock is connected to the data terminal,
The output of the (h−1) th delay element is connected to the input of the hth (h is all natural numbers satisfying 2 ≦ h ≦ (n−1)),
An output of the h-th delay element is connected to a clock terminal of the h-th flip-flop, and the output clock is connected to a data terminal;
The output clock is connected to an input of the nth delay element;
The output of the nth delay element is connected to the clock terminal of the nth flip-flop, the input clock is connected to the data terminal,
The output of the (j−1) th delay element is connected to the input of the jth delay element (j is all natural numbers satisfying n ≦ j ≦ (2 × n−2)),
An output of the jth delay element is connected to a clock terminal of the jth flip-flop, and the input clock is connected to a data terminal;
The output of the first flip-flop to the output of the (2 × n−2) th flip-flop are connected to the phase difference determination circuit,
The DLL according to claim 15, wherein the phase difference determination control circuit generates and outputs the selection signal according to an output of the first flip-flop to an output of the (2 × n−2) th flip-flop. circuit. The jitter correction circuit includes a first delayed clock obtained by giving a predetermined delay amount to the input clock, and an i-th delayed clock (i is all natural numbers satisfying 1 ≦ i ≦ (k−1), k Is the (i + 1) th delay clock that gives the predetermined delay amount to a natural number of 2 or more,
The kth delay clock is the output clock;
1st selector to jth (j is a natural number satisfying 1 ≦ j ≦ k) selectors,
The n-th selector (n is an all natural number satisfying 1 ≦ n ≦ j) receives the n-th delay clock through a plurality of delay lines, and the plurality of delays according to the selection signal. Select one of the lines and output as the nth corrected delay clock;
The plurality of delay lines connected to the nth selector are larger than the steady delay amount and a delay line having a steady delay amount that is a common delay amount for the first to jth selectors. A delay line having a delay amount, and a delay line having a delay amount smaller than the steady delay amount,
When j ≠ k, the (j + 1) th to kth delay clocks are output as the (j + 1) th to kth correction delay clocks through one delay line having the steady delay amount. ,
The DLL circuit according to claim 15, wherein the kth correction delay clock is the correction output clock.

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