JP2022188583A - Substrate for semiconductor device - Google Patents

Substrate for semiconductor device Download PDF

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JP2022188583A
JP2022188583A JP2021096735A JP2021096735A JP2022188583A JP 2022188583 A JP2022188583 A JP 2022188583A JP 2021096735 A JP2021096735 A JP 2021096735A JP 2021096735 A JP2021096735 A JP 2021096735A JP 2022188583 A JP2022188583 A JP 2022188583A
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copper plate
semiconductor device
recess
plate
copper
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JP2022188583A5 (en
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智生 高井
Tomoo Takai
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NGK Insulators Ltd
NGK Electronics Devices Inc
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NGK Insulators Ltd
NGK Electronics Devices Inc
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Priority to JP2021096735A priority Critical patent/JP2022188583A/en
Priority to PCT/JP2022/011601 priority patent/WO2022259676A1/en
Priority to CN202280040561.7A priority patent/CN117480599A/en
Priority to DE112022002069.5T priority patent/DE112022002069T5/en
Publication of JP2022188583A publication Critical patent/JP2022188583A/en
Publication of JP2022188583A5 publication Critical patent/JP2022188583A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

To provide a substrate for a semiconductor device capable of inhibiting the wetting spread of solder and other bonding materials even when recesses are formed in the copper plate.SOLUTION: A substrate for a semiconductor device according to the present invention has an insulating plate having first and second surfaces, a first copper plate bonded to the first surface of the insulating plate to form a conductive pattern, and a second copper plate bonded to the second surface of the insulating plate, and a plurality of recesses are formed in at least one of the first and second copper plates, and a diameter D1 of an opening of each recess is smaller than the maximum diameter D2 inside than the opening of the recess.SELECTED DRAWING: Figure 3

Description

本発明は、半導体装置用基板に関する。 The present invention relates to a semiconductor device substrate.

パワートランジスタモジュールなどに用いる半導体装置用基板として、セラミック焼結体等の絶縁板の表面に銅板を備えたＤＢＯＣ基板（Ｄｉｒｅｃｔ Ｂｏｎｄｉｎｇ ｏｆ Ｃｏｐｐｅｒ Ｓｕｂｓｔｒａｔｅ）が知られている。そして、銅板の周縁には、例えば、特許文献１に示すような凹部を形成することができる。これにより、半導体装置の温度変化による熱応力が絶縁板に作用しても、複数の凹部により、銅板の周縁に生じる熱応力を緩和することができる。その結果、絶縁板の割れ、銅板の剥がれを防止することができる。 2. Description of the Related Art DBOC substrates (Direct Bonding of Copper Substrates), in which a copper plate is provided on the surface of an insulating plate such as a ceramic sintered body, are known as substrates for semiconductor devices used in power transistor modules and the like. Then, a concave portion as shown in Patent Document 1, for example, can be formed on the peripheral edge of the copper plate. Thereby, even if thermal stress due to temperature change of the semiconductor device acts on the insulating plate, the thermal stress generated in the peripheral edge of the copper plate can be alleviated by the plurality of recesses. As a result, cracking of the insulating plate and peeling of the copper plate can be prevented.

国際公報第２０１９／１６７５０９号公報International Publication No. 2019/167509

しかしながら、凹部を形成すると、上記のように銅板の周縁に生じる熱応力を緩和できるものの、銅板主面における半田等の接合材の濡れ広がりが凹部で阻害される恐れがあった。本発明は、上記問題を解決するためになされたものであり、銅板に凹部が形成されていても半田等の接合材の濡れ広がりの阻害を抑制することができる、半導体装置用基板を提供することを目的とする。 However, although the formation of the recess can alleviate the thermal stress generated in the peripheral edge of the copper plate as described above, the recess may hinder the wetting and spreading of the bonding material such as solder on the main surface of the copper plate. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a substrate for a semiconductor device capable of suppressing inhibition of wetting and spreading of a bonding material such as solder even if a concave portion is formed in a copper plate. for the purpose.

本発明に係る半導体装置用基板は、第１面及び第２面を有する絶縁板と、前記絶縁板の第１面に接合され、導電パターンを形成するための第１銅板と、前記絶縁板の第２面に接合される第２銅板と、を備え、前記第１銅板及び第２銅板の少なくとも一方に複数の凹部が形成され、前記各凹部の開口の径Ｄ１が、当該凹部の開口よりも内部の最大径Ｄ２よりも小さい。 A substrate for a semiconductor device according to the present invention comprises: an insulating plate having a first surface and a second surface; a first copper plate bonded to the first surface of the insulating plate to form a conductive pattern; and a second copper plate bonded to the second surface, wherein a plurality of recesses are formed in at least one of the first copper plate and the second copper plate, and the diameter D1 of the opening of each recess is larger than the opening of the recess. It is smaller than the internal maximum diameter D2.

上記半導体装置用基板において、前記凹部の開口縁部と対応する、前記第１銅板または前記第２銅板の縁部は、前記開口の径方向内方に突出し、且つ、断面円弧状に形成することができる。 In the semiconductor device substrate, the edge of the first copper plate or the second copper plate, which corresponds to the edge of the recess, protrudes radially inward of the opening and has an arc-shaped cross section. can be done.

上記半導体装置用基板において、前記縁部の曲率半径は、２．０μｍ以上とすることができる。 In the semiconductor device substrate described above, the radius of curvature of the edge portion may be 2.0 μm or more.

上記半導体装置用基板において、前記径Ｄ１に対する前記最大径Ｄ２は、１．０８以上とすることができる。 In the semiconductor device substrate described above, the maximum diameter D2 with respect to the diameter D1 may be 1.08 or more.

上記半導体装置用基板において、前記凹部は、前記絶縁板まで達しないように形成することができる。 In the semiconductor device substrate described above, the recess may be formed so as not to reach the insulating plate.

上記半導体装置用基板においては、前記第１銅板及び第２銅板の少なくとも一方の周縁に沿って、複数の前記凹部を形成することができる。 In the semiconductor device substrate, a plurality of recesses may be formed along the peripheral edge of at least one of the first copper plate and the second copper plate.

上記半導体装置用基板においては、前記第１銅板の中央付近に、複数の前記凹部を形成することができる。 In the semiconductor device substrate, a plurality of recesses may be formed near the center of the first copper plate.

上記半導体装置用基板においては、前記第１銅板及び第２銅板の両方に、複数の前記凹部をそれぞれ形成することができる。 In the semiconductor device substrate, both the first copper plate and the second copper plate may be formed with a plurality of recesses.

本発明によれば、銅板に凹部が形成されていても、半田等の接合材の濡れ広がりの阻害を抑制することができる。 ADVANTAGE OF THE INVENTION According to this invention, even if the recessed part is formed in the copper plate, it can suppress the obstruction of the wet spread of joining materials, such as solder.

本発明に係る半導体装置用基板を有する半導体装置の一実施形態を示す断面図である。1 is a cross-sectional view showing an embodiment of a semiconductor device having a semiconductor device substrate according to the present invention; FIG. 半導体装置用基板の平面図である。1 is a plan view of a substrate for a semiconductor device; FIG. 半導体装置用基板の拡大断面図である。1 is an enlarged cross-sectional view of a substrate for a semiconductor device; FIG. 凹部の他の例を示す断面図である。FIG. 5 is a cross-sectional view showing another example of a recess; 実施例１の凹部の断面図である。4 is a cross-sectional view of a recess in Example 1. FIG. 実施例１の凹部の縁部の拡大断面図である。4 is an enlarged cross-sectional view of the edge of the recess in Example 1. FIG. 実施例３の凹部の断面図である。FIG. 11 is a cross-sectional view of a recess in Example 3; 実施例３の凹部の縁部の拡大断面図である。FIG. 11 is an enlarged cross-sectional view of the edge of the recess in Example 3; 実施例４の凹部の断面図である。FIG. 11 is a cross-sectional view of a recess in Example 4; 実施例４の凹部の縁部の拡大断面図である。FIG. 12 is an enlarged cross-sectional view of the edge of the recess in Example 4; 実施例６の凹部の断面図である。FIG. 11 is a cross-sectional view of a recess in Example 6; 実施例６の凹部の縁部の拡大断面図である。FIG. 12 is an enlarged cross-sectional view of the edge of the recess in Example 6;

以下、本発明に係る半導体装置用基板の一実施形態について、図面を参照しながら説明する。図１は、本実施形態に係る半導体装置用基板を有する半導体装置の断面図である。 An embodiment of a semiconductor device substrate according to the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor device having a semiconductor device substrate according to this embodiment.

＜１．半導体装置の概要＞
本実施形態に係る半導体装置は、例えば、自動車、空調機、産業用ロボット、業務用エレベータ、家庭用電子レンジ、ＩＨ電気炊飯器、発電（風力発電、太陽光発電、燃料電池など）、電鉄、ＵＰＳ（無停電電源）などの様々な電子機器においてパワーモジュールとして用いられる。 <1. Overview of semiconductor devices>
The semiconductor device according to this embodiment includes, for example, automobiles, air conditioners, industrial robots, commercial elevators, household microwave ovens, IH electric rice cookers, power generation (wind power generation, solar power generation, fuel cells, etc.), electric railways, It is used as a power module in various electronic devices such as UPS (uninterruptible power supply).

図１に示すように、本実施形態に係る半導体装置１は、半導体装置用基板２、第１接合材５、第２接合材５’、半導体チップ６、ボンディングワイヤ７、及びヒートシンク８を備えている。 As shown in FIG. 1, a semiconductor device 1 according to this embodiment includes a semiconductor device substrate 2, a first bonding material 5, a second bonding material 5', a semiconductor chip 6, bonding wires 7, and a heat sink 8. there is

半導体装置用基板２は、いわゆるＤＢＯＣ基板（Ｄｉｒｅｃｔ Ｂｏｎｄｉｎｇ ｏｆ Ｃｏｐｐｅｒ Ｓｕｂｓｔｒａｔｅ）であり、絶縁体である板状の絶縁板３と、その第１面（上面）に接合された第１銅板４と、第２面（下面）に接合された第２銅板４’とを備える。 The semiconductor device substrate 2 is a so-called DBOC substrate (Direct Bonding of Copper Substrate), and includes a plate-like insulating plate 3 which is an insulator, a first copper plate 4 bonded to a first surface (upper surface) thereof, and a second copper substrate. and a second copper plate 4' joined to two surfaces (lower surfaces).

絶縁板３は、熱伝導性に優れた、酸化アルミニウム、窒化アルミニウム、窒化珪素等の熱伝導性が高いセラミックスにより構成されている。絶縁板３の厚みは、例えば、０．２５～０．６３５ｍｍであることが好ましく、０．２５～０．３８ｍｍであることがさらに好ましい。 The insulating plate 3 is made of a highly thermally conductive ceramic such as aluminum oxide, aluminum nitride, or silicon nitride. The thickness of the insulating plate 3 is, for example, preferably 0.25 to 0.635 mm, more preferably 0.25 to 0.38 mm.

第１銅板４には、導電パターン等の伝送回路が形成されている。一方、第２銅板４’は、平板状に形成されている。これらの銅板４，４’の厚みは、例えば、０．１～２．０ｍｍであることが好ましく、０．２～０．４ｍｍであることがさらに好ましい。銅板４，４’が厚いと半導体装置用基板２の放熱性が高まるが、一方で熱応力が大きくなり信頼性が低下する恐れがある。よって半導体装置１の用途や絶縁板３の機械的強度などにより銅板４，４’の厚みが設定される。また、第２銅板４’には、後述するように凹部が形成されている。 A transmission circuit such as a conductive pattern is formed on the first copper plate 4 . On the other hand, the second copper plate 4' is formed in a flat plate shape. The thickness of these copper plates 4, 4' is, for example, preferably 0.1 to 2.0 mm, more preferably 0.2 to 0.4 mm. If the copper plates 4, 4' are thick, the heat dissipation of the semiconductor device substrate 2 is enhanced, but on the other hand, the thermal stress may be increased and the reliability may be lowered. Therefore, the thickness of the copper plates 4 and 4' is set according to the use of the semiconductor device 1, the mechanical strength of the insulating plate 3, and the like. Further, recesses are formed in the second copper plate 4' as will be described later.

この半導体装置用基板２の上面、つまり第１銅板４の上面の一部には、第１接合材５を介して半導体チップ６が接合されている。また、ボンディングワイヤ７により、半導体チップ６と第１銅板４とが接続されている。 A semiconductor chip 6 is bonded to the upper surface of the semiconductor device substrate 2 , that is, to a portion of the upper surface of the first copper plate 4 with a first bonding material 5 interposed therebetween. Also, the semiconductor chip 6 and the first copper plate 4 are connected by bonding wires 7 .

一方、半導体装置用基板２の下面、つまり第２銅板４’の下面には、第２接合材５’を介してヒートシンク８が接合されている。ヒートシンク８は、公知のものであり、例えば銅などの金属によって構成することができる。 On the other hand, a heat sink 8 is bonded to the bottom surface of the semiconductor device substrate 2, that is, the bottom surface of the second copper plate 4', via a second bonding material 5'. The heat sink 8 is known and can be made of metal such as copper.

なお、接合材５，５’は、半田や銀ろうなどで形成することができる。接合材５，５’が半田である場合には、例えば、錫－銀－銅からなる合金、錫－亜鉛－ビスマスからなる合金、錫－銅からなる合金、錫－銀－インジウム－ビスマスからなる合金のうち少なくともいずれかの合金を主成分とする鉛フリー半田を採用することができる。 Note that the bonding materials 5 and 5' can be formed of solder, silver solder, or the like. When the bonding materials 5 and 5' are solder, for example, tin-silver-copper alloy, tin-zinc-bismuth alloy, tin-copper alloy, tin-silver-indium-bismuth. A lead-free solder containing at least one alloy as a main component can be used.

＜２．第２銅板に形成される凹部＞
上述したように、第２銅板４’には凹部が形成されている。この点について、詳細に説明する。図２は第２銅板から見た半導体装置用基板の平面図、図３は図２の拡大断面図である。図２及び図３に示すように、第２銅板４’には、複数の凹部９が、所定間隔をおいて、第２銅板４’の周縁に沿って形成されている。各凹部９は半球状に形成されており、開口の平面形状は円形に形成されている。そして、各凹部９には、上述した第２接合材５’が流れ込むようになっている。 <2. Recess Formed in Second Copper Plate>
As described above, recesses are formed in the second copper plate 4'. This point will be described in detail. 2 is a plan view of the semiconductor device substrate viewed from the second copper plate, and FIG. 3 is an enlarged sectional view of FIG. As shown in FIGS. 2 and 3, a plurality of recesses 9 are formed along the periphery of the second copper plate 4' at predetermined intervals in the second copper plate 4'. Each recess 9 is formed in a hemispherical shape, and the planar shape of the opening is formed in a circular shape. Then, the above-described second bonding material 5 ′ flows into each recess 9 .

各凹部９は平面視して円形となっており、円の中心を通る、第２銅板４’の厚み方向の断面図が図３である。平面視して円形である各凹部９の開口の直径はＤ１で表される。各凹部９は第２銅板４’内部で球体に近い空洞となっている。そのため各凹部９の断面形状は図３のように円形の一部を切り取った形状になる。第２銅板４’の厚み方向に垂直な方向の各凹部９の寸法のうち、最大の寸法をＤ２とする。また第２銅板４’の厚み方向の各凹部９の寸法のうち、最大の寸法をＤ３とする。Ｄ３は各凹部９の深さ寸法である。 Each concave portion 9 is circular in plan view, and FIG. 3 is a cross-sectional view in the thickness direction of the second copper plate 4' passing through the center of the circle. The diameter of the opening of each concave portion 9, which is circular in plan view, is represented by D1. Each recess 9 is a cavity that is nearly spherical inside the second copper plate 4'. Therefore, the cross-sectional shape of each concave portion 9 is a shape obtained by cutting a part of a circle as shown in FIG. Let D2 be the maximum dimension of the recesses 9 in the direction perpendicular to the thickness direction of the second copper plate 4'. D3 is the maximum dimension of the recesses 9 in the thickness direction of the second copper plate 4'. D3 is the depth dimension of each recess 9 .

各凹部９の開口の径Ｄ１は、開口よりも内部の最大径Ｄ２よりも小さくなっている。そのため、各凹部９の開口縁部と対応する、第２銅板４’の縁部９１は、開口の径方向内方に突出している。また、本実施形態では、この縁部９１の先端が断面円弧状に形成されている。 The diameter D1 of the opening of each recess 9 is smaller than the maximum diameter D2 inside the opening. Therefore, the edge 91 of the second copper plate 4' corresponding to the opening edge of each recess 9 protrudes radially inward of the opening. Further, in this embodiment, the tip of the edge portion 91 is formed to have an arcuate cross-section.

各凹部９の径Ｄ１は、３００～７００μｍであることが好ましく、４００～６００μｍであることがさらに好ましい。また、最大径Ｄ２は、３２０～７００μｍであることが好ましく、４５０～７００μｍであることがさらに好ましい。径Ｄ１に対する最大径Ｄ２の割合は、１．０５～１．２０であることが好ましく、１．０８～１．１５であることが好ましい。 The diameter D1 of each recess 9 is preferably 300-700 μm, more preferably 400-600 μm. Also, the maximum diameter D2 is preferably 320 to 700 μm, more preferably 450 to 700 μm. The ratio of the maximum diameter D2 to the diameter D1 is preferably 1.05 to 1.20, more preferably 1.08 to 1.15.

凹部９の深さＤ３は、第２銅板４’の厚みよりも小さく、１００～４００μｍであることが好ましく、２５０～３９０μｍであることがさらに好ましい。凹部９の径Ｄ１に対する凹部９の深さＤ３の割合は、０．５～０．８であることが好ましく、０．６～０．８であることがさらに好ましい。 The depth D3 of the concave portion 9 is smaller than the thickness of the second copper plate 4', preferably 100-400 μm, more preferably 250-390 μm. The ratio of the depth D3 of the recess 9 to the diameter D1 of the recess 9 is preferably 0.5 to 0.8, more preferably 0.6 to 0.8.

また、第２銅板４’の縁部９１の断面の曲率半径は、１．５～１０．０μｍであることが好ましく、２．０～８．０μｍであることがさらに好ましい。但し、縁部９１の断面形状は必ずしも円弧状でなくてもよく、鋭角状に形成されていてもよい。 The cross-sectional curvature radius of the edge 91 of the second copper plate 4' is preferably 1.5 to 10.0 μm, more preferably 2.0 to 8.0 μm. However, the cross-sectional shape of the edge portion 91 does not necessarily have to be arcuate, and may be formed to have an acute angle.

凹部９の間隔Ｗは、狭すぎると第２接合材５’の濡れ広がりが悪くなる一方、間隔Ｗが大きすぎると、凹部の応力緩和効果が得られないおそれがある。そのため、凹部９の間隔Ｗは、好ましくは、０．１～０．５ｍｍであることが好ましく、０．１５～０．３ｍｍであることがさらに好ましい。 If the spacing W between the recesses 9 is too narrow, the second bonding material 5' will not spread well. Therefore, the interval W between the concave portions 9 is preferably 0.1 to 0.5 mm, more preferably 0.15 to 0.3 mm.

＜３．半導体装置用基板の製造方法＞
次に、上述した半導体装置用基板２の製造方法の一例について説明する。まず、絶縁板３の上面及び下面に第１及び第２銅板４，４’を配置した積層体を形成する。ここで、用いられる各銅板の表面は酸化されている。次に、この積層体を１０６５℃～１０８３℃の窒素雰囲気条件下で１０分程度加熱する。これによって、絶縁板３と第１及び第２銅板４，４’とが接合する界面にＣｕ－Ｏ共晶液相が生成され、絶縁板３の各面が濡れる。続いて、この積層体を冷却することによってＣｕ－Ｏ共晶液相が固化されて、絶縁板３に第１及び第２銅板４，４’が接合される。なお、第１及び第２銅板４，４’は真空中においてチタンなどの活性金属を含むロウ材で絶縁板３に接合されてもよい。 <3. Method for manufacturing semiconductor device substrate>
Next, an example of a method for manufacturing the semiconductor device substrate 2 described above will be described. First, a laminate is formed by arranging the first and second copper plates 4, 4' on the upper and lower surfaces of the insulating plate 3. As shown in FIG. Here, the surface of each copper plate used is oxidized. Next, this laminate is heated at 1065° C. to 1083° C. under a nitrogen atmosphere for about 10 minutes. As a result, a Cu--O eutectic liquid phase is generated at the interfaces where the insulating plate 3 and the first and second copper plates 4, 4' are joined, and each surface of the insulating plate 3 is wetted. Subsequently, the laminate is cooled to solidify the Cu—O eutectic liquid phase, and the first and second copper plates 4 and 4 ′ are bonded to the insulating plate 3 . The first and second copper plates 4, 4' may be joined to the insulating plate 3 in a vacuum with a brazing material containing an active metal such as titanium.

次に、第２銅板４’に凹部９を形成する。まず、第２銅板４’の凹部９と対応する円形の貫通孔が形成されたマスク層を第２銅板４’に積層する。これら貫通孔の内径は、凹部９の開口の径Ｄ１よりも小さく、例えば、径Ｄ１の３５～５５％とすることができる。そして、０．５～５ｍ／ｍｉｎのエッチングスピードでエッチングを行い、凹部９を形成する。 Next, recesses 9 are formed in the second copper plate 4'. First, a mask layer having circular through holes corresponding to the concave portions 9 of the second copper plate 4' is laminated on the second copper plate 4'. The inner diameter of these through-holes is smaller than the diameter D1 of the opening of the recess 9, and can be, for example, 35 to 55% of the diameter D1. Then, etching is performed at an etching speed of 0.5 to 5 m/min to form recesses 9 .

なお、第１銅板４に形成されている伝送回路は、例えば、サブトラクティブ法又はアディティブ法によって形成することができる。 The transmission circuit formed on the first copper plate 4 can be formed by, for example, a subtractive method or an additive method.

＜４．特徴＞
上記実施形態によれば、以下の効果を得ることができる。
（１）半導体装置１の温度変化による熱応力が半導体装置用基板２に作用しても、複数の凹部９により、第２銅板４’の周縁に生じる熱応力を緩和することができる。その結果、半導体装置用基板２の割れ、第２銅板４’の剥がれを防止することができる。 <4. Features>
According to the above embodiment, the following effects can be obtained.
(1) Even if thermal stress due to temperature change of the semiconductor device 1 acts on the semiconductor device substrate 2, the plurality of recesses 9 can alleviate the thermal stress generated in the peripheral edge of the second copper plate 4'. As a result, cracking of the semiconductor device substrate 2 and peeling of the second copper plate 4' can be prevented.

（２）凹部９の開口の径Ｄ１が、凹部９の内部の最大径Ｄ２よりも小さいため、凹部９を形成しながらも、第２銅板４’の主面の面積を増やすことができる。これにより、平坦な第２銅板４’の主面上を流れてきた半田などの接合材５’の濡れ広がりが凹部９で阻害されることを低減できる。その結果、第２銅板４’とヒートシンク８の間に接合材５’の空洞が生じることが抑制され、半導体チップ６で生じた熱を良好にヒートシンク８まで伝えることができる。 (2) Since the diameter D1 of the opening of the recess 9 is smaller than the maximum diameter D2 inside the recess 9, the area of the main surface of the second copper plate 4' can be increased while forming the recess 9. As a result, it is possible to reduce the obstruction of the wetting and spreading of the bonding material 5 ′ such as solder flowing over the main surface of the flat second copper plate 4 ′ by the recesses 9 . As a result, the formation of cavities in the bonding material 5 ′ between the second copper plate 4 ′ and the heat sink 8 is suppressed, and the heat generated in the semiconductor chip 6 can be transferred to the heat sink 8 satisfactorily.

（３）凹部９の開口縁部における第２銅板４’の縁部９１が、開口の径方向内方に突出しているため、突出部の分だけ第２銅板４’の体積が増える。このため半導体装置用基板２の放熱性が向上する。 (3) Since the edge 91 of the second copper plate 4' at the edge of the opening of the recess 9 protrudes radially inward of the opening, the volume of the second copper plate 4' increases by the amount of the protrusion. Therefore, the heat dissipation of the semiconductor device substrate 2 is improved.

（４）開口縁部における第２銅板４’の縁部９１の断面形状が円弧状であるため、第２接合材５’を第２銅板４’の主面から凹部９内にスムーズに案内することができ、凹部９に流れ込みやすくなる。特に、縁部９１の曲率半径が大きいほど、第２接合材５’が流れ込みやすくなる。このため、凹部９内にボイドが形成されることを抑制できる。よってボイド内部での部分放電を抑制でき、また、ボイドによる放熱性の低下を抑制できる。 (4) Since the cross-sectional shape of the edge 91 of the second copper plate 4' at the opening edge is arc-shaped, the second bonding material 5' is smoothly guided into the recess 9 from the main surface of the second copper plate 4'. , making it easier to flow into the recess 9 . In particular, the larger the radius of curvature of the edge portion 91, the easier the flow of the second bonding material 5'. Therefore, formation of voids in the recess 9 can be suppressed. Therefore, partial discharge inside the voids can be suppressed, and deterioration of heat dissipation due to the voids can be suppressed.

＜５．変形例＞
以上、本発明の一実施形態について説明したが、本発明はこれに限定されるものではなく、その趣旨を逸脱しない限りにおいて種々の変更が可能である。なお、以下の変形例は適宜、組み合わせることができる。 <5. Variation>
Although one embodiment of the present invention has been described above, the present invention is not limited to this, and various modifications are possible without departing from the gist of the present invention. Note that the following modified examples can be combined as appropriate.

（１）上記実施形態では、第２銅板４’の周縁に沿って１列の凹部９を形成しているが、２列以上形成することもできる。 (1) In the above embodiment, one row of recesses 9 is formed along the peripheral edge of the second copper plate 4', but two or more rows may be formed.

（２）上記実施形態では、第２銅板４’にのみ凹部９を形成しているが、第１銅板４にも凹部９を形成することができる。この場合、第２銅板４’と同様に、第１銅板４の周縁に沿って１列以上の凹部９を形成することができる。また、第１銅板４の中央付近に凹部９を形成することもできる。この凹部９は、例えば、半導体チップ６の位置決めに用いることができる。 (2) In the above embodiment, the recesses 9 are formed only in the second copper plate 4 ′, but the recesses 9 can also be formed in the first copper plate 4 . In this case, one or more rows of recesses 9 can be formed along the peripheral edge of the first copper plate 4 as in the case of the second copper plate 4 ′. Also, the concave portion 9 can be formed in the vicinity of the center of the first copper plate 4 . This concave portion 9 can be used, for example, for positioning the semiconductor chip 6 .

（３）凹部９の開口の形状は特には限定されず、上記のような円形のほか、楕円状、あるいは矩形の角部を丸くした形状等にすることもできる。この場合、開口の径Ｄ１は、最大径とすることができる。最大径としては、開口の形状に対する外接円相当径を設定することができる。また、凹部９の断面形状は略円形の一部であるほか、楕円の一部であってもよい。 (3) The shape of the opening of the concave portion 9 is not particularly limited, and in addition to the circular shape described above, it may be an elliptical shape, or a rectangular shape with rounded corners. In this case, the diameter D1 of the opening can be the maximum diameter. As the maximum diameter, a circumscribed circle equivalent diameter for the shape of the opening can be set. Moreover, the cross-sectional shape of the recess 9 may be a part of a substantially circular shape, or a part of an ellipse.

（４）上記実施形態では、凹部９は第２銅板４’内に形成され、絶縁板３まで達していないが、例えば、図４に示すように、第２銅板４’を貫通し、絶縁板３まで達していてもよい。この場合は凹部９による熱応力緩和効果が高まる。一方、凹部９が絶縁板３まで達している場合に比べ、凹部９が絶縁板３に達していない場合の方が第２銅板４’の体積が相対的に増える。このため放熱性が高まる。さらに凹部９の体積が小さくなるため第２接合材５’の流れ込み不足によるボイドの形成も抑制できる。 (4) In the above embodiment, the recess 9 is formed in the second copper plate 4' and does not reach the insulating plate 3, but as shown in FIG. It may reach up to 3. In this case, the thermal stress relieving effect of the concave portion 9 is enhanced. On the other hand, the volume of the second copper plate 4 ′ relatively increases when the recess 9 does not reach the insulating plate 3 as compared to when the recess 9 reaches the insulating plate 3 . Therefore, heat dissipation is enhanced. Furthermore, since the volume of the recessed portion 9 is reduced, formation of voids due to insufficient flow of the second bonding material 5' can be suppressed.

以下、本発明の実施例について説明する。但し、本発明は、以下の実施例に限定されない。 Examples of the present invention will be described below. However, the present invention is not limited to the following examples.

絶縁板として厚みが０．３２ｍｍのアルミナを準備した。そして、この絶縁板の両面に厚みが０．４ｍｍの表面が酸化された銅板を配置し、１０７０℃の窒素雰囲気条件下で１０分程度加熱して絶縁板に銅板を接合した。こうして得られた半導体装置用基板の一方の銅板の周縁に沿って、以下のような凹部を形成し、実施例１～６に係る半導体装置用基板を得た。 Alumina having a thickness of 0.32 mm was prepared as an insulating plate. A copper plate having a thickness of 0.4 mm and having an oxidized surface was placed on both sides of the insulating plate, and heated at 1070° C. for about 10 minutes in a nitrogen atmosphere to bond the copper plate to the insulating plate. A concave portion as described below was formed along the peripheral edge of one of the copper plates of the semiconductor device substrate thus obtained, and semiconductor device substrates according to Examples 1 to 6 were obtained.

凹部は、エッチングにより形成した。凹部用のマスクに形成する貫通孔の径、及びエッチンクスピードは以下の表１の通りである。絶縁板と銅板を接合した接合体の銅板表面に、エッチングレジスト、あるいはドライフィルムによるマスキングを施し、マスキングされていない銅板部分を化学的にエッチングすることで、所望の形状の回路パターンが形成される。エッチングスピードは長さ約５ｍのエッチングエリアに接合体を通過させるスピードを示す。エッチングエリアではエッチング液が接合体に向けて噴射され、銅板がエッチングされる。

Figure 2022188583000002
このようなエッチングにより、実施例１～６においては、以下の表２に示すような凹部が形成された。このうち、実施例６の凹部は、銅板を貫通し、絶縁板まで達している。こうして、実施例１～６に係る半導体装置用基板が得られた。なお、以下の表２における縁部の長さとは、凹部の最大径Ｄ２よりも突出している部分の長さであり、（Ｄ２－Ｄ１）／２により算出される。
Figure 2022188583000003
 The recess was formed by etching. Table 1 below shows the diameter of the through-holes formed in the recess mask and the etching speed. A circuit pattern with a desired shape is formed by masking the surface of the copper plate of the bonded body in which an insulating plate and a copper plate are bonded with an etching resist or dry film, and chemically etching the unmasked copper plate portion. . Etching speed indicates the speed at which the bonded material is passed through an etching area having a length of about 5 m. In the etching area, an etchant is sprayed toward the bonded body to etch the copper plate.
Figure 2022188583000002
 By such etching, recesses as shown in Table 2 below were formed in Examples 1 to 6. Of these, the concave portion of Example 6 penetrates the copper plate and reaches the insulating plate. Thus, semiconductor device substrates according to Examples 1 to 6 were obtained. The length of the edge portion in Table 2 below is the length of the portion that protrudes from the maximum diameter D2 of the recess, and is calculated by (D2-D1)/2.
Figure 2022188583000003

また、実施例１，３，４，６において形成された凹部の断面形状、及び縁部の拡大図を、それぞれ、図５～図８に示す。 5 to 8 show the cross-sectional shapes of the recesses formed in Examples 1, 3, 4, and 6, and enlarged views of the edge portions, respectively.

以上のように、実施例１～６においては、いずれも最大径Ｄ２が開口の径Ｄ１よりも大きい凹部を形成することができた。そのため、凹部を形成しながらも銅板の主面の面積を増大することができた。したがって、例えば、ヒートシンクを接合材によって銅板に接合する際には、平坦な銅板の主面上を流れてきた接合材の濡れ広がりが凹部で阻害されることを低減できる。また、銅板の体積が増えるため、放熱性を高めることができる。さらに、いずれの凹部も、縁部の断面を円弧状に形成されている。したがって、接合材を銅板の主面から凹部に内部に向かって回り込みやすくすることができる。 As described above, in each of Examples 1 to 6, it was possible to form a concave portion having a maximum diameter D2 larger than the diameter D1 of the opening. Therefore, it was possible to increase the area of the main surface of the copper plate while forming the recesses. Therefore, for example, when a heat sink is bonded to a copper plate with a bonding material, it is possible to reduce the obstruction of the wetting and spreading of the bonding material flowing over the main surface of the flat copper plate by the concave portion. Moreover, since the volume of the copper plate increases, heat dissipation can be improved. Further, each concave portion has an arcuate cross-section of the edge portion. Therefore, it is possible to make it easier for the bonding material to flow from the main surface of the copper plate toward the inside of the recess.

２…半導体装置用基板
３…絶縁板
４，４’…銅板
９…凹部
９１…縁部 2 Semiconductor device substrate 3 Insulating plates 4, 4' Copper plate 9 Recess 91 Edge

Claims (8)

第１面及び第２面を有する絶縁板と、
前記絶縁板の第１面に接合され、導電パターンを形成するための第１銅板と、
前記絶縁板の第２面に接合される第２銅板と、
を備え、
前記第１銅板及び第２銅板の少なくとも一方に複数の凹部が形成され、
前記各凹部の開口の径Ｄ１が、当該凹部の開口よりも内部の最大径Ｄ２よりも小さい、半導体装置用基板。 an insulating plate having a first surface and a second surface;
a first copper plate bonded to the first surface of the insulating plate for forming a conductive pattern;
a second copper plate bonded to the second surface of the insulating plate;
with
A plurality of recesses are formed in at least one of the first copper plate and the second copper plate,
A substrate for a semiconductor device, wherein the diameter D1 of the opening of each recess is smaller than the maximum diameter D2 inside the opening of the recess. 前記凹部の開口縁部と対応する、前記第１銅板または前記第２銅板の縁部は、前記開口の径方向内方に突出し、且つ、断面円弧状に形成されている、請求項１に記載の半導体装置用基板。 2. The edge portion of the first copper plate or the second copper plate corresponding to the opening edge portion of the concave portion according to claim 1, wherein the edge portion protrudes radially inward of the opening and is formed to have an arcuate cross section. substrates for semiconductor devices. 前記縁部の曲率半径が、２．０μｍ以上である、請求項２に記載の半導体装置用基板。 3. The semiconductor device substrate according to claim 2, wherein said edge has a radius of curvature of 2.0 [mu]m or more. 前記径Ｄ１に対する前記最大径Ｄ２の割合が、１．０８以上である、請求項１から３のいずれかに記載の半導体装置用基板。 4. The semiconductor device substrate according to claim 1, wherein a ratio of said maximum diameter D2 to said diameter D1 is 1.08 or more. 前記凹部は、前記絶縁板まで達していない、請求項１から４のいずれかに記載の半導体装置用基板。 5. The semiconductor device substrate according to claim 1, wherein said recess does not reach said insulating plate. 前記第１銅板及び第２銅板の少なくとも一方の周縁に沿って、複数の前記凹部が形成されている、請求項１から５のいずれかに記載の半導体装置用基板。 6. The semiconductor device substrate according to any one of claims 1 to 5, wherein a plurality of said concave portions are formed along a peripheral edge of at least one of said first copper plate and said second copper plate. 前記第１銅板の中央付近に、複数の前記凹部が形成されている、請求項１から６のいずれかに記載の半導体装置用基板。 7. The semiconductor device substrate according to claim 1, wherein a plurality of said recesses are formed near the center of said first copper plate. 前記第１銅板及び第２銅板の両方に、複数の前記凹部がそれぞれ形成されている、請求項１から７のいずれかに記載の半導体装置用基板。 8. The semiconductor device substrate according to claim 1, wherein a plurality of recesses are formed in both said first copper plate and said second copper plate.
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